System and method for automatically generating FPGA test case based on large language model

Abstract

The invention discloses an FPGA test case automatic generation system and method based on a large language model. The system comprises a demand input module, a demand structuring module, a large language model case generation module, a case confirmation module, a verification execution module and a closed-loop optimization module. The large language model can automatically analyze the unstructured demand document and extract key information such as function points, input and output, boundary conditions and the like, and manual one-by-one interpretation is not needed. A big language model is guided through Prompt Engineering to dismantle complex requirements into test key points which cannot be subdivided, and it is ensured that all logic branches are covered by tests. The large language model can dynamically generate diversified test cases based on test key points, including a normal process, an abnormal process and an edge scene. And in combination with FPGA design specifications, historical error cases and other plug-in knowledge bases, the large language model can generate test cases closer to actual hardware behaviors.

Description

Technical Field

[0001] This invention relates to the field of FPGA testing technology, specifically to an automatic FPGA test case generation system and method based on a large language model. Background Technology

[0002] In the development and application of FPGA designs, testing is a crucial step in ensuring that functionality and performance meet design requirements. Traditional FPGA testing methods typically rely on manually writing test cases, which is not only extremely time-consuming and labor-intensive but also prone to incomplete test coverage due to human error, failing to effectively uncover hidden problems in the design. As the complexity of FPGA designs continues to increase, the limitations of traditional testing methods become increasingly apparent. Traditional FPGA verification heavily relies on engineers manually writing testbench and test vectors, which is extremely labor-intensive for large designs or frequent iterations, and easily leads to the omission of boundary conditions or abnormal scenarios, making it difficult to meet the high-quality and high-reliability requirements of modern electronic systems for FPGAs.

[0003] In recent years, artificial intelligence technology has made significant progress in many fields. Its advantages in data processing, pattern recognition, and automated decision-making have provided new ideas for solving FPGA testing problems. By introducing large language models, it is possible to automatically generate FPGA test cases, thereby improving testing efficiency and accuracy. However, existing technologies lack a complete, end-to-end automatic FPGA test case generation solution based on large language models, which fails to fully leverage the advantages of large language models and also makes it difficult to solve many pain points of traditional testing methods. Summary of the Invention

[0004] The purpose of this invention is to provide an automatic FPGA test case generation system and method based on a large language model, so as to solve the problems existing in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an FPGA test case automatic generation system based on a large language model, comprising a requirement input module, a requirement structuring module, a large language model test case generation module, a test case confirmation module, a verification execution module, and a closed-loop optimization module; The requirement input module is used to receive basic information and marking information related to FPGA design provided by engineers. The requirement structuring module is used to break down the input requirements and build a scenario library to form atomic test points; The large language model test case generation module is used to receive atomic test points and scenario libraries, and generate executable test cases that meet the requirements. The test case confirmation module is used by engineers to check test cases and to feed back test cases that fail the check and modification suggestions to the large language model test case generation module. The verification execution module is used to integrate the confirmed test cases into the FPGA verification environment, execute the test cases, and perform result analysis. The closed-loop optimization module is used to feed the test results back to the large language model test case generation module, and optimize the prompt words through reinforcement learning to achieve iterative optimization of test cases.

[0006] Preferably, the requirement structuring module includes a prompt word design unit and a basic scenario library establishment unit; the prompt word design unit is used to design prompt words specifically for large language models, adopting a hierarchical prompt strategy, and includes basic prompt templates, test point decomposition rules, and output format requirements, decomposing the overall design requirements into atomic test points; the basic scenario library establishment unit is used to establish a basic scenario library covering common test modes, including functional test scenarios, boundary test scenarios, and abnormal situation test scenarios.

[0007] Preferably, the verification execution module can adapt and integrate test cases with the FPGA verification environment to ensure that test cases can be executed interactively, and at the same time determine the Pass or Fail status of the execution result; the closed-loop optimization module drives the large language model to optimize prompt words by receiving the test results from the verification execution module.

[0008] The generation method of the FPGA test case automatic generation system based on large language models includes the following steps: Step 1, Requirements Input: Receive basic FPGA design information provided by the engineer through the requirements input module, and also receive key information marked by the engineer. Step 2, Requirements Structuring: Design prompts through the prompt design unit of the requirements structuring module, break down the FPGA design requirements into atomic test points, and build a basic scenario library through the basic scenario library building unit; Step 3: Generate test cases from the large language model: The large language model test case generation module receives the atomic test points and the basic scenario library, generates test cases that conform to the syntax and cover functions, boundaries, and abnormal situations, and forms test files that can be run directly after self-checking and correction. Step 4, Test Case Confirmation: Engineers check the generated test cases through the test case confirmation module. Test cases that fail the check are fed back to the large language model test case generation module along with modification suggestions, triggering iterative optimization. Step 5, Verification and Execution: The verification and execution module integrates the confirmed test cases into the FPGA verification environment, executes the test cases and analyzes the results, recording the Pass or Fail status of the test results; the closed-loop optimization module feeds the test results back to the large language model test case generation module, optimizes the prompt words through reinforcement learning, and the large language model iteratively generates more accurate test cases based on the optimized prompt words.

[0009] Preferably, in step 1, the basic information related to FPGA design includes FPGA design requirements document, interface definition and verification target, and the key information marked by the engineer includes the input-output relationship of key modules, the types of defects to be eliminated, key module identifiers, interface signal identifiers and expected behavior identifiers.

[0010] Preferably, in step 2, the hierarchical prompting strategy of the prompting word design unit designs corresponding prompting words for different test types. For functional testing, each functional module is broken down into independent test sub-functions, and the test direction is clearly defined for each sub-function. For performance testing, the prompting words include the specific requirements of performance indicators and test methods. For abnormal situation testing, the prompting words describe in detail various possible abnormal scenarios. The functional test scenarios in the basic scenario library cover various input-output combinations under normal functional operation, the boundary test scenarios mainly consider the boundary value of the input signal, and the abnormal situation test scenarios cover various situations that may cause FPGA malfunction.

[0011] Preferably, in step 3, when generating test cases using the large language model, an external knowledge base including FPGA design specifications and historical error cases is used to ensure that the generated test cases closely resemble actual hardware behavior. In terms of functional testing, the generated test cases comprehensively cover all functions of the FPGA, ensuring that each functional module is correctly verified under various normal and abnormal input conditions. In terms of performance testing, the test cases can accurately measure the performance indicators of the FPGA. In terms of abnormal scenario testing, the test cases can simulate various possible abnormal situations and detect whether the FPGA's response under these conditions meets expectations.

[0012] Preferably, in step 4, the engineer checks the test cases to ensure they cover the critical path of the design, whether any obvious boundary conditions are missing, whether there are any logical contradictions, and whether they conform to the FPGA syntax specification. The modification suggestions include the uncovered critical path parts, the types of missing boundary conditions, and a detailed description of any logical contradictions. The large language model test case generation module regenerates test cases based on the modification suggestions until they meet the engineer's requirements. The engineer regularly summarizes the review feedback, analyzes the problems in the large language model generation, corrects them, and regenerates or updates the design description to form an iterative optimization.

[0013] Preferably, in step 5, when the verification execution module integrates the test cases into the FPGA verification environment, it ensures that the test cases can correctly interact with the FPGA design. When analyzing the test results, it determines whether the execution result of each test case meets expectations, accurately records the Pass or Fail status, and analyzes the reasons for failure in detail for failed test cases and synchronizes them to the closed-loop optimization module. The closed-loop optimization module feeds back the test results and reasons for failure to the large language model test case generation module. The large language model optimizes the prompt words in a targeted manner through a reinforcement learning mechanism. The optimized prompt words are used to guide the generation of the next round of test cases. Through continuous iteration, the accuracy of the generated test cases is gradually improved, forming a continuously optimized closed-loop system.

[0014] Compared with the prior art, the beneficial effects of the present invention are: This invention's large language model can automatically parse unstructured requirement documents, extracting key information such as function points, inputs and outputs, and boundary conditions, eliminating the need for manual interpretation. Through prompt engineering, the large language model is guided to break down complex requirements into indivisible test points, ensuring that tests cover all logical branches.

[0015] The large language model can dynamically generate diverse test cases based on test points, including normal processes, abnormal processes, and edge scenarios. Combined with external knowledge bases such as FPGA design specifications and historical error cases, the large language model can generate test cases that more closely resemble actual hardware behavior.

[0016] Testers can describe test requirements using natural language, and the large language model automatically converts them into executable test cases without requiring code writing. The generated test cases are displayed visually, allowing testers to adjust parameters through drag-and-drop and fill-in-the-blank methods, further lowering the barrier to entry. Attached Figure Description

[0017] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is a flowchart of the execution process of the present invention; Figure 3 This is a simulation diagram of the test cases for this invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] Please see Figure 1-3 This invention provides an automatic FPGA test case generation system based on a large language model, including a requirement input module, a requirement structuring module, a large language model test case generation module, a test case confirmation module, a verification execution module, and a closed-loop optimization module; The requirement input module is used to receive basic information such as FPGA design requirement documents, interface definitions and verification targets provided by engineers. At the same time, it receives key information such as the input-output relationships of key modules marked by engineers, the types of defects to be eliminated, key module identifiers, interface signal identifiers and expected behaviors, so as to provide basic data support for the generation of subsequent test cases. The requirement structuring module includes a prompt word design unit and a basic scenario library establishment unit. The prompt word design unit adopts a hierarchical prompt strategy, designing prompt words that include basic prompt templates, test point decomposition rules, and output format requirements. For functional testing, each functional module is broken down into independent test sub-functions, and the test direction is clearly defined for each sub-function. For performance testing, the prompt words include specific requirements for performance indicators and test methods. For abnormal situation testing, the prompt words describe various possible abnormal scenarios in detail, ensuring that the prompt word descriptions are accurate and unambiguous, thereby decomposing the overall design requirements into atomic test points. The basic scenario library establishment unit establishes a basic scenario library covering functional test scenarios, boundary test scenarios, and abnormal situation test scenarios. Functional test scenarios include various input-output combinations under normal functional operation, boundary test scenarios mainly consider the boundary value of input signals, and abnormal situation test scenarios cover various situations that may cause FPGA malfunctions. The large language model test case generation module receives the atomic test points and basic scenario library output by the requirement structuring module. Combined with external knowledge bases such as FPGA design specifications and historical error cases, it generates test cases that conform to the syntax and cover functions, boundaries, and abnormal situations. In terms of functional testing, the generated test cases comprehensively cover all functions of the FPGA, ensuring that each functional module is correctly verified under various normal and abnormal input conditions. In terms of performance testing, the test cases can accurately measure the performance indicators of the FPGA. In terms of abnormal scenario testing, the test cases can simulate various possible abnormal situations and detect whether the FPGA's response under these situations meets expectations. After self-checking and correction, the generated test cases form a test file that can be run directly. The test case verification module provides engineers with a channel to check test cases. Engineers can quickly browse test cases through this module to check whether the test cases conform to the FPGA syntax specification, whether they cover the critical path of the design, whether obvious boundary conditions are missing, and whether there are logical contradictions. If test cases that fail the check are found, detailed modification suggestions are fed back to the large language model test case generation module. The modification suggestions include pointing out the part of the critical path that is not covered in the test case, the type of missing boundary condition, and a detailed description of the logical contradictions. The large language model test case generation module regenerates test cases based on the modification suggestions until they meet the requirements of engineers. Engineers regularly summarize the review feedback, analyze the problems in the large language model generation, and regenerate or update the design description after correction, forming an iterative optimization. The verification execution module is responsible for integrating the test cases confirmed by engineers into the FPGA verification environment, ensuring that the test cases can correctly interact with the FPGA design, then executing the test cases, analyzing the test results, determining whether the execution result of each test case meets expectations, recording the pass or fail status, and analyzing the reasons for failure in detail for failed test cases. The closed-loop optimization module feeds back the test results and failure reasons recorded by the verification execution module to the large language model test case generation module. The large language model optimizes the prompt words through a reinforcement learning mechanism. The optimized prompt words are used to guide the generation of test cases in the next round. By continuously feeding back the test results to the large language model and optimizing the prompt words, the large language model iteratively generates more accurate test cases, forming a closed-loop optimization system.

[0020] An automatic generation method for FPGA test cases based on a large language model includes the following steps: Step 1, Requirements Input: Engineers provide basic information such as FPGA design requirements documents, interface definitions, and verification targets through the requirements input module. This includes module function descriptions, interface definitions, and verification targets. It clarifies information such as signal types, bit widths, and functional points to be covered between modules. At the same time, it marks key modules, interface signals, and expected behaviors, clarifies the input-output relationships of key modules, and identifies the types of defects to be eliminated. This information is received and stored in real time by the requirements input module, providing a basis for subsequent processing.

[0021] Step 2, Requirements Structuring: The prompt word design unit of the requirements structuring module designs prompt words specifically for the large language model based on the FPGA design requirements provided by the engineers. The prompt words adopt a hierarchical prompt strategy, including basic prompt templates, test point decomposition rules, output format requirements, etc., to ensure that the prompt words are accurate and unambiguous. For functional testing, each functional module is broken down into independent test sub-functions, and corresponding prompt words are designed for each sub-function, clearly informing the large language model which aspects of the sub-function need to be tested. For performance testing, the prompt words include specific requirements for performance indicators and test methods. For abnormal situation testing, the prompt words describe in detail various possible abnormal scenarios. Through these prompt words, the overall design requirements are broken down into atomic test points. At the same time, the basic scenario library building unit builds a basic scenario library, covering common test modes. Functional test scenarios include various input-output combinations under normal functional operation, boundary test scenarios mainly consider the boundary value of input signals, and abnormal situation test scenarios cover various situations that may cause FPGA malfunction.

[0022] Step 3: Generate Test Cases from the Large Language Model: The large language model test case generation module receives the atomic test points output by the prompt word design unit and the basic scenario library established by the basic scenario library building unit. Combined with external knowledge bases such as FPGA design specifications and historical error cases, it generates test cases that conform to the syntax and cover functions, boundaries, and abnormal situations. In terms of functional testing, the generated test cases comprehensively cover all functions of the FPGA, ensuring that each functional module is correctly verified under various normal and abnormal input conditions. In terms of performance testing, the test cases can accurately measure the performance indicators of the FPGA. In terms of abnormal scenario testing, the test cases can simulate various possible abnormal situations and detect whether the FPGA's response under these situations meets expectations. After self-checking and correction, the generated test cases form a test file that can be run directly.

[0023] Step 4: Test Case Confirmation: Engineers use the test case confirmation module to quickly browse and perform a preliminary check on the test cases generated by the large language model. This check ensures the test cases conform to the FPGA syntax specification and cover the critical paths of the FPGA design. Critical paths refer to the key data transmission and processing flows within the FPGA; ensuring these paths are adequately tested is crucial for the overall correctness of the FPGA's functionality. The module also checks for any missing boundary conditions, whether test cases are included for boundary values ​​and their vicinity, and whether there are any logical contradictions between test cases. If engineers find any test cases that fail the preliminary check, they return detailed modification suggestions to the large language model test case generation module. These suggestions include identifying uncovered critical path portions, missing boundary condition types, and specific descriptions of any logical contradictions. The large language model test case generation module regenerates test cases based on these suggestions until they meet the engineers' requirements. Engineers periodically summarize review feedback, analyze issues generated by the large language model, and regenerate or update the design description after corrections, resulting in iterative optimization.

[0024] Step 5, Verification and Execution: The verification and execution module integrates the test cases, confirmed by engineers, into the FPGA verification environment to ensure that the test cases can correctly interact with the FPGA design. Then, the test cases are executed, and the test results are analyzed to determine whether the execution result of each test case meets expectations, recording the pass or fail status. For failed test cases, the reasons for failure are analyzed in detail, and this information is synchronized to the closed-loop optimization module. The closed-loop optimization module feeds back the test results (pass / fail) and failure reasons from the verification and execution module to the large language model test case generation module. The large language model uses a reinforcement learning mechanism to specifically optimize the prompt words. The optimized prompt words are used to guide the next round of test case generation, and the large language model iteratively generates more accurate test cases based on the optimized prompt words. By continuously repeating steps 3 to 5, an optimized closed-loop system is formed, continuously improving the quality and accuracy of test cases.

[0025] Example: The implementation process of the FPGA test case automatic generation system and method based on a large language model provided by this invention is as follows: Step 1, Requirements Input: Engineers provide the design requirements document for the FPGA chip, the interface definitions of each module, and the verification targets through the requirements input module. They must clarify the signal types and bit widths of the clock, reset, and data bus between modules, and the functional points to be covered include data transmission, logic operations, and abnormal alarms. At the same time, they must mark the key functional modules, core interface signals, and expected behaviors, and clarify the types of defects to be eliminated, such as data transmission errors and logic operation anomalies.

[0026] Step 2, Requirements Structuring: The prompt design unit of the requirements structuring module adopts a hierarchical prompt strategy, designing basic prompt templates, test point decomposition rules, and output format requirements. For functional testing, the data transmission module and logic operation module are broken down into independent test sub-functions, and the prompts clearly define the input and output verification direction of each sub-function. For performance testing, the prompts include test requirements and methods for performance indicators such as data transmission rate and logic operation latency. For abnormal situation testing, the prompts describe in detail possible abnormal scenarios such as clock signal abnormalities, data bus interference, and input signal over-range. The overall design requirements are broken down into atomic test points such as "verifying the data transmission accuracy of the data transmission module at normal clock frequency," "verifying the operation results of the logic operation module at input signal boundary values," and "verifying the alarm function of the FPGA when the clock signal is interrupted." The basic scenario library establishment unit establishes functional test scenarios, boundary test scenarios, and abnormal situation test scenarios. Functional test scenarios cover normal input and output combinations of each module, boundary test scenarios include the maximum, minimum, and critical values ​​of each input signal, and abnormal situation test scenarios cover various abnormal situations such as clock abnormalities, signal interference, and data loss.

[0027] Step 3: Generate Test Cases from the Large Language Model: The large language model test case generation module receives the atomic test points and basic scenario library, and combines them with the design specifications of this type of FPGA, historical data transmission errors, and error case knowledge bases such as logical operation anomalies, to generate test cases that conform to the FPGA syntax specifications. Among them, functional test cases cover normal functions such as one-way and two-way transmission of the data transmission module, and arithmetic functions such as addition, subtraction, multiplication, and division of the logic operation module; performance test cases can measure the data transmission rate under different data volumes and the logical operation latency of operations with different complexities; abnormal scenario test cases simulate clock signal interruption, data bus interference, input signal over-range, etc., to detect whether the FPGA response meets expectations; after self-checking and correction, the generated test cases form a test file that can be run directly.

[0028] Step 4: Test Case Confirmation: Engineers reviewed test cases through the test case confirmation module and found that some test cases did not cover the boundary scenarios of the data transmission module under high load, and that there were contradictory logical judgment conditions in one test case. For these issues, engineers provided modification suggestions, clearly indicating the need to add boundary test cases for data transmission under high load, as well as the specific location and direction of the logical contradictions, and fed this feedback to the large language model test case generation module. The large language model test case generation module regenerated test cases based on the modification suggestions, adding boundary test cases for high load scenarios and correcting the logical contradictions. Engineers checked again and confirmed that the test cases met the requirements. Subsequently, engineers regularly summarized the feedback from this review, analyzed the reasons for the omission of high load boundary scenarios when generating test cases in the large language model, revised the relevant design descriptions, and provided an optimization basis for subsequent test case generation.

[0029] Step 5, Verification and Execution: The verification and execution module integrates the confirmed test cases into the verification environment of the FPGA chip, ensuring that the test cases and the FPGA design can interact normally. All test cases are executed, and the execution results of each test case are analyzed. Most test cases result in a Pass, while two abnormal scenario test cases result in a Fail. Analysis shows that the failure was due to the FPGA failing to trigger the preset alarm mechanism under specific data bus interference intensities. The closed-loop optimization module feeds back the Pass / Fail status of all test cases and the specific failure reasons of the two failed test cases to the large language model test case generation module. The large language model optimizes the prompt words through reinforcement learning, enhancing the guidance for data bus interference intensity gradient testing. Based on the optimized prompt words, the large language model iteratively generates more accurate test cases, supplementing the test scenarios under different interference intensity gradients. Steps 3 to 5 are executed again. The newly generated test cases can accurately detect the FPGA's response under different data bus interference intensities, effectively covering previously missed test scenarios, and significantly improving the accuracy and coverage of the test cases.

[0030] This invention achieves automated and intelligent generation of FPGA test cases through large language model technology, comprehensively solving the problems of low efficiency, insufficient coverage, high cost, and reliance on human experience in traditional FPGA testing. It provides an efficient and reliable technical solution for FPGA testing and has significant engineering application value.

[0031] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An automatic FPGA test case generation system based on a large language model, characterized by: It includes a requirements input module, a requirements structuring module, a large language model test case generation module, a test case verification module, a verification and execution module, and a closed-loop optimization module; The requirement input module is used to receive basic information and marking information related to FPGA design provided by engineers. The requirement structuring module is used to break down the input requirements and build a scenario library to form atomic test points; The large language model test case generation module is used to receive atomic test points and scenario libraries, and generate executable test cases that meet the requirements. The test case confirmation module is used by engineers to check test cases and to feed back test cases that fail the check and modification suggestions to the large language model test case generation module. The verification execution module is used to integrate the confirmed test cases into the FPGA verification environment, execute the test cases, and perform result analysis. The closed-loop optimization module is used to feed the test results back to the large language model test case generation module, and optimize the prompt words through reinforcement learning to achieve iterative optimization of test cases.

2. The FPGA test case automatic generation system based on a large language model according to claim 1, characterized in that: The requirement structuring module includes a prompt word design unit and a basic scenario library establishment unit. The prompt word design unit is used to design prompt words specifically for large language models, and adopts a hierarchical prompt strategy. The content includes basic prompt templates, test point decomposition rules, and output format requirements, decomposing the overall design requirements into atomic test points. The basic scenario library establishment unit is used to establish a basic scenario library covering common test modes, including functional test scenarios, boundary test scenarios, and abnormal situation test scenarios.

3. The FPGA test case automatic generation system based on a large language model according to claim 1, characterized in that: The verification execution module can adapt and integrate test cases with the FPGA verification environment to ensure that test cases can be executed interactively, and at the same time determine the Pass or Fail status of the execution result; the closed-loop optimization module receives the test results from the verification execution module and drives the large language model to optimize the prompt words.

4. The generation method of the FPGA test case automatic generation system based on a large language model according to any one of claims 1-3, characterized in that: Includes the following steps: Step 1, Requirements Input: Receive basic FPGA design information provided by the engineer through the requirements input module, and also receive key information marked by the engineer. Step 2, Requirements Structuring: Design prompts through the prompt design unit of the requirements structuring module, break down the FPGA design requirements into atomic test points, and build a basic scenario library through the basic scenario library building unit; Step 3: Generate test cases from the large language model: The large language model test case generation module receives the atomic test points and the basic scenario library, generates test cases that conform to the syntax and cover functions, boundaries, and abnormal situations, and forms test files that can be run directly after self-checking and correction. Step 4, Test Case Confirmation: Engineers check the generated test cases through the test case confirmation module. Test cases that fail the check are fed back to the large language model test case generation module along with modification suggestions, triggering iterative optimization. Step 5, Verification and Execution: The verification and execution module integrates the confirmed test cases into the FPGA verification environment, executes the test cases and analyzes the results, recording the Pass or Fail status of the test results; the closed-loop optimization module feeds the test results back to the large language model test case generation module, optimizes the prompt words through reinforcement learning, and the large language model iteratively generates more accurate test cases based on the optimized prompt words.

5. The FPGA test case automatic generation system based on a large language model according to claim 4, characterized in that: In step 1, the basic information related to FPGA design includes FPGA design requirements document, interface definition and verification target, and the key information marked by the engineer includes the input-output relationship of key modules, the types of defects to be eliminated, key module identifiers, interface signal identifiers and expected behavior identifiers.

6. The FPGA test case automatic generation system based on a large language model according to claim 4, characterized in that: In step 2, the hierarchical prompting strategy of the prompt word design unit designs corresponding prompt words for different test types. For functional testing, each functional module is broken down into independent test sub-functions, and the test direction is clearly defined for each sub-function. For performance testing, the prompt words include the specific requirements of performance indicators and test methods. For abnormal situation testing, the prompt words describe in detail various possible abnormal scenarios. The functional test scenarios in the basic scenario library cover various input-output combinations under normal functional operation, the boundary test scenarios mainly consider the boundary value of the input signal, and the abnormal situation test scenarios cover various situations that may cause FPGA malfunction.

7. The FPGA test case automatic generation system based on a large language model according to claim 4, characterized in that: In step 3, when generating test cases from the large language model, an external knowledge base such as FPGA design specifications and historical error cases is used to ensure that the generated test cases closely resemble actual hardware behavior. In terms of functional testing, the generated test cases comprehensively cover all functions of the FPGA, ensuring that each functional module is correctly verified under various normal and abnormal input conditions; in terms of performance testing, the test cases can accurately measure the performance indicators of the FPGA; in terms of abnormal scenario testing, the test cases can simulate various possible abnormal situations and detect whether the FPGA's response under these situations meets expectations.

8. The FPGA test case automatic generation system based on a large language model according to claim 4, characterized in that: In step 4, the engineer checks the test cases to ensure they cover the critical path of the design, identify any omissions of obvious boundary conditions, detect any logical contradictions, and verify compliance with FPGA syntax specifications. The suggested modifications include details of any uncovered critical path portions, types of omitted boundary conditions, and specific descriptions of any existing logical contradictions. The large language model test case generation module regenerates test cases based on these modifications until they meet the engineer's requirements. The engineer periodically summarizes review feedback, analyzes issues in the large language model generation, corrects them, and regenerates or updates the design description, thus forming an iterative optimization process.

9. The FPGA test case automatic generation system based on a large language model according to claim 4, characterized in that: In step 5, when the verification execution module integrates test cases into the FPGA verification environment, it ensures that the test cases can correctly interact with the FPGA design. When analyzing the test results, it determines whether the execution result of each test case meets expectations, accurately records the Pass or Fail status, and analyzes the reasons for failure in detail for failed test cases and synchronizes them to the closed-loop optimization module. The closed-loop optimization module feeds back the test results and reasons for failure to the large language model test case generation module. The large language model optimizes the prompt words in a targeted manner through reinforcement learning mechanism. The optimized prompt words are used to guide the generation of test cases in the next round. Through continuous iteration, the accuracy of the generated test cases is gradually improved, forming a continuously optimized closed-loop system.

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