Cache access control method and device

Abstract

The invention relates to the technical field of computers, and provides a cache access control method and device, and the method comprises the steps: determining hit information during cache access; and when the hit information is that the cache access competition fails and the tag is not hit, directly sending a cache access request of the target data to the next-level cache of the current cache. According to the embodiment of the invention, when the cache access competition fails and the tag is missed, the tag unit is directly accessed, the cache miss condition can be found in time, so that the request is sent to the next-level cache in time, and the pre-judgment processing remarkably shortens the response time of the miss condition.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a cache access control method and apparatus. Background Technology

[0002] In existing superscalar processor architectures, the Load-Store Unit (LSU) optimizes the execution efficiency of load / store instructions and cache access performance through various strategies. The main technical methods include:

[0003] (1) Cache allocation strategy

[0004] Write Allocation: When the target address of a storage operation does not hit the L1D cache (L1 DataCache), the system will first load the corresponding cache line from the lower storage level into the L1D cache before performing the write operation.

[0005] Read Allocation: When the target data of a load instruction does not hit the L1D cache, the system will automatically load the complete cache line containing the data from the lower storage level and then return the requested data to the processor core.

[0006] (2) Cache access channel management

[0007] Single-channel time-division multiplexing: Load, store operations, and fill and eviction operations of the lower-level cache share the same cache access channel, and the current access permissions are determined by an arbitration mechanism.

[0008] Dynamic priority adjustment: The system usually assigns higher priority to load instructions to improve execution efficiency, but under certain conditions (such as storage instruction backlog), the priority can be dynamically adjusted to avoid pipeline blockage.

[0009] (3) Cache addressing and access

[0010] Virtual Index Physical Tag (VIPT) technology: L1D cache uses virtual addresses for cache indexing, and combines the physical addresses translated by TLB / MMU for tag comparison to improve access parallelism.

[0011] Multi-level cache access: The system is configured with a multi-level cache system. When the upper-level cache is not hit, the system can initiate a lower-level storage access request, reducing waiting time.

[0012] (4) Optimization of cache organization structure

[0013] Multi-way group interconnection design: adopt a multi-way group interconnection structure (such as 4-way) to reduce the conflict rate and balance hardware overhead.

[0014] Cache bank partitioning: Dividing the cache into multiple banks supports parallel access by multiple instructions, thereby improving throughput.

[0015] Multi-label parallel access: Supports simultaneous label comparison for multiple instructions to meet the parallel execution requirements of superscalar processors.

[0016] However, the above strategy suffers from response latency issues in handling cache misses. When an instruction is aborted due to port contention, it must wait for rescheduling before a complete cache access process can begin. Only then, if a cache miss occurs, is the next-level cache access request triggered. This serialized processing method prolongs the response time for cache misses, increasing overall access latency. Summary of the Invention

[0017] This application provides a cache access control method and apparatus to solve the problem of response delay in the handling of cache misses in the prior art.

[0018] To address the aforementioned technical problems, this application provides a cache access control method, the method comprising:

[0019] Determine cache hit information during cache access;

[0020] When the hit information indicates that the cache access contention failed and the tag was not hit, the cache access request for the target data is directly sent to the next level cache of the current cache.

[0021] As a further embodiment of this application, the cache access control method further includes:

[0022] Optimize the cached memory using the following steps:

[0023] Based on the multi-way set-associative structure, all cache lines in the cache are divided into multiple cache groups;

[0024] The cache group is divided into multiple data blocks according to the specified bit index of the virtual address;

[0025] Based on a preset number of bytes, a single cache line is split into multiple sub-data segments;

[0026] The multi-path group interconnection structure is grouped according to the preset number of paths;

[0027] Based on the grouping of the multi-way group associative structure, the sub-data segments of the cache lines of the corresponding paths are integrated to obtain a storage body with optimized granularity.

[0028] In a further embodiment of this application, the preset number of bytes is 4, and the first and second paths in the multi-group associative structure are divided into a first group, and the third and fourth paths in the multi-group associative structure are divided into a second group.

[0029] In a further embodiment of this application, determining the cache hit information includes:

[0030] Send a tag access request for the target data to the tag unit; send a cache access request for the target data to the L1D cache;

[0031] Receive the tag access contention result sent by the tag unit and the cache access contention result sent by the L1D cache;

[0032] When the tag access contention result is successful and the cache access contention result is unsuccessful, a tag access confirmation message is sent to the tag unit;

[0033] Receive the tag hit result sent by the tag unit;

[0034] Based on the cache access contention results and tag hit results, the cache hit information is determined.

[0035] In a further embodiment of this application, after directly sending the cache access request for the target data to the next level cache of the current cache, the method further includes: canceling subsequent pipeline operations.

[0036] As a further embodiment of this application, the cache access control method further includes:

[0037] When a tag access request is first sent to the tag unit, key access information is recorded in real time; wherein, the key access information includes: route information;

[0038] During repeated accesses, cache access is performed based on the key access information.

[0039] In a further embodiment of this application, the real-time recording of key access information includes: recording the key access information in an instruction queue.

[0040] As a further embodiment of this application, the cache access control method further includes:

[0041] Critical access information in the instruction queue is cleared before a cache line is evicted to the L2 cache.

[0042] As a further embodiment of this application, it also includes:

[0043] When repeatedly accessing the cache, check whether the instruction queue records path information;

[0044] If path information exists, then storage conflict detection is performed using optimized granular storage.

[0045] If no path information exists, then storage conflict detection is performed using the original granularity of the storage.

[0046] As a further embodiment of this application, the cache access control method further includes:

[0047] If the path predictor predicts or matches path information, then based on the predicted or matched path information, memory conflict detection is performed using memory with optimized granularity.

[0048] As a further embodiment of this application, the cache access control method further includes:

[0049] When the cache access request is a load operation, the hit information is a successful cache access contention and a failed tag access contention, and the conflict operation of the load operation is a fill operation, the sub-storage in the tag unit that is not occupied by the fill operation is accessed. The tag storage in the tag unit is divided into multiple sub-storages according to the path information.

[0050] A second aspect of this application provides a cache access control device, comprising:

[0051] The determination unit is used to determine the cache hit information during cache access.

[0052] The access unit is used to directly send a cache access request for the target data to the next level cache of the current cache when the hit information indicates that the cache access contention has failed and the tag has not been hit.

[0053] In a further embodiment of this application, the cache access control device further includes:

[0054] The memory bank optimization unit performs the following operations:

[0055] Based on the multi-way set-associative structure, all cache lines in the cache are divided into multiple cache groups;

[0056] The cache group is divided into multiple data blocks according to the specified bit index of the virtual address;

[0057] Based on a preset number of bytes, a single cache line is split into multiple sub-data segments;

[0058] The multi-path group interconnection structure is grouped according to the preset number of paths;

[0059] Based on the grouping of the multi-way group associative structure, the sub-data segments of the cache lines of the corresponding paths are integrated to obtain a storage body with optimized granularity.

[0060] The cache access method and apparatus provided in this application can directly access the tag unit when cache access contention fails or tag contention succeeds, which can promptly detect cache misses and send requests to the next level cache in a timely manner. This predictive processing significantly shortens the response time for misses.

[0061] To make the above and other objects, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 The flowchart illustrates the cache access process when the existing load instruction cache is not hit.

[0064] Figure 2 A flowchart of a cache access control method according to an embodiment of this application is shown;

[0065] Figure 3 A detailed flowchart of the cache access control method according to an embodiment of this application is shown;

[0066] Figure 4 A flowchart of a cache body optimization method in an embodiment of this application is shown;

[0067] Figure 5A This diagram illustrates the cache body partitioning in the existing cache.

[0068] Figure 5B This illustration shows a schematic diagram of cache body partitioning in an embodiment of this application;

[0069] Figure 6A This diagram illustrates the buffer access process in an existing cache.

[0070] Figure 6B This illustration shows a schematic diagram of the buffer access process in the cache according to an embodiment of this application;

[0071] Figure 7 Another flowchart of the cache access control method according to an embodiment of this application is shown;

[0072] Figure 8A A flowchart of a cached repeated access process in the prior art is shown;

[0073] Figure 8B A flowchart illustrating the cache re-access process according to an embodiment of this application is shown;

[0074] Figure 9 Another flowchart of the cache access control method according to an embodiment of this application is shown;

[0075] Figure 10A A flowchart of the prior art conflict access process is shown;

[0076] Figure 10B A flowchart illustrating the conflict access process according to an embodiment of this application is shown;

[0077] Figure 11 This illustration shows a schematic diagram of the path division in the tag storage of a tag unit according to an embodiment of this application;

[0078] Figure 12A A structural diagram of a cache access control device according to an embodiment of this application is shown;

[0079] Figure 12B A structural diagram of a cache access control device according to an embodiment of this application is shown;

[0080] Figure 13 A structural diagram of a computer device according to an embodiment of this application is shown.

[0081] Explanation of symbols in the attached drawings:

[0082] 1201. Determine the unit;

[0083] 1202, Access Unit;

[0084] 1203. Memory Optimization Unit;

[0085] 1302. Computer equipment;

[0086] 1304, Processor;

[0087] 1306. Memory;

[0088] 1308. Drive mechanism;

[0089] 1310. Input / output module;

[0090] 1312. Input devices;

[0091] 1314. Output devices;

[0092] 1316. Presentation equipment;

[0093] 1318. Graphical User Interface;

[0094] 1320. Network interface;

[0095] 1322. Communication link;

[0096] 1324. Communication bus. Detailed Implementation

[0097] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0098] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0099] This specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel.

[0100] To more clearly illustrate the technical solution of this application, the technical terms used are explained below:

[0101] (1) Load-Store Unit (LSU)

[0102] The LSU is a functional module in the central processing unit that is dedicated to executing memory access instructions. It includes: an address generation circuit, configured to calculate valid memory addresses; an access control logic unit, which implements hardware-level memory access permission checks; and a cache interface controller, which manages the data transfer protocol between the L1 data cache and the memory subsystem.

[0103] LSU accurately identifies the type of load / store operation (including data formats such as byte / word / vector) through instruction decoding, and performs complex address calculations including base address, index, and offset. While completing the virtual-to-physical address translation, it works in conjunction with the L1 cache (L1D) to achieve efficient data read and write.

[0104] (2) Level 1 Data Cache (L1D), i.e., L1 cache

[0105] The L1 cache is the cache layer closest to the processor core, used to store the most frequently used data and instructions, implementing data buffering between the processor core and the memory subsystem. It is typically small but extremely fast. The capacity of the L1 cache is generally between tens of KB and hundreds of KB; for example, some modern processors have an L1 cache capacity of 32KB or 64KB. Due to its proximity to the processor core, access latency is extremely low, typically around one clock cycle. The L1 cache uses a Virtual Indexed Physical Tag (VIPT) addressing mechanism and is organized in a multi-way set-associative structure, with 4-way or 8-way being the preferred implementation. The cache line size is preferably 64 bytes.

[0106] (3) Second-level cache (L2 Cache, L2)

[0107] The L2 cache, located between the L1 cache and main memory, stores more data and instructions, providing more backup in case of L1 cache misses. When the processor needs data or instructions that are not in the L1 cache, it will first look in the L2 cache. The size of the L2 cache typically ranges from several hundred KB to several MB; for example, common L2 cache sizes are 256 KB or 512 KB. The access latency of the L2 cache is generally around a few clock cycles, slightly higher than that of the L1 cache.

[0108] (4) Level 3 Cache (L3)

[0109] The L3 cache is a shared cache located between processor cores, allowing multiple cores to share the same L3 cache. This helps reduce data transfer latency between cores, providing fast data sharing when multiple cores need to access the same data. The capacity of the L3 cache typically ranges from a few MB to tens of MB; for example, common L3 cache capacities are 8 MB or 16 MB. The access latency of the L3 cache is generally around ten clock cycles, slower than L1 and L2 caches, but still much faster than main memory. The Level 1 data cache (L1D Cache), as the first-level high-speed data buffer between the processor and the memory subsystem, directly determines the overall throughput efficiency of the instruction pipeline due to its access latency.

[0110] (5) Virtual Index Physical Tag (VIPT) Addressing Mechanism

[0111] VIPT addressing mechanism is a cached addressing method, including:

[0112] a. Indexing phase: Using partial bits of the virtual address to index the cache group;

[0113] b. Tag matching stage: The high-order bits of the physical address after MMU conversion are used as the tag;

[0114] c. Parallel processing stage: TLB queries and cache accesses are executed in parallel pipelines.

[0115] (6) Cache management operations

[0116] An eviction operation is defined as the process of selecting a target cache line according to a replacement policy and writing its contents back to the next lower level of memory.

[0117] The fill operation is defined as the process of loading data from the lower-level memory into a specified L1D cache line by filling the buffer.

[0118] A fill buffer is a temporary storage device specifically designed to handle data transfer when a cache miss occurs.

[0119] (7) Memory Management Unit (MMU)

[0120] Address translation device, including:

[0121] Multi-level page table traversal engine;

[0122] The Transfer Bypass Cache (TLB) stores the mapping between virtual page numbers and physical page frames;

[0123] Address Space Identifier (ASID) management circuitry.

[0124] (8) Loading instruction processing system

[0125] The load instruction processing system includes:

[0126] Load Queue (LQ): A storage structure that stores load instructions that failed to execute successfully;

[0127] Way predictor: A prediction unit that records historical access paths and stores the path information of the most recent N visits;

[0128] Load replay mechanism: When arbitration failure or cache miss is detected, the instruction is re-added to the control logic of the execution pipeline.

[0129] (9) Cache consistency management

[0130] Cache coherence management is used in multi-core processor systems, including:

[0131] A consensus protocol based on bus snooping;

[0132] Employ MESI or a variant of the cache state maintenance mechanism;

[0133] Enables real-time monitoring and updating of cache status between cores.

[0134] (10) Multi-way group interconnection structure

[0135] The multi-way set-associative architecture is a storage device organization structure characterized by: a configurable number of groups, preferably ranging from 64 to 256 groups; each group containing a fixed number of storage paths; and the use of a pseudo-LRU replacement algorithm to manage cache lines.

[0136] The existing LSU cache access strategy suffers from response latency issues in handling cache misses. When an instruction is aborted due to port contention, it must wait for rescheduling before the complete cache access process can begin. Only if a cache miss occurs during this period will the next-level cache access request be triggered. This serialized processing method prolongs the response time for cache misses, increasing the overall access latency.

[0137] Specifically, such as Figure 1 As shown, consider a scenario where a load instruction experiences a cache miss. When a load instruction conflicts with another operation in the cache bank, even if the contention for accessing the tag's port is successful (e.g., ...), the cache miss will still occur. Figure 1 In steps 101 to 104, the tag unit will not be accessed; instead, subsequent process operations will be directly cancelled (e.g., ...). Figure 1 (Step 105) Wait for re-execution. During re-execution, the competition process will be repeated until the tag and cache are successfully acquired, and then the next step will be executed.

[0138] To solve the above technical problems, such as Figure 2 As shown, this application provides a cache access control method, including:

[0139] Step 201: Determine the cache hit information during cache access;

[0140] Step 202: When the hit information is that the cache access contention failed and the tag was not hit, the cache access request for the target data is sent directly to the next level cache of the current cache.

[0141] In some real-time methods, such as Figure 3 As shown, the specific execution process of the cache access control method includes:

[0142] Step 301: Send the target data tag (TAG) access request to the tag unit TAG.

[0143] Step 302: Send a cache access request for the target data to the L1D cache.

[0144] Step 303: Receive the TAG access contention result sent by the tag unit.

[0145] Step 304: Receive the CACHE access contention result sent by L1D cache.

[0146] Step 305: When the tag access contention result is successful and the cache access contention result is unsuccessful, send TAG access confirmation information to the tag unit TAG.

[0147] Step 306: Receive the tag hit result sent by the tag unit TAG.

[0148] Step 307: When the TAG hit result is TAG miss, send a cache access request for the target data to the L2 cache.

[0149] Step 308: Cancel subsequent operations in the pipeline.

[0150] Step 309: The L2 cache returns L2 data to the L2 cache, waking up the LSU to re-access the tag unit (TAG) and L1D cache.

[0151] Steps 310 to 316 are the process of re-accessing the tag unit TAG and L1D cache to obtain data.

[0152] In this embodiment, when cache access contention fails or tag contention succeeds, the tag unit is accessed directly, which can promptly detect cache misses and send requests to the next level cache in a timely manner. This predictive processing significantly shortens the response time for misses.

[0153] In existing technologies, cache bodies only support single-port access, leading to conflicts when multiple instructions access the same memory bank simultaneously. More importantly, existing technologies divide cache bodies into fixed-size blocks, which cannot adapt to the memory access characteristics of different application scenarios. When data access patterns exhibit locality of reference, this significantly increases the probability of memory conflicts, hindering the realization of instruction-level parallelism.

[0154] To address the issue of insufficient access parallelism in cache memory partitioning schemes, one embodiment of this application provides, as follows: Figure 4 As shown, the cache body partitioning method in the cache is optimized through the following operations:

[0155] Step 401: Based on the multi-way set-associative structure, divide all cache lines in the cache into multiple cache groups.

[0156] Step 402: Divide the cache group into multiple data blocks according to the specified bit index of the virtual address.

[0157] Step 403: Split a single cache line into multiple sub-data segments according to a preset number of bytes.

[0158] When implementing this step, a single cache entry can be split into multiple sub-data segments of the same byte size using a uniform preset byte count, or into multiple sub-data segments of different byte sizes using different preset word counts. For example, a preset byte count of 4 bytes or 8 bytes can be selected.

[0159] Step 404: Group the multi-way interconnected structure according to the preset number of paths.

[0160] During this step, dynamic path grouping can be used to group the multi-path grouped structure, meaning that each group can contain the same or different numbers of paths. Alternatively, the multi-path grouped structure can be grouped based on access frequency. Or, a probabilistic approach with weighted factors can be used to group the multi-path grouped structure.

[0161] Step 405: Based on the grouping of the multi-way group associative structure, integrate the sub-data segments of the cache lines of the corresponding paths to obtain a storage body with optimized granularity.

[0162] This embodiment employs a two-level optimization: the first level reduces the data width of a single memory bank; the second level allocates each path in the multi-way set-associative structure to different memory bank groups. This embodiment reduces the granularity of memory banks and increases the number of memory banks through a refined cache memory bank partitioning strategy, while employing an innovative multi-way grouping method to enable caches of the same capacity to support higher parallelism access.

[0163] In one specific implementation, the preset number of bytes is 4. The first and second paths in the multi-group associative structure are divided into a first group, and the third and fourth paths in the multi-group associative structure are divided into a second group.

[0164] Taking a 64KB cache as an example, assuming each cache line is 64 bytes, there are a total of 1024 cache lines. When the cache is 4-way set-associative, these 1024 cache lines can be divided into 256 sets.

[0165] In the traditional partitioning, each 8 bytes is a bank, so a cache line can be divided into 8 banks. Then, using VA[6] as the index, the 256 set is divided into two blocks. This results in a total of 16 banks, each containing 8 bytes of the 128 cache lines. The specific structure is as follows: Figure 5A As shown.

[0166] The memory bank is optimized in the manner described in this embodiment as follows:

[0167] Level 1 optimization: Halve the storage granularity to 4 bytes and increase the number of storage banks to 32. Specifically, as follows... Figure 5B As shown.

[0168] Due to register size limitations, scaler load instructions can be a maximum of 8 bytes, so load instructions smaller than 8 bytes are common. Using 8 bytes as the storage granularity is a relatively coarse-grained approach. Consider a 4-byte load instruction; although it only occupies half the width of the original storage block, it occupies the entire block. Therefore, we can consider finer-graining the storage granularity, dividing it into 4-byte blocks, thus doubling the number of storage blocks. Using the 4-byte load instruction as an example, it now occupies one storage block, but the other 4 bytes can be freed up for other operations.

[0169] Second-level optimization: Combining the multi-way group associativity feature, the number of memory banks is doubled to 64 through way grouping.

[0170] Building upon the first level of optimization, the memory bank can be further partitioned. Since different paths corresponding to the same set are distributed across the same memory bank, simultaneous reads and writes to different paths within the same set can cause conflicts. Therefore, the paths in a multi-path grouped associative structure can be considered for further partitioning of the memory bank. For example, paths 0 / 1 can be combined, and paths 2 / 3 can be combined, dividing the memory bank into two blocks using paths. The specific structure is as follows: Figure 5B As shown, the entire cache storage is divided into 64 blocks, reducing the frequency of collisions.

[0171] like Figure 6A As shown, suppose two load instructions, originally located on the same memory bank, conflict with the cache. The successfully competing load instruction, Load A, can execute smoothly, while the unsuccessful load instruction, Load B, not only wastes one clock cycle of pipeline entry but also requires another clock cycle to cancel the pipeline operation. Even if it immediately wins the opportunity to pipeline, it is still at least two clock cycles slower than Load A and requires four clock cycles to access the cache. When Load B and Load A conflict with each other, Load B can obtain data in at least six clock cycles.

[0172] like Figure 6B As shown, after increasing the number of memory modules according to the technical solution of this application, Load B and Load A no longer conflict, and both instructions can be executed smoothly. Load B and Load A can obtain data in as little as 4 clock cycles.

[0173] Existing solutions lack effective optimization for repeated access scenarios, especially when instructions need to be replayed. The entire cache access process, including redundant tag comparison operations, still needs to be repeated. This design not only increases unnecessary power consumption but also further intensifies contention for cache access ports.

[0174] To solve the above technical problems, such as Figure 7 As shown, the cache access control method also includes:

[0175] Step 701: When sending the cache access request to the cache for the first time, record the key access information in real time; the key access information includes route information.

[0176] In some implementations, key access information is recorded in real time, including recording the key access information in an instruction queue. In other implementations, the key access information may be recorded in other units outside the instruction queue, or stored using compressed encoding.

[0177] Step 702: When repeatedly accessing the cache, perform cache access based on key access information.

[0178] This embodiment records key access information to the instruction queue upon initial execution. During replay, it utilizes the recorded path information for fast access. This mechanism effectively avoids repeated tag comparison operations, reducing both power consumption and access conflicts. The technical principle of this embodiment is illustrated below with a specific example:

[0179] like Figure 8A As shown, if a loading instruction successfully accesses a tag, but is canceled due to outdated data in the cache or other reasons, it will still need to compete for the tag access port upon re-execution. Failure to compete for the tag port will result in cancellation, and the process will continue to wait for re-execution. Specifically:

[0180] like Figure 8A In steps 1 to 9, when a load instruction has already accessed the tag unit (TAG) in the pipeline for accessing the tag unit (TAG) and the cache, and is canceled for some reason, it will be placed in the instruction queue (LQ) to wait for scheduling to retry.

[0181] like Figure 8AIn steps 1 to 5 of the second group and steps 1 to 8 of the third group, when the load instruction is executed again, it will continue to participate in tag contention, but this is actually unnecessary. This is because after the tag unit (TAG) has been accessed, there are two access results: one is a tag hit, where the corresponding cached path information can be found in the tag unit (TAG); the other is a tag miss, in which case the L1D cache does not contain the cache line corresponding to the load instruction, and the corresponding cache line needs to be filled into the L1D from the lower-level cache (or memory). When the cache line is returned, the loaded instruction will be woken up from the instruction queue.

[0182] In this application, when the tag unit is accessed for the first time, key access information is recorded in the instruction queue LQ. For subsequent accesses, the tag unit does not need to be accessed again. Figure 8B As shown.

[0183] In both tag-hit and tag-miss scenarios, load instructions do not need to look up tags during replay. When a tag hits, the found path information is directly recorded in the instruction queue, ready for use during re-execution without repeatedly accessing the tag unit. When a tag misses, two scenarios occur: First, when data returns to the LSU, load instructions in the instruction queue are prematurely awakened for execution. Although L1D has not yet allocated a path to the cache line returned from L2 (and has not yet filled L1D), this load instruction does not need to access the cache and can forward data directly from the pipeline. Second, when data returns from L2, due to a window period, load instructions in the instruction queue are not prematurely awakened, but will eventually be awakened when the cache is filled. In this case, data cannot be forwarded, but path information is known. When L1D allocates a path to the cache line, the path information is updated in the instruction queue, and the re-access of the load instruction does not require repeated access to the tag unit. Thus, regardless of the scenario, there is no need for tag port contention when this load instruction is re-executed.

[0184] In practice, once route information is recorded in the instruction queue, it is necessary to respond to cache eviction or cache snooping. Before a cache line is evicted to the L2 cache, the corresponding route information in the instruction queue must be cleared to prevent incorrect access to the cache line.

[0185] In one embodiment of this application, as Figure 9 As shown, the cache access control method also includes:

[0186] Step 901: When repeatedly accessing the cache, determine whether the instruction queue records path information.

[0187] Step 902: If path information exists, then perform memory conflict detection using optimized granularity memory. Optimized granularity memory includes, for example: Figure 5B As shown.

[0188] Specifically, if no conflict is detected in the storage conflict detection, the process is executed immediately; if a conflict exists, the process waits for a retry.

[0189] Step 903: If no path information exists, perform memory conflict detection using the original granularity of the memory. The original granularity of the memory is as follows: Figure 5A As shown.

[0190] Specifically, if no conflict is detected in the storage conflict detection, the process is executed immediately; if a conflict exists, the process waits for a retry.

[0191] Step 904: If the path predictor predicts or matches path information, then based on the predicted or matched path information, use the optimized granularity of the storage to perform storage conflict detection.

[0192] Specifically, if no conflict is detected in the storage conflict detection, the process is executed immediately; if a conflict exists, the process waits for a retry.

[0193] The technical principles are illustrated below through exemplary embodiments:

[0194] Continuing with the previous specific implementation, after dividing the cache storage, there are a total of 64 storage banks. In the microarchitecture, since load and store instructions cannot know which path in the cache they will be on before execution, path information cannot be used for arbitration. Therefore, although there are 64 storage banks, they are effectively only used as 32. In the previous optimization, because the path information of load instructions that have already accessed the tag unit is recorded in the instruction queue, the path information can be used for further arbitration during repeated accesses. The path information for each operation requiring bank conflict resolution is as follows:

[0195] Fill operation: Road information is known;

[0196] Evict operation: Road information is known;

[0197] Loading operation for issue: Road information unknown;

[0198] Loading operations for replay access: The path information is known (the load of forward data that can be returned from L2 does not need to participate in arbitration);

[0199] Store address portion (instruction): Road information unknown;

[0200] Store data section (data): Road information is known;

[0201] The presence of a way predictor in the microarchitecture means that when a load operation is executed and there is no actual way information during cache storage port contention, a portion of the loads will have a predicted way information because they hit the way predictor.

[0202] Therefore, when arbitrating cache storage, operations with path information can use the path information for storage arbitration, while operations without path information are treated as occupying 4 paths for arbitration.

[0203] In one embodiment of this application, the tag unit has multiple ports, such as three ports, through which the tag unit can be accessed independently. Additionally, each port has two storage banks (bank0 and bank1), and each storage bank includes information channels 0, 1, 2, and 3.

[0204] In practice, each port is contested by different operations, such as Fill, Evict (including evictions caused by cache replacement and eviction requests generated by cache policing), Store, and Load operations. Operations on any number of ports can be executed in parallel, and source operations on different ports do not affect each other and can be executed simultaneously. Even within the same port, if two operations access different memory banks, they can still be executed concurrently.

[0205] Although padding or eviction carries path information, loading operations do not. Therefore, in actual arbitration, the arbitration focuses on whether the two operations access the same memory bank, without adding path information. In the prior art, if a loading operation and a padding operation conflict during tag cell access, the corresponding flowchart is as follows: Figure 10A As shown, when tag access contention fails and cache access contention succeeds, the subsequent pipeline operations are canceled and the process waits for retry scheduling. During retry scheduling, tag and cache contention is re-initiated.

[0206] Since load operations are speculatively executed and are sensitive to latency, it's advisable to consider the following approach during tag port contention: if a load instruction fails to compete for a storage space, but the load instruction only conflicts with the padding or eviction operations, the load instruction should attempt to access a storage space belonging to a different set of path information, excluding the tag storage space occupied by the padding instruction. If the tag is hit when accessing the other two paths, execution can continue in the pipeline; if the tag is not hit, a request cannot be directly sent to the next-level cache, and the tag must be accessed again.

[0207] Specifically, the tag storage in the tag unit with multiple ports is divided into multiple sub-storages according to the route information. Figure 11 The system includes three ports, and Way01 and Way23 are sub-memory blocks in each memory bank of each port.

[0208] like Figure 10B As shown, when the cache access request is a loading operation, the hit information is that the cache access contention is successful and the tag access contention is unsuccessful, and the conflict operation of the loading operation is a filling operation, the sub-storage that is not occupied by the filling operation in the tag unit is accessed. The tag storage in the tag unit is divided into multiple sub-storages according to the path information.

[0209] This embodiment analyzes the characteristics of different types of access operations (Load, Fill) in detail, enabling a parallel execution mechanism for load and fill operations. Through a refined arbitration mechanism aided by path information, the system can make fuller use of cache access bandwidth.

[0210] The cache access control method provided in this application can achieve the following technical effects:

[0211] (1) Significantly improves cache access parallelism

[0212] Through an innovative multi-level storage partitioning mechanism, traditional cache access resources are refined into more independent units. An intelligent arbitration strategy based on access path information is employed to achieve parallel execution of different operation types.

[0213] (2) Effectively reduce the delay of critical operations

[0214] Speculative execution mechanisms allow latency-sensitive Load instructions to avoid regular access conflicts. Predictive miss handling triggers lower-level cache access requests in advance.

[0215] (3) Significantly reduce power consumption overhead

[0216] Avoid duplicate label comparison operations and reduce redundant execution caused by conflicts.

[0217] (4) Enhance the overall performance of the system

[0218] The number of pipeline bubble cycles is reduced, and instruction-level parallelism is significantly improved.

[0219] (5) Improve architectural scalability

[0220] The modular design supports configurations of different sizes, and the parameterized implementation adapts to various processor architectures.

[0221] (6) Wide range of application adaptability

[0222] It supports multiple modern processor architectures, is compatible with different cache hierarchies, and adapts to various computing scenarios from mobile devices to data centers.

[0223] This technical solution achieves a comprehensive improvement in cache access efficiency while maintaining system correctness through innovative cache organization design, intelligent access arbitration strategy, and efficient speculative execution mechanism. These optimization measures work together to address the high-concurrency access challenges faced by modern processors, providing key technical support for next-generation high-performance computing architectures.

[0224] Based on the same inventive concept, this application also provides a cache access control device, as described in the following embodiments. Since the principle by which the cache access control device solves the problem is similar to that of the cache access control method, the implementation of the cache access control device can refer to the cache access control method, and repeated details will not be elaborated further.

[0225] Specifically, such as Figure 12A As shown, the cache access control device includes:

[0226] The determining unit 1201 is used to determine the hit information during cache access;

[0227] Access unit 1202 is used to directly send a cache access request for the target data to the next level cache of the current cache when the hit information is that the cache access contention failed and the tag was not hit.

[0228] In this embodiment, when cache access contention fails or tag contention succeeds, the tag unit is accessed directly, which can promptly detect cache misses and send requests to the next level cache in a timely manner. This predictive processing significantly shortens the response time for misses.

[0229] In one embodiment of this application, as Figure 12B As shown, the cache access control device also includes:

[0230] The memory optimization unit 1203 is used to perform the following operations:

[0231] Based on the multi-way set-associative structure, all cache lines in the cache are divided into multiple cache groups;

[0232] The cache group is divided into multiple data blocks according to the specified bit index of the virtual address;

[0233] Based on a preset number of bytes, a single cache line is split into multiple sub-data segments;

[0234] The multi-path group interconnection structure is grouped according to the preset number of paths;

[0235] Based on the grouping of the multi-way group associative structure, the sub-data segments of the cache lines of the corresponding paths are integrated to obtain a storage body with optimized granularity.

[0236] This embodiment employs a two-level optimization: the first level reduces the data width of a single memory bank; the second level allocates each Way in the multi-way set-associative structure to different memory bank groups. This embodiment reduces the granularity of memory banks and increases the number of memory banks through a refined cache memory bank partitioning strategy, while employing an innovative multi-way grouping method to enable caches of the same capacity to support higher parallelism access.

[0237] In one embodiment of this application, a computer device is also provided, such as... Figure 13 As shown, computer device 1302 includes the LSU, L1 cache, and L2 cache described above. Computer device 1302 also includes one or more processors 1304, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. Computer device 1302 may also include any memory 1306 for storing information of any kind, such as code, settings, data, etc. Non-limitingly, for example, memory 1306 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Furthermore, any memory can provide volatile or non-volatile retention of information. Furthermore, any memory can represent a fixed or removable component of computer device 1302. In one case, when processor 1304 executes associated instructions stored in any memory or combination of memories, computer device 1302 can perform any operation of the associated instructions. The computer device 1302 also includes one or more drive mechanisms 1308 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0238] Computer device 1302 may also include an input / output module 1310 (I / O) for receiving various inputs (via input device 1312) and providing various outputs (via output device 1314). A specific output mechanism may include a presentation device 1316 and an associated graphical user interface (GUI) 1318. In other embodiments, the input / output module 1310 (I / O), input device 1312, and output device 1314 may be omitted, and the device may function solely as a computer device within a network. Computer device 1302 may also include one or more network interfaces 1320 for exchanging data with other devices via one or more communication links 1322. One or more communication buses 1324 couple the components described above together.

[0239] Communication link 1322 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1322 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0240] This application also provides a computer-readable storage medium, such as a non-transient computer-readable storage medium, on which a computer program is stored, and which, when run by a processor, performs the steps of the above-described method.

[0241] This application also provides a computer-readable instruction, wherein when a processor executes the instruction, the program therein causes the processor to perform the steps of the above-described method.

[0242] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0243] It should also be understood that, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship.

[0244] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0245] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0246] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, apparatuses, or units, or they may be electrical, mechanical, or other forms of connection.

[0247] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0248] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0249] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0250] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A cache access control method, characterized in that, The method includes: Determine cache hit information during cache access; When the hit information indicates that the cache access contention failed and the tag was not hit, the cache access request for the target data is directly sent to the next level cache of the current cache.

2. The method as described in claim 1, characterized in that, Also includes: Optimize the cached memory using the following steps: Based on the multi-way set-associative structure, all cache lines in the cache are divided into multiple cache groups; The cache group is divided into multiple data blocks according to the specified bit index of the virtual address; Based on a preset number of bytes, a single cache line is split into multiple sub-data segments; The multi-path group interconnection structure is grouped according to the preset number of paths; Based on the grouping of the multi-way group associative structure, the sub-data segments of the cache lines of the corresponding paths are integrated to obtain a storage body with optimized granularity.

3. The method as described in claim 2, characterized in that, The preset number of bytes is 4. The first and second paths in the multi-group associative structure are divided into the first group, and the third and fourth paths in the multi-group associative structure are divided into the second group.

4. The method as described in claim 2, characterized in that, Determine cache hit information, including: Send a tag access request for the target data to the tag unit; Send a cache access request for the target data to the L1D cache; Receive the tag access contention result sent by the tag unit and the cache access contention result sent by the L1D cache; When the tag access contention result is successful and the cache access contention result is unsuccessful, a tag access confirmation message is sent to the tag unit; Receive the tag hit result sent by the tag unit; Based on the cache access contention results and tag hit results, the cache hit information is determined.

5. The method as described in claim 3, characterized in that, After sending the cache access request for the target data directly to the next level cache of the current cache, it also includes: canceling subsequent pipeline operations.

6. The method as described in claim 3, characterized in that, Also includes: When a tag access request is first sent to the tag unit, key access information is recorded in real time; wherein, the key access information includes: route information; During repeated accesses, cache access is performed based on the key access information.

7. The method as described in claim 6, characterized in that, The real-time recording of key access information includes: recording the key access information in an instruction queue.

8. The method as described in claim 7, characterized in that, Also includes: Critical access information in the instruction queue is cleared before a cache line is evicted to the L2 cache.

9. The method as described in claim 7, characterized in that, Also includes: When repeatedly accessing the cache, check whether the instruction queue records path information; If path information exists, then storage conflict detection is performed using optimized granular storage. If no path information exists, then storage conflict detection is performed using the original granularity of the storage.

10. The method as described in claim 9, characterized in that, Also includes: If the path predictor predicts or matches path information, then based on the predicted or matched path information, memory conflict detection is performed using memory with optimized granularity.

11. The method as described in claim 4, characterized in that, Also includes: When the cache access request is a load operation, the hit information is a successful cache access contention and a failed tag access contention, and the conflict operation of the load operation is a fill operation, the sub-storage in the tag unit that is not occupied by the fill operation is accessed. The tag storage in the tag unit is divided into multiple sub-storages according to the path information.

12. A cache access control device, characterized in that, include: The determination unit is used to determine the cache hit information during cache access. The access unit is used to directly send a cache access request for the target data to the next level cache of the current cache when the hit information indicates that the cache access contention has failed and the tag has not been hit.

13. The apparatus as claimed in claim 12, characterized in that, Also includes: The memory bank optimization unit performs the following operations: Based on the multi-way set-associative structure, all cache lines in the cache are divided into multiple cache groups; The cache group is divided into multiple data blocks according to the specified bit index of the virtual address; Based on a preset number of bytes, a single cache line is split into multiple sub-data segments; The multi-path group interconnection structure is grouped according to the preset number of paths; Based on the grouping of the multi-way group associative structure, the sub-data segments of the cache lines of the corresponding paths are integrated to obtain a storage body with optimized granularity.

14. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor of a computer device, it implements the method according to any one of claims 1 to 11.

15. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by the processor of a computer device, it implements the method according to any one of claims 1 to 11.

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