Flash memory controller, solid state disk controller and electronic equipment

Abstract

The invention discloses a flash memory controller, a solid state disk controller and electronic equipment, and belongs to the technical field of storage. The flash memory controller comprises a queue manager and a flash memory processor; the queue manager is coupled with the flash memory processor; the queue manager is used for managing a command queue aiming at a flash memory crystal grain, the command queue comprises a flash memory operation command to be executed, and the flash memory operation command comprises at least one of a cache reading command and a cache programming command; and the flash memory processor is used for executing the flash memory operation command.

Description

Technical Field

[0001] This application belongs to the field of storage technology, specifically relating to a flash memory controller, a solid-state drive controller, and an electronic device. Background Technology

[0002] Cache Read / Cache Program commands are high-efficiency commands for flash memory, designed to improve data bandwidth by hiding the latency between command and address loading through pipelined operations. However, the "prefetching" and "delayed acknowledgment" characteristics of Cache Read / Cache Program commands break the traditional simple paradigm of "send command - wait for completion - process result," introducing cross-dependencies between operations.

[0003] In related technologies, these cross-operations are managed and scheduled entirely by the firmware (FW) in software, breaking down a cached command into multiple discrete, highly dependent small-granular units and being responsible for their synchronization.

[0004] However, this method of having firmware handle caching commands in related technologies results in firmware code filled with complex conditional checks, making it difficult to guarantee correct synchronization under all boundary conditions and posing a reliability risk. Summary of the Invention

[0005] This application provides a flash memory controller, a solid-state drive controller, and an electronic device that can solve the reliability risk problem of firmware-based caching commands in related technologies.

[0006] In a first aspect, embodiments of this application provide a flash memory controller, including: a queue manager and a flash memory processor; the queue manager is coupled to the flash memory processor; The queue manager is used to manage a command queue for flash memory dies, the command queue containing flash memory operation commands to be executed, the flash memory operation commands including at least one of cache read commands and cache program commands; The flash memory processor is used to execute the flash memory operation commands.

[0007] Secondly, embodiments of this application provide a solid-state drive controller, including the flash memory controller as described in the first aspect.

[0008] Thirdly, embodiments of this application provide an electronic device, including a central processing unit and a solid-state drive controller as described in the second aspect.

[0009] In this embodiment, a queue manager in the flash memory controller manages the command queue for the flash memory chip, and a flash memory processor in the flash memory controller executes at least one of cache read commands and cache program commands. Thus, cache commands can be implemented through the hardware of the flash memory controller. Since the reliability of hardware-implemented cache commands is much higher than that of complex firmware, this embodiment reduces the data risk caused by firmware logic errors, improves the reliability when processing cache commands, and solves the reliability risk problem of firmware-based cache command implementation in related technologies. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an SSD controller; Figure 2 This is a schematic diagram of a flash memory controller provided in an embodiment of this application; Figure 3 This is a schematic diagram of another hard disk controller provided in an embodiment of this application; Figure 4 This is a schematic diagram of the automated cache reading workflow provided in the embodiments of this application; Figure 5-1 This is a schematic diagram illustrating the process by which the queue manager submits commands to the scheduling unit; Figure 5-2 This is a schematic diagram illustrating the implementation process of cache read commands.

[0011] Figure 6 This is a schematic diagram of the cache programming automation workflow provided in the embodiments of this application; Figure 7-1 This is a schematic diagram illustrating the process by which the queue manager submits commands to the scheduling unit; Figure 7-2 This is a schematic diagram illustrating the implementation process of caching programming commands; Figure 8 This is a structural block diagram of an SSD controller provided in an embodiment of this application; Figure 9 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0015] First, the following combination Figure 1 A brief introduction to solid state drive (SSD) controllers. Figure 1 This is a schematic diagram of an SSD controller. The SSD controller, for example, is a System-on-Chip (SOC). Figure 1 As shown, the SSD controller includes a host interface module, a flash translation layer (FTL) processing module, and a flash controller, such as a NAND flash controller. The host interface module acts as a bridge between the flash controller and the host (e.g., a computer, mobile phone, or other electronic device), adapting to different host interface standards such as Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), and Universal Serial Bus (USB). Through specific hardware circuits and software protocol stacks, efficient data transmission and command interaction between the host and the flash controller are achieved, ensuring the host can successfully read and write data stored in the flash memory.

[0016] NAND flash memory has complex physical address management and a limited write / erase lifespan. The FTL (Flash Memory Transfer) module can translate simple logical addresses provided by the host into actual physical addresses in the flash memory. Simultaneously, the FTL module can execute wear leveling strategies to prevent premature damage to some storage blocks due to overuse; it can perform garbage collection to clean up invalid data and free up space; and it can manage metadata, recording critical information such as address mappings. The FTL module is used to manage and plan the use of flash memory, extending its lifespan and improving performance. It should be understood that in this embodiment, the SSD controller may include a central processing unit (CPU), and the FTL module may be integrated within the CPU of the SSD controller as part of the CPU. The host interface module may also be a hardware-based host interface controller.

[0017] The flash memory controller can perform operations on the flash memory (e.g., according to the specific electrical characteristics and instruction set of NAND flash memory) according to the specific electrical characteristics and instruction set of the flash memory. Figure 1 The flash memory controller performs basic operations such as reading, writing, and erasing of NAND flash memory. It features robust error correction code (ECC) functionality in hardware, enabling the detection and correction of errors during data transmission and storage. Through multi-channel control, it allows for concurrent operation of multiple flash memory chips, improving overall read and write speeds. The flash memory controller precisely and systematically directs these operations, ensuring reliable data storage and retrieval.

[0018] The flash memory controller provided in this application embodiment is used in the control technology of storage devices, such as the SSD controller described above.

[0019] The flash memory controller provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0020] For reference Figure 2 , Figure 2 This is a schematic diagram of a flash memory controller provided in an embodiment of this application. For example... Figure 2 As shown, the flash memory controller 200 includes a queue manager (QM) 210 and a flash memory processor 220; the queue manager 210 is coupled to the flash memory processor 220. The queue manager 210 is used to manage a command queue for flash memory dies, the command queue containing flash memory operation commands to be executed, the flash memory operation commands including at least one of cache read commands and cache program commands; The flash memory processor 220 is used to execute the flash memory operation commands.

[0021] In this embodiment, the flash memory processor 220 can be a single-core processor or a customized dedicated processor. For example, the flash memory processor can be a NAND flash memory processor (NAND Flash Processing Unit, NPU). The following embodiments all use NAND flash memory as an example for description. However, it should be noted that the flash memory in this embodiment is not limited to NAND flash memory; it can also be other types of flash memory, such as NOR flash memory.

[0022] In the embodiments of this application, both cache read commands and cache programming commands can be in the form of cache operation sequences. The cache operation sequence in the embodiments of this application can be a cache read operation sequence or a cache programming operation sequence.

[0023] Cache Read is a pipelined read operation whose core purpose is to allow the read of previously loaded data in advance during the process of transferring data from the memory cell array to the page cache (internal data transfer) by the flash memory chip. This eliminates the idle waiting time between two read operations on the data bus, significantly improving the throughput of continuous reads. The cache read process is as follows: The host initiates a read of page A. The flash memory controller sends a read command sequence with an address to the flash memory chip through the channel and waits for the first tR. After the data of page A is ready, it begins reading data from the page cache on the flash memory chip. Simultaneously with or during the output of the data of page A, the flash memory controller initiates the next read. In other words, it is not necessary to wait for all the data of page A to be read before sending the cache read operation sequence for page A+1. This cache read operation sequence can include 31h, replacing the normal / regular read command 30h. After sending the cache read operation sequence to the flash memory chip, the remaining data of page A in the current page cache can be read. At the same time, the flash memory controller begins preparing for the next read.

[0024] Here, tR refers to the time required to read data from a page in the flash memory array into its internal page cache register. This process occurs in the first stage of flash memory operation. When a read command is initiated, the flash memory chip starts a high-precision read voltage sequence to sense the charge state of the memory cell and convert it into a digital signal, which is then temporarily stored in the flash memory chip's page cache.

[0025] Cache programming is a pipelined programming write operation. Its core purpose is to allow the next piece of data to be written to be pre-loaded into the page cache during the process of writing data to the memory cell array, thereby eliminating the idle waiting time of the data bus between two write operations and significantly improving the throughput of continuous writes. That is, the time for transferring data from the flash controller to the page cache of the flash chip overlaps with the time for programming data from the page cache to the memory cell array. The cache write process includes a data transfer phase and a programming write phase. In the data transfer phase, the flash controller serially transfers the data of page B to the flash chip, and the flash chip temporarily stores the data of page B in the page cache. In the programming write phase, the flash chip begins its internal programming operation after receiving the programming command from the flash controller. While internal programming is performed on page B, the flash controller can initiate the next cache programming operation through a sequence of cache programming commands, meaning that while internal programming is performed on page B, the data of page B+1 can be transferred to the page cache of the flash chip. After programming is complete, the flash controller can confirm the success or failure of the programming operation by reading the status register.

[0026] In this embodiment, a queue manager in the flash memory controller manages the command queue for the flash memory chip, and a flash memory processor in the flash memory controller executes at least one of cache read commands and cache program commands. Thus, cache commands can be implemented through the hardware of the flash memory controller. Since the reliability of hardware-implemented cache commands is much higher than that of complex firmware, this embodiment reduces the data risk caused by firmware logic errors, improves the reliability when processing cache commands, and solves the reliability risk problem of firmware-based cache command implementation in related technologies.

[0027] In this embodiment, the queue manager can provide state information on whether a command / task thread needs to be switched, and the state information may include the queue state. The queue manager 210 can also be used to: determine a scheduling decision based on the queue state of the command queue and whether each command in the command queue is allowed to execute a specified command; the specified command includes at least one of the cache read command and the cache programmable command; wherein the queue state includes an empty queue or a non-empty queue; the command queue includes a cache operation sequence; the scheduling decision includes any one of starting the cache operation sequence, maintaining the cache operation sequence, and terminating the cache operation sequence. Specifically, the cache operation sequence can be started when the queue state of the command queue is a non-empty queue and the first command in the command queue is allowed to execute the specified command; or it can be started when the queue state of the command queue is a non-empty queue and multiple consecutive commands in the command queue are allowed to execute the specified command. After the cache operation sequence is started, if the cache operation sequence is in a non-empty state, the cache operation sequence can be maintained; if the cache operation sequence is in an empty state after the cache operation sequence is started, the cache operation sequence can be terminated. The cache operation sequence can be a cache read operation sequence or a cache programmable operation sequence. In this way, various scheduling strategies can be flexibly determined.

[0028] Figure 3 This is a schematic diagram of a hard disk controller provided in an embodiment of this application. (Refer to...) Figure 3 The hard drive controller comprises the host interface controller, the central processing unit (CPU), and the flash memory controller. The flash memory controller is the hardware core and execution engine of the entire system, responsible for receiving commands from higher layers and directly driving the flash memory chips to complete specific operations. Specifically, the flash memory controller can implement interface protocols with the host or FTL, receiving macroscopic read and write requests. The flash memory controller can contain all the low-level physical logic required to drive the flash memory, such as generating precise timing signals, managing the data bus (DQ), command bus (CLE), and address bus (ALE).

[0029] Furthermore, the flash controller integrates multiple modules, serving as the physical carrier and interconnection hub for these modules. Specifically, the flash controller includes a queue manager and a flash processor, with the queue manager coupled to the flash processor. The queue manager manages command queues for flash dies, containing cached operation commands to be executed. These cached operation commands include at least one of cache read commands and cache program commands. The command queue is the system's internal buffer and scheduling center, with each physical flash die or logical unit number (LUN) corresponding to an independent command queue. The command queue can temporarily store flash operation (e.g., read or program) commands from the FTL waiting to be executed. Commands in the command queue can be tagged with priority attributes, such as high-priority read requests and low-priority erase requests. Moreover, the depth and status of the command queue can be maintained in real time, providing input for the queue manager's scheduling decisions. The depth of the command queue can be the number of commands contained in the queue, and the status of the command queue can be empty or not empty.

[0030] In this embodiment, the queue manager is responsible for global scheduling and caching strategy decisions. Specifically, the queue manager can, for example, obtain the status and priority of the command queues corresponding to all flash dies through real-time scanning, and can decide whether to start, maintain, or terminate the cache operation sequence according to a preset strategy. The prediction strategy can be a strategy related to at least one of the queue depth threshold and priority rules. For example, when a series of high-priority read commands are detected in the command queue of a certain die, a cache read process can be initiated. The queue manager can also be used to arbitrate access rights to flash die resources and can issue instructions to downstream components, such as thread task creation modules, to create corresponding task threads to perform operations. The queue manager in the flash controller, for example, can also perform resource status tracking. It tracks the "ready / busy" status of each flash granularity (e.g., memory cell / LUN / plane) in real time in the form of a bitmap. It allocates or releases the right to occupy a specific flash granularity in response to requests from NPU task threads. It ensures that only one task thread can access a physical cell at a time to avoid conflicts.

[0031] A bitmap is a data structure that maps or represents a certain state using binary bits. The flash memory controller 100 can use a bitmap mechanism to manage the state of flash memory resources. The smallest management unit of the flash memory resources can be at the plane level, plane group level, or logical unit number (LUN) level. This allows for fine-grained resource management and improves resource utilization through these smallest management units.

[0032] Taking NAND flash memory as an example, the flash memory controller supports flexible and configurable resource management granularity. Depending on actual needs, the smallest management unit of flash memory resources can be set to the plane, plane group, or LUN level to achieve efficient monitoring and scheduling of resources at different levels. The following is a brief introduction to plane, plane group, and LUN levels. A flash memory chip contains resources at multiple die-level management units; a die-level management unit contains resources at multiple plane-level management units; a plane group is a combination of multiple planes; and a LUN-level management unit corresponds to a chip-level management unit. This application's embodiments support the use of fine-grained plane levels for bitmap identification.

[0033] The state of the flash memory resources includes the ready state of the flash memory resources, and the ready state of the flash memory resources can be uniformly managed using a bitmap mechanism.

[0034] The flash memory processor in this embodiment can be a NAND Processing Unit (NPU). The NPU is a dedicated processor optimized for NAND operations. It is the executor of commands, supports fast switching between multiple threads, and executes specific NAND operations. The flash memory processor may include a scheduling unit, an execution unit, and a flash memory status recording unit. The scheduling unit, execution unit, and flash memory status recording unit can all be hardware components. The scheduling unit can provide thread scheduling functions and manage thread switching. For example, the scheduling unit receives task threads from the thread task creation module, determines which task thread will obtain the execution right of the NPU based on priority, resource dependency, and other strategies, and is also responsible for suspending, resuming, and context switching of task threads. Execution Unit: Responsible for executing instructions in the instruction set, including calculation, logical judgment, command issuance, etc. Flash Memory Status Recording Unit: Captures and maintains the latest status register (SR) value of each flash memory die in real time, such as SR[5] and SR[6], programming failure status, etc. In the cache read operation, SR[5] and SR[6] provide key pipeline control information. SR[5] (Cache Ready) indicates when data can be output. Once the value of SR[5] indicates that the cache is ready, data output can begin. SR[6] (Device Ready) indicates that the flash memory can receive new commands. For example, SR[5]=0 indicates that the page cache is busy, such as loading data from the array into the page cache, or outputting data from the page cache; SR[5]=1 indicates that the page cache is ready, data is ready to be output from the cache, or the cache can receive new data. SR[6]=0 indicates that the device is busy, such as performing array read, programming, or erase operations; SR[6]=1 indicates that the device is ready to accept new commands. Properly utilizing these two status bits is key to achieving an efficient cache read pipeline, which can significantly hide array read latency (tR) and improve continuous read performance.

[0035] In some embodiments of this application, the scheduling unit is used to obtain a first command from the command queue; the flash memory status recording unit is used to store the register status of the flash memory chips; and the execution unit is used to query the register status corresponding to the first command from the flash memory status recording unit, and execute the first command if the register status corresponding to the first command satisfies a first condition. The registers of the flash memory chips may include SR[5] and SR[6], and the registers of the flash memory chips can be indicated by the values ​​of SR[5] and SR[6]. The first condition can be a condition related to at least one of SR[5] and SR[6]. For example, the first condition can be that SR[5] indicates that the page cache is ready. Thus, by storing the register status of each flash memory chip through the flash memory status recording unit, the execution unit can directly query this flash memory status recording unit to obtain the register status when executing the first command, without having to access the flash memory chip to obtain the register status, thereby improving the efficiency of status query and thus improving the efficiency of command execution. For example, the first command can be a read command. When executing the read command, this status recording unit can be queried directly, without having to access the slow flash memory every time, greatly improving efficiency.

[0036] In some embodiments of this application, during the execution of the first command by the execution unit, the queue manager is further configured to submit the second command to the scheduling unit if a second command is detected in the command queue. The execution unit is further configured to save the context of the first command, put the first command into a sleep state, exit the execution of the first command, and execute the second command. The execution priority of the second command may be higher than that of the first command. Specifically, the first command may be a normal read or normal program command, and the second command may be a command that allows cache operations, such as cache read or cache program operations. Thus, through the cooperation of the queue manager and the execution unit, it can be ensured that the second command that allows cache operations is executed first, improving the execution efficiency of cache operations. Simultaneously, by timely releasing the die occupancy rights through hardware and relinquishing the flash memory processor's scheduling unit during operation intervals, the overall system throughput can be improved.

[0037] Meanwhile, the embodiments of this application can not only automatically save the context of the current first command, release resources, and switch commands, but also seamlessly restore the original command to continue execution at an appropriate time. Specifically, in some embodiments of this application, the execution unit is also used to query the register status of the second command from the flash memory status recording unit. When the register status of the second command meets the second condition, the execution of the second command is actively exited and the execution of the first command is resumed. The register status of the second command can be the register status of the flash memory chip operated by the second command. The register of the flash memory chip can include SR[5] and SR[6], and the register of the flash memory chip can be indicated by the values ​​of SR[5] and SR[6]. The second condition can be a condition related to at least one of SR[5] and SR[6]. For example, the second condition can be that SR[6] indicates that the device is ready and the flash memory can accept new commands. In this way, it can be guaranteed that the first command and the second command can be executed concurrently, improving execution efficiency.

[0038] In some embodiments of this application, the first command is a normal read command or a cached read command, and the second command is a cached read command. Thus, when the command queue contains both normal read commands and cached read commands, the cooperation between the various units within the flash memory controller not only improves the reliability of cached read command execution but also ensures that all commands can be executed concurrently, thereby improving command execution efficiency.

[0039] In some embodiments of this application, when the second command is a cache read command, the execution unit is further configured to: determine whether the page address of the second command is continuous with the page address of the first command; if the page address of the second command is continuous with the page address of the first command, execute the sequential cache read command; if the page address of the second command is not continuous with the page address of the first command, execute the random cache read command. In the execution of the cache read command in this application, the flash memory processor can automatically compare the page addresses of the preceding and following commands, and accordingly, can autonomously select whether to execute the sequential cache read command or the random cache read command, ensuring more intelligent hardware processing.

[0040] In this embodiment, not only can the flash memory status recording unit record the register status of the flash memory chip, but the register status of the flash memory chip recorded by the flash memory status recording unit can also be updated according to the command status, i.e., the execution status of the command. Specifically, in some embodiments of this application, the execution unit is further configured to: obtain the command status of a target command, the target command including at least one of the first command and the second command; update the register status corresponding to the target command in the flash memory status recording unit based on the command status of the target command; and, if the target command includes the first command, obtain the register status corresponding to the first command from the flash memory status recording unit after the first command resumes execution. It should be understood that, in this embodiment, the target command can be the first command, and the register status corresponding to the first command in the flash memory status recording unit can be updated based on the command status of the first command during or after the execution of the second command. In this way, after the first command resumes execution, the register status of the unit can be directly obtained from the flash memory status recording unit, thereby completing status reporting and resource cleanup.

[0041] The first command can be a normal programming command, and the second command can be a cached programming command; the command status includes programming success or programming failure. Furthermore, in some embodiments of this application, the execution unit can also be used to: replace the programming confirmation command with a cached programming confirmation command when a second command is detected in the command queue. Afterwards, the execution unit can save the context of the first command, put the first command into a sleep state, exit the execution of the first command, and execute the second command. In this way, the commands executed by the execution unit can be conveniently switched from normal programming commands to cached programming commands.

[0042] Figure 4 This is a schematic diagram of the automated cache reading workflow provided in the embodiments of this application. Figure 5-1 This is a diagram illustrating the process by which the queue manager submits commands to the scheduling unit. Figure 5-2 This is a schematic diagram illustrating the implementation process of cache read commands. Figure 5-2 In this context, NIOU represents the smallest independently controllable unit in a NAND flash memory, RDY indicates ready, and ARDY (array ready) indicates array ready. It should be noted that the processor core in this embodiment can be the execution unit mentioned above. (Refer to...) Figure 4 The automated cache reading workflow provided in this application embodiment is as follows: (1) The processor core of the flash memory controller executes command A, which is the normal read command: 00-30h command, and continuously reads the status of the status register SR[5] from the flash memory status recording unit. When the status of SR[5] indicates that it is ready, it prepares to execute 06-E0h to read data output. Among them, SR[5] is the 5th bit of the status register, and one flash memory die can record one bit.

[0043] (2) Hardware Dynamic Decision-Making and Interruption: Before reading the data corresponding to command A, the queue manager detects in real time that there is a high-priority read command, i.e., command B, in the same die queue. The queue manager submits command B to the scheduling unit. Command B can be the next command after command A.

[0044] Reference Figure 5-1 The queue manager submits commands to the scheduling unit according to the following rules: It monitors the command queue status corresponding to flash memory chip N. If the command queue is not empty, it determines whether the next command B after command A is a high-priority read command. If not, it waits for command A to complete before submitting command B to the execution unit for normal read execution. If so, it waits to execute the command in cached read mode and further determines whether command A allows command B to execute. If command A allows command B to execute, it submits command B to the scheduling unit for cached read execution. If command A does not allow command B to execute, it waits for command A to complete before submitting command B to the execution unit for normal read execution.

[0045] (3) Command A Suspension and Resource Release: The NPU suspends the execution of Command A and executes the following branches: Send preset instruction -> Wait for the current operation to complete (SR[5] ready) -> Actively release the die occupancy right -> Save the context of Command A -> Command A sleeps and exits the NPU. Among them, the preset instruction is a high-level command used to optimize the performance of continuous read. The preset instruction is used to eliminate the tR waiting time between continuous read operations, thereby maximizing the interface bandwidth utilization.

[0046] (4) Cache Read command execution: Command B is scheduled to be executed. The NPU recognizes that command B is in the cache read context and waits for the die resources to become available (i.e., the resources of command A have been released). The execution address comparison is performed: if the page address of command B is continuous with that of command A, then command 31h is sent; if they are not continuous, then command 00-31h (with the new address) is sent.

[0047] (5) Obtain register status until SR[6] is ready -> release die occupation -> exit NPU execution of command B and actively return the execution right to command A.

[0048] (6) Command A resumes and completes: Command A resumes execution, continuing from the breakpoint to complete the 06-E0h data reading -> resource release -> exit.

[0049] Process termination judgment: When command B resumes execution, the queue manager will determine whether the current command is the final command (no subsequent high-priority requests or the cache sequence length limit has been reached). If so, after SR[5] is ready, the 3Fh command is sent to terminate the cache sequence, and the data is read after SR[6] is ready; if not, steps 2-5 are repeated, allowing the higher-priority command C to be embedded. Here, command C can be the next command after command B.

[0050] Figure 6 This is a schematic diagram of the automated caching programming workflow provided in the embodiments of this application. Figure 7-1 This is a diagram illustrating the process by which the queue manager submits commands to the scheduling unit. Figure 7-2 This is a schematic diagram illustrating the implementation process of caching programming commands. Figure 7-2 In this context, NIOU represents the smallest independently controllable unit in a NAND flash memory, RDY indicates ready, and ARDY (array ready) indicates array ready. It should be noted that the processor core in this embodiment can be the execution unit mentioned above. (Refer to...) Figure 6 The automated cache reading workflow provided in this application embodiment is as follows: (1) The processor core of the flash memory controller executes command A, which is the normal programming command: send 80h-address-data -> prepare to send 10h (programming confirmation).

[0051] (2) Hardware Dynamic Decision-Making and Command Replacement: The queue manager detects the presence of a high-priority programming command B. The queue manager submits command B to the scheduling unit. NPU execution branch: Replace command 10h with command 15h (cache programming confirmation) -> Send. Here, the programming confirmation in cache programming refers to the process of verifying that data has been successfully and correctly programmed (written) from the page cache register into the flash memory's storage cell array. This is not a simple "command received" confirmation, but rather a verification of a successful physical write.

[0052] Reference Figure 7-1The queue manager submits commands to the scheduling unit according to the following rules: It monitors the command queue status corresponding to flash memory chip N. If the command queue is not empty, it determines whether the next command B after command A is a high-priority read command. If not, it waits for command A to complete before submitting command B to the execution unit for cache programming. If so, it waits for the command to be executed in cache programming mode and further determines whether command A allows command B to execute. If command A allows command B to execute, it submits command B to the scheduling unit for cache programming; if command A does not allow command B to execute, it waits for command A to complete before submitting command B to the execution unit for cache programming.

[0053] (3) Command A is suspended and enters sleep mode, and exits execution: The status of the status register SR[6] is continuously read from the flash memory status recording unit. When the status of SR[6] indicates that it is ready, the die occupancy is released -> the context of command A (including the current status) is saved -> command A goes to sleep and exits the NPU.

[0054] (4) Command B execution: Command B is scheduled and executes the same process as command A: 80h - data -> If there is no higher priority command at this time and command B is the last command, send 10h; if command B is not the last command, send 15h -> Continuously obtain the status of register SR[5] until ready state -> Obtain the command status of command B (programming successful or programming failed) and the command status of command A -> Release resources and exit NPU.

[0055] (5) After obtaining the command status (programming success or programming failure) of command B and the command status of command A, command B can update the register status of the flash memory chip recorded in the flash memory status recording unit.

[0056] (6) Command A recovery and status acquisition: After command B exits, command A is scheduled to be recovered. After checking that SR[6] is ready, the programming status (i.e. programming success or programming failure) of command A, which was previously returned by the operation of command B, is extracted from the flash memory status record unit. Status reporting and resource cleanup are completed, and then the execution of command A is exited.

[0057] As can be seen from the above analysis, the hardware automation of cache read operations or cache programming operations in this application has the following effects: Transparency to firmware: The firmware only submits macro-level tasks; the start, maintenance, and termination of all cache sequences are managed by the hardware. Intelligent decision-making: The hardware compares page address continuity in real time and automatically selects the 31h or 00-31h command; it dynamically monitors queue depth and priority to decide whether to interrupt or continue the cache process. Guaranteed atomicity: Each read operation (30h+E0h) or programming operation (80h+10h / 15h) is complete and its state is clear within its own context. Resource efficiency: The hardware promptly releases die occupancy and yields the NPU during operation intervals, improving the overall system throughput.

[0058] Furthermore, by transferring all the complex decision-making logic (splitting, synchronization, command selection, and state management) of caching operations from the firmware to a dedicated hardware unit, this embodiment significantly reduces firmware complexity and development / verification costs. The firmware code becomes concise and reliable, allowing focus solely on business logic without addressing underlying timing coupling. This embodiment enables hardware to monitor queues and states in real-time at nanosecond speeds and make scheduling decisions, far faster than the microsecond / millisecond response time of firmware. This improves the efficiency of cache command usage and system data bandwidth. The hardware can utilize caching features more actively and accurately, reducing idle time for the dies. Because the state of each command is promptly confirmed within its own context (data is read immediately, and the programming state is ultimately explicitly obtained), the data buffer is released earlier and more definitively, improving memory resource utilization and overall system performance determinism. Since the hardware module can globally optimize scheduling strategies and dynamically adjust caching behavior based on real-time load, the system achieves higher scheduling flexibility and resource utilization, better handling sudden traffic spikes and multi-priority scenarios. Because hardware management offers far greater reliability and determinism than complex firmware state machines, it significantly improves the reliability and stability of the system when handling complex NAND operations, and reduces data risks caused by firmware logic errors.

[0059] Please see Figure 8 , Figure 8 This is a structural block diagram of an SSD controller provided in an embodiment of this application. Figure 8 As shown, this application embodiment provides an SSD controller 800, which includes a flash memory controller 200 and a central processing unit 300. The flash memory controller 200 can be any of the flash memory controllers in any embodiment of this application; details regarding the flash memory controller 200 can be found in the preceding description and will not be repeated here to avoid repetition. The central processing unit may include the FTL processing module mentioned above.

[0060] Please see Figure 9 , Figure 9This is a structural block diagram of an electronic device provided in an embodiment of this application. For example... Figure 9 As shown in the figure, this application embodiment provides an electronic device 900, which includes an SSD controller 1200. The electronic device provided in this application embodiment can achieve the same technical effect as the SSD controller in the above embodiment, and will not be described again here to avoid repetition.

[0061] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0062] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0063] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A flash memory controller, characterized in that, include: A queue manager and a flash processor; the queue manager is coupled to the flash processor; The queue manager is used to manage a command queue for flash memory dies, the command queue containing flash memory operation commands to be executed, the flash memory operation commands including at least one of cache read commands and cache program commands; The flash memory processor is used to execute the flash memory operation commands.

2. The flash memory controller according to claim 1, characterized in that, The flash memory processor includes a scheduling unit, an execution unit, and a flash memory status recording unit; The scheduling unit is used to obtain the first command from the command queue; The flash memory status recording unit is used to store the register status of the flash memory chip; The execution unit is configured to query the register status corresponding to the first command from the flash memory status recording unit, and execute the first command if the register status corresponding to the first command meets the first condition.

3. The flash memory controller according to claim 2, characterized in that, The queue manager is also configured to submit the second command to the scheduling unit when a second command is detected in the command queue; The execution unit is further configured to save the context of the first command, put the first command into a sleep state, exit the execution of the first command, and execute the second command.

4. The flash memory controller according to claim 3, characterized in that, The execution unit is further configured to query the register status of the second command from the flash memory status recording unit, and if the register status of the second command meets the second condition, actively exit the execution of the second command and resume the execution of the first command.

5. The flash memory controller according to claim 4, characterized in that, The first command is a normal read command, and the second command is a cache read command; The execution unit is further configured to: determine whether the page address of the second command is continuous with the page address of the first command; and execute a sequential cache read command if the page address of the second command is continuous with the page address of the first command. If the page address of the second command is not contiguous with the page address of the first command, execute the random cache read command.

6. The flash memory controller according to claim 4, characterized in that, The execution unit is also used for: Obtain the command status of a target command, wherein the target command includes at least one of the first command and the second command; based on the command status of the target command, update the register status in the flash memory status recording unit corresponding to the target command; If the target command includes the first command, after the first command resumes execution, the register state corresponding to the first command is obtained from the flash memory state recording unit.

7. The flash memory controller according to claim 6, characterized in that, The first command is a normal programming command, and the second command is a cached programming command; the command status includes programming success or programming failure. The execution unit is further configured to: replace the programming confirmation command with a cached programming confirmation command when a second command is detected in the command queue.

8. The flash memory controller according to any one of claims 1-7, characterized in that, The queue manager is further configured to: determine a scheduling decision based on the queue status of the command queue and whether each command in the command queue is allowed to execute a specified command; the specified command includes at least one of the cache read command and the cache programmable command; The queue state includes an empty queue or a non-empty queue; the command queue includes a cache operation sequence; and the scheduling decision includes any one of starting the cache operation sequence, maintaining the cache operation sequence, and terminating the cache operation sequence.

9. A solid-state drive controller, characterized in that, It includes a central processing unit and a flash memory controller according to any one of claims 1-8.

10. An electronic device, characterized in that, Includes the solid-state drive controller according to claim 9.

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