LDMOS device electrical performance optimization method based on SAC algorithm

Abstract

The invention discloses an LDMOS device electrical performance optimization method based on an SAC algorithm, and belongs to the technical field of semiconductor power device design. The method comprises the following steps: sampling in a process parameter range, and extracting electrical characteristics by utilizing TCAD simulation to construct a data set; a deep neural network agent model is constructed and trained; designing a state space, an action space and a reward function, building an SAC deep reinforcement learning framework, and accessing the proxy model to the environment; and training the SAC model to obtain optimal process parameters. According to the method, the DNN proxy model is used for replacing high-time-consumption simulation, and the SAC algorithm is combined for self-adaptive adjustment, so that the problem of difficulty in multi-target collaborative optimization in a high-dimensional parameter space is effectively solved, the optimization period is remarkably shortened, collaborative improvement of static and dynamic performance of a device is realized, and an optimization result has high reliability through circuit verification.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device design technology, and in particular to a method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm. Background Technology

[0002] Currently, LDMOS (Lateral Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) devices are widely used in power integrated circuits due to their advantages such as high voltage withstand capability and low on-resistance. However, existing LDMOS device optimization methods have the following defects and shortcomings: Existing LDMOS device optimization methods often focus only on one aspect of electrical performance, such as optimizing breakdown voltage or specific on-resistance alone, and cannot simultaneously optimize the static and dynamic performance of LDMOS. Because LDMOS devices have numerous process design parameters, each of which affects electrical performance, and there are trade-offs between these electrical properties, such as the silicon limit constraint between breakdown voltage (BV) and specific on-resistance (Ron,sp), it is difficult to simultaneously improve one while maintaining the performance of the other.

[0003] For complex parameter tuning and optimization problems, the method of manually adjusting device parameters based on physical principle analysis is difficult to control the coordinated optimization of multiple electrical properties, and TCAD simulation requires a lot of time.

[0004] For optimizing the process of LDMOS devices, existing population-based or genetic optimization algorithms have low dynamic adaptability, requiring the entire optimization process to be rerun to adapt to changes, making online adjustment difficult; it is difficult to find the optimal solution for high-dimensional data; the population is re-evaluated in each iteration, making it impossible to reuse historical evaluation results; and the collaborative optimization of multiple objectives relies on manual weight setting or Pareto sorting, resulting in high parameter tuning costs.

[0005] Therefore, there is an urgent need for a multi-objective optimization method that can learn autonomously, adapt adaptively, and is highly efficient, in order to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this invention is to provide a method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm, which solves the problems of difficulty in coordinating the optimization of static and dynamic performance of LDMOS devices in the prior art, as well as the low optimization efficiency and high cost.

[0007] To achieve the above objectives, this invention provides a method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm, comprising the following steps: S1. Within the design range of process parameters, perform data sampling, simulate the LDMOS device process in SentaurusTCAD software, extract the electrical characteristic parameters of the device from the simulation results, and use the LDMOS design parameters and electrical performance parameters as a dataset.

[0008] S2. Construct a deep neural network (DNN) as a proxy model and train the deep neural network using the generated dataset.

[0009] S3. Design the state space, action space, and reward function for reinforcement learning, build a deep reinforcement learning neural network model based on the SAC algorithm, and connect the trained agent model to the reinforcement learning environment.

[0010] S4. Train the SAC (Soft Actor-Critic) model to obtain the optimal process design parameters output by the SAC algorithm, thereby obtaining an LDMOS device with synergistic optimization of breakdown voltage, specific on-resistance, and gate-drain charge under the process conditions.

[0011] Further, step S1 specifically includes: S11. Parameter space definition: Determine the 14-dimensional process and structural parameters of the LDMOS device as design variables, with each parameter within a certain constant range.

[0012] S12. Experimental design and sampling: The Latin hypercube sampling method is used to generate 2000 uniformly distributed experimental configuration schemes in the 14-dimensional parameter space to ensure sufficient exploration of the parameter space.

[0013] S13. TCAD Process Simulation: A 3D process simulation flow for LDMOS was established in the Sentaurus TCAD simulation software. The process simulation includes the following key steps: three N-drift region implantations and annealings, each implantation using independent energy and dose parameters; then plasma etching to grow an oxide layer to form an STI structure; followed by gate oxide growth and polysilicon deposition lithography; then two P-body ion implantations; then spacer sidewall formation; and finally drain and source ion implantations.

[0014] S14. Physical model configuration: In the simulation, the High-Field Saturation model and the Ennormal (IALMob) model are activated as carrier mobility models; the OldSlotboom bandgap narrowing model is adopted; the recombination mechanisms include Shockley-Read-Hall (SRH) recombination, Auger recombination, and avalanche breakdown model.

[0015] S15. Electrical characteristic extraction: Perform device electrical simulation for each set of parameter configurations to extract three core performance indicators: (1) Breakdown voltage (BV): The BV value is obtained when the drain voltage is scanned to a sufficiently large value in the off state and the electric field strength in the silicon material reaches the critical breakdown electric field.

[0016] (2) Specific on-resistance (Ron,sp): under gate voltage Drain voltage Under the given conditions, calculate the product of the on-resistance and the area of ​​the active region.

[0017] (3) Gate drain charge (QGD): Under the Mixmode simulation conditions of TCAD, a step voltage signal is applied to the gate to turn on the device, and the charging charge corresponding to the gate drain capacitance is obtained by integrating the CV characteristics.

[0018] S16 Data Cleaning and Preprocessing: Remove invalid data that does not converge in the simulation or has abnormal electrical characteristics; perform min-max normalization on all input parameters and output characteristics to scale the data to the [0,1] interval.

[0019] Further, step S2 specifically includes: S21. Model architecture design: Construct a fully connected deep neural network as a proxy model for TCAD simulation. The structure includes: Input layer: 14 neurons, corresponding to 14-dimensional process parameters; Hidden layers: four fully connected layers, with the number of neurons being 512, 256, 128, and 64 respectively (decreasing geometrically). Output layer: 3 neurons, predicting BV, Ron,sp, and QGD respectively; Activation function: All hidden layers use the ReLU activation function, the connection method is fully connected, and the weights are initialized using the Xavier normal distribution.

[0020] S22 model training configuration: The loss function is mean squared error (MSE); the optimizer is Adam, with an initial learning rate of 0.0005; five-fold cross-validation is implemented, with the training set accounting for 80% and the validation set accounting for 20%; the convergence criterion is: when the validation set's coefficient of determination R... 2 Training will be terminated if the loss is ≥0.98 and there is no decrease in loss for 10 consecutive rounds.

[0021] S23 Model Validation: The predicted values ​​of the surrogate model and the actual values ​​of the TCAD simulation should meet the following requirements: BV prediction mean absolute percentage error (MAPE) < 3%, Ron,sp prediction MAPE < 4%, and QGD prediction MAPE < 5%.

[0022] Furthermore, step S3 specifically includes: S31. State Space Definition: Define the state vector. It is a three-dimensional continuous space that includes the current electrical performance of the device: .

[0023] S32. Action Space Definition: Define action vectors It is a 14-dimensional continuous space, corresponding to adjustable process parameters (i.e., the parameters described in Table 1). Each motion component, after normalization, follows a truncated normal distribution in the interval [-1, 1].

[0024] S33. Reward Function Design: Design a reward function to guide multi-objective collaborative optimization. The expression is: .

[0025] in, Based on static merit value Normalization ( ), Based on dynamic excellence value Normalization ); As a penalty, when BV < 80 (for 60V rated devices), .

[0026] S34 and SAC algorithm network architectures: (1) Policy network: The input is a 3-dimensional state vector, and the output is the mean and standard deviation of a 14-dimensional action distribution. The structure consists of two hidden layers with 256 neurons in each layer, ReLU activation, and tanh activation in the output layer.

[0027] (2) Q-value network: Four critic networks were constructed, including , Current action state value network, and , Target action state value network.

[0028] and The network input dimension is 17, the hidden layer structure is [256, 256], and the output is a scalar. value.

[0029] and Network structure same The network parameters are synchronized through a soft update mechanism, using the following formula: , where τ is the soft update rate.

[0030] (3) Temperature coefficient : Trainable parameter, initial value 0.2, automatically adjusted by minimizing entropy loss.

[0031] S35 reinforcement learning environment ensemble: Encapsulates the trained DNN surrogate model as the state transition function of the environment: Environmental receiving action Then, the DNN model is called to instantly predict the next state. Set up an experience replay buffer with a capacity of 100,000 transfer samples.

[0032] Furthermore, step S4 specifically includes: S41. Training Initialization: Configure hyperparameters: learning rate 0.0005, discount factor Batch size 256, soft update rate The maximum number of training rounds is 1000, and the maximum number of steps per round is 1000.

[0033] S42. Training process: Round start: Randomly sample the initial state from the dataset. ; Policy execution: The Actor network samples actions based on the current state. ; Environment Interaction: DNN Proxy Model Calculates the Next State With instant rewards ; Experience storage: Store the transferred samples in the playback buffer; Policy Update: Sample data from the buffer, update the Critic network parameters to minimize the TD error, update the Actor network parameters to maximize the sum of expected reward and entropy, and update the temperature coefficient. .

[0034] Convergence criterion: Training is terminated when the average cumulative reward fluctuation is less than 5% over 50 consecutive rounds.

[0035] S43. Optimal Parameter Extraction: After training converges, extract the action parameters that maximize the cumulative reward as the optimal process scheme.

[0036] Furthermore, the method also includes switching circuit verification, constructing the switching circuit in TCAD mixed-mode simulation, and extracting the switching behavior of LDMOS. and Over time, the energy consumed during the switching transients of the devices before and after optimization is compared.

[0037] Therefore, the electrical performance optimization method for LDMOS devices based on the SAC algorithm using the above-described structure has the following beneficial effects: (1) Compared with the traditional traversal method, the present invention uses a DNN proxy model to replace the time-consuming TCAD simulation, which shortens the optimization cycle by more than 90% and significantly improves the optimization efficiency.

[0038] (2) This invention optimizes both static performance (BV, Ron, sp) and dynamic performance (QGD) without exceeding the limits of silicon materials, thus achieving a breakthrough in synergistic performance.

[0039] (3) The SAC algorithm in this invention automatically balances exploration and utilization through the entropy maximization mechanism, without the need for manual adjustment of complex weight parameters, and has strong adaptability. Furthermore, this invention verifies device performance through switching circuits, forming a double-layer closed loop of rapid exploration by proxy model and high-precision verification by TCAD, ensuring the physical reliability of the optimization results.

[0040] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the LDMOS device structure in an embodiment of the present invention; Figure 2 This is a schematic diagram of the DNN network structure in an embodiment of the present invention; Figure 3 This is a schematic diagram of the neural network for the SAC algorithm in an embodiment of the present invention; Figure 4 This is a schematic diagram of the SAC algorithm optimization process in an embodiment of the present invention.

[0042] Figure 5 This is a switching circuit diagram according to an embodiment of the present invention. Detailed Implementation

[0043] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0044] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] Example like Figure 1-5As shown, this invention provides a method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm. By combining a deep neural network (DNN) surrogate model with the soft actor critic (SAC) algorithm, it solves the problem of the difficulty in co-optimizing the static and dynamic performance of LDMOS devices. The specific implementation steps are as follows: Step S1, Dataset Construction and Preprocessing: S11. Parameter space definition: Determine the 14-dimensional process and structural parameters of the LDMOS device as design variables (action space). The parameters and their physical meanings are shown in Table 1. Table 1

[0046] S12. Experimental design sampling: The Latin hypercube sampling method is used to generate 2000 uniformly distributed experimental configuration schemes in the above 14-dimensional parameter space to ensure sufficient exploration of the parameter space and minimize simulation redundancy.

[0047] S13. TCAD Process Simulation: Establish a 3D process simulation workflow for LDMOS using Sentaurus TCAD simulation software. The process simulation includes the following key steps: Three N-drift region injections and annealings were performed, with each injection using independent energy and dose parameters; Plasma etching is performed to grow an oxide layer and form a shallow trench isolation oxide (STI) structure. (Note: Drift region implantation is performed first to avoid the distribution of implanted ions being affected by the oxide after the STI is formed.) Next, gate oxide layer growth and polysilicon deposition photolithography are performed; Two Pbody ion implantations were then performed. Forming the Spacer sidewalls; Finally, drain-source ion implantation is performed.

[0048] S14. Physical model configuration: Activate the following physical models during simulation to ensure accuracy: Carrier mobility: High-Field Saturation model and Ennormal (IALMob) model; Band structure: Old Slotboom bandgap narrowing model; Composite mechanisms: Shockley-Read-Hall (SRH) composite, Auger composite, and avalanche breakdown model.

[0049] S15. Electrical characteristic extraction: Perform device electrical simulation for each set of parameter configurations and extract three core performance indicators (forming the state space): Breakdown voltage (BV): When the drain voltage Vd is scanned to a sufficiently large value in the off-state, the electric field strength in the silicon material reaches the critical breakdown electric field. When the time is right, the BV value is obtained.

[0050] Specific on-resistance: at gate voltage Drain voltage Under the given conditions, calculate the product of the on-resistance and the area of ​​the active region.

[0051] Gate Drain Charge (QGD): Under the mixed-mode simulation conditions of TCAD, a step voltage signal of 10V is applied to the gate, causing the device to turn on from the off state. Within a certain time, The gate current remains unchanged. Charging is performed on this platform, which is called the Miller platform. The charge corresponding to the gate-drain capacitance is obtained by integrating the CV characteristics; the charge in this stage is denoted as... .

[0052] S16. Data Cleaning and Preprocessing Invalid data that fails to converge or exhibits abnormal electrical characteristics are removed. All input parameters and output characteristics are subjected to min-max normalization to scale the data. Intervals are used to eliminate differences in dimensions.

[0053] Step S2: Construction and training of the deep neural network proxy model: S21. Model architecture design: Construct a fully connected deep neural network as a proxy model for TCAD simulation. The network structure is as follows: Input layer: 14 neurons, corresponding to 14-dimensional process parameters; Hidden layers: four fully connected layers, with the number of neurons decreasing geometrically at 512, 256, 128, and 64 respectively; Output layer: 3 neurons, predicting BV, Ron,sp, and QGD respectively; Activation function: All hidden layers use the ReLU activation function to introduce non-linearity; Connection method: Fully connected layers are used, and the weights are initialized using a Xavier normal distribution.

[0054] S22, Model Training Configuration: Loss function: Mean squared error; Optimizer: The Adam optimizer was selected, with an initial learning rate of 0.0005 and an adaptive learning rate adjustment strategy. Validation strategy: Implement five-fold cross-validation, randomly dividing the dataset into 5 mutually exclusive subsets. Each time, 4 subsets are used for training and 1 for testing, repeating this process 5 times to ensure each subset is used as the test set at least once. The training set accounts for 80% of the dataset, and the validation set accounts for 20%. Convergence criterion: When the coefficient of determination on the validation set... Training will be terminated if the losses do not decrease for 10 consecutive rounds, and the maximum number of training rounds is limited to 1000 rounds.

[0055] S23. Model validation, proxy model predictions Compared with the actual value of TCAD simulation They should be strictly distributed along the diagonal. Nearby, the mean absolute percentage error (MAPE) must meet the following requirements: BV predicts MAPE <3%; Ron,sp predicts MAPE < 4%; QGD predicts MAPE <5%; Step S3: Design and framework construction of SAC reinforcement learning environment: S31. State space definition, defining the state vector. It is a three-dimensional continuous space that includes the current electrical performance of the device: ; S32. Action space definition, defining action vectors. This is a 14-dimensional continuous space, corresponding to adjustable process parameters (i.e., the 14 parameters in Table 1). Each motion component, after normalization, obeys... The truncated normal distribution of the interval.

[0056] S33. Reward Function Design: Design a reward function to guide multi-objective collaborative optimization. In this embodiment, the optimization objective is to improve the static merit value. Reduce dynamic merit value At the same time, ensuring that BV is not lower than 80V, the expression for the reward function is: ; in: Based on static merit value Normalized static performance terms; For dynamic merit value Normalized dynamic performance terms; As a penalty, for 60V rated devices, a penalty is imposed when BV < 80V. This embodiment sets... .

[0057] S34 and SAC algorithm network architectures: Policy Network: Input is a 3D state vector, output is the mean and standard deviation of a 14D action distribution. The structure consists of two hidden layers, each with 256 neurons, using ReLU activation, and the output layer uses tanh activation to limit the action range.

[0058] Value Network: A total of four critic networks were constructed, including , Current action state value network, and , Target action state value network.

[0059] in, and The current state-action value estimation network takes 3-dimensional state variables and 14-dimensional action variables as inputs, and has the following hidden layer structure. The output is a scalar. Values, the parameters in the network are denoted as ; and Target network, structure same A network, where the parameters are denoted as... .

[0060] Soft update mechanism: Parameters in the target network are synchronized through a soft update mechanism, as shown in the following formula: ; in, The soft update rate is set to 0.02 in this embodiment.

[0061] Temperature coefficient These are trainable parameters, initially set to 0.2, which are automatically adjusted to balance exploration and exploitation by minimizing entropy loss. The loss function for the temperature coefficient is calculated as follows and updated using gradient descent: ; in, The target entropy value.

[0062] S35. Encapsulation of reinforcement learning environments: The trained DNN agent model is encapsulated as a state transition function of the environment, as shown in the following formula: ; Environmental receiving action Then, the DNN model is called to instantly predict the next state. This avoids time-consuming TCAD simulations. An experience playback buffer is set with a capacity of 100,000 transfer samples.

[0063] Step S4: SAC model training and acquisition of optimal process parameters: S41. Training Initialization: The hyperparameters are configured as follows: Learning rate: 0.0005; Discount factor 0.992; Batch size: 256; Soft update rate : 0.02; Maximum number of training rounds: 1000 rounds; Maximum number of steps per round: 1000 steps; S42. Training process: Round start: Randomly sample the initial state from the dataset. ; Policy execution: The Actor network samples actions based on the current state. ; Environment Interaction: DNN Proxy Model Calculates the Next State With instant rewards ; Experience storage: transferring samples Store in the playback buffer; Policy Update: Sample 256 data points from the buffer and update the network in the following order: Update dual-Critic network parameters To minimize TD error; Update Actor network parameters To maximize the sum of expected reward and entropy; Update temperature coefficient To maintain the target entropy value ; Soft update target network: .

[0064] Convergence criterion: Training is terminated when the average cumulative reward fluctuation is less than 5% over 50 consecutive rounds.

[0065] S43. Optimal parameter extraction: After training convergence, extract the action parameters that maximize the cumulative reward as the optimal process scheme.

[0066] S44. Switching circuit verification: Construct the switching circuit in TCAD mixed-mode simulation and extract the LDMOS switching behavior. and Over time, the energy consumed during the switching transients of the devices before and after optimization is compared.

[0067] Through the above embodiments, this invention uses DNN to replace the time-consuming TCAD simulation as a reinforcement learning environment, and utilizes the entropy maximization mechanism of the SAC algorithm to automatically balance the weights of static performance and dynamic performance, successfully achieving efficient collaborative optimization of multiple objectives for LDMOS devices.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm, characterized in that, Includes the following steps: S1. Within the design range of process parameters, perform data sampling, simulate the LDMOS device process in TCAD software, extract the electrical characteristic parameters of the device from the simulation results, and use the LDMOS design parameters and electrical performance parameters as a dataset. S2. Construct a deep neural network (DNN) as a proxy model, and train the deep neural network using the generated dataset. S3. Design the state space, action space, and reward function for reinforcement learning, build a deep reinforcement learning neural network model based on the SAC algorithm, and connect the trained agent model to the reinforcement learning environment. S4. Train the SAC model to obtain the optimal process design parameters output by the SAC algorithm, thereby obtaining an LDMOS device with synergistic optimization of breakdown voltage, specific on-resistance, and gate-drain charge under this process condition.

2. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S1, the design range of process parameters is defined as 14-dimensional process and structural parameters, including: STI oxide length, gate and STI overlap length, length of STI extending from the N drift region, length of gate covering the P channel, first ion implantation energy and dose in the drift region, second ion implantation energy and dose in the drift region, third ion implantation energy and dose in the drift region, first ion implantation energy and dose in the channel region, and second ion implantation energy and dose in the channel region. The electrical performance parameters include: breakdown voltage BV, specific on-resistance Ron,sp, and gate-drain charge QGD.

3. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S1, the data sampling adopts the Latin hypercube sampling method to generate 2000 uniformly distributed experimental configuration schemes in a 14-dimensional parameter space. In step S2, the deep neural network proxy model is a fully connected deep neural network, and its network structure includes: Input layer: 14 neurons, corresponding to 14-dimensional process parameters; Hidden layers: four fully connected layers with 512, 256, 128, and 64 neurons respectively; Output layer: 3 neurons, predicting BV, Ron,sp, and QGD respectively; Activation function: The hidden layer uses the ReLU activation function.

4. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 3, characterized in that, In step S2, before training the DNN proxy model, all input parameters and output characteristics are subjected to min-max normalization to scale the data to the [0,1] interval. The training method employs five-fold cross-validation, and the convergence criterion is: when the coefficient of determination on the validation set... Training will be terminated if the losses do not decrease for 10 consecutive rounds.

5. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S3, the state space is defined as a three-dimensional continuous space that includes the current electrical performance of the device. ; The motion space is defined as a 14-dimensional continuous space, corresponding to 14 adjustable process parameters.

6. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S3, the design expression of the reward function is: ; in, Based on static merit value Normalized static performance terms For dynamic merit value Normalized dynamic performance terms; This is a penalty item; a set penalty value is applied when the breakdown voltage BV < 80.

7. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S3, the neural network architecture of the SAC algorithm includes: Policy network: The input is a 3-dimensional state vector, and the output is the mean and standard deviation of a 14-dimensional action distribution; the structure consists of two hidden layers, each with 256 neurons, and the output layer uses the tanh activation function to limit the action range; Q-value network: includes two current action state value networks, Q0 and Q1, and... , Two target action-state value networks; The input dimensions of the Q0 and Q1 networks are 3-dimensional state variables and 14-dimensional action variables, the hidden layer structure is [256, 256], and the output is the scalar Q value.

8. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 7, characterized in that, In step S3 and Network parameters are synchronized to the Q0 and Q1 networks via a soft update mechanism, with a soft update rate of [missing information]. ; The SAC algorithm also includes a temperature coefficient α, which is a trainable parameter with an initial value of 0.

2. It is automatically adjusted to balance exploration and exploitation by minimizing entropy loss.

9. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, In step S3, the trained DNN proxy model is encapsulated as a state transition function of the environment: ; Environmental receiving action Then, the DNN proxy model is invoked to instantly predict the next state. ; Set up an experience replay buffer with a capacity of 100,000 transfer samples.

10. The method for optimizing the electrical performance of LDMOS devices based on the SAC algorithm according to claim 1, characterized in that, The step S4 is followed by a verification step: A switching circuit was constructed in TCAD mixed-mode simulation to extract the drain current of the LDMOS switching behavior. and drain-source voltage By comparing the energy consumed during the switching transients of the device before and after optimization over time, the device performance can be verified.

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