Memory device

Abstract

A memory device includes: a first memory cell array including a plurality of bit lines; a second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines, and arranged adjacent to the first memory cell array in a first direction; and a first bit line sense amplifier array, the first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array, and a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines.

Description

Technical Field

[0001] This disclosure relates to memory devices. Background Technology

[0002] Volatile memory devices such as dynamic random access memory (DRAM) store data by storing charge in the capacitive load (capacitor) of the memory cell and read data by determining the charge stored in the capacitor.

[0003] Bit line sense amplifiers can be connected to memory cells to sense the data stored in the memory cells. Bit line sense amplifiers can detect and amplify the voltage difference between a bit line and its complementary bit line, determined based on the data stored in the memory cell.

[0004] Meanwhile, when designing DRAM using an open bitline structure, dummy bitlines are required to sense the outermost memory cell array block, which can become a factor that degrades the integration or manufacturing efficiency of semiconductor memory devices, such as the total number of gross dies per wafer or the net number of dies per wafer. Summary of the Invention

[0005] Some aspects of this disclosure relate to memory devices that can provide higher total die counts per wafer and / or other advantages as discussed herein.

[0006] A memory device according to some implementations of this disclosure may include: a first memory cell array, the first memory cell array including a plurality of bit lines; a second memory cell array, the second memory cell array including a plurality of complementary bit lines corresponding to the plurality of bit lines and arranged adjacent to the first memory cell array in a first direction; and a first bit line sense amplifier array, the first bit line sense amplifier array having at least a portion overlapping the first memory cell array on the first memory cell array, and including a plurality of first bit line sense amplifiers connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines.

[0007] A memory device according to some implementations of this disclosure may include: a first substrate, the first substrate including a first block and a second block, the first block including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, the second block including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells; and a second substrate, the second substrate being located above the first substrate and including a bit line sense amplifier, the bit line sense amplifier being connected to one of the plurality of bit lines and one of the plurality of complementary bit lines and disposed on the first block, the complementary bit line corresponding to one of the plurality of bit lines.

[0008] A memory device according to some implementations of this disclosure may include: a first memory cell array, the first memory cell array including a plurality of bit lines; a second memory cell array, the second memory cell array including a plurality of complementary bit lines and arranged adjacent to the first memory cell array in a first direction; a first bit line sense amplifier array, the first bit line sense amplifier array disposed on the first memory cell array and connected to a plurality of first bit lines among the plurality of bit lines and a plurality of first complementary bit lines among the plurality of complementary bit lines; and a second bit line sense amplifier array, the second bit line sense amplifier array disposed on the second memory cell array and connected to a plurality of second bit lines among the plurality of bit lines that are different from the plurality of first bit lines and a plurality of second complementary bit lines among the plurality of complementary bit lines that are different from the plurality of first complementary bit lines. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example of a memory device.

[0010] Figure 2 This is a perspective view illustrating an example of a memory device.

[0011] Figure 3 It is shown as follows Figure 2 A diagram showing an example of a memory device.

[0012] Figure 4 This is a perspective view illustrating an example of a memory device.

[0013] Figure 5 It is shown as follows Figure 4 A diagram showing an example of a memory device.

[0014] Figure 6 This is a diagram showing an example of a memory device.

[0015] Figure 7This is a diagram illustrating an example of an array of memory cells included in a memory device.

[0016] Figure 8 This is a circuit diagram illustrating an example of a bit-line sense amplifier included in a memory device.

[0017] Figure 9 This is a diagram showing an example of a memory device.

[0018] Figure 10 This is a diagram showing an example of a memory device.

[0019] Figure 11 This is a diagram showing an example of a memory device.

[0020] Figure 12 This is a diagram showing an example of a memory device.

[0021] Figure 13 This is a perspective view illustrating an example of a memory device.

[0022] Figure 14 This is a cross-sectional view of an example memory device.

[0023] Figure 15 This is a cross-sectional view of an example memory device.

[0024] Figure 16 This is a block diagram illustrating an example of a computing device. Detailed Implementation

[0025] In the following detailed description, certain examples are illustrated. As those skilled in the art will recognize, the described examples can be modified in various ways without departing from the spirit or scope of this disclosure.

[0026] Throughout the specification, the same reference numerals designate the same elements. In the flowcharts described with reference to the accompanying drawings, the order of operations or steps may be changed, several operations or steps may be combined, a certain operation or step may be divided, and a particular operation or step may be omitted without departing from the scope of this disclosure.

[0027] In the description, unless explicit expressions such as "a" or "single" are used, expressions described in the singular in this specification may be interpreted as singular or plural. Unless otherwise indicated, terms including ordinal numbers such as first, second, etc., are used only to describe various components and are not construed as limiting these components to a particular order. Unless otherwise indicated, these terms are used only to distinguish one component from other components.

[0028] Figure 1 This is a block diagram illustrating an example of a memory device. (Reference) Figure 1The memory device 100 may include a memory cell array 110, a row decoder 120, a bit line sense amplifier array 130, an input / output circuit 140, and a control logic circuit 150.

[0029] The memory cell array 110 may include multiple memory cells arranged in the row and column directions. The multiple memory cells may be connected to multiple word lines WL extending in the row direction and multiple bit lines BL extending in the column direction.

[0030] For illustrative purposes, and as a representative example, each of the plurality of memory cells will be described below as an example of a dynamic random access memory (DRAM) cell. However, the memory cells are not limited to this, and each of the plurality of memory cells can be any type of volatile memory cell (such as a static random access memory (SRAM) cell) or any type of non-volatile memory cell (such as a flash memory cell). That is, the scope of this disclosure is not limited to the type of memory device 100.

[0031] The row decoder 120 can control multiple word lines WL. For example, the row decoder 120 can activate some of the multiple word lines WL based on the address ADDR provided to the control logic circuit 150.

[0032] Bit line sense amplifier array 130 may include multiple bit line sense amplifiers S / A. For example, bit line sense amplifier array 130 may include first bit line sense amplifier SA1 to nth bit line sense amplifier SAn.

[0033] Multiple bit line sense amplifiers SA1 to SAn can be connected to multiple bit lines BL, respectively. For example, each of the multiple bit line sense amplifiers SA1 to SAn can be connected to a bit line and its complementary bit line (hereinafter referred to as the complementary bit line). The multiple bit line sense amplifiers SA1 to SAn can detect and amplify the voltage level change of the connected bit line BL based on the voltage level difference between the connected bit line and the complementary bit line.

[0034] The input / output circuit 140 can output data to the outside corresponding to the voltage level change of the bit line BL amplified by the bit line readout amplifier array 130, or receive data from the outside.

[0035] The control logic circuit 150 can receive commands CMD and addresses ADDR. The control logic circuit 150 can control the overall operation of the memory device 100 based on the commands CMD and addresses ADDR.

[0036] In some implementations, control logic circuitry 150 may provide multiple control signals to bit line sense amplifier array 130. For example, control logic circuitry 150 may provide multiple control signals to bit line sense amplifier array 130 to control the operation of each of the multiple bit line sense amplifiers S / A.

[0037] Figure 2 This is a perspective view illustrating an example of a memory device. Figure 3 This indicates a memory device (e.g., such as...) Figure 2 The diagram shows the memory device.

[0038] refer to Figure 2 and Figure 3 The memory device 200 may include a memory region MR and a peripheral circuit region PCR. The peripheral circuit region PCR may be stacked three-dimensionally on the memory region MR along the third direction D3. That is, the memory device 200 may have a periphery-on-cell (PoC) structure.

[0039] The memory region MR may include a first substrate SUB1 and a memory cell array MCA formed on the first substrate SUB1 (e.g., Figure 1 The memory cell array 110 shown. The peripheral circuit region PCR may include a second substrate SUB2 and peripheral circuitry PC formed on the second substrate SUB2 (e.g., as shown). Figure 1 The diagram shows a row decoder 120, a bit line sense amplifier array 130, an input / output circuit 140, and a control logic circuit 150. Below, the memory cell array (MCA) may also be referred to as MAT or a module (mat).

[0040] Figure 4 This is a perspective view illustrating an example of a memory device. Figure 5 This indicates a memory device (e.g., such as...) Figure 4 A diagram showing an example of a memory device.

[0041] refer to Figure 4 and Figure 5 The memory device 300 may include a peripheral circuit region PCR and a memory region MR. The memory region MR may be stacked three-dimensionally on the peripheral circuit region PCR along the third direction D3. That is, the memory device 300 may have a peripheral upper unit (CoP) structure.

[0042] The peripheral circuit region PCR may include a second substrate SUB2 and peripheral circuit PC (e.g., ...) formed on the second substrate SUB2. Figure 1The diagram shows a row decoder 120, a bit line sense amplifier array 130, an input / output circuit 140, and a control logic circuit 150. The memory region MR may include a first substrate SUB1 and a memory cell array MCA formed on the first substrate SUB1. Figure 1 The memory cell array 110 shown.

[0043] Figure 2 and Figure 3 The memory device 200 with the PoC structure shown and Figure 4 and Figure 5 The memory device 300 with the CoP structure shown can have a substantially similar wiring connection structure, except that the stacking order on the third-direction D3 is reversed. For ease of description, below, in Figure 2 and Figure 3 The memory device described below is presented within the context of the PoC structure shown. However, it will be understood that the disclosed apparatus and configuration are also applicable to CoP memory devices.

[0044] Figure 6 This is a diagram illustrating an example of a memory device. (Reference) Figure 6 The memory device 400 may include multiple memory cell arrays MCA1 and MCA2. The multiple memory cell arrays MCA1 and MCA2 may include a first memory cell array MCA1 and a second memory cell array MCA2. The first memory cell array MCA1 and the second memory cell array MCA2 may be arranged spaced apart along a first direction D1. For example, the first memory cell array MCA1 and the second memory cell array MCA2 may be located in the same... Figure 2 and Figure 3 On the first substrate SUB1 shown.

[0045] The first memory cell array MCA1 may include multiple bit lines BL1 to BL8, multiple word lines WL1 to WL8, and multiple memory cells MC connected to the multiple bit lines BL1 to BL8 and the multiple word lines WL1 to WL8. The second memory cell array MCA2 may include multiple complementary bit lines BLB1 to BLB8.

[0046] In the Sub-Word Line Drivers area (SWD), you can configure the sub-word line drivers. A sub-word line driver can activate a specific word line from WL1 to WL8.

[0047] The memory device 400 may include multiple bit line sense amplifier arrays BSA1 and BSA2. The multiple bit line sense amplifier arrays BSA1 and BSA2 may include a first bit line sense amplifier array BSA1 and a second bit line sense amplifier array BSA2.

[0048] The first bit line sense amplifier array BSA1 and the second bit line sense amplifier array BSA2 can each include multiple bit line sense amplifiers. For example, the first bit line sense amplifier array BSA1 and the second bit line sense amplifier array BSA2 can be located in the same... Figure 2 and Figure 3 On the second substrate SUB2 shown.

[0049] exist Figure 6 For better understanding and ease of description, the first bit-line sense amplifier array BSA1 and the second bit-line sense amplifier array BSA2 are depicted as being located along a first direction D1 between the separation space of the first memory cell array MCA1 and the second memory cell array MCA2. However, the arrangement of the amplifier arrays and memory cell arrays is not limited to this. For example, the first bit-line sense amplifier array BSA1 may be located on the first memory cell array MCA1 along a third direction D3, such that at least a portion of the first bit-line sense amplifier array BSA1 overlaps with the first memory cell array MCA1, and / or the second bit-line sense amplifier array BSA2 may be located on the second memory cell array MCA2 along a third direction D3, such that at least a portion of the second bit-line sense amplifier array BSA2 overlaps with the second memory cell array MCA2. Further discussion of the arrangement of these elements will be provided below.

[0050] The first direction D1 and the second direction D2 can be, for example, lateral directions parallel to the top and / or bottom surfaces of the first substrate SUB1 and / or the second substrate SUB2. The first direction D1 and the second direction D2 can be orthogonal or intersecting. The third direction D3 can be a vertical direction orthogonal to the first direction D1 and the second direction D2 and orthogonal to the top and / or bottom surfaces of the first substrate SUB1 and / or the second substrate SUB2.

[0051] Some of the bit lines BL1 to BL8 included in the first memory cell array MCA1 can be connected to the multiple bit line sense amplifiers included in the first bit line sense amplifier array BSA1. Some of the remaining bit lines BL1 to BL8 included in the first memory cell array MCA1 can be connected to the multiple bit line sense amplifiers included in the second bit line sense amplifier array BSA2.

[0052] Some of the complementary bit lines BLB1 to BLB8 included in the second memory cell array MCA2 can be connected to the multiple bit line sense amplifiers included in the first bit line sense amplifier array BSA1. Some of the remaining bit lines among the complementary bit lines BLB1 to BLB8 included in the second memory cell array MCA2 can be connected to the multiple bit line sense amplifiers included in the second bit line sense amplifier array BSA2.

[0053] Figure 7 This is a diagram illustrating an example of an array of memory cells included in a memory device.

[0054] refer to Figure 7 The memory cell array (MCA) may include a first memory cell array (MCA1) and a second memory cell array (MCA2). The first memory cell array (MCA1) may include a first memory cell region (MCR1) in which multiple memory cells are arranged, and a first edge region (ER1) and a second edge region (ER2) in which no memory cells are arranged. The first edge region (ER1) may correspond to a region within the edge region that is not adjacent to the second memory cell array (MCA2), while the second edge region (ER2) may correspond to a region within the edge region that is adjacent to the second memory cell array (MCA2). For example, the first edge region (ER1) may be an edge region opposite to the edge region (ER2) adjacent to the second memory cell array (MCA2).

[0055] The second memory cell array MCA2 may include a second memory cell region MCR2 in which multiple memory cells are arranged, and a third edge region ER3 and a fourth edge region ER4 in which no memory cells are arranged. The third edge region ER3 may correspond to a region within the edge region that is adjacent to the first memory cell array MCA1, while the fourth edge region ER4 may correspond to a region within the edge region that is not adjacent to the first memory cell array MCA1. For example, the fourth edge region ER4 may be an edge region opposite to the edge region ER3 adjacent to the first memory cell array MCA1.

[0056] See below for reference. Figure 9 As described, multiple engagement contacts can be arranged in the first edge region ER1 and the second edge region ER2, wherein multiple bit lines ( Figure 6 BL1 to BL8 are connected to the cell metal wiring, which connects multiple bit lines BL1 to BL8 and the first bit line sense amplifier array located on the first memory cell array MCA1. Figure 6 BSA1) and the second bit line sense amplifier array located on the second memory cell array MCA2 ( Figure 6 BSA2). Furthermore, multiple engagement contacts can be arranged in the third edge region ER3 and the fourth edge region ER4, where multiple complementary bit lines ( Figure 6 The BLB1 to BLB8 are connected to the cell metal wiring, which connects multiple complementary bit lines BLB1 to BLB8, as well as the first bit line sense amplifier array BSA1 located on the first memory cell array MCA1 and the second bit line sense amplifier array BSA2 located on the second memory cell array MCA2.

[0057] Figure 8 This is a diagram illustrating an example of a bit line sense amplifier (e.g., a bit line sense amplifier BLSA included in a first bit line sense amplifier array BSA1 or a second bit line sense amplifier array BSA2) included in a memory device.

[0058] refer to Figure 8 The bit line sense amplifier BLSA can be connected to both the bit line BL and the complementary bit line BLB. The bit line BL can be... Figure 6 The shown bit line is one of the multiple bit lines BL1 to BL8, and the complementary bit line BLB can be... Figure 6 The complementary bit line shown is one of the complementary bit lines BLB1 to BLB8 that corresponds to bit line BL.

[0059] Bit lines BL can be connected to multiple memory cells, and each of the multiple memory cells can be connected to one of the multiple word lines WL. Additionally, complementary bit lines BLB can be connected to multiple memory cells, and each of the multiple memory cells can be connected to one of the multiple word lines WL.

[0060] In some implementations, the bit line sense amplifier BLSA can be connected to a bit line BL and its corresponding complementary bit line BLB. For ease of explanation, Figure 8 The diagram shows a memory cell MC1 connected to bit line BL, a word line WLi connected to memory cell MC1, a memory cell MC2 connected to complementary bit line BLB, and a word line WLj connected to memory cell MC2.

[0061] in addition, Figure 8 The diagram shows that memory cell MC1 includes a switching transistor AT1 and a capacitor SC1, and memory cell MC2 includes a switching transistor AT2 and a capacitor SC2, but the structures of memory cells MC1 and MC2 are not limited to these.

[0062] The bit-line sense amplifier BLSA 570 may include an N-type sense amplifier 571, a P-type sense amplifier 573, an input / output gate circuit 540, a partial sense amplifier 560, and transistors M1 and M2. In some implementations, Figure 8The transistors M1 to M10, CST1, and CST2 shown can be metal-oxide-semiconductor (MOS) transistors. In some implementations, transistors M1, M3, M4, M7, M8, M9, M10, CST1, and CST2 can be n-channel transistors, such as NMOS transistors. Alternatively, transistors M2, M5, and M6 can be p-channel transistors, such as PMOS transistors. The source, drain, and gate of transistors M1 to M10, CST1, and CST2 can serve as a first input terminal, a second input terminal, and a control terminal, respectively. The transistor type is not limited to those described above.

[0063] The N-type sense amplifier 571 may include a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 may be electrically connected to the complementary bit line BLB via a conductive line 571_2. The gate of the fourth transistor M4 may be electrically connected to the bit line BL via a conductive line 571_1. The sources of the third transistor M3 and the fourth transistor M4 may be electrically connected to the bit line BL and the complementary bit line BLB, respectively. A first voltage LAB may be input to the drains of the third transistor M3 and the fourth transistor M4 in response to an N-type sense amplifier drive signal LANG. The N-type sense amplifier drive signal LANG may have an activation level (e.g., high level) for turning on the first transistor M1 or an inactive level (e.g., low level) for turning off the first transistor M1. The first voltage LAB may be ground.

[0064] The third transistor M3 and the fourth transistor M4 can be turned on or off according to the voltage change of the bit line BL or the complementary bit line BLB. When the third transistor M3 is turned on, it can provide the first voltage LAB to the bit line BL. When the fourth transistor M4 is turned on, it can provide the first voltage LAB to the complementary bit line BLB.

[0065] The P-type sense amplifier 573 may include a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 is electrically connected to the complementary bit line BLB via a conductive line 573_2. The gate of the sixth transistor M6 is electrically connected to the bit line BL via a conductive line 573_1. The sources of the fifth transistor M5 and the sixth transistor M6 are electrically connected to the bit line BL and the complementary bit line BLB, respectively. A second voltage LA is input to the drains of the fifth transistor M5 and the sixth transistor M6 in response to a P-type sense amplifier drive signal LAPG. The P-type sense amplifier drive signal LAPG may have an activation level (e.g., low level) for turning on the second transistor M2 or an inactive level (e.g., high level) for turning off the second transistor M2. The second voltage LA may be a power supply voltage.

[0066] The fifth transistor M5 and the sixth transistor M6 can be turned on or off according to the voltage change of the bit line BL or the complementary bit line BLB. When the fifth transistor M5 is turned on, it can provide a second voltage LA to the bit line BL. When the sixth transistor M6 is turned on, it can provide a second voltage LA to the complementary bit line BLB.

[0067] Input / output gate 540 may include a first column select transistor CST1 and a second column select transistor CST2. The drain of the first column select transistor CST1 may be electrically connected to bit line BL, and the drain of the second column select transistor CST2 may be electrically connected to the complementary bit line BLB. The source of the first column select transistor CST1 may be electrically connected to the local input / output line LIO, and the source of the second column select transistor CST2 may be electrically connected to the complementary local input / output line LIOB. Column select line CSL may be connected to the gate of the first column select transistor CST1 and the gate of the first column select transistor CST2. The bit line pair BL and BLB connected to the sense amplifier 570 may be connected to the local input / output line pair LIO and LIOB via column select transistors CST1 and CST2.

[0068] The column selection transistors CST1 and CST2 in the input / output gate circuit 540 can transfer the potentials output from the N-type sense amplifier 571 and the P-type sense amplifier 573 to the local sense amplifier 560 in response to the column selection signal of the column selection line CSL.

[0069] The local sense amplifier 560 may include a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 may be electrically connected within the local sense amplifier 560 via conductive line 561_1.

[0070] A local enable signal PLSAE can be input to the gates of the eighth transistor M8 and the tenth transistor M10. The gates of the eighth transistor M8 and the tenth transistor M10 are turned on by the local enable signal PLSAE, thereby activating the local sense amplifier 560. When the local sense amplifier 560 is activated, the seventh transistor M7 and the ninth transistor M9 can invert the data in the local input / output pairs LIO and LIOB, respectively, and output them to the global input / output pairs GIO and GIOB.

[0071] The bit line sense amplifier BLSA operates as follows: First, when word lines WLi and WLj are activated, the switching transistor AT1 of memory cell MC1 is turned on, causing charge to move between bit line BL and capacitor SC1 in memory cell MC1, and the switching transistor AT2 of memory cell MC2 is turned on, causing charge to move between complementary bit line BLB and capacitor SC2 in memory cell MC2. Then, the N-type sense amplifier 571 or P-type sense amplifier 573 amplifies the potential difference between bit line BL and complementary bit line BLB. Next, when the column select signal becomes active, input / output gate 540 can output data from bit line BL or complementary bit line BLB through local input / output line LIO or complementary local input / output line LIOB, respectively. That is, in response to the column select signal, column select transistors CST1 and CST2 in input / output gate 540 can transfer the potential output from N-type sense amplifier 571 or P-type sense amplifier 573 to local sense amplifier 560. The local sense amplifier 560 is activated by the local enable signal PLSAE to invert the received local input / output pairs LIO and LIOB and output them to the global input / output pairs GIO and GIOB.

[0072] The sense amplifier 570 may also include a precharge unit. Before or after the operation of the N-type sense amplifier 571 or the P-type sense amplifier 573, the precharge unit can balance the voltages of the bit line BL and the complementary bit line BLB to the precharge voltage.

[0073] Figure 9 and Figure 10 This is a diagram illustrating an example of a memory device. (Reference) Figure 9 and Figure 10 The memory device 500 includes a first memory cell array MCA1 and a second memory cell array MCA2 disposed adjacent to the first memory cell array MCA1 in a first direction D1. The first memory cell array MCA1 and the second memory cell array MCA2 may be adjacent to each other and spaced apart in the first direction D1. The first memory cell array MCA1 may include multiple bit lines BL1 to BL8 extending in the first direction D1. The second memory cell array MCA2 may include multiple complementary bit lines BLB1 to BLB8 extending in the first direction D1 and corresponding to the multiple bit lines BL1 to BL8.

[0074] The first bit line sense amplifier array BSA1 and the second bit line sense amplifier array BSA2 may each include multiple bit line sense amplifiers BLSA1 to BLSA8.

[0075] For example, the first bit line sense amplifier array BSA1 may include a first bit line sense amplifier BLSA1, a second bit line sense amplifier BLSA2, a fifth bit line sense amplifier BLSA5, and a sixth bit line sense amplifier BLSA6.

[0076] The second bit-line sense amplifier array BSA2 may include a third bit-line sense amplifier BLSA3, a fourth bit-line sense amplifier BLSA4, a seventh bit-line sense amplifier BLSA7, and an eighth bit-line sense amplifier BLSA8.

[0077] The first bit line sense amplifier BLSA1 and the second bit line sense amplifier BLSA2 can be arranged spaced apart along the first direction D1. The fifth bit line sense amplifier BLSA5 and the sixth bit line sense amplifier BLSA6 can be arranged spaced apart along the first direction D1.

[0078] The first bit line sense amplifier BLSA1 and the fifth bit line sense amplifier BLSA5 can be arranged spaced apart along the second direction D2. The second bit line sense amplifier BLSA2 and the sixth bit line sense amplifier BLSA6 can be arranged spaced apart along the second direction D2.

[0079] The third bit-line sense amplifier BLSA3 and the fourth bit-line sense amplifier BLSA4 can be arranged spaced apart along the first direction D1. The seventh bit-line sense amplifier BLSA7 and the eighth bit-line sense amplifier BLSA8 can be arranged spaced apart along the first direction D1.

[0080] The third bit-line sense amplifier BLSA3 and the seventh bit-line sense amplifier BLSA7 can be arranged spaced apart along the second direction D2. The fourth bit-line sense amplifier BLSA4 and the eighth bit-line sense amplifier BLSA8 can be arranged spaced apart along the second direction D2.

[0081] The first bit line sense amplifier array BSA1 can be located on the first memory cell array MCA1, such that at least a portion of it overlaps with the first memory cell array MCA1 along the third direction D3. The second bit line sense amplifier array BSA2 can be located on the second memory cell array MCA2, such that at least a portion of it overlaps with the second memory cell array MCA2 along the third direction D3.

[0082] The memory device 500 may have a wiring connection structure such that, among the data stored in the plurality of memory cells included in the first memory cell array MCA1, odd-numbered data is sensed by the first bit line readout amplifier array BSA1, while even-numbered data is sensed by the second bit line readout amplifier array BSA2.

[0083] For example, the first bit line BL1 and its corresponding first complementary bit line BLB1 can be connected to the first bit line sense amplifier BLSA1, the third bit line BL3 and its corresponding third complementary bit line BLB3 can be connected to the second bit line sense amplifier BLSA2, the fifth bit line BL5 and its corresponding fifth complementary bit line BLB5 can be connected to the fifth bit line sense amplifier BLSA5, and the seventh bit line BL7 and its corresponding seventh complementary bit line BLB7 can be connected to the sixth bit line sense amplifier BLSA6.

[0084] On the other hand, the second bit line BL2 and its corresponding second complementary bit line BLB2 can be connected to the third bit line sense amplifier BLSA3, the fourth bit line BL4 and its corresponding fourth complementary bit line BLB4 can be connected to the fourth bit line sense amplifier BLSA4, the sixth bit line BL6 and its corresponding sixth complementary bit line BLB6 can be connected to the seventh bit line sense amplifier BLSA7, and the eighth bit line BL8 and its corresponding eighth complementary bit line BLB8 can be connected to the eighth bit line sense amplifier BLSA8.

[0085] As described above, the unit metal wiring can connect bit lines (and complementary bit lines) and bit line sense amplifier arrays located on different planes, and the unit metal wiring can be connected to bit lines (and complementary bit lines) through bit line contacts located in the edge region, and connected to bit line sense amplifiers through bit line sense amplifier contacts.

[0086] For example, such as Figure 10 As shown, the first bit line BL1, the third bit line BL3, the fifth bit line BL5 and the seventh bit line BL7 can each be connected to the cell metal wiring through multiple bit line contacts located at the first edge region ER1, and can be connected to the first bit line sense amplifier BLSA1, the second bit line sense amplifier BLSA2, the fifth bit line sense amplifier BLSA5 and the sixth bit line sense amplifier BLSA6 through the cell metal wiring respectively.

[0087] The second bit line BL2, the fourth bit line BL4, the sixth bit line BL6, and the eighth bit line BL8 can each be connected to the cell metal wiring via multiple bit line contacts located at the second edge region ER2, and can be connected to the third bit line sense amplifier BLSA3, the fourth bit line sense amplifier BLSA4, the seventh bit line sense amplifier BLSA7, and the eighth bit line sense amplifier BLSA8 via the cell metal wiring, respectively.

[0088] The first complementary bit line BLB1, the third complementary bit line BLB3, the fifth complementary bit line BLB5, and the seventh complementary bit line BLB7 can each be connected to the cell metal wiring through multiple bit line contacts located at the third edge region ER3, and can be connected to the first bit line sense amplifier BLSA1, the second bit line sense amplifier BLSA2, the fifth bit line sense amplifier BLSA5, and the sixth bit line sense amplifier BLSA6 respectively through the cell metal wiring.

[0089] The second complementary bit line BLB2, the fourth complementary bit line BLB4, the sixth complementary bit line BLB6, and the eighth complementary bit line BLB8 can each be connected to the cell metal wiring via multiple bit line contacts located at the fourth edge region ER4, and can be connected to the third bit line sense amplifier BLSA3, the fourth bit line sense amplifier BLSA4, the seventh bit line sense amplifier BLSA7, and the eighth bit line sense amplifier BLSA8 via the cell metal wiring, respectively.

[0090] Figure 11 and Figure 12 This is a diagram illustrating an example of a memory device. The following mainly describes... Figure 9 and Figure 10 The differences described for the memory device 500 are as follows. Unless otherwise indicated or suggested by the context, the description of the elements provided for the memory device 500 is equally applicable. Figure 11 and Figure 12 The corresponding element of the memory device 600.

[0091] refer to Figure 11 and Figure 12 The memory device 600 may have a structure in which two adjacent bit lines (and their corresponding two complementary bit lines) are connected to a first bit line sense amplifier array BSA1, and two adjacent bit lines (and their corresponding two complementary bit lines) arranged sequentially in the second direction D2 are connected to a second bit line sense amplifier array BSA2.

[0092] For example, the first bit line BL1 and its corresponding first complementary bit line BLB1 can be connected to the fourth bit line sense amplifier BLSA4, the second bit line BL2 and its corresponding second complementary bit line BLB2 can be connected to the third bit line sense amplifier BLSA3, the third bit line BL3 and its corresponding third complementary bit line BLB3 can be connected to the second bit line sense amplifier BLSA2, and the fourth bit line BL4 and its corresponding fourth complementary bit line BLB4 can be connected to the first bit line sense amplifier BLSA1.

[0093] The fifth bit line BL5 and its corresponding fifth complementary bit line BLB5 can be connected to the eighth bit line sense amplifier BLSA8, the sixth bit line BL6 and its corresponding sixth complementary bit line BLB6 can be connected to the seventh bit line sense amplifier BLSA7, the seventh bit line BL7 and its corresponding seventh complementary bit line BLB7 can be connected to the sixth bit line sense amplifier BLSA6, and the eighth bit line BL8 and its corresponding eighth complementary bit line BLB8 can be connected to the fifth bit line sense amplifier BLSA5.

[0094] In some implementations, with Figure 9 and Figure 10 The cell metal wiring of the memory device 500 shown differs in some ways. Figure 11 and Figure 12 The cell metal wiring of the memory device 600 shown can be connected to multiple bit lines through bit line contacts located in the outer edge region rather than in the edge region where the first memory cell array MCA1 and the second memory cell array MCA2 are adjacent to each other.

[0095] For example, the first bit line BL1 to the eighth bit line BL8 can each be connected to the cell metal wiring via multiple bit line contacts located in the first edge region ER1, which is not adjacent to the second memory cell array MCA2, and can be connected to the fourth bit line sense amplifier BLSA4, the third bit line sense amplifier BLSA3, the second bit line sense amplifier BLSA2, the first bit line sense amplifier BLSA1, the eighth bit line sense amplifier BLSA8, the seventh bit line sense amplifier BLSA7, the sixth bit line sense amplifier BLSA6, and the fifth bit line sense amplifier BLSA5 via the cell metal wiring.

[0096] The first complementary bit line BLB1 to the eighth complementary bit line BLB8 can each be connected to the cell metal wiring via multiple bit line contacts located at the fourth edge region ER4, which is not adjacent to the first memory cell array MCA1. They can also be connected to the fourth bit line sense amplifier BLSA4, the third bit line sense amplifier BLSA3, the second bit line sense amplifier BLSA2, the first bit line sense amplifier BLSA1, the eighth bit line sense amplifier BLSA8, the seventh bit line sense amplifier BLSA7, the sixth bit line sense amplifier BLSA6, and the fifth bit line sense amplifier BLSA5 via the cell metal wiring.

[0097] Figures 9 to 12 Examples of cell metal wiring and bit line contact connections are shown for purposes of understanding, but wiring and contact connections are not limited thereto, and the connection relationships of cell metal wiring and bit line contacts can be implemented in various ways by memory device integration and process methods without departing from the scope of this disclosure.

[0098] Figure 13 This is a perspective view illustrating an example of a memory device. (Reference) Figure 13 The memory device 700 may include a first memory cell array MCA1, a second memory cell array MCA2 disposed adjacent to the first memory cell array MCA1 in a first direction D1, a first bit line sense amplifier BLSA1 and a second bit line sense amplifier BLSA2 having at least a portion overlapping with the first memory cell array MCA1 in a third direction D3, and a third bit line sense amplifier BLSA3 and a fourth bit line sense amplifier BLSA4 having at least a portion overlapping with the second memory cell array MCA2 in a third direction D3.

[0099] The first memory cell array MCA1 and the second memory cell array MCA2 can be located on the same first substrate SUB1 as described above, and the first bit line sense amplifier BLSA1 to the fourth bit line sense amplifier BLSA4 can be located on the same second substrate SUB2 as described above.

[0100] The first bit line BL1 included in the first memory cell array MCA1 can be connected to the first bit line sense amplifier BLSA1 via a cell metal wiring extending in the first direction D1, and the first complementary bit line BLB1 included in the second memory cell array MCA2 can be connected to the first bit line sense amplifier BLSA1 via a cell metal wiring extending in the first direction D1.

[0101] exist Figure 13 For ease of description and illustration, a pair of bit lines and their corresponding complementary bit lines, as well as the unit metal wiring connecting them, are shown, but additional bit lines, complementary bit lines, and unit metal wiring may be included to connect to the bit line sense amplifier as described herein.

[0102] Figure 14 and Figure 15 This is a cross-sectional view of an example memory device. Specifically, Figure 14 It is along Figure 2 The cross-sectional view of line C-C', and Figure 15 It is along Figure 4 A cross-sectional view of line C-C'. Figure 14 and Figure 15 The memory devices shown have substantially similar wiring connections, differing only in stacking order; therefore, the following references... Figure 14 Describe detailed wiring connections, and these detailed wiring connections will be understood to apply equally to... Figure 15 .

[0103] refer to Figure 14The memory device 800 may include a memory region MR and a peripheral circuit region PCR. The memory region MR may include a first substrate SUB1, a plurality of memory cell arrays MCA1 and MCA2 formed on the first substrate SUB1, and a cell wiring layer CWL for connecting the plurality of memory cell arrays MCA1 and MCA2 to the peripheral circuit region PCR. The peripheral circuit region PCR may include a second substrate SUB2 and a first-line sense amplifier BLSA1 formed on the second substrate SUB2.

[0104] The first memory cell array MCA1 and the second memory cell array MCA2 may each include a plurality of substantially identical cell structures. For example, each memory cell array MCA1 or MCA2 may include a capacitor structure CAP, a capacitor contact 814, a memory channel layer 815, and a gate electrode 816.

[0105] The capacitor structure CAP may include a lower electrode 811, a capacitor dielectric layer 812, and an upper electrode 813. The lower electrode 811 may be electrically connected to a capacitor contact 814. The lower electrode 811 may be formed as a post type extending in a third direction D3. However, the scope of this disclosure is not limited to the cell configuration.

[0106] The memory channel layer 815 can be located on the capacitor contact 814. That is, the memory channel layer 815 can be stacked on the capacitor contact 814 on the third-direction D3.

[0107] The gate electrode 816 can extend from both sides of the memory channel layer 815 in the first direction D1. An interlayer insulating layer can be located between the gate electrode 816 and the memory channel layer 815. The interlayer insulating layer can be formed from a single continuous layer of material or multiple insulating patterns.

[0108] The first memory cell array MCA1 may include a first bit line BL1. The second memory cell array MCA2 may include a first complementary bit line BLB1. The first bit line BL1 and the first complementary bit line BLB1 may extend along a second direction D2.

[0109] The cell routing layer (CWL) can be disposed on the first memory cell array (MCA1) and the second memory cell array (MCA2). The cell routing layer (CWL) may include bit line contacts (BLC) where the bit lines (and complementary bit lines) are connected to the cell metal wiring, cell metal wiring (CMW) for connecting the bit lines (and complementary bit lines) to the peripheral circuit region (PCR), and bit line sense amplifier contacts (BLSAC) where the cell metal wiring (CMW) is connected to the through-silicon via (TSV).

[0110] For example, the first bit line BL1 can be connected to the cell metal wiring CMW via the bit line contact BLC. The first complementary bit line BLB1 can be connected to the cell metal wiring CMW via the bit line contact BLC. The cell metal wiring CMW connected to the first bit line BL1 can be located on the first memory cell array MCA1, and the cell metal wiring CMW connected to the first complementary bit line BLB1 can be located on the first memory cell array MCA1 and the second memory cell array MCA2.

[0111] The unit metal wiring CMW can extend along the second direction D2 and connect to multiple through silicon vias TSV in the peripheral circuit region PCR via bit line readout amplifier contacts BLSAC.

[0112] The peripheral circuit region PCR may include a second substrate SUB2 and a first-line sense amplifier BLSA1 formed thereon. The peripheral circuit region PCR may include an interlayer insulating layer, multiple circuit elements formed on the second substrate SUB2, and multiple metal layers connected to the multiple circuit elements. Each of the multiple metal layers may be implemented using a material with a different resistance.

[0113] Figure 16 This is a block diagram illustrating an example of a computing device. (Reference) Figure 16 The computing device 1000 includes a processor 1010, a memory 1020, a memory controller 1030, a storage device 1040, a communication interface 1050, and a bus 1060. The computing device 1000 may also include other general-purpose components.

[0114] The processor 1010 can control the overall operation of each component of the computing device 1000. The processor 1010 can be implemented using at least one of various processing units such as a central processing unit (CPU), an application processor (AP), or a graphics processing unit (GPU).

[0115] The memory 1020 can store various data and commands. The memory 1020 can be implemented as shown in the reference. Figures 1 to 15 The memory device described.

[0116] The memory controller 1030 can control the transfer of data or commands to and from the memory 1020. In some implementations, the memory controller 1030 can be provided as a separate chip from the processor 1010. In some implementations, the memory controller 1030 can be provided as an internal component of the processor 1010.

[0117] Storage device 1040 can store programs and data in a non-temporary manner. In some implementations, storage device 1040 can be implemented as non-volatile memory.

[0118] The communication interface 1050 can support wired and wireless Internet communication of the computing device 1000. In addition, the communication interface 1050 can support various communication methods other than Internet communication.

[0119] Bus 1060 can provide communication functionality between components of computing device 1000. Bus 1060 may include at least one type of bus depending on the communication protocol between the components.

[0120] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of any claims that may be made. Certain features described in this disclosure within the context of a single implementation can also be implemented in combination within a single implementation. Conversely, various features described in the context of a single implementation can also be implemented individually in multiple implementations or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination can be removed from that combination in some cases, and the combination can be for sub-combinations or variations thereof.

[0121] While various examples have been described in detail above, the scope of this disclosure is not limited thereto, and it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of this disclosure. Furthermore, the foregoing implementations can be implemented by removing some elements, and each example can be implemented in combination with one another.

Claims

1. A memory device, the memory device comprising: A first memory cell array, the first memory cell array including multiple bit lines; A second memory cell array, comprising multiple complementary bit lines corresponding to the multiple bit lines, wherein the second memory cell array is arranged adjacent to the first memory cell array in a first lateral direction; and A first bit line sense amplifier array, the first bit line sense amplifier array at least partially overlapping the first memory cell array along a vertical direction, wherein the first bit line sense amplifier array comprises: A plurality of first bit line sense amplifiers are connected to (i) a plurality of first bit lines among the plurality of bit lines and (ii) a plurality of first complementary bit lines among the plurality of complementary bit lines.

2. The memory device according to claim 1, wherein: The first memory cell array is located on the first substrate, and The first bit line sense amplifier array is located on the second substrate, which is located above the first substrate.

3. The memory device according to claim 2, wherein, The second memory cell array is located on the first substrate.

4. The memory device according to claim 1, further comprising: A second bit-line sense amplifier array, the second bit-line sense amplifier array at least partially overlapping the second memory cell array along the vertical direction, wherein the second bit-line sense amplifier array comprises: A plurality of second bit line sense amplifiers are connected to (i) a plurality of second bit lines that are different from the plurality of first bit lines and (ii) a plurality of second complementary bit lines that are different from the plurality of first complementary bit lines.

5. The memory device according to claim 4, wherein, The second bit line sense amplifier array and the first bit line sense amplifier array are located on the same substrate.

6. The memory device according to claim 4, in, The plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers via a plurality of first engagement contacts located in a first edge region of the first memory cell array, wherein the first edge region is not adjacent to the second memory cell array, and The plurality of second bit lines are connected to a plurality of second cell wirings, wherein the plurality of second cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of second engagement contacts located in a second edge region of the first memory cell array, wherein the second edge region is adjacent to the second memory cell array.

7. The memory device according to claim 6, in, The plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers via a plurality of third bonding contacts located in a third edge region of the second memory cell array, wherein the third edge region is adjacent to the first memory cell array, and The plurality of second complementary bit lines are connected to a plurality of fourth cell wirings, wherein the plurality of fourth cell wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth engagement contacts located in the fourth edge region of the second memory cell array, wherein the fourth edge region is not adjacent to the first memory cell array.

8. The memory device according to claim 7, wherein: The plurality of bit lines and the plurality of complementary bit lines extend in the first lateral direction, and The plurality of first unit wirings, the plurality of second unit wirings, the plurality of third unit wirings, and the plurality of fourth unit wirings extend in the first lateral direction.

9. The memory device of claim 8, further comprising a cell wiring layer located on the first memory cell array and the second memory cell array. in, The plurality of first unit wirings, the plurality of second unit wirings, the plurality of third unit wirings, and the plurality of fourth unit wirings are located in the unit wiring layer.

10. The memory device according to claim 4, wherein: The plurality of first position lines and the plurality of second position lines are arranged alternately along a second lateral direction intersecting the first lateral direction, and The plurality of first complementary bit lines and the plurality of second complementary bit lines are arranged alternately along the second lateral direction.

11. The memory device according to claim 4, wherein: Two of the plurality of first-line sense amplifiers are connected to two adjacent first-line lines among the plurality of first-line lines. One of the plurality of second bit lines is positioned between the two adjacent first bit lines, and The two first-bit line readout amplifiers are spaced apart in the first lateral direction.

12. The memory device according to claim 4, in, The plurality of first bit lines are connected to a plurality of first cell wirings, wherein the plurality of first cell wirings are connected to the plurality of first bit line sense amplifiers via a plurality of first engagement contacts located in a first edge region of the first memory cell array, wherein the first edge region is not adjacent to the second memory cell array, and The plurality of second bit lines are connected to a plurality of second unit wirings, wherein the plurality of second unit wirings are connected to the plurality of second bit line readout amplifiers through a plurality of second engagement contacts located in the first edge region.

13. The memory device according to claim 12, in, The plurality of first complementary bit lines are connected to a plurality of third cell wirings, wherein the plurality of third cell wirings are connected to the plurality of first bit line sense amplifiers via a plurality of third bonding contacts located in a second edge region of the second memory cell array, wherein the second edge region is not adjacent to the first memory cell array, and The plurality of second complementary bit lines are connected to a plurality of fourth unit wirings, wherein the plurality of fourth unit wirings are connected to the plurality of second bit line sense amplifiers through a plurality of fourth engagement contacts located in the second edge region.

14. The memory device of claim 13, wherein: Two adjacent first-position lines from the plurality of first-position lines and two adjacent second-position lines from the plurality of second-position lines are alternately arranged along a second lateral direction intersecting the first lateral direction, and Two adjacent first complementary bit lines from the plurality of first complementary bit lines and two adjacent second complementary bit lines from the plurality of second complementary bit lines are arranged alternately along the second lateral direction.

15. The memory device of claim 14, wherein: Two of the plurality of first-line sense amplifiers are connected to the two adjacent first-line sense amplifiers, and The two first-bit line readout amplifiers are spaced apart in the first lateral direction.

16. A memory device, the memory device comprising: A first substrate, the first substrate including a first block and a second block, the first block including a plurality of first memory cells and a plurality of bit lines connected to the plurality of first memory cells, the second block including a plurality of second memory cells and a plurality of complementary bit lines connected to the plurality of second memory cells; as well as A second substrate, located above the first substrate, includes a bit line sense amplifier. The bit line sense amplifier at least partially overlaps with the first block along the vertical direction. The bit line sense amplifier is connected to (i) the first bit line of the plurality of bit lines and (ii) the first complementary bit line of the plurality of complementary bit lines, wherein the first complementary bit line corresponds to the first bit line.

17. The memory device of claim 16, wherein: The plurality of bit lines are located on the plurality of first memory cells, and the plurality of complementary bit lines are located on the plurality of second memory cells. The first substrate includes a unit wiring layer, the unit wiring layer comprising: The first unit wiring connects the first bit line and the bit line sense amplifier, and... The second unit wiring connects the first complementary bit line and the bit line sense amplifier.

18. The memory device of claim 17, wherein: The first unit wiring overlaps with the first block along the vertical direction, and The second unit wiring overlaps with the first block and the second block along the vertical direction.

19. The memory device according to claim 17, wherein, The second substrate includes a plurality of through-paths connecting the first unit wiring and the second unit wiring to the bit line sense amplifier.

20. A memory device, the memory device comprising: A first memory cell array, the first memory cell array including multiple bit lines; A second memory cell array, comprising multiple complementary bit lines, wherein the second memory cell array is adjacent to the first memory cell array in a first direction; A first bit line sense amplifier array, the first bit line sense amplifier array being located on the first memory cell array and at least partially overlapping the first memory cell array in a vertical direction, wherein the first bit line sense amplifier array is connected to (i) a plurality of first bit lines of the plurality of bit lines and (ii) a plurality of first complementary bit lines of the plurality of complementary bit lines; and A second bit-line sense amplifier array is located on the second memory cell array and at least partially overlaps with the second memory cell array along the vertical direction, wherein the second bit-line sense amplifier array is connected to (i) a plurality of second bit lines that are different from the plurality of first bit lines and (ii) a plurality of second complementary bit lines that are different from the plurality of first complementary bit lines.

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