Non-feedback Buck converter loop and control method

Abstract

The invention discloses a non-feedback Buck converter loop and a control method, which can solve the problem that the precision requirement of a digital-to-analog converter is too high, eliminate the precision loss and stability risk introduced by a feedback network, break through the contradiction between micro-step adjustment and system complexity, and remarkably reduce the system complexity and cost. The loop comprises a reference voltage adjusting module and a digital interface, the reference voltage adjusting module and the digital interface are connected with a digital-to-analog converter, the digital-to-analog converter is connected with an error amplifier, the error amplifier is connected with the SUMN input end of a PWM comparison module, and the output end of the digital-to-analog converter is further sequentially connected with a first resistor and a second resistor. A voltage division point between the first resistor and the second resistor is connected to an SUMN input end of the PWM comparison module, the PWM comparison module is connected with the LOGIC / POWER module, the LOGIC / POWER module is connected with the inductor, the inductor is connected with the error amplifier and an SUMP input end of the PWM comparison module, an SW acquisition point between the LOGIC / POWER module and the inductor is connected with the oblique wave generator, and the oblique wave generator is connected with the SUMP input end of the PWM comparison module.

Description

Technical Field

[0001] This invention relates to the field of switching power supply control technology, specifically to a feedback-free Buck converter loop and control method. Background Technology

[0002] In traditional Buck converter designs, output voltage regulation typically relies on a resistor divider feedback network (composed of resistors R1 and R2) to divide the output voltage into a feedback voltage, which is then compared with a fixed reference voltage at the input of the error amplifier. This feedback voltage is then used to adjust the duty cycle via a PWM modulator to achieve voltage regulation. When output voltage adjustment via a digital interface is required, the conventional approach is to dynamically adjust the reference voltage of the error amplifier using a digital-to-analog converter. However, existing technologies suffer from the following key drawbacks:

[0003] Feedback networks introduce accuracy loss: the accuracy deviation of the voltage divider resistors (typically ±1%) and temperature drift will cause the feedback voltage to deviate from the actual output voltage, directly affecting the output accuracy;

[0004] The step size requirement for digital-to-analog converters is stringent: if the target output voltage adjustment step size is ΔV (e.g., 10mV), then the required step size ΔVDAC of the digital-to-analog converter must satisfy the relationship: ΔVDAC=ΔV×(R2 / (R1+R2)). When the voltage division ratio is 0.5, the required step size of the digital-to-analog converter for a 10mV output voltage step size is only 5mV.

[0005] Design bottlenecks of digital-to-analog converters: The 5mV microstep size places extremely high demands on the resolution, linearity and temperature drift of the digital-to-analog converter, requiring the use of a high-precision digital-to-analog converter with more than 12 bits, which significantly increases chip cost and design complexity;

[0006] Loop compensation burden: The feedback network introduces additional poles / zeros, which need to be offset by Type II / III compensation networks, increasing design difficulty and layout area;

[0007] Noise sensitivity issue: Feedback traces are susceptible to interference from switch noise, requiring strict layout and isolation measures.

[0008] To address the above issues, existing technologies generally employ two solutions. The first is a high-precision digital-to-analog converter (DAC) solution, which uses a 12-bit or higher DAC to generate a micro-step reference voltage. However, this approach suffers from bottlenecks such as high cost, high power consumption, and weak noise immunity. The second solution uses a precision resistor solution, employing 0.1% precision resistors to reduce voltage division errors. However, this approach cannot solve the problem of DAC step size compression, and resistor temperature drift still affects long-term stability.

[0009] The existing architecture has irreconcilable contradictions. First, there is a contradiction between accuracy and cost, with the need for micro-step size conflicting with the accuracy limits of digital-to-analog converters / resistors. Second, the design of compensation networks and noise immunity requirements increase system costs. Finally, there is a contradiction regarding stability, as the feedback network requires complex compensation to maintain loop stability. Summary of the Invention

[0010] To address the problems in the prior art, this invention provides a feedback-free Buck converter loop and control method, which can solve the problem of excessively high accuracy requirements in digital-to-analog converters, eliminate the accuracy loss and stability risks introduced by feedback networks, overcome the contradiction between micro-step adjustment and system complexity, and significantly reduce system complexity and cost.

[0011] To achieve the above objectives, the present invention provides a feedback-free Buck converter loop, including a reference voltage adjustment module and a digital interface. The output terminals of the reference voltage adjustment module and the digital interface are connected to a digital-to-analog converter (DAC). The reference voltage adjustment module controls the DAC to generate a reference voltage controlled by the digital interface. The output terminal of the DAC is connected to the reference voltage input terminal of an error amplifier (EA). The output terminal of the error amplifier (EA), after filtering, is connected to the SUMN input terminal of a PWM comparator module. The output terminal of the DAC is also sequentially connected to a first resistor R1 and a second resistor R2. The voltage divider point between the first resistor R1 and the second resistor R2 is connected to the SUMN input terminal of the PWM comparator module. The output terminal of the PWM comparator module is connected to a LOGIC / POWER module. The LOGIC / POWER module is connected to an inductor L. The output terminal of the inductor L is connected to the output voltage input terminal of the error amplifier (EA) and the SUMP input terminal of the PWM comparator module. The SW acquisition point between the LOGIC / POWER module and the inductor L is connected to a ramp generator. The ramp generator is connected to the SUMP input terminal of the PWM comparator module.

[0012] Furthermore, the reference voltage regulation module includes a bandgap voltage source BG and a linear regulator LDO connected together. The output of the linear regulator LDO is connected to the digital-to-analog converter DAC. The bandgap voltage source BG is used to generate a reference voltage source, and the linear regulator LDO is used to boost the VBG voltage output by the bandgap voltage source BG to a set value.

[0013] Furthermore, the output voltage VOUT of the inductor L is 0.6V to 1.23V, the reference voltage VREF output by the digital-to-analog converter DAC is 0.6V to 1.23V, the maximum VBG voltage output by the bandgap voltage source BG is 1.2V, and the linear regulator LDO boosts the VBG voltage to a maximum of 1.23V.

[0014] Furthermore, the digital interface includes a MIPI interface or an I2C interface.

[0015] Furthermore, the code value of the digital interface controls the voltage divider resistor of the digital-to-analog converter (DAC), so that for every bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is: VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary digital input.

[0016] Furthermore, the digital-to-analog converter (DAC) adopts a segmented resistor architecture, with DNL < ±0.5 LSB in 10 mV steps, where DNL is the local linearity.

[0017] Furthermore, the output stage of the digital-to-analog converter (DAC) is equipped with a buffer, the conversion rate of which is >1V / μs.

[0018] Furthermore, the input terminal of the error amplifier EA is connected to an RC filter, which is an RC low-pass filter with a cutoff frequency fc > 10 × switching frequency.

[0019] Another aspect of the present invention provides a control method for a feedbackless Buck converter loop. The feedbackless Buck converter loop described above includes: a reference voltage adjustment module controlling a digital-to-analog converter (DAC) to generate a reference voltage VREF controlled by a digital interface; an error amplifier EA amplifying the error between the reference voltage VREF and the output voltage VOUT to generate a VEA signal; the VEA signal being divided by the error amplifier EA and then superimposed with the divided voltage VRFEF_DIV of the reference voltage VREF to form the SUMN input signal of the PWM comparator module; the acquired SW signal being processed by a ramp generator to generate a ramp signal; the ramp signal being superimposed on the output voltage VOUT to form the SUMP input signal of the PWM comparator module; and the PWM comparator module comparing the SUMN input signal and the SUMP input signal to control the switching transistor's on / off state, thereby achieving loop control.

[0020] Furthermore, the output voltage VOUT is 0.6V to 1.23V. The reference voltage adjustment module includes a connected bandgap voltage source BG and a linear regulator LDO. The maximum VBG voltage output by the bandgap voltage source BG is 1.2V. The linear regulator LDO boosts the VBG voltage to a maximum of 1.23V, thereby controlling the reference voltage VREF output by the digital-to-analog converter (DAC) to be 0.6V to 1.23V. The code value of the digital interface controls the voltage divider resistor of the DAC, so that for every bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is: VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary digital input.

[0021] Compared with existing technologies, this invention eliminates the feedback network, allowing the output voltage VOUT to be directly connected to the error amplifier EA. This achieves a 1:1 match between the DAC step size and the output voltage VOUT step size, thereby reducing the DAC accuracy requirement by more than 50% and solving the problem of excessively high DAC accuracy requirements. The inherent deviation of the feedback resistor (typically ±1%) and temperature drift cause VFB to deviate from the true VOUT, directly affecting output accuracy. The feedback network introduces additional poles / zeros, requiring complex compensation networks (such as Type II / III) to maintain phase margin, increasing design complexity. The feedback traces are susceptible to switching node (SW) noise interference, requiring strict layout isolation measures. This invention, by directly connecting the output voltage VOUT to the input of the error amplifier EA, completely eliminates voltage divider errors and the burden of the compensation network, while shortening the sensitive signal path, suppressing noise coupling, and eliminating the accuracy loss and stability risks introduced by the feedback network. Existing technologies, in order to meet the requirements of micro-step size, are forced to adopt high-cost solutions (such as 12-bit digital-to-analog converters (DACs) or 0.1% precision resistors), but still cannot solve the problem of DAC step size compression, and resistor temperature drift affects long-term stability. This invention, with its feedback network architecture, significantly reduces system complexity and cost while maintaining 10mV-level micro-step size adjustment capability, overcoming the contradiction between micro-step size adjustment and system complexity, and providing a scalable solution for high-precision digital power supplies.

[0022] The essential difference between this invention and existing technologies lies in its architectural breakthrough: the complete elimination of the feedback network. In traditional solutions, the feedback network is the necessary path connecting the output voltage VOUT and the error amplifier EA. This invention achieves a direct connection between the output voltage VOUT and the non-inverting input of the error amplifier EA, completely removing voltage divider resistors and associated compensation components, such as the R / C components in Type II / III networks. This transformation simplifies the loop structure from "VOUT → voltage divider → VFB → EA" to "VOUT → EA," eliminating the constraint of the voltage divider ratio (α = R2 / (R1 + R2)) on the system gain. Furthermore, the direct control mechanism of the DAC-VREF in this invention contrasts with existing technologies that indirectly affect the output voltage VOUT by adjusting the reference voltage VREF through the digital-to-analog converter (DAC) (requiring α attenuation). This invention uses the output of the digital-to-analog converter (DAC) directly as the reference voltage VREF of the error amplifier EA, establishing a 1:1 mapping relationship between the output voltage VOUT and α, so that the step size of the DAC (ΔVDAC) is completely consistent with the step size of the output voltage VOUT (ΔVOUT) (ΔVDAC = ΔVOUT), breaking through the step size compression limitation of ΔVDAC = ΔVOUT × α in the traditional scheme. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the system loop of the present invention. Detailed Implementation

[0024] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] This invention relates to switching power supply control, specifically voltage regulation loop control of a Buck-type DC-DC converter, and is particularly suitable for scenarios requiring high-precision micro-step output voltage regulation.

[0026] See details Figure 1This invention discloses a feedback-free Buck converter loop, comprising a reference voltage adjustment module and a digital interface. The outputs of the reference voltage adjustment module and the digital interface are connected to a digital-to-analog converter (DAC). The reference voltage adjustment module controls the DAC to generate a reference voltage controlled by the digital interface. The output of the DAC is connected to the reference voltage input of an error amplifier EA. The output of the error amplifier EA, after filtering, is connected to the SUMN input of a PWM comparator module. The output of the DAC is also sequentially connected to a first resistor R1 and a second resistor R2. The voltage divider point between the first resistor R1 and the second resistor R2 is connected to the SUMN input of the PWM comparator module. The output of the PWM comparator module is connected to a LOGIC / POWER module. The LOGIC / POWER module is connected to an inductor L. The output of the inductor L is connected to the output voltage input of the error amplifier EA and the SUMP input of the PWM comparator module. The SW acquisition point between the LOGIC / POWER module and the inductor L is connected to a ramp generator. The ramp generator is connected to the SUMP input of the PWM comparator module.

[0027] Specifically, the reference voltage regulation module includes a bandgap voltage source (BG) and a linear regulator (LDO). The output of the LDO is connected to a digital-to-analog converter (DAC). The bandgap voltage source (BG) generates the reference voltage source, and the LDO boosts the VBG voltage output from the BG to a set value. The output voltage VOUT of the inductor L is 0.6V to 1.23V, the reference voltage VREF output by the DAC is 0.6V to 1.23V, the maximum VBG voltage output by the BG is 1.2V, and the LDO boosts the VBG voltage to a maximum of 1.23V.

[0028] The bandgap voltage source BG of this invention provides a high-precision reference voltage source VBG. A linear regulator LDO boosts the VBG voltage output from the bandgap voltage source BG to meet the required upper limit of 1.23V. A digital-to-analog converter (DAC) converts the digital signal output from MIPI or I2C into an analog signal output, with an output reference voltage VREF of 0.6V to 1.23V. An error amplifier EA compares the sampled output voltage VOUT with the reference voltage VREF. The error amplifier generates a VEA signal, which is then divided by the error amplifier EA and superimposed with the voltage divider VRFEF_DIV generated at the voltage divider point between the first resistor R1 and the second resistor R2 to form the SUMN input signal of the PWM comparator module. The SW signal acquired by the LOGIC / POWER module and inductor L is processed by a ramp generator to produce a ramp signal. This ramp signal is superimposed on the output voltage VOUT to form the SUMP input signal for the PWM comparator module. The PWM comparator module compares the SUMN input signal and the SUMP input signal, outputting a square wave with a variable duty cycle to control the switching transistor's on / off state. The main function of the LOGIC / POWER module is to adjust the on / off timing of the switching devices to maintain stable output voltage and respond to load changes.

[0029] The entire loop uses a V2ACOT architecture, commonly used for high-frequency, fast transient response synchronous buck converter control. The loop is primarily compensated by a ramp signal and an error amplifier EA, with the loop gain mainly influenced by the gain of the error amplifier EA. The system acquires the SW signal, which is then processed by a ramp generator to produce a ramp signal. The ramp generator filters out the DC component of the SW signal, and the DC-filtered ramp signal is superimposed on the output voltage VOUT. The two signals are added together to obtain the input signal SUMP of the PWM comparator module. The error amplifier EA amplifies the error between the output of the digital-to-analog converter (DAC) and the output voltage VOUT, generating a VEA signal. VEA is divided by the error amplifier EA module, resulting in a DC value of only tens of mV. The VEA signal is then superimposed on the divided voltage VRFEF_DIV of the reference voltage VREF generated by the DAC to form the input signal SUMN of the PWM comparator module. SUMN is then compared with SUMP to control the switching transistors, ultimately achieving loop control.

[0030] Specifically, the digital interface includes either a MIPI interface or an I2C interface. The code value of the digital interface controls the voltage divider resistor of the digital-to-analog converter (DAC), so that for each bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is:

[0031] VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary input.

[0032] The present invention increases the step size of the digital-to-analog converter (DAC), while also considering the optimization of the DAC's linearity and the guarantee of dynamic response. The DAC adopts a segmented resistor architecture, with DNL < ±0.5LSB at a 10mV step size, where DNL represents local linearity. A buffer is added to the output stage of the DAC, with a slew rate >1V / μs, to avoid slew rate limitations during reference voltage VREF transitions. Furthermore, the system stability is better compensated by increasing the Miller capacitance inside the error amplifier EA to move the dominant pole to a lower frequency, replacing the original feedback network pole; and by introducing a left-half-plane zero-point cancellation to the power stage pole at the output of the error amplifier EA.

[0033] The circuit architecture of this invention enables the direct-drive design of the error amplifier EA with the output voltage VOUT, supporting a wide input voltage range of 0.6V to 1.23V and ensuring the feasibility of direct connection of the output voltage VOUT. Secondly, since the output voltage VOUT is directly connected to the error amplifier EA, the noise immunity of the error amplifier EA needs to be enhanced. An RC filter is added to the input of the error amplifier EA. The RC filter uses an RC low-pass filter with a cutoff frequency fc > 10 × switching frequency to suppress direct-feedback switching noise.

[0034] The present invention discloses a control method for a feedbackless Buck converter loop, based on the aforementioned feedbackless Buck converter loop, comprising: a reference voltage adjustment module controlling a digital-to-analog converter (DAC) to generate a reference voltage VREF controlled by a digital interface; an error amplifier (EA) amplifying the error between the reference voltage VREF and the output voltage VOUT to generate a VEA signal; the VEA signal being divided by the error amplifier EA and then superimposed with the divided voltage VRFEF_DIV of the reference voltage VREF to form the SUMN input signal of the PWM comparator module; the acquired SW signal being processed by a ramp generator to generate a ramp signal; the ramp signal being superimposed on the output voltage VOUT to form the SUMP input signal of the PWM comparator module; the PWM comparator module comparing the SUMN input signal and the SUMP input signal to control the switching transistor to turn on and off, thereby realizing loop control.

[0035] The output voltage VOUT ranges from 0.6V to 1.23V. The maximum VBG voltage output by the bandgap voltage source BG is 1.2V. The linear regulator LDO boosts the VBG voltage to a maximum of 1.23V, thereby controlling the reference voltage VREF output by the digital-to-analog converter (DAC) to be between 0.6V and 1.23V. The code value of the digital interface controls the voltage divider resistor of the DAC, so that for every bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is: VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary digital input.

[0036] The accuracy and cost advantages of this invention:

[0037] Indicator Conventional scheme (feedback network) The invention Boost amplitude VOUT absolute error ± 3% (resistor divider deviation) ± 0.5% (no divider) 83% improvement DAC resolution ≥ 12 bits (step 5 mV) 10 bits (step 10 mV) 30% cost reduction Temperature drift influence Resistor + DAC double temperature drift DAC temperature drift only Error source reduction 50%

[0038] The system-level performance advantages of this invention:

[0039] Accuracy improvement: Eliminating voltage divider resistor error (±1%→0%), VOUT absolute accuracy improved from ±3% to ±0.5%;

[0040] Enhanced noise immunity: Sensitive nodes reduced by 50% (VFB traces removed), SW noise coupling reduced by 20dB;

[0041] Area reduction: The Type II / III network (5-8 elements) is modified to a single RC network (2 elements), the number of compensation network elements is reduced by 60%, and the layout area is reduced by 30%.

[0042] Scalability Breakthrough:

[0043] Breakthrough in VOUT step size adjustment: Traditional solutions are limited by the feedback network VFB. For example, if VREF = 500mv, then the minimum output of VOUT is greater than 500mv. This architecture can remove this limitation, and VOUT directly reflects the change of VREF.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A feedback-free Buck converter loop, characterized in that, The system includes a reference voltage regulation module and a digital interface. The outputs of the reference voltage regulation module and the digital interface are connected to a digital-to-analog converter (DAC). The reference voltage regulation module controls the DAC to generate a reference voltage controlled by the digital interface. The output of the DAC is connected to the reference voltage input of an error amplifier (EA). The output of the error amplifier (EA), after filtering, is connected to the SUMN input of a PWM comparator module. The output of the DAC is also sequentially connected to a first resistor R1 and a second resistor R2. The voltage divider point between the first resistor R1 and the second resistor R2 is connected to the SUMN input of the PWM comparator module. The output of the PWM comparator module is connected to a LOGIC / POWER module. The LOGIC / POWER module is connected to an inductor L. The output of the inductor L is connected to the output voltage input of the error amplifier (EA) and the SUMP input of the PWM comparator module. The SW acquisition point between the LOGIC / POWER module and the inductor L is connected to a ramp generator. The ramp generator is connected to the SUMP input of the PWM comparator module.

2. The feedback-free Buck converter loop according to claim 1, characterized in that, The reference voltage regulation module includes a bandgap voltage source BG and a linear regulator LDO connected together. The output of the linear regulator LDO is connected to the digital-to-analog converter DAC. The bandgap voltage source BG is used to generate a reference voltage source, and the linear regulator LDO is used to boost the VBG voltage output by the bandgap voltage source BG to a set value.

3. A feedback-free Buck converter loop according to claim 2, characterized in that, The output voltage VOUT of the inductor L is 0.6V to 1.23V, the reference voltage VREF of the digital-to-analog converter DAC is 0.6V to 1.23V, the maximum VBG voltage output by the bandgap voltage source BG is 1.2V, and the linear regulator LDO boosts the VBG voltage to a maximum of 1.23V.

4. A feedback-free Buck converter loop according to claim 3, characterized in that, The digital interface includes a MIPI interface or an I2C interface.

5. A feedback-free Buck converter loop according to claim 4, characterized in that, The code value of the digital interface controls the voltage divider resistor of the digital-to-analog converter (DAC). For each bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is: VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary digital input.

6. A feedback-free Buck converter loop according to claim 1, characterized in that, The digital-to-analog converter (DAC) adopts a segmented resistor architecture, with DNL < ±0.5 LSB in 10 mV steps.

7. A feedback-free Buck converter loop according to claim 1, characterized in that, The output stage of the digital-to-analog converter (DAC) is equipped with a buffer, and the conversion rate of the buffer is >1V / μs.

8. A feedback-free Buck converter loop according to claim 1, characterized in that, The input of the error amplifier EA is connected to an RC filter, which is an RC low-pass filter with a cutoff frequency fc > 10 × switching frequency.

9. A control method for a feedback-free Buck converter loop, characterized in that, A feedback-free Buck converter loop according to any one of claims 1 to 7 includes: a reference voltage regulation module controlling a digital-to-analog converter (DAC) to generate a reference voltage VREF controlled by a digital interface; an error amplifier EA amplifying the error between the reference voltage VREF and the output voltage VOUT to generate a VEA signal; the VEA signal being divided by the error amplifier EA and then superimposed with the divided voltage VRFEF_DIV of the reference voltage VREF to form the SUMN input signal of the PWM comparator module; the acquired SW signal being passed through a ramp generator to generate a ramp signal; the ramp signal being superimposed on the output voltage VOUT to form the SUMP input signal of the PWM comparator module; the PWM comparator module comparing the SUMN input signal and the SUMP input signal to control the switching transistor to turn on and off, thereby realizing the control of the loop.

10. The control method for a feedback-free Buck converter loop according to claim 9, characterized in that, The output voltage VOUT is 0.6V to 1.23V. The reference voltage adjustment module includes a bandgap voltage source BG and a linear regulator LDO. The maximum VBG voltage output by the bandgap voltage source BG is 1.2V. The linear regulator LDO boosts the VBG voltage to a maximum of 1.23V, thereby controlling the reference voltage VREF output by the digital-to-analog converter DAC to be 0.6V to 1.23V. The code value of the digital interface controls the voltage divider resistor of the digital-to-analog converter (DAC). For each bit increase in the code value, the reference voltage VREF output by the DAC increases by 10mV. The corresponding expression for the output voltage VOUT is: VOUT = 0.6V + D<0:5> * 10mV, where D<0:5> represents a 6-bit binary digital input.

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