Motor controller, power system and vehicle

Abstract

The invention provides a motor controller, a power system and a vehicle, and relates to the technical field of motors, the motor controller comprises a direct current bus capacitor unit, the direct current bus capacitor unit comprises a first capacitor and a second capacitor which are connected in series, the first capacitor and the second capacitor are adjacent, and at least parts of the first capacitor and the second capacitor are oppositely arranged; the first connecting bar assembly is used for connecting the first capacitor and the second capacitor in series; and the power unit is electrically connected with the first connecting bar assembly. According to the motor controller, the internal stray inductance of the motor controller can be reduced, the working efficiency of the system is improved, and the model selection cost of the bus capacitor and the power module is reduced.

Description

Technical Field

[0001] This application relates to the field of motor technology, and more particularly to a motor controller, power system, and vehicle. Background Technology

[0002] The application of three-level power topology in the electric drive system of new energy vehicles can improve the working efficiency of motor controllers, motors and electric drive systems.

[0003] Currently, most motor controllers using three-level power topologies do not fully consider the impact of factors such as the size and shape of the bus capacitor and the interface position between the bus capacitor and the power module on the interconnection and transfer between the power module and the bus capacitor during the design process. This results in a large stray inductance in the power commutation circuit. This stray inductance is often the main reason for the efficiency deviation between actual testing and theoretical / simulation analysis of the three-level power topology. It may also lead to large turn-off stress when the power module is switched on and off, as well as high selection costs for the bus capacitor and the power module. Summary of the Invention

[0004] In view of the above problems, this application provides a motor controller, a power system, and a vehicle, which can reduce the internal inductance of the motor controller, improve the system efficiency, and reduce the selection cost of bus capacitors and power modules.

[0005] In a first aspect, this application provides a motor controller, comprising: a DC bus capacitor unit, including: a first capacitor and a second capacitor connected in series, the first capacitor and the second capacitor being adjacent and at least partially opposite to each other; a first connecting bus assembly for connecting the first capacitor and the second capacitor in series; and a power unit electrically connected to the first connecting bus assembly.

[0006] In some embodiments, the first connection bus assembly includes: a first positive bus connected to the positive terminal of the first capacitor; a first intermediate bus connected to the intermediate terminal of the first capacitor and the intermediate terminal of the second capacitor respectively; a first negative bus connected to the negative terminal of the second capacitor; the first positive bus, the first intermediate bus and the first negative bus are each provided with a first terminal, and a plurality of the first terminals are stacked to form a first external terminal, and the first external terminal is electrically connected to the power unit.

[0007] In some embodiments, the first capacitor and the second capacitor are arranged side by side and opposite to each other along a first direction.

[0008] In some embodiments, the intermediate electrode of the first capacitor and the intermediate electrode of the second capacitor are located on different sides along a third direction, which is perpendicular to the first direction; the first intermediate row includes a first intermediate connecting portion and a second intermediate connecting portion, the first intermediate connecting portion is connected to the intermediate electrode of the first capacitor and overlaps with the first negative row, and the second intermediate connecting portion is connected to the intermediate electrode of the second capacitor and overlaps with the first positive row.

[0009] In some embodiments, a plurality of the first terminals are stacked on the side of the second capacitor opposite to the first capacitor along a second direction to form the first external terminal.

[0010] In some embodiments, the first capacitor and the second capacitor are arranged side by side and opposite to each other along a second direction, which is perpendicular to the first direction.

[0011] In some embodiments, the intermediate electrode of the first capacitor and the intermediate electrode of the second capacitor are located on different sides along a third direction; the first intermediate row includes a first intermediate connecting portion and a second intermediate connecting portion, the first intermediate connecting portion is connected to the intermediate electrode of the first capacitor and overlaps with the first negative row, and the second intermediate connecting portion is connected to the intermediate electrode of the second capacitor and overlaps with the first positive row.

[0012] In some embodiments, a plurality of the first terminals are stacked on the side of the second capacitor opposite to the first capacitor along a second direction to form the first external terminal.

[0013] In some embodiments, the intermediate terminals of the first capacitor and the second capacitor are located on the same side along a third direction; the first negative bus includes a negative bus body and a first negative terminal connection portion, the negative bus body and the first negative terminal connection portion being located on opposite sides of the DC bus capacitor unit along a third direction; the first intermediate bus includes a first intermediate connection portion and a second intermediate connection portion, the first intermediate connection portion being connected to the intermediate terminal of the first capacitor and overlapping with the negative bus body, the second intermediate connection portion being connected to the intermediate terminal of the second capacitor and overlapping with the negative bus body; the first negative terminal connection portion is connected to the negative terminal of the second capacitor and is arranged side by side with the first positive bus along a second direction.

[0014] In some embodiments, a plurality of the first terminals are stacked between the first capacitor and the second capacitor to form the first external terminal.

[0015] In some embodiments, the first capacitor and the second capacitor are arranged along a third direction and are positioned opposite each other, with the third direction, the second direction and the first direction being perpendicular to each other.

[0016] In some embodiments, the intermediate electrodes of the first capacitor and the second capacitor are disposed opposite each other along a third direction, and the positive electrode of the first capacitor and the negative electrode of the second capacitor are disposed away from each other along a third direction. The first intermediate row includes a first intermediate connecting portion and a second intermediate connecting portion, the first intermediate connecting portion being connected to the intermediate electrode of the first capacitor, and the second intermediate connecting portion being connected to the intermediate electrode of the second capacitor.

[0017] In some embodiments, a plurality of the first terminals are stacked between the first capacitor and the second capacitor to form the first external terminal.

[0018] In some embodiments, the intermediate electrode of the first capacitor and the intermediate electrode of the second capacitor are located on different sides of each along a third direction; there are two first intermediate rows, one of which is connected to the intermediate electrode of the first capacitor and the other is connected to the intermediate electrode of the second capacitor, and the first terminals of the first positive row, the first negative row and the two first intermediate rows are stacked between the first capacitor and the second capacitor.

[0019] In some embodiments, the first capacitor and the second capacitor are staggered by a distance of 0-15 mm in a direction perpendicular to the arrangement direction.

[0020] In some embodiments, the DC bus capacitor unit further includes a third capacitor, the positive terminal of which is connected to the first positive busbar and the negative terminal of which is connected to the first negative busbar, so that the third capacitor is connected in parallel with the branch containing the first capacitor and the second capacitor.

[0021] In some embodiments, the third capacitor is located on the same side of the first capacitor and the second capacitor, or the third capacitor is located on the side of one of the first capacitor and the second capacitor that is away from the other.

[0022] In some embodiments, the power unit includes: a power module; a second connector assembly for electrical connection to the first connector assembly; and a three-phase output assembly for connection to a motor.

[0023] In some embodiments, the power module and the DC bus capacitor unit are stacked in a third direction and arranged opposite each other, or the power module and the DC bus capacitor unit are arranged side by side along a second direction; and the second connection bar assembly is disposed on the side of the power module facing the first external terminal of the first connection bar assembly.

[0024] In some embodiments, the three-phase output component and the second connection bus component are located on opposite sides of the power module along a second direction.

[0025] In some embodiments, the second connection bar assembly is in three groups, each group corresponding to one phase of the three phases. The three groups of the second connection bar assembly are arranged along a first direction. Each group includes a second positive bar, a second middle bar, and a second negative bar. The second positive bar corresponds to and is electrically connected to the first positive bar, the second middle bar corresponds to and is electrically connected to the first middle bar, and the second negative bar corresponds to and is electrically connected to the first negative bar.

[0026] In some embodiments, the second positive row, the second middle row, and the second negative row all include second terminals, and a plurality of second terminals belonging to the same group are arranged side by side along a first direction.

[0027] In some embodiments, the second positive row, the second middle row, and the second negative row each include a second terminal, and a plurality of second terminals belonging to the same group are stacked along a third direction; and the arrangement of the plurality of second terminals belonging to the same group is the same as the arrangement of the plurality of first terminals in the first external terminals.

[0028] Secondly, this application provides a power system, including: a power battery, a motor, and the aforementioned motor controller, wherein the motor controller is electrically connected to the power battery and the motor respectively.

[0029] Thirdly, this application provides a vehicle including the aforementioned power system or the aforementioned motor controller.

[0030] The motor controller, power system, and vehicle of this application arrange the first and second capacitors of the DC bus capacitor unit adjacent to each other, which can shorten the distance between the first and second capacitors and help to shorten the length of the first connection row assembly, thereby reducing the parasitic inductance inside the DC bus capacitor unit and reducing the overall inductance of the three-level topology power circulating circuit. Furthermore, arranging the first and second capacitors at least partially opposite each other helps to make the conductor lengths between the first external terminal and each electrode of the first and second capacitors as uniform as possible, improves the symmetry of different commutation circuits, reduces the difference in inductance between different circuits, and improves the current sharing between capacitors. This comprehensively improves the working efficiency of the motor controller system, optimizes the switching characteristics and drive parameters of the power module, and also helps to reduce the selection cost of the bus capacitor and power module. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 The circuit diagram is for a three-level power topology 1;

[0033] Figure 2 The circuit diagram is for a three-level power topology 2;

[0034] Figure 3 This is a structural schematic diagram of the DC bus capacitor unit of Embodiment 1 of this application from one angle.

[0035] Figure 4 This is an exploded view of the DC bus capacitor unit of Embodiment 1 of this application;

[0036] Figure 5 This is one of the schematic diagrams showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 1 of this application;

[0037] Figure 6 This is the second schematic diagram showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 1 of this application;

[0038] Figure 7 This is a schematic diagram of the DC bus capacitor unit of Embodiment 2 of this application from one angle;

[0039] Figure 8 This is an exploded view of the DC bus capacitor unit of Embodiment 2 of this application;

[0040] Figure 9 This is one of the schematic diagrams showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 2 of this application;

[0041] Figure 10 This is the second schematic diagram showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 2 of this application;

[0042] Figure 11 This is a schematic diagram of the DC bus capacitor unit of Embodiment 3 of this application from one angle;

[0043] Figure 12 This is an exploded view of the DC bus capacitor unit of Embodiment 3 of this application;

[0044] Figure 13 This is one of the schematic diagrams showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 3 of this application;

[0045] Figure 14 This is the second schematic diagram showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 3 of this application;

[0046] Figure 15 This is a schematic diagram of the DC bus capacitor unit of Embodiment 4 of this application from one angle;

[0047] Figure 16 This is an exploded view of the DC bus capacitor unit of Embodiment 4 of this application;

[0048] Figure 17 This is one of the schematic diagrams showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 4 of this application;

[0049] Figure 18 This is the second schematic diagram showing the relative positions of the DC bus capacitor unit and the power unit in Embodiment 4 of this application;

[0050] Figure 19 This is a top view of the power unit according to Embodiment 1 of this application;

[0051] Figure 20 This is a top view of the power unit according to Embodiment 2 of this application;

[0052] Figure 21 This is a side view of the power unit according to Embodiment 3 of this application;

[0053] Figure 22 This is a side view of the power unit of Embodiment 4 of this application.

[0054] Explanation of reference numerals in the attached figures:

[0055] 100-Motor Controller;

[0056] 1-DC bus capacitor unit;

[0057] 11 - First capacitor; 12 - Second capacitor; 13 - Third capacitor;

[0058] 14-First connecting row assembly;

[0059] 141-First positive electrode; 1411-First positive electrode connection; 1412-Second positive electrode connection;

[0060] 142-First intermediate row; 1421-First intermediate connecting part; 1422-Second intermediate connecting part;

[0061] 143-First negative electrode; 1431-First negative electrode connection; 1432-Second negative electrode connection;

[0062] 144 - First external terminal; 1441 - First terminal;

[0063] 2-Power unit;

[0064] 21-Power Module;

[0065] 22-Second connecting row assembly; 221-Second positive row; 222-Second intermediate row; 223-Second negative row; 224-Second external terminal; 2241-Second terminal;

[0066] 23-Three-phase output components;

[0067] 200-Power Battery;

[0068] 300-Motor. Detailed Implementation

[0069] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0070] The application of three-level power topology in the electric drive system of new energy vehicles can improve the working efficiency of motor controllers, motors, and the electric drive system. Currently, most motor controllers using three-level power topology do not fully consider the impact of factors such as the size and shape of the bus capacitor and the interface position between the bus capacitor and the power module on the interconnection and transfer between the power module and the bus capacitor during actual engineering design. This results in a large stray inductance in the power commutation circuit. This stray inductance is often the main reason for the efficiency deviation between actual testing and theoretical / simulation analysis of the three-level power topology, and may also lead to large turn-off stress when the power module switches, as well as high selection costs for the bus capacitor and power module.

[0071] First, refer to Figure 1 and Figure 2 The two three-level power topologies provided mainly include: a power battery 200, a DC bus capacitor unit 1, a transfer unit, a three-level power module 21, and a motor 300. The power battery can be a high-voltage battery pack. The transfer unit is used to realize the electrical connection between the bus capacitor of the DC bus capacitor unit 1 and the power module 21. The motor 300 can be a three-phase asynchronous AC motor or other motors.

[0072] in, Figure 1To support simultaneous switching between two-level and three-level operating modes, a three-level power topology 1 (hereinafter referred to as Topology 1) is constructed. In Topology 1, the DC bus capacitor unit 1 includes two bus capacitors: a first capacitor 11 (i.e., C1) and a second capacitor 12 (i.e., C2). C1 and C2 are connected in series. The two bus capacitors are connected to a first connection bus assembly 14. The power module 21 is connected to a second connection bus assembly 22. The first connection bus assembly 14 has a first external terminal 144 (including terminals P1, M1, and N1). The second connection bus assembly 22 has a second external terminal 224 (including terminals P2, M2, and N2). The adapter unit includes the first external terminal 144 and the second external terminal 224. The power module 21 includes multiple power devices (vertical tubes: Tx1, Tx4; horizontal tubes: Tx2, Tx3, where x = 1, 2, 3).

[0073] Wherein, L1 is the equivalent parasitic inductance of the first capacitor 11, including the parasitic inductance of the first capacitor 11 itself, and the parasitic inductance of the first connecting bus assembly 14 connected to the first capacitor 11 (such as the inductance of the conductor between the positive terminal of the first capacitor 11 and the P1 terminal, and the parasitic inductance of the conductor between the negative terminal (hereinafter referred to as the intermediate terminal) of the first capacitor 11 and the M1 terminal); L2 is the equivalent parasitic inductance of the second capacitor 12, including the parasitic inductance of the second capacitor 12 itself, and the parasitic inductance of the first connecting bus assembly 14 connected to the second capacitor 12 (such as the inductance of the conductor between the positive terminal (hereinafter referred to as the intermediate terminal) of the second capacitor 12 and the M1 terminal, and the parasitic inductance of the conductor between the negative terminal of the second capacitor 12 and the N1 terminal); and L1 and L2 are the parasitic inductances inside the DC bus capacitor unit 1.

[0074] L5 is the equivalent parasitic inductance between terminals P1 and P2, L6 is the equivalent parasitic inductance between terminals M1 and M2, L7 is the equivalent parasitic inductance between terminals N1 and N2, and L5, L6, and L7 are the equivalent parasitic inductances of the adapter unit.

[0075] L4 is the equivalent parasitic inductance of the three-level power module 21.

[0076] When the motor controller 100 of topology 1 operates in three-level mode, its power circuit and corresponding inductance mainly exist in the following forms: ①Loop1: L1+L5+L4+L6; or ②Loop2: L2+L7+L4+L6; or ③Loop3: L1+L5+L4+L7+L2.

[0077] In other words, for Topology 1 to achieve the maximum efficiency improvement, it should ensure that the parasitic inductance of the aforementioned components is minimized: the parasitic inductance (L1 and L2) inside the DC bus capacitor unit 1 is minimized, the interconnection parasitic inductance (L5, L6, and L7) of the transfer unit is minimized, and the parasitic inductance (L4) inside the power module 21 is minimized. When the motor controller 100 operates in two-level mode, its power circuit parasitic inductance is the same as that of the third type in three-level mode.

[0078] Figure 2 For another three-level power topology 2 (hereinafter referred to as topology 2), compared with topology 1, the DC bus capacitor unit 1 also includes a third capacitor 13 (i.e., C3), where L3 is the equivalent parasitic inductance of C3; since C3 is connected in parallel with the series branch of C1 and C2, in the actual circuit, it is necessary to add a connection between the two branches, that is, the positive terminal of C3 is connected to the positive terminal of C1, and the negative terminal of C3 is connected to the negative terminal of C2 (L8 is the equivalent parasitic inductance of the conductor of the corresponding connection part).

[0079] It should be noted that, due to the introduction of the third capacitor 13, when the motor controller 100 operates in two-level mode, C3 can serve as its main supporting capacitor, meaning that C3 is much larger than the capacitance of C1 and C2 connected in series. C3 can also serve as a filter capacitor in three-level mode. This design has a good effect on controlling the DC bus ripple voltage, and the overall size and capacitance of the DC bus capacitor unit 1 can be smaller than those of Topology 1. Meanwhile, in practical operation, C1 and C2, besides serving as supporting capacitors in three-level mode, can also serve as pulse capacitors in two-level mode (providing a smaller power commutation loop for power devices). Therefore, the minimum inductance design of the power loop in Topology 2 is roughly the same as in Topology 1, namely, reducing the parasitic inductance of C1, C2, power module 21, and the junction of DC bus capacitor unit 1 and power module 21. That is, its power commutation loop and inductance mainly exist in the following forms: ① Loop 1: L1+L5+L4+L6; or ② Loop 2: L2+L7+L4+L6; or ③

[0080] Loop3: L1+L5+L4+L7+L2; and ④Loop4: L3+L8+L5+L4+L7. Considering that Loop4 accounts for a very small proportion in the commutation circuit, it can be ignored here. When the motor controller 100 operates in two-level mode, its power commutation circuit and its inductance are the same as those in the ③ and ④ types of the three-level mode. However, since L1 and L2 are much smaller than L3, and L5+L7 is much smaller than L8+L5+L7, the power commutation in the two-level mode is mainly of form ③. Therefore, in the design of inductance, the power commutation circuit of topology 2 in the two-level operating mode can focus on ③Loop3.

[0081] In other words, if topology 2 is to meet the goal of maximizing efficiency improvement, it should ensure that: the parasitic inductance (L1 and L2) inside the DC bus capacitor unit 1 is minimized, the interconnection and transfer stray inductance (L5, L6 and L7) of the transfer unit is minimized, and the stray inductance (L4) inside the power module 21 is minimized, which is consistent with topology 1.

[0082] In view of this, this application provides a motor controller 100, a power system, and a vehicle. By arranging the first capacitor 11 and the second capacitor 12 of the DC bus capacitor unit 1 adjacently, the distance between the first capacitor 11 and the second capacitor 12 can be shortened, which is beneficial to shortening the length of the first connection bus assembly 14, thereby reducing the parasitic inductance inside the DC bus capacitor unit 1 and reducing the overall inductance of the three-level topology power loop. Furthermore, symmetrically arranging the first capacitor 11 and the second capacitor 12 is beneficial to make the conductor length between the first external terminal 144 and each electrode of the first capacitor 11 and the second capacitor 12 as uniform as possible, making the symmetry of different commutation loops (i.e., Loop 1 and Loop 2) better, reducing the difference in inductance between different loops, thereby improving the current sharing between capacitors, thus comprehensively improving the system operating efficiency of the motor controller 100, optimizing the switching characteristics and drive parameters of the power module 21, and also helping to reduce the selection cost of the bus capacitor and the power module 21.

[0083] Specifically, refer to Figures 3-18 In this embodiment, the motor controller 100 is a three-level topology motor controller 100. The motor controller 100 may include a DC bus capacitor unit 1 and a power unit 2.

[0084] The DC bus capacitor unit 1 may include multiple bus capacitors and a first connection bus assembly 14. The multiple bus capacitors include a first capacitor 11 and a second capacitor 12, which are connected in series.

[0085] The first capacitor 11 may include one or more core packages, and the second capacitor 12 may include one or more core packages. "Multiple" means two or more. This embodiment does not limit this. The number of core packages of the first capacitor 11 and the second capacitor 12 can be reasonably selected according to the capacitance requirements.

[0086] The first capacitor 11 and the second capacitor 12 can be set horizontally (i.e., the two electrodes of the bus capacitor are located on both sides of the bus capacitor in the horizontal direction) or vertically (i.e., the two electrodes are located on both sides of the bus capacitor in the vertical direction).

[0087] For ease of explanation, the following description will use the example of the first capacitor 11 and the second capacitor 12 each including a core package, and the first capacitor 11 and the second capacitor 12 being arranged vertically.

[0088] The first capacitor 11 and the second capacitor 12 are arranged adjacent to each other and at least partially opposite each other in the mounting space of the DC bus capacitor unit 1. For example, the first capacitor 11 and the second capacitor 12 can be adjacent to each other and at least partially opposite each other along a first direction (i.e., Y direction); or, the first capacitor 11 and the second capacitor 12 can be adjacent to each other and at least partially opposite each other along a second direction (i.e., X direction); or, the first capacitor 11 and the second capacitor 12 can be adjacent to each other and at least partially opposite each other along a third direction (i.e., Z direction). The first direction, the second direction and the third direction are perpendicular to each other. The first connecting bus assembly 14 can be used to connect the first capacitor 11 and the second capacitor 12 in series and then electrically connect them to the power unit 2.

[0089] The adjacent arrangement here refers to the absence of other electronic components between the first capacitor 11 and the second capacitor 12, so as to minimize the distance between the first capacitor 11 and the second capacitor 12. This helps to shorten the length of the first connection bus assembly 14 between the first external terminal 144 and each bus capacitor, thereby reducing the parasitic inductance L1 and L2 inside the DC bus capacitor unit 1 in the above three-level power topology. Of course, the gap between the first capacitor 11 and the second capacitor 12 can be set or they can be arranged closely according to the actual installation space.

[0090] The first capacitor 11 and the second capacitor 12 are at least partially opposite each other. They can be arranged symmetrically along their arrangement direction (i.e., the first direction, the second direction, or the third direction); or the main structures of the first capacitor 11 and the second capacitor 12 can be opposite each other along their arrangement direction, while their respective partial structures can be offset along directions perpendicular to the arrangement direction. For example, taking the arrangement of the first capacitor 11 and the second capacitor 12 along the first direction as an example, the first capacitor 11 and the second capacitor 12 can be completely symmetrical in the first direction, or they can be offset by a certain distance in the second direction and the third direction, and the offset area is much smaller than the area where they are opposite each other.

[0091] Optionally, the area of ​​the overlapping region of the projections of the first capacitor 11 and the second capacitor 12 in their respective arrangement directions can account for 80%-100% of their respective projected areas, where 100% indicates that the first capacitor 11 and the second capacitor 12 are symmetrical in their arrangement directions. It is understood that, where the installation space of the DC bus capacitor unit 1 allows, the first capacitor 11 and the second capacitor 12 should be as symmetrical as possible.

[0092] This configuration helps to make the conductor lengths between the first external terminal 144 and the electrodes of the first capacitor 11 and the second capacitor 12 as uniform as possible, improves the symmetry of different commutation loops (i.e., Loop 1 and Loop 2), reduces the difference in inductance between different loops, and improves current sharing. Of course, the wiring method of the first connecting bus assembly 14 can be flexibly configured as needed.

[0093] The power unit 2 may include a second connection bus assembly 22 and a power module 21. The second connection bus assembly 22 may be electrically connected to the first connection bus assembly 14 to realize the electrical connection between the power module 21 and the bus capacitor.

[0094] In this embodiment, the motor controller 100 arranges the first capacitor 11 and the second capacitor 12 of the DC bus capacitor unit 1 adjacently, which shortens the distance between the first capacitor 11 and the second capacitor 12. This helps to shorten the length of the first connection bus assembly 14, thereby reducing the parasitic inductance of the bus capacitor section and reducing the overall inductance of the three-level topology power loop. Arranging the first capacitor 11 and the second capacitor 12 at least partially opposite each other helps to make the conductor length between the first external terminal 144 and each electrode of the first capacitor 11 and the second capacitor 12 as uniform as possible, making the symmetry of different commutation loops (i.e., Loop 1 and Loop 2) better, reducing the difference in inductance between different loops, and improving the current sharing between capacitors. This comprehensively improves the system efficiency of the motor controller 100, optimizes the switching characteristics and drive parameters of the power module 21, and also helps to reduce the selection cost of the bus capacitor and the power module 21.

[0095] In some embodiments, combined with Figure 4 , Figure 8 , Figure 12 and Figure 16 The first connection bus assembly 14 may include a first positive bus 141, a first intermediate bus 142, and a first negative bus 143. Any one of the first positive bus 141, the first intermediate bus 142, and the first negative bus 143 may be a connection bus made of copper, aluminum, or other conductive materials. The first positive bus 141 is connected to the positive terminal of the first capacitor 11; the first intermediate bus 142 is connected to the intermediate terminals of the first capacitor 11 and the second capacitor 12, respectively; and the first negative bus 143 is connected to the negative terminal of the second capacitor 12. The first positive bus 141, the first intermediate bus 142, and the first negative bus 143 are each provided with a first terminal 1441 (i.e., the aforementioned terminals P1, M1, and N1). Multiple first terminals 1441 are stacked to form a first external terminal 144 electrically connected to the power unit 2. In other words, the first connection bus assembly 14 in this embodiment is a stacked busbar. Optionally, the portion of each connecting row (including the first positive row 141, the first intermediate row 142, and the first negative row 143) that is connected to the bus capacitor can be provided with a hollow structure or a continuous surface.

[0096] Understandably, on the one hand, since the first intermediate row 142 can interconnect the intermediate poles of the first capacitor 11 and the second intermediate row 222, when the first capacitor 11 and the second capacitor 12 are arranged adjacently and at least partially opposite each other, it is beneficial to shorten the length of the first intermediate row 142, thereby reducing the parasitic inductance of the first intermediate row 142. On the other hand, by stacking multiple first terminals 1441, the parasitic inductance between any two adjacent first terminals 1441 can be reduced, thereby reducing the overall parasitic inductance of the first connection row assembly 14, which is beneficial to reduce the parasitic inductance inside the DC bus capacitor unit 1.

[0097] In some embodiments, combined with Figures 3-6 The first capacitor 11 and the second capacitor 12 are along the first direction (i.e. Figure 4 The capacitors are arranged horizontally side-by-side and symmetrically in the Y-direction. The middle electrode of the first capacitor 11 and the middle electrode of the second capacitor 12 are respectively located along their respective third directions (i.e., Figure 3 In the Z direction, the upper end of the first capacitor 11 is the positive terminal (P terminal) and the lower end is the middle terminal (M terminal), and the upper end of the second capacitor 12 is the middle terminal (M terminal) and the lower end is the negative terminal (N terminal).

[0098] The first intermediate row 142 may include a first intermediate connection portion 1421 and a second intermediate connection portion 1422. The first intermediate connection portion 1421 extends to the bottom end of the first capacitor 11 to connect with the middle electrode of the first capacitor 11. The first intermediate connection portion 1421 is also superimposed with the first negative row 143 to reduce the stray inductance between the first intermediate row 142 and the first negative row 143. The second intermediate connection portion 1422 extends to the top end of the second capacitor 12 to connect with the middle electrode of the second capacitor 12. The second intermediate connection portion 1422 is superimposed with the first positive row 141 to reduce the stray inductance between the first intermediate row 142 and the first positive row 141.

[0099] Furthermore, to achieve the connection between the first intermediate connection portion 1421 and the second intermediate connection portion 1422, the first intermediate row 142 also includes a first intermediate transition connection portion. Along the first direction, the first intermediate transition connection portion is located between the first capacitor 11 and the second capacitor 12. The first intermediate transition connection portion extends in the third direction and its height is approximately equal to the height of the first capacitor 11 and the second capacitor 12. The two ends of the first intermediate transition connection portion are respectively connected to the first intermediate connection portion 1421 and the second intermediate connection portion 1422, thereby realizing the interconnection between the first capacitor 11 and the second capacitor 12 and ensuring that the length of the first intermediate transition connection portion is minimized, so as to reduce the parasitic inductance of the first intermediate row 142 itself and reduce the overall inductance of the first connection row assembly 14.

[0100] Understandably, when both the first capacitor 11 and the second capacitor 12 include multiple cores, the multiple cores of the first capacitor 11 and the second capacitor 12 are arranged along the second direction, the first intermediate connection part 1421 is simultaneously connected to the intermediate electrode of the multiple cores of the first capacitor 11, and the second intermediate connection part 1422 is simultaneously connected to the intermediate electrode of the multiple cores of the second capacitor 12.

[0101] By adopting the above arrangement, the parasitic inductance of the first connection row assembly 14 can be reduced, which is beneficial to reducing the parasitic inductances L1 and L2 inside the DC bus capacitor unit 1.

[0102] In some embodiments, a plurality of first terminals 1441 are stacked on the side of the second capacitor 12 facing away from the first capacitor 11 along a second direction to form a first external terminal 144. Exemplarily, the plurality of first terminals 1441 may extend along a third direction and be stacked in a PMN configuration along the second direction to form a first external terminal 144 with a line exiting along the third direction; alternatively, the plurality of first terminals 1441 may also extend along the second direction and be stacked in a PMN configuration along the third direction to form a first external terminal 144 with a line exiting along the second direction. Of course, this application is not limited to these embodiments, and the stacking method and line exit direction of the plurality of first terminals 1441 can be flexibly adjusted according to the setting position of the power module 21. Thus, by stacking the plurality of first terminals 1441, it is beneficial to reduce the parasitic inductance between the terminals, thereby further reducing the parasitic inductance of the first connection bus assembly 14.

[0103] In some embodiments, reference Figures 7-10 The first capacitor 11 and the second capacitor 12 are along the second direction (i.e. Figure 8 The capacitors are arranged horizontally side by side (in the X direction) and positioned relative to each other. The middle electrode of the first capacitor 11 and the middle electrode of the second capacitor 12 are located on different sides of each other in the third direction. The upper end of the first capacitor 11 is the positive electrode (P electrode) and the lower end is the middle electrode (M electrode). The upper end of the second capacitor 12 is the middle electrode (M electrode) and the lower end is the negative electrode (N electrode).

[0104] The first intermediate row 142 includes a first intermediate connection portion 1421 and a second intermediate connection portion 1422. The first intermediate connection portion 1421 extends to the bottom end of the first capacitor 11 to connect with the intermediate electrode of the first capacitor 11. The first intermediate connection portion 1421 is also superimposed with the first negative row 143 to reduce the stray inductance between the first intermediate row 142 and the first negative row 143. The second intermediate connection portion 1422 extends to the top end of the second capacitor 12 to connect with the intermediate electrode of the second capacitor 12. Furthermore, the second intermediate connection portion 1422 is superimposed with the first positive row 141 to reduce the stray inductance between the first intermediate row 142 and the first positive row 141.

[0105] Along the second direction, the first intermediate transition connection is located between the first capacitor 11 and the second capacitor 12. The first intermediate transition connection extends along the third direction and its height is approximately equal to the height of the first capacitor 11 and the second capacitor 12. The two ends of the first intermediate transition connection are connected to the first intermediate connection 1421 and the second intermediate connection 1422, respectively, thereby realizing the interconnection between the first capacitor 11 and the second capacitor 12 and ensuring that the length of the first intermediate transition connection is minimized, so as to reduce the parasitic inductance of the first intermediate row 142 itself and reduce the overall inductance of the first connection row assembly 14.

[0106] Understandably, when both the first capacitor 11 and the second capacitor 12 include multiple core packages, the multiple core packages of the first capacitor 11 and the second capacitor 12 are arranged along the first direction, the first intermediate connection part 1421 is simultaneously connected to the intermediate electrode of the multiple core packages of the first capacitor 11, and the second intermediate connection part 1422 is simultaneously connected to the intermediate electrode of the multiple core packages of the second capacitor 12.

[0107] By adopting the above arrangement, the parasitic inductance of the first connection row assembly 14 can be reduced, which is beneficial to reducing the parasitic inductances L1 and L2 inside the DC bus capacitor unit 1.

[0108] In some embodiments, a plurality of first terminals 1441 are stacked on the side of the second capacitor 12 facing away from the first capacitor 11 along a second direction to form a first external terminal 144. Exemplarily, the plurality of first terminals 1441 may extend along a third direction and be stacked in a PMN configuration along the second direction to form a first external terminal 144 with a line exiting along the third direction; alternatively, the plurality of first terminals 1441 may also extend along the second direction and be stacked in a PMN configuration along the third direction to form a first external terminal 144 with a line exiting along the second direction. Of course, this application is not limited to these embodiments, and the stacking method and line exit direction of the plurality of first terminals 1441 can be flexibly adjusted according to the setting position of the power module 21. Thus, by stacking the plurality of first terminals 1441, it is beneficial to reduce the parasitic inductance between the terminals, thereby further reducing the parasitic inductance of the first connection bus assembly 14.

[0109] In some embodiments, reference Figures 11-14 The first capacitor 11 and the second capacitor 12 are along the second direction (i.e. Figure 12 The capacitors 11 and 12 are arranged side by side and opposite to each other in the X direction shown in the diagram. The middle terminals of the first capacitor 11 and the second capacitor 12 are located on the same side in the third direction, respectively. The upper end of the first capacitor 11 is the positive terminal (P terminal) and the lower end is the middle terminal (M terminal). The upper end of the second capacitor 12 is the negative terminal (N terminal) and the lower end is the middle terminal (M terminal).

[0110] The first negative busbar 143 may include a negative busbar main body and a first negative terminal connection portion 1431. The negative busbar main body and the first negative terminal connection portion 1431 are respectively located on both sides of the DC bus capacitor unit 1 along a third direction. For example, the negative busbar main body is located at the bottom end of the first capacitor 11 and the second capacitor 12, and the first negative terminal connection portion 1431 is located on the upper side of the second capacitor 12. Further, in order to realize the connection between the negative busbar main body and the first negative terminal connection portion 1431, the first negative busbar 143 may also include a first negative busbar 143 transition connection portion. The first negative busbar 143 transition connection portion is located on the side of the second capacitor 12 facing away from the first capacitor 11 along a second direction. The first negative busbar 143 transition connection portion extends along a third direction, and its two ends are respectively connected to the negative busbar main body and the first negative terminal connection portion 1431.

[0111] The first intermediate row 142 may include a first intermediate connecting portion 1421 and a second intermediate connecting portion 1422. The first intermediate connecting portion 1421 is located at the bottom end of the first capacitor 11 and connected to the middle electrode of the first capacitor 11. The first intermediate connecting portion 1421 overlaps with the negative row main body to reduce the parasitic inductance between the first intermediate row 142 and the first negative row 143. The second intermediate connecting portion 1422 is located at the bottom end of the second capacitor 12 and connected to the middle electrode of the second capacitor 12. It also overlaps with the negative row main body to reduce the parasitic inductance between the first intermediate row 142 and the first negative row 143. The first negative electrode connecting portion 1431 is connected to the negative electrode of the second capacitor 12 and is arranged side by side with the first positive row 141 along the second direction.

[0112] By adopting the above arrangement, the parasitic inductance of the first connection row assembly 14 can be reduced, which is beneficial to reducing the parasitic inductances L1 and L2 inside the DC bus capacitor unit 1.

[0113] In some embodiments, a plurality of first terminals 1441 are stacked between the first capacitor 11 and the second capacitor 12 to form a first external terminal 144. For example, the bottom ends of the first terminals 1441 of the first intermediate row 142 are connected to the first intermediate connecting portion 1421 and the second intermediate connecting portion 1422 respectively. The first terminals 1441 of the first intermediate row 142 extend along a third direction between the first capacitor 11 and the second capacitor 12 and extend to the upper side of the first capacitor 11 and the second capacitor 12. The first terminals 1441 of the first positive row 141 and the first terminals 1441 of the first negative row 143 are located on both sides of the first terminals 1441 of the first intermediate row 142 along the second direction. In this way, a plurality of first terminals 1441 can be stacked in PMN along the second direction to form a first external terminal 144 with a line output along the third direction.

[0114] It should be noted that the outgoing configuration of the first external terminal 144 in this embodiment is such that the first external terminal 144 coincides with the symmetrical center plane of the first capacitor 11 and the second capacitor 12 in the second direction. At this time, for the power module 21, the power converter loops Loop1 and Loop2 corresponding to any one of its U phase, V phase and W phase are symmetrical to each other, which can reduce the difference in the total parasitic inductance of different converter loops and maximize the current sharing of current flowing through different capacitors.

[0115] Furthermore, the first intermediate row 142 serves to interconnect the first capacitor 11 and the second capacitor 12. Since the first intermediate row 142 is located on the symmetrical center plane of the first capacitor 11 and the second capacitor 12, its conductor length can be minimized, thereby reducing the parasitic inductance of the interconnection portion of the first capacitor 11 and the second capacitor 12. As for the first positive row 141, since its first terminal 1441 is closer to the positive terminal of the first capacitor 11 in the second direction, its length can be shortened, thus reducing the parasitic inductance of this portion. In summary, the wiring method of the first external terminal 144 in this embodiment can further reduce the parasitic inductance inside the DC bus capacitor unit 1.

[0116] In some embodiments, reference Figures 15-18 The first capacitor 11 and the second capacitor 12 are along a third direction (i.e. Figure 16 The Z-direction vertical arrangement shown can be such that the first capacitor 11 is located above the second capacitor 12, or the first capacitor 11 is located below the second capacitor 12, with the first capacitor 11 and the second capacitor 12 arranged opposite to each other.

[0117] The intermediate electrode of the first capacitor 11 and the intermediate electrode of the second capacitor 12 are arranged opposite each other along a third direction, and the positive electrode of the first capacitor 11 and the negative electrode of the second capacitor 12 are arranged away from each other along a third direction. That is, the upper end of the first capacitor 11 is the positive electrode (P electrode) and the lower end is the intermediate electrode (M electrode), and the upper end of the second capacitor 12 is the intermediate electrode (M electrode) and the lower end is the negative electrode (N electrode).

[0118] The first intermediate row 142 may include a first intermediate connecting portion 1421 and a second intermediate connecting portion 1422. The first intermediate connecting portion 1421 is located at the bottom end of the first capacitor 11 and is connected to the middle electrode of the first capacitor 11. The second intermediate connecting portion 1422 is located on the upper side of the second capacitor 12 and is connected to the middle electrode of the second capacitor 12. The first intermediate connecting portion 1421 and the second intermediate connecting portion 1422 are arranged opposite each other in the vertical direction, and the first intermediate connecting portion 1421 is located on the upper side of the second intermediate connecting portion 1422.

[0119] Optionally, when both the first capacitor 11 and the second capacitor 12 include multiple core packages, the multiple core packages of the first capacitor 11 and the second capacitor 12 are arranged along a first direction, the first intermediate connection part 1421 is simultaneously connected to the intermediate electrode of the multiple core packages of the first capacitor 11, and the second intermediate connection part 1422 is simultaneously connected to the intermediate electrode of the multiple core packages of the second capacitor 12.

[0120] By adopting the above arrangement, the parasitic inductance of the first connection row assembly 14 can be reduced, which is beneficial to reducing the parasitic inductances L1 and L2 inside the DC bus capacitor unit 1.

[0121] In some embodiments, a plurality of first terminals 1441 are stacked between a first capacitor 11 and a second capacitor 12 to form a first external terminal 144, and the first external terminal 144 is located on one side of the first capacitor 11 and the second capacitor 12 along a second direction. For example, one end of the first terminal 1441 of the first intermediate row 142 along the second direction is connected to the first intermediate connecting portion 1421 and the second intermediate connecting portion 1422 respectively, and the other end extends along the second direction. The first terminal 1441 of the first positive row 141 and the first terminal 1441 of the first negative row 143 are located on both sides of the first terminal 1441 of the first intermediate row 142 along a third direction. Thus, a plurality of first terminals 1441 can be stacked in a PMN configuration along a third direction to form a first external terminal 144 with a line extending along the second direction.

[0122] It should be noted that the outgoing wiring method of the first external terminal 144 in this embodiment makes the first external terminal 144 coincide with the symmetrical center plane of the first capacitor 11 and the second capacitor 12 in the third direction. At this time, for the power module 21, the power converter loops Loop1 and Loop2 corresponding to any one of its U phase, V phase and W phase are symmetrical to each other, which can reduce the difference in the total parasitic inductance of different converter loops and maximize the current sharing of current flowing through different capacitors.

[0123] Furthermore, the first intermediate row 142 serves to interconnect the first capacitor 11 and the second capacitor 12. Since the first intermediate row 142 is located on the symmetrical center plane of the first capacitor 11 and the second capacitor 12, its conductor length can be minimized, thereby reducing the parasitic inductance of the interconnection portion of the first capacitor 11 and the second capacitor 12. In summary, the wiring method of the first external terminal 144 in this embodiment can further reduce the parasitic inductance inside the DC bus capacitor unit 1.

[0124] In addition to the above-mentioned first intermediate row 142 being a single unit, the first intermediate row 142 including a first intermediate connecting portion 1421 and a second connecting portion, this application also provides another embodiment of the first intermediate row 142, wherein the intermediate electrode of the first capacitor 11 and the intermediate electrode of the second capacitor 12 are respectively located on different sides along a third direction. For example, when the top of the first capacitor 11 is the intermediate electrode, the bottom of the second capacitor 12 is the intermediate electrode; or, when the bottom of the first capacitor 11 is the intermediate electrode, the top of the second capacitor 12 is the intermediate electrode.

[0125] There can be two first intermediate rows 142. One first intermediate row 142 is connected to the middle terminal of the first capacitor 11, and the other first intermediate row 142 is connected to the middle terminal of the second capacitor 12. The first positive row 141, the first negative row 143, and the first terminals 1441 of the two first intermediate rows 142 are stacked between the first capacitor 11 and the second capacitor 12. For example, the first terminals 1441 (P1) of the first positive row 141, the first terminals 1441 (N1) of the first negative row 143, and the first terminals 1441 (M11 and M12) of the two first intermediate rows 142 can be stacked in the manner of MPNM or MNPM. In this way, it can be ensured that the first external terminal 144 coincides with the symmetrical center plane of the first capacitor 11 and the second capacitor 12. At this time, for the power module 21, the power converter loops Loop1 and Loop2 corresponding to any one of its U phase, V phase, and W phase are symmetrical to each other, which can reduce the difference in the total parasitic inductance of different converter loops and maximize the current sharing of the current flowing through different capacitors.

[0126] Considering that the DC bus capacitor unit 1 has various components inside its housing, in order to better avoid other components and improve the flexibility of the bus capacitor spatial layout, in this embodiment, the first capacitor 11 and the second capacitor 12 are staggered by a distance of 0-15mm in a direction perpendicular to the arrangement direction. For example, the distance can be 0, 1mm, 3mm, 5mm, 8mm, 10mm, 12mm, or 15mm, and of course, this application is not limited to this. This facilitates flexible adjustment of the structure of the DC bus capacitor unit 1.

[0127] In some embodiments, reference Figure 3 , Figure 7 , Figure 11 and Figure 15 The DC bus capacitor unit 1 may also include a third capacitor 13 (i.e., Figure 1 and Figure 2 In the case of C3), the third capacitor 13 is also a bus capacitor. The positive terminal of the third capacitor 13 is connected to the first positive bus 141, and the negative terminal of the third capacitor 13 is connected to the first negative bus 143, so that the third capacitor 13 is connected in parallel with the branch where the first capacitor 11 and the second capacitor 12 are located.

[0128] For example, refer to Figure 4 , Figure 8 , Figure 12 and Figure 16 The first positive electrode 141 may include a first positive electrode connection portion 1411 and a second positive electrode connection portion 1412, wherein the first positive electrode connection portion 1411 is connected to the positive electrode of the first capacitor 11, and the second positive electrode connection portion 1412 is connected to the positive electrode of the third capacitor 13; the first negative electrode 143 may include a first negative electrode connection portion 1431 and a second negative electrode connection portion 1432, wherein the first negative electrode connection portion 1431 is connected to the negative electrode of the second capacitor 12, and the second negative electrode connection portion 1432 is connected to the negative electrode of the third capacitor 13.

[0129] In other words, the first positive row 141 can also interconnect the positive terminal of the third capacitor 13 with the positive terminal of the first capacitor 11, and the second negative row 223 can also interconnect the negative terminal of the third capacitor 13 with the negative terminal of the second capacitor 12.

[0130] To further reduce the parasitic inductance of the portion of the first positive busbar 141 used to interconnect the positive terminals of the first capacitor 11 and the third capacitor 13, and the parasitic inductance of the portion of the first negative busbar 143 used to interconnect the negative terminals of the second capacitor 12 and the third capacitor 13, in this embodiment, the positive terminals of the third capacitor 13 and the first capacitor 11 are located on the same side of the bus capacitor along a third direction, and the negative terminals of the third capacitor 13 and the second capacitor 12 are located on the same side of the bus capacitor along a third direction. For example, the positive terminal of the third capacitor 13 is located above it, and the positive terminal of the first capacitor 11 is located above it; the negative terminal of the third capacitor 13 is located below it, and the negative terminal of the second capacitor 12 is located below it. In this way, the lengths of the first positive busbar 141 and the first negative busbar 143 can be shortened, thereby reducing the parasitic inductance of the portions of the first positive busbar 141 and the first negative busbar 143 used for capacitor interconnection, and thus achieving the purpose of reducing the internal parasitic inductance of the DC bus capacitor unit 1.

[0131] Since the parasitic inductance of the third capacitor 13 in the power commutation loop does not need to be considered, in some embodiments, the third capacitor 13 can be located on the same side of the first capacitor 11 and the second capacitor 12, or the third capacitor 13 can be located on the side of one of the first capacitor 11 and the second capacitor 12 that is farther away from the other. This provides greater flexibility in the spatial arrangement of the third capacitor 13, facilitating its flexible placement while fully considering the parasitic inductance within the DC bus capacitor unit 1.

[0132] In some embodiments, the power unit 2 may include a power module 21, a second connection bus assembly 22, and a three-phase output assembly 23. The power module 21 may consist of multiple power devices, which may include one or more of IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and diodes. The power devices may be made of silicon or gallium nitride (GaN).

[0133] The second connecting bus assembly 22 is used for electrical connection with the first connecting bus assembly 14. Specifically, the second connecting bus assembly 22 includes a second positive bus 221, a second intermediate bus 222, and a second negative bus 223. Any one of the second positive bus 221, the second intermediate bus 222, and the second negative bus 223 can be a connecting bus made of copper, aluminum, or other conductive materials. The second positive bus 221 corresponds to and is electrically connected to the first positive bus 141, the second intermediate bus 222 corresponds to and is electrically connected to the first intermediate bus 142, and the second negative bus 223 corresponds to and is electrically connected to the first negative bus 143. This achieves the electrical connection between the power module 21 and the bus capacitor. Understandably, the second positive row 221, the second middle row 222, and the second negative row 223 each form their second terminals 2241 (terminals P2, M2, and N2, respectively). Each second terminal 2241 is connected to the corresponding first terminal 1441, that is, terminal P1 is connected to terminal P2, terminal M1 is connected to terminal M2, and terminal N1 is connected to terminal N2.

[0134] The three-phase output component 23 is used to connect to the motor 300. In this way, the power module 21 can convert the DC power output from the power battery 200 into three-phase AC power and output it to the motor 300 through the three-phase output component 23, so that the motor 300 can convert electrical energy into mechanical energy and provide it to the driven component.

[0135] In some embodiments, reference Figure 5 , Figure 9 , Figure 13 and Figure 17 The power module 21 and the bus capacitor are stacked in a third direction and arranged opposite each other. The second connection bus assembly 22 is located on the side of the power module 21 facing the first external terminal 144 of the first connection bus assembly 14.

[0136] For example, when the first external terminal 144 extends along a third direction and is located above the bus capacitor, the power module 21 can be located above the bus capacitor, and the second connection bus assembly 22 extends downward along a third direction. The second connection bus assembly 22 is arranged opposite to the first external terminal 144 along a third direction to facilitate connection with each terminal of the first external terminal 144. This helps to shorten the sum of the lengths of the first external terminal 144 and the second external terminal 224, thereby reducing the parasitic inductance of the interconnection portion between the DC bus capacitor unit 1 and the power module 21 (corresponding to parasitic inductances L5, L6, and L7 in topology 1 and topology 2).

[0137] Or, refer to Figure 6 , Figure 10 , Figure 14 and Figure 18 In other embodiments, the power module 21 and the bus capacitor are arranged side by side in the horizontal direction along the second direction, and the second connection bus assembly 22 is located on the side of the power module 21 facing the first external terminal 144 of the first connection bus assembly 14.

[0138] For example, when the first external terminal 144 extends along the second direction and is located above the bus capacitor, the power module 21 can be located on one side of the bus capacitor along the second direction, and each terminal of the second connection assembly 22 can extend along the second direction to facilitate connection with each terminal of the first external terminal 144. This shortens the interconnection path length between the first external terminal 144 and the second external terminal 224, thereby reducing the parasitic inductance of the interconnection portion between the DC bus capacitor unit 1 and the power module 21 (corresponding to parasitic inductances L5, L6, and L7 in topologies 1 and 2).

[0139] Understandably, when the power module 21 and the DC bus capacitor unit 1 are arranged horizontally side by side along the second direction, the second connecting bus assembly 22 and the first external terminal 144 are opposite and connected along the second direction. Since the power module 21 does not occupy the space above the bus capacitor, the height of the first external terminal 144 along the third direction needs to be adapted to the height of the second connecting bus assembly 22. That is, by adjusting the height of the power module 21 relative to the DC bus capacitor unit 1 and adjusting the height of the first external terminal 144 along the third direction to facilitate the connection of the second connecting bus assembly 22, the second connecting bus assembly 22 can be made flush with the upper surface of the DC bus capacitor unit 1 as much as possible, so as to minimize the length of the first external terminal 144 in the third direction, thereby shortening the parasitic inductance of the transition part of the DC bus capacitor unit 1 and the power module 21 (corresponding to the parasitic inductances L5, L6 and L7 in topology 1 and topology 2), which helps to reduce the system noise of the motor controller 100 and improve the power density of the motor controller 100.

[0140] It should be noted that, while ensuring that the interconnection parasitic inductances L5, L6 and L7 are minimized, the relative positions of the first terminal 1441 (including P1, M1 and N1) and the second terminal 2241 (including P2, M2 and N2) and their junction in the third direction can be moved or finely adjusted according to the actual product size and structural form to meet the product structural layout requirements.

[0141] Additionally, it should be noted that the first terminal 1441 and the second terminal 2241 are in one-to-one correspondence. That is, when the first connecting row assembly 14 includes only one first intermediate row 142, the first external terminal 144 is formed by stacking three first terminals 1441 (i.e., P1, M1, N1). At this time, the second external terminal 224 of the second connecting row assembly 22 also includes three second terminals 2241 (i.e., P2, M2, N2). When the first connecting row assembly 14 includes two first intermediate rows 142, the first external terminal 144 is formed by stacking four first terminals 1441 (i.e., P1, M11, M12, N1). At this time, the second external terminal 224 of the second connecting row assembly 22 also includes four second terminals 2241 (i.e., P2, M21, M22, N2).

[0142] In some embodiments, reference Figures 19-22 The three-phase output component 23 and the second connection bus component 22 are located on opposite sides of the power module 21 along the second direction. This allows the connection between the second connection bus component 22 and the DC bus capacitor unit 1, and the connection between the three-phase output component 23 and the motor 300, to be independent of each other. It also provides greater design flexibility for the spatial arrangement of the DC bus capacitor unit 1 and the motor 300 relative to the power module 21. At the same time, for the motor controller 100 as a whole, it helps to shorten the length of the three-phase output component 23 and the second output component, thereby reducing the stray inductance of the system as a whole and improving the system efficiency.

[0143] Since the function of the power module 21 is to convert AC and DC power, that is, to convert the DC power from the power battery 200 into three-phase AC power, or to convert AC power into DC power to charge the power battery, the circuit inside the power module 21 includes three phases, namely U phase, V phase and W phase. In order to realize the interconnection of the three phases with the DC bus capacitor unit 1, the second connection bus assembly 22 can be set into three groups, each group corresponding to one phase of the three phases. That is, the U phase is connected to one second connection bus assembly 22, the V phase is connected to one second connection bus assembly 22, and the W phase is connected to one second connection bus assembly 22. All three second connection bus assemblies 22 are connected to the first connection bus assembly 14, thereby interconnecting each phase of the power module 21 with the DC bus capacitor unit 1, so as to realize the normal operation of the power module 21.

[0144] In some embodiments, the second positive row 221, the second middle row 222, and the second negative row 223 each include a second terminal 2241, and a plurality of second terminals 2241 belonging to the same group are arranged side by side along a first direction.

[0145] For example Figure 19 As shown, when there are three second terminals 2241, the multiple second terminals 2241 corresponding to U (i.e., P2, M2 and N2) are arranged horizontally side by side along the first direction, the multiple second terminals 2241 corresponding to V (i.e., P2, M2 and N2) are arranged horizontally side by side along the first direction, and the multiple second terminals 2241 corresponding to W (i.e., P2, M2 and N2) are arranged horizontally side by side along the first direction.

[0146] Or, such as Figure 20 As shown, when there are four second terminals 2241, the multiple second terminals 2241 corresponding to U (i.e., P2, M21, M22, N2) are arranged horizontally side by side along the first direction; the multiple second terminals 2241 corresponding to V (i.e., P2, M21, M22, N2) are arranged horizontally side by side along the first direction; and the multiple second terminals 2241 corresponding to W (i.e., P2, M21, M22, N2) are arranged horizontally side by side along the first direction. Thus, the arrangement of each second terminal 2241 is relatively simple and easy to implement.

[0147] In this embodiment, the arrangement order of the multiple second terminals 2241 in each group along the first direction can be adjusted as needed. It can be the same as or different from the arrangement order of the multiple first terminals 1441. Furthermore, the arrangement order of the three groups of second terminals 2241 can be the same or different. In this way, greater flexibility can be provided for the layout of the multiple second terminals 2241.

[0148] In addition to the layout scheme of the second external terminal 224 in the above embodiments, in some other embodiments, specifically, the second positive row 221, the second middle row 222 and the second negative row 223 all include second terminals 2241, and multiple second terminals 2241 belonging to the same group are stacked along a third direction.

[0149] Specifically, such as Figure 22As shown, when there are three second terminals 2241, the multiple second terminals 2241 corresponding to U (i.e., P2, M2 and N2) are stacked along a third direction, so that the second connection bus assembly 22 corresponding to U is formed as a stack to reduce parasitic inductance; the multiple second terminals 2241 corresponding to V (i.e., P2, M2 and N2) are stacked along a third direction, so that the second connection bus assembly 22 corresponding to V is formed as a stack to reduce parasitic inductance; the multiple second terminals 2241 corresponding to W (i.e., P2, M2 and N2) are stacked along a third direction, so that the second connection bus assembly 22 corresponding to W is formed as a stack to reduce parasitic inductance. Furthermore, the second terminals 2241 belonging to different groups and having the same polarity are arranged horizontally side by side along the first direction, that is, the second terminal 2241 (P2) corresponding to U, the second terminal 2241 (P2) corresponding to V, and the second terminal 2241 (P2) corresponding to W are arranged horizontally side by side along the first direction; the second terminal 2241 (M2) corresponding to U, the second terminal 2241 (M2) corresponding to V, and the second terminal 2241 (M2) corresponding to W are arranged horizontally side by side along the first direction; the second terminal 2241 (N2) corresponding to U, the second terminal 2241 (N2) corresponding to V, and the second terminal 2241 (N2) corresponding to W are arranged horizontally side by side along the first direction, so that the second terminals 2241 with the same polarity can be connected to the corresponding first terminals 1441 with the same polarity.

[0150] Or, such as Figure 21 As shown, when there are four second terminals 2241, the multiple second terminals 2241 corresponding to U (i.e., P2, M21, M22, N2) are stacked along a third direction, thereby forming a stacked arrangement of the second connection bus assembly 22 corresponding to U to reduce parasitic inductance; the multiple second terminals 2241 corresponding to V (i.e., P2, M21, M22, N2) are stacked along a third direction, thereby forming a stacked arrangement of the second connection bus assembly 22 corresponding to V to reduce parasitic inductance; the multiple second terminals 2241 corresponding to W (i.e., P2, M21, M22, N2) are stacked along a third direction, thereby forming a stacked arrangement of the second connection bus assembly 22 corresponding to W to reduce parasitic inductance.

[0151] Furthermore, the second terminals 2241, belonging to different groups and having the same polarity, are arranged horizontally side by side along the first direction. Specifically, the second terminal 2241(P2) corresponding to U, the second terminal 2241(P2) corresponding to V, and the second terminal 2241(P2) corresponding to W are arranged horizontally side by side along the first direction; the second terminal 2241(M21) corresponding to U, the second terminal 2241(M21) corresponding to V, and the second terminal 2241(M21) corresponding to W are arranged horizontally side by side along the first direction; and... The second terminal 2241(M22) corresponding to U, the second terminal 2241(M22) corresponding to V, and the second terminal 2241(M22) corresponding to W are arranged horizontally side by side along the first direction; the second terminal 2241(N2) corresponding to U, the second terminal 2241(N2) corresponding to V, and the second terminal 2241(N2) corresponding to W are arranged horizontally side by side along the first direction so that multiple second terminals 2241 with the same polarity can be connected to the corresponding first terminal 1441 with the same polarity.

[0152] In this way, the parasitic inductance of the second connection bus assembly 22 itself can be reduced, thereby reducing the parasitic inductance of the power module 21.

[0153] It is understood that in this embodiment, the arrangement of the multiple second terminals 2241 belonging to the same group is the same as the arrangement of the multiple first terminals 1441 in the first external terminals 144. That is, when the multiple first terminals 1441 in the first external terminals 144 are stacked in a PMN or NMP manner, the multiple second terminals 2241 belonging to the same group are also stacked in a PMN or NMP manner; when the multiple first terminals 1441 in the first external terminals 144 are stacked in an MPNM or MNPM manner, the multiple second terminals 2241 belonging to the same group are also stacked in an MPNM or MNPM manner. In this way, it is convenient for the corresponding first terminals 1441 and second terminals 2241 to be at the same height, thereby achieving connection with the shortest connection path.

[0154] In summary, the motor controller 100 of this application embodiment, by adjusting and designing the arrangement of the bus capacitors, the outgoing wiring method of the first connecting bus assembly 14, the layout between the power module 21 and the DC bus capacitor unit 1, and the outgoing wiring method of the second connecting bus assembly 22, can respectively reduce the parasitic inductances L1 and L2 in the DC bus capacitor unit 1, the parasitic inductances L5, L6 and L7 inside the transfer unit, and the parasitic inductance L4 inside the power module 21, thereby reducing the system noise of the motor controller 100 and increasing the power density of the motor controller 100. Furthermore, in addition to the topologies 1 and 2 mentioned above, it is also applicable to other three-level power topologies containing bus capacitors C1 and C2, which can expand the scope of application and facilitate large-scale and batch implementation.

[0155] The power system of the second aspect embodiment of this application is described below.

[0156] The power system of this embodiment may include: a power battery 200, a motor 300 and a motor controller 100 as described in the above embodiment, wherein the motor controller 100 is electrically connected to the power battery 200 and the motor 300 respectively.

[0157] The power system of this application embodiment, by providing the motor controller 100 in the above embodiment, can improve system working efficiency, enhance working stability and reliability, and help reduce costs.

[0158] The vehicle of the third aspect of this application is described below.

[0159] The vehicle in this embodiment may include the power system described above or the motor controller 100 described above.

[0160] The vehicle in this application embodiment, by being equipped with the power system or motor controller 100 as described in the above embodiment, has higher system efficiency, higher reliability and stability, which is beneficial to improving the user's driving experience.

[0161] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0162] It should be noted that the embodiments referred to in the specification, such as "one embodiment," "embodiment," "exemplary embodiment," and "some embodiments," may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0163] Generally speaking, terms should be understood at least in part by their use in context. For example, at least in part by context, the term "one or more" as used in the text can be used to describe any feature, structure, or characteristic of the singular meaning, or a combination of features, structures, or characteristics of the plural meaning. Similarly, at least in part by context, terms such as "a" or "the" can also be understood to convey either singular or plural usage.

[0164] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also “on something” with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “on top of something” but also “on top of something” without an intermediate feature or layer therebetween (i.e., directly on something).

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A motor controller, characterized in that, include: The DC bus capacitor unit includes: A first capacitor and a second capacitor connected in series, wherein the first capacitor and the second capacitor are arranged adjacent to each other and at least partially opposite to each other; A first connecting bus assembly is used to connect the first capacitor and the second capacitor in series; The power unit is electrically connected to the first connection bus assembly.

2. The motor controller according to claim 1, characterized in that, The first connection bar assembly includes: The first positive terminal is connected to the positive terminal of the first capacitor; The first intermediate row is connected to the middle terminal of the first capacitor and the middle terminal of the second capacitor, respectively; The first negative terminal is connected to the negative terminal of the second capacitor; The first positive row, the first middle row, and the first negative row are each provided with a first terminal. Multiple first terminals are stacked together to form a first external terminal, which is electrically connected to the power unit.

3. The motor controller according to claim 2, characterized in that, The first capacitor and the second capacitor are arranged side by side and opposite to each other along a first direction.

4. The motor controller according to claim 3, characterized in that, The middle electrode of the first capacitor and the middle electrode of the second capacitor are located on different sides along a third direction, which is perpendicular to the first direction. The first intermediate row includes a first intermediate connecting part and a second intermediate connecting part. The first intermediate connecting part is connected to the intermediate electrode of the first capacitor and overlaps with the first negative row. The second intermediate connecting part is connected to the intermediate electrode of the second capacitor and overlaps with the first positive row.

5. The motor controller according to claim 3, characterized in that, Multiple first terminals are stacked on the side of the second capacitor opposite to the first capacitor along the second direction to form the first external terminal.

6. The motor controller according to claim 2, characterized in that, The first capacitor and the second capacitor are arranged side by side and opposite to each other along the second direction. The second direction is perpendicular to the first direction.

7. The motor controller according to claim 6, characterized in that, The middle electrode of the first capacitor and the middle electrode of the second capacitor are located on different sides along a third direction, respectively. The first intermediate row includes a first intermediate connecting part and a second intermediate connecting part. The first intermediate connecting part is connected to the intermediate electrode of the first capacitor and overlaps with the first negative row. The second intermediate connecting part is connected to the intermediate electrode of the second capacitor and overlaps with the first positive row.

8. The motor controller according to claim 7, characterized in that, Multiple first terminals are stacked on the side of the second capacitor opposite to the first capacitor along the second direction to form the first external terminal.

9. The motor controller according to claim 6, characterized in that, The middle terminals of the first capacitor and the second capacitor are located on the same side along a third direction, respectively. The first negative busbar includes a negative busbar main body and a first negative electrode connection part, wherein the negative busbar main body and the first negative electrode connection part are respectively located on both sides of the DC bus capacitor unit along a third direction; The first intermediate row includes a first intermediate connecting part and a second intermediate connecting part. The first intermediate connecting part is connected to the intermediate electrode of the first capacitor and overlaps with the negative row main body. The second intermediate connecting part is connected to the intermediate electrode of the second capacitor and overlaps with the negative row main body. The first negative terminal connection is connected to the negative terminal of the second capacitor and is arranged side by side with the first positive terminal along the second direction.

10. The motor controller according to claim 9, characterized in that, Multiple first terminals are stacked between the first capacitor and the second capacitor to form the first external terminal.

11. The motor controller according to claim 2, characterized in that, The first capacitor and the second capacitor are arranged along a third direction and positioned opposite each other. The third direction, the second direction, and the first direction are all perpendicular to each other.

12. The motor controller according to claim 11, characterized in that, The middle terminals of the first capacitor and the second capacitor are positioned opposite each other along a third direction, while the positive terminals of the first capacitor and the negative terminals of the second capacitor are positioned away from each other along a third direction. The first intermediate row includes a first intermediate connecting part and a second intermediate connecting part. The first intermediate connecting part is connected to the intermediate electrode of the first capacitor, and the second intermediate connecting part is connected to the intermediate electrode of the second capacitor.

13. The motor controller according to claim 12, characterized in that, Multiple first terminals are stacked between the first capacitor and the second capacitor to form the first external terminal.

14. The motor controller according to any one of claims 3, 6, and 11, characterized in that, The middle electrode of the first capacitor and the middle electrode of the second capacitor are located on different sides along a third direction, respectively. There are two first intermediate rows, one of which is connected to the middle terminal of the first capacitor, and the other is connected to the middle terminal of the second capacitor. The first positive row, the first negative row, and the first terminals of the two first intermediate rows are stacked between the first capacitor and the second capacitor.

15. The motor controller according to any one of claims 1-12, characterized in that, The first capacitor and the second capacitor are staggered by a distance of 0-15mm in a direction perpendicular to the arrangement direction.

16. The motor controller according to any one of claims 2-13, characterized in that, The DC bus capacitor unit also includes: The third capacitor has its positive terminal connected to the first positive line and its negative terminal connected to the first negative line, so that the third capacitor is connected in parallel with the branch containing the first capacitor and the second capacitor.

17. The motor controller according to claim 16, characterized in that, The third capacitor is located on the same side of the first capacitor and the second capacitor, or the third capacitor is located on the side of one of the first capacitor and the second capacitor that is away from the other.

18. The motor controller according to any one of claims 2-13, characterized in that, The power unit includes: Power module; The second connecting bus assembly is used for electrical connection with the first connecting bus assembly; A three-phase output assembly is used to connect to a motor.

19. The motor controller according to claim 18, characterized in that, The power module and the DC bus capacitor unit are stacked and arranged opposite each other in a third direction, or the power module and the DC bus capacitor unit are arranged side by side along a second direction; Furthermore, the second connection bus assembly is located on the side of the power module facing the first external terminal of the first connection bus assembly.

20. The motor controller according to claim 19, characterized in that, The three-phase output component and the second connection bus component are located on opposite sides of the power module along the second direction.

21. The motor controller according to claim 19, characterized in that, The second connecting busbar assembly consists of three groups, each corresponding to one phase of the three phases, and the three groups of the second connecting busbar assembly are arranged along the first direction. Each group includes a second positive row, a second middle row, and a second negative row, wherein the second positive row corresponds to and is electrically connected to the first positive row, the second middle row corresponds to and is electrically connected to the first middle row, and the second negative row corresponds to and is electrically connected to the first negative row.

22. The motor controller according to claim 21, characterized in that, The second positive row, the second middle row, and the second negative row all include a second terminal. Multiple second terminals belonging to the same group are arranged side by side along the first direction.

23. The motor controller according to claim 21, characterized in that, The second positive row, the second middle row, and the second negative row all include second terminals, and multiple second terminals belonging to the same group are stacked along a third direction; Furthermore, the arrangement of multiple second terminals belonging to the same group is the same as the arrangement of multiple first terminals in the first external terminals.

24. A power system, characterized in that, include: Power battery; Electric motor; The motor controller according to any one of claims 1-23, wherein the motor controller is electrically connected to the power battery and the motor respectively.

25. A vehicle, characterized in that, Includes the power system as described in claim 24 or the motor controller as described in any one of claims 1-23.

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