Image sensing device

Abstract

Disclosed is an image sensing apparatus capable of implementing a plurality of gains. In an embodiment, an image sensing device includes: a first pixel including a first dual conversion gain (DCG) transistor and a second DCG transistor that adjust a capacitance of a first floating diffusion region shared by a plurality of pixels included in a first pixel group; and a second pixel including a third DCG transistor and a fourth DCG transistor that adjust capacitance of a second floating diffusion region shared by a plurality of pixels included in a second pixel group arranged on one side of the first pixel group. A gate of the first DCG transistor and a gate of the second DCG transistor are arranged closer to the second pixel from a center of the first pixel, and a gate of the third DCG transistor and a gate of the fourth DCG transistor are arranged closer to the first pixel from a center of the second pixel.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to image sensing devices, and more specifically to image sensing devices capable of achieving multiple gains. Background Technology

[0002] Image sensing devices capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With advancements in industries such as automotive, medical, computer, and communications, the demand for high-performance image sensing devices is growing across a wide range of fields, including smartphones, digital cameras, gaming consoles, IoT (Internet of Things), robotics, security cameras, and medical miniature cameras.

[0003] Image sensing devices can be broadly classified into charge-coupled device (CCD) image sensing devices and complementary metal-oxide-semiconductor (CMOS) image sensing devices. CCD image sensing devices offer better image quality, but tend to consume more power and are larger compared to CMOS image sensing devices. CMOS image sensing devices are smaller and consume less power than CCD image sensing devices. Furthermore, CMOS image sensing devices are manufactured using CMOS fabrication technology, allowing photosensitive elements and other signal processing circuitry to be integrated onto a single chip, enabling the production of miniaturized image sensing devices at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the Invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device capable of reducing junction capacitance and implementing multiple conversion gains when two different dual conversion gain (DCG) transistors are electrically connected to each other.

[0005] Various embodiments of the disclosed technology relate to image sensing devices capable of more precisely adjusting the ratio of multiple conversion gains.

[0006] In an embodiment of the disclosed technology, an image sensing device may include: a first pixel comprising a first dual conversion gain (DCG) transistor and a second DCG transistor that change the capacitance of a first floating diffusion region shared by a plurality of pixels included in a first pixel group; and a second pixel comprising a third DCG transistor and a fourth DCG transistor that change the capacitance of a second floating diffusion region shared by a plurality of pixels included in a second pixel group disposed on one side of the first pixel group, wherein the gates of the first DCG transistor and the second DCG transistor are arranged closer to the second pixel from the center of the first pixel, and the gates of the third DCG transistor and the fourth DCG transistor are arranged closer to the first pixel from the center of the second pixel.

[0007] In some implementations, the image sensing device may further include: a first dual conversion gain (DCG) electrical interconnect configured to electrically interconnect a terminal of a first DCG transistor and a terminal of a third DCG transistor; and a second DCG electrical interconnect configured to electrically interconnect a terminal of a second DCG transistor and a terminal of a fourth DCG transistor.

[0008] In some implementations, the first pixel may include a first photoelectric conversion element and a second photoelectric conversion element, each of which generates photocharge in response to incident light; and the second pixel may include a third photoelectric conversion element and a fourth photoelectric conversion element, each of which generates photocharge in response to incident light.

[0009] In some implementations, the image sensing device may further include a pixel isolation structure disposed between the first photoelectric conversion element and the second photoelectric conversion element, and between the third photoelectric conversion element and the fourth photoelectric conversion element.

[0010] In some implementations, the gate of the first DCG transistor may overlap with the first photoelectric conversion element; the gate of the second DCG transistor may overlap with the second photoelectric conversion element; the gate of the third DCG transistor may overlap with the third photoelectric conversion element; and the gate of the fourth DCG transistor may overlap with the fourth photoelectric conversion element.

[0011] In some implementations, the first pixel may further include: a first transfer transistor configured to move photocharge generated by the first photoelectric conversion element to a first floating diffusion region; and a second transfer transistor configured to move photocharge generated by the second photoelectric conversion element to the first floating diffusion region. The second pixel may further include: a third transfer transistor configured to move photocharge generated by the third photoelectric conversion element to a second floating diffusion region; and a fourth transfer transistor configured to move photocharge generated by the fourth photoelectric conversion element to the second floating diffusion region.

[0012] In some implementations, the first pixel group may further include a first driving transistor configured to amplify an electrical signal corresponding to the photocharge stored in the first floating diffusion region. The second pixel group may further include a second driving transistor configured to amplify an electrical signal corresponding to the photocharge stored in the second floating diffusion region.

[0013] In some implementations, the first pixel group may further include a first selection transistor configured to output an electrical signal amplified by the first driving transistor. The second pixel group may further include a second selection transistor configured to output an electrical signal amplified by the second driving transistor.

[0014] In some implementations, the first pixel group may include a first reset transistor configured to reset the first floating diffusion region, and the second pixel group may include a second reset transistor configured to reset the second floating diffusion region.

[0015] In some implementations, the image sensing device may further include: a third dual conversion gain (DCG) electrical interconnect configured to electrically interconnect one terminal of the first DCG transistor and the other terminal of the second DCG transistor; and a fourth DCG electrical interconnect configured to electrically interconnect one terminal of the third DCG transistor and the other terminal of the fourth DCG transistor.

[0016] In some implementations, the first floating diffusion region may be electrically connected to another terminal of the first DCG transistor; and the second floating diffusion region may be electrically connected to another terminal of the third DCG transistor.

[0017] In another embodiment of the disclosed technology, an image sensing device may include: a first pixel including a first photoelectric conversion element and a second photoelectric conversion element configured to generate photocharge in response to incident light; a second pixel including a third photoelectric conversion element and a fourth photoelectric conversion element configured to generate photocharge in response to incident light and contacting one side surface of the first pixel; a third pixel including a fifth photoelectric conversion element and a sixth photoelectric conversion element configured to generate photocharge in response to incident light and contacting the other side surface of the first pixel; and a fourth pixel including a seventh photoelectric conversion element and an eighth photoelectric conversion element configured to generate photocharge in response to incident light and contacting the third pixel. The first pixel may include: a first dual conversion gain (DCG) transistor and a second DCG transistor, which change the conversion gain of the first pixel and the second pixel and are arranged closer to the third pixel from the center of the first pixel. The third pixel may include: a third DCG transistor and a fourth DCG transistor, which change the conversion gain of the third pixel and the fourth pixel and are arranged closer to the first pixel from the center of the third pixel.

[0018] In some implementations, a terminal of the first DCG transistor and a terminal of the third DCG transistor can be electrically connected to each other; and a terminal of the second DCG transistor and a terminal of the fourth DCG transistor can be electrically connected to each other.

[0019] In some implementations, the first pixel may include a first floating diffusion region configured to store photocharge generated by the first and second photoelectric conversion elements. The second pixel may include a second floating diffusion region configured to store photocharge generated by the third and fourth photoelectric conversion elements.

[0020] In some implementations, another terminal of the first DCG transistor may be electrically connected to the first floating diffusion region; and another terminal of the third DCG transistor may be electrically connected to the second floating diffusion region.

[0021] In some implementations, one terminal of the first DCG transistor can be electrically connected to another terminal of the second DCG transistor; and one terminal of the third DCG transistor can be electrically connected to another terminal of the fourth DCG transistor.

[0022] In some implementations, the first pixel and the second pixel can have high conversion gain when all four DCG transistors are off; the first pixel and the second pixel can have medium conversion gain when the first DCG transistor is on and the four DCG transistors are off; and the first pixel and the second pixel can have low conversion gain when all four DCG transistors are on.

[0023] In some implementations, the intermediate conversion gain can be twice that of the low conversion gain.

[0024] In some implementations, the high conversion gain can be eight times that of the low conversion gain.

[0025] In some implementations, the third and fourth pixels have high conversion gain when all four DCG transistors are off; medium conversion gain when the third DCG transistor is on and the first, second, and fourth DCG transistors are off; and low conversion gain when all four DCG transistors are on.

[0026] It should be understood that both the foregoing general description of the disclosed technology and the following detailed description are illustrative and explanatory, and are intended to provide a further explanation of the claimed disclosure. Attached Figure Description

[0027] The above and other features and advantages of the disclosed technology will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0028] Figure 1This is a block diagram illustrating examples of image sensing devices based on some implementations of the disclosed technology.

[0029] Figure 2 These are examples of some implementation methods based on the disclosed technology. Figure 1 A plan view of an example pixel array of an image sensing device.

[0030] Figure 3 These are examples of some implementation methods based on the disclosed technology. Figure 2 The circuit diagram shows an example of the first pixel region or the second pixel region.

[0031] Figure 4 These are examples of some implementation methods based on the disclosed technology. Figure 2 A plan view of an example of the first pixel region shown.

[0032] Figure 5A This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line A-A' is shown.

[0033] Figure 5B This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line B-B' is shown.

[0034] Figure 5C This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line C-C' is shown.

[0035] Figure 6 These are examples of some implementation methods based on the disclosed technology. Figure 2 A plan view of another example of the second pixel region shown. Detailed Implementation

[0036] This patent document provides embodiments and examples of image sensing devices capable of achieving multiple gains, which can be used in configurations to substantially solve one or more technical or engineering problems and mitigate limitations or drawbacks encountered in some image sensing devices in the art. Some embodiments of the disclosed technology relate to image sensing devices capable of reducing junction capacitance and achieving multiple conversion gains when two different dual conversion gain (DCG) transistors are electrically connected to each other. Some embodiments of the disclosed technology relate to image sensing devices capable of more precisely adjusting the ratio of multiple conversion gains. Recognizing the above-mentioned problems, image sensing devices based on some embodiments of the disclosed technology can achieve higher conversion gains by reducing junction capacitance and can have a more precisely designed conversion gain ratio. In some embodiments, the term "dual conversion gain transistor" refers to a type of transistor within a pixel on a CMOS image sensing device that allows two different amplification levels (or conversion gains) to be applied to the captured photocharge. Dual conversion gain (DCG) can improve the dynamic range of an image sensor by adjusting the conversion gain based on the amount of light. The disclosed technology can be implemented in some embodiments not only for configurations using dual conversion gain transistors but also for configurations using transistors with three or more conversion gains, such as triple conversion gain transistors.

[0037] Implementations of the disclosed technology will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. While this disclosure is readily adaptable to various modifications and alternatives, specific embodiments are shown by way of example in the drawings. However, this disclosure should not be construed as limiting itself to the embodiments set forth herein.

[0038] In the following description, various embodiments will be illustrated with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents, and / or substitutions of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the disclosed technology.

[0039] Figure 1 This is a block diagram illustrating an example of an image sensing device 1 based on some implementations of the disclosed technology.

[0040] Reference Figure 1 The image sensing device 1 based on the disclosed technology may include a timing controller 110, a row driver 120, a pixel array 200, a correlated dual sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, and a column driver 160. Figure 1The components of the image sensing device illustrated herein are discussed by way of example only, and this patent document covers many other changes, substitutions, variations, alterations, and modifications. In this patent document, the term "pixel" may be used to refer to an image sensing pixel configured to detect incident light to generate an electrical signal carrying an image in the incident light.

[0041] The timing controller 110 can provide timing and control signals to at least one of the row driver 120, correlated dual sampler (CDS) 130, ADC 140, output buffer 150 and column driver 160.

[0042] The row driver 120 can activate the pixel array 200 to perform specific operations on the pixels included in the corresponding row based on timing signals and control signals received from the timing controller 110.

[0043] In some implementations, the row driver 120 can select at least one pixel in at least one row of the pixel array 200 and can provide control signals to the selected pixel for performing a specific operation. The row driver 120 can generate a row selection signal to select at least one row from a plurality of rows. When the row driver 120 selects a specific row from a plurality of rows to perform a specific operation, the row driver 120 may not perform the specific operation on rows adjacent to the selected specific row.

[0044] The pixels of the row selected by the row driver 120 can sequentially transmit analog reference signals and image signals to the correlated dual sampler (CDS) 130. The reference signal can be an electrical signal provided to the CDS 130 when the floating diffuse region of each pixel is reset to the power supply voltage VDD. The image signal can be an electrical signal provided to the CDS 130 when the photocharge generated by each pixel accumulates in the floating diffuse (FD) region.

[0045] The reference signal can be a signal that indicates the unique pixel noise of each pixel, and the reference signal and the image signal can be collectively referred to as the pixel signal as needed.

[0046] Pixel array 200 may include multiple pixels arranged in multiple rows and multiple columns. The multiple pixels can be connected to row driver 120 via multiple row lines extending in the row direction. The multiple pixels can be connected to CDS 130 via multiple column lines extending in the column direction. Pixel array 200 may include at least one pixel PX arranged along both row and column directions. For example, pixel array 200 may be arranged as a two-dimensional (2D) pixel array comprising multiple unit pixels in rows and columns.

[0047] Multiple unit pixels included in pixel array 200 can convert light signals into electrical signals and can be connected to specific internal pixel circuits.

[0048] The pixel array 200 can receive pixel control signals, including a row selection signal, a pixel reset signal, and a row transmission signal, from the row driver 120. At least one pixel in a row selected by the row driver 120 according to the pixel control signal can perform a specific operation in response to the row selection signal, the pixel reset signal, and the row transmission signal.

[0049] The CDS130 can receive a reference signal and an image signal corresponding to each column of the pixel array 200, and can sample the levels of the reference signal and the image signal. In an image sensing device designed to use CMOS, the CDS130 can sample the pixel signal twice to remove the difference between the two samples, and can perform correlated double sampling to remove unwanted offset values ​​of the pixels, such as fixed noise. For example, the CDS130 can compare the pixel output voltage obtained before and after the accumulation of photocharge generated by the incident light in the floating diffusion region to remove unwanted offset values, making it possible to measure the pixel output voltage based on the incident light.

[0050] CDS130 can send reference signals and image signals generated in columns based on timing signals and control signals from timing controller 110 to ADC 140 as CDS signals.

[0051] The ADC 140 can convert analog CDS signals received from the CDS130 into digital signals and output the resulting digital signals.

[0052] The output buffer 150 can temporarily hold and output the digital signal provided by the ADC 140.

[0053] The column driver 160 can select columns from the output buffer 150 based on the timing signal and control signal of the timing controller 110, and can control the temporarily held digital signals to be output according to the selection order.

[0054] Figure 2 These are examples of some implementation methods based on the disclosed technology. Figure 1 A plan view of an example of the pixel array 200 of the image sensing device 1 shown.

[0055] Reference Figure 1 and Figure 2 The pixel array 200 may include, for example, a structure in which a plurality of pixels (PX) are arranged in a two-dimensional (2D) matrix structure. The pixel array 200 may include M pixels (PX) arranged in the horizontal direction (where M is an integer greater than or equal to 2). The pixel array 200 may include N pixels (PX) arranged in the vertical direction (where N is an integer greater than or equal to 2).

[0056] The pixel array 200 may include a first pixel region 210 and a second pixel region 220. The first pixel region 210 may be an area in which eight pixels (PX) are arranged in a (2×4) matrix structure. The second pixel region 220 may be an area in which four pixels are arranged in a (1×4) matrix structure. Although for ease of description... Figure 2 Each of the first pixel region 210 and the second pixel region 220 is illustrated as a region located at the edge of the pixel array 200; however, the disclosed technique is not limited thereto. It should be noted that any eight pixels (PX) arranged in a (2×4) matrix structure in the pixel array 200 can correspond to the first pixel region 210, and any four pixels (PX) arranged in a (1×4) matrix structure can correspond to the second pixel region 220. For clarity, Figure 2 Multiple pixels (PX), which may be part of the first pixel region 210 and / or the second pixel region 220, may be depicted as spaced apart from each other. However, the multiple pixels (PX) may also be arranged to be in contact with each other. In some embodiments, the first pixel region 210 or the second pixel region 220 may be as described below, such as Figure 3 Configure it as discussed in the diagram below.

[0057] Figure 3 These are examples of some implementation methods based on the disclosed technology. Figure 2 The circuit diagram of the example model of the first pixel region 210 or the second pixel region 220 shown.

[0058] Reference Figure 3 , Figure 3 The circuit diagram may include the first photoelectric conversion element to the sixteenth photoelectric conversion element (PD1-PD16), the first transmission transistor to the sixteenth transmission transistor (TX1-TX16), the first reset transistor and the second reset transistor (RX1, RX2), the first floating diffusion node and the second floating diffusion node (FD1, FD2), the first driving transistor to the sixth driving transistor (DX1-DX6), the first selection transistor to the fourth selection transistor (SX1-SX4), and the first DCG transistor to the fourth DCG transistor (GX1-GX4).

[0059] Each of the first to the sixteenth photoelectric conversion elements (PD1-PD16) can generate photocharge in response to incident light within the photocharge accumulation section.

[0060] As will be discussed below, the transfer transistors (TX1-TX16, RX1-RX2, SX1-SX4, GX1-GX4) can receive electrical signals (e.g., transfer signals, reset signals, select signals, and gain signals) through their gate terminals. In some implementations, the transfer transistors (TX1-TX16) can receive transfer signals through their gate terminals, the reset transistors (RX1-RX2) can receive reset signals through their gate terminals, the select transistors (SX1-SX4) can receive select signals through their gate terminals, and the DCG transistors (GX1-GX4) can receive gain signals through their gate terminals. Each electrical signal can have a logic high level or a logic low level. When a high-level electrical signal is applied to the gate of the transistor, the transistor can be turned on. When a low-level electrical signal is applied to the gate of the transistor, the transistor can be turned off. However, this disclosure is not limited thereto. In another example, the transistors can be implemented as PMOS transistors, and thus can be turned on by a low-level electrical signal and turned off by a high-level electrical signal.

[0061] The first to sixteenth transmission transistors (TX1-TX16) can each receive transmission signals (TS1-TS16) through their gate terminals. When each of the first to sixteenth transmission transistors (TX1-TX16) is turned on, photocharge can move to the first floating diffusion node or the second floating diffusion node (FD1, FD2), and when each of the first to sixteenth transmission transistors (TX1-TX16) is turned off, it can prevent the photocharge accumulated in the first to sixteenth photoelectric conversion elements (PD1-PD16) from moving to the first floating diffusion node or the second floating diffusion node (FD1, FD2).

[0062] For example, the first transfer transistor (TX1) is turned on during the pixel readout period to transfer the photocharge generated by the first photoelectric conversion element (PD1) to the first floating diffusion node (FD1). The ninth transfer transistor (TX9) can be turned on during the pixel readout period to transfer the photocharge generated by the ninth photoelectric conversion element (PD9) to the second floating diffusion node (FD2). The pixel readout period can occur after the photocharge accumulation period.

[0063] In one embodiment, some of the first through sixteenth transfer transistors (TX1-TX16) can be turned on simultaneously. In another embodiment, the first through sixteenth transfer transistors (TX1-TX16) can be turned on and off sequentially, such that one transistor turns on and then off, followed by the next transistor turning on and then off. For example, one of the first through sixteenth transfer transistors (TX1-TX16) turns on and then off, and then the next transistor among the first through sixteenth transfer transistors (TX1-TX16) turns on and then off. This process continues sequentially until the last transistor among the first through sixteenth transfer transistors (TX1-TX16) is finally turned on and off.

[0064] The first reset transistor and the second reset transistor (RX1, RX2) can receive reset signals (RS1, RS2) through their respective gate terminals. For example, the first reset transistor (RX1) can receive the reset signal (RS1) through its gate terminal, and the second reset transistor (RX2) can receive the reset signal (RS2) through its gate terminal. The first reset transistor (RX1) can be turned on during the pixel reset period to reset the voltage of the first floating diffusion node (FD1) to the power supply voltage (VDD). The second reset transistor (RX2) can be turned on during the pixel reset period to reset the voltage of the second floating diffusion node (FD2) to the power supply voltage (VDD). In this case, the pixel reset period can be located before the pixel readout period.

[0065] The first floating diffusion node (FD1) may have a first capacitor (CFD1) as its intrinsic capacitor. The second floating diffusion node (FD2) may have a second capacitor (CFD2) as its intrinsic capacitor.

[0066] The first to eighth transmission transistors (TX1-TX8) and the first floating diffusion node (FD1) can be electrically connected to each other via the first central electrical interconnect. The ninth to sixteenth transmission transistors (TX9-TX16) and the second floating diffusion node (FD2) can be electrically connected to each other via the second central electrical interconnect.

[0067] During the pixel readout period, each of the first to third driving transistors (DX1-DX3) can receive the voltage of the first floating diffusion node (FD1) through its gate terminal. The first to third driving transistors (DX1-DX3) can amplify an electrical signal corresponding to the voltage level of the first floating diffusion node (FD1) and can send the amplified electrical signal to the first and second selection transistors (SX1-SX2). The first to third driving transistors (DX1-DX3) can be connected to the power supply voltage (VDD) through their drain terminals.

[0068] During the pixel readout period, each of the fourth to sixth driving transistors (DX4-DX6) can receive the voltage of the second floating diffusion node (FD2) through its gate terminal. The fourth to sixth driving transistors (DX4-DX6) can amplify the electrical signal corresponding to the voltage level of the second floating diffusion node (FD2) and can send the amplified electrical signal to the third and fourth selection transistors (SX3-SX4). The fourth to sixth driving transistors (DX4-DX6) can be connected to the power supply voltage (VDD) through their drain terminals.

[0069] The first to fourth selection transistors (SX1-SX4) can each receive selection signals (SS1-SS4) through their gate terminals. When each of the first and second selection transistors (SX1-SX2) is turned on in response to the corresponding selection signal (SS1-SS4), the amplified electrical signals output from the first to third driving transistors (DX1-DX3) can be output to the column bus (CBL). When each of the third and fourth selection transistors (SX3-SX4) is turned on in response to the corresponding selection signal (SS1-SS4), the amplified electrical signals output from the fourth to sixth driving transistors (DX4-DX6) can be output to the column bus (CBL).

[0070] When multiple drive transistors (or multiple select transistors) are operated in parallel, the output impedance is reduced compared to using only a single drive transistor, thereby reducing electrical signal distortion and improving signal transmission efficiency. Furthermore, since the current is distributed among multiple transistors, the thermal load on each transistor is reduced. As a result, overheating of the transistors can be prevented, thereby enhancing the thermal management efficiency of the image sensing device 1 and improving the reliability and lifespan of the transistors. Additionally, since the parallel connection of transistors can distribute the noise of each transistor, the overall noise can be reduced and the signal-to-noise ratio (SNR) of the pixel signal can be improved. In another example, each of the drive transistor and select transistor connected to the first floating diffusion node (FD1) or the second floating diffusion node (FD2) can be implemented as a single transistor.

[0071] The first to fourth DCG transistors (GX1-GX4) can each receive gain signals (GS1-GS4) through their respective gate terminals. Each of the gain signals (GS1-GS4) can have a high level during the pixel readout period.

[0072] A first DCG transistor (GX1) may be electrically connected to a first floating diffusion node (FD1). The first DCG transistor (GX1) may have a first parasitic capacitor (not shown). When the first DCG transistor (GX1) is turned on, current can flow between the first floating diffusion node (FD1) and the first parasitic capacitor, thereby increasing the capacitance of the first floating diffusion node (FD1). As the capacitance of the first floating diffusion node (FD1) increases, the voltage per unit charge can decrease, resulting in a decrease in conversion gain.

[0073] The second DCG transistor (GX2) may be electrically connected to the first DCG transistor (GX1). The second DCG transistor (GX2) may include a second parasitic capacitor (not shown). When the first DCG transistor (GX1) and the second DCG transistor (GX2) are turned on, the capacitance of the first floating diffusion node (FD1) may be further increased. As the capacitance of the first floating diffusion node (FD1) further increases, the voltage per unit charge may be further reduced, resulting in a further reduction in the conversion gain.

[0074] The third DCG transistor (GX3) can be electrically connected to the second floating diffusion node (FD2). The third DCG transistor (GX3) can also be electrically connected to the first floating diffusion node (FD1). The third DCG transistor (GX3) may include a third parasitic capacitor (not shown). When the third DCG transistor (GX3) is turned on, current can flow between the second floating diffusion node (FD2) and the third parasitic capacitor, allowing the capacitance of the second floating diffusion node (FD2) to increase. As the capacitance of the second floating diffusion node (FD2) increases, the voltage per unit charge can decrease, resulting in a decrease in conversion gain.

[0075] A fourth DCG transistor (GX4) can be electrically connected to a second DCG transistor (GX2). The fourth DCG transistor (GX4) can also be electrically connected to a fourth parasitic capacitor (not shown). When the third DCG transistor (GX3) and the fourth DCG transistor (GX4) are turned on, the capacitance of the second floating diffusion node (FD2) can be further increased. As the capacitance of the second floating diffusion node (FD2) further increases, the voltage per unit charge can be further reduced, resulting in a further reduction in the conversion gain.

[0076] The image sensing device 1, based on some embodiments of the disclosed technology, can implement, for example, triple conversion gain (TCG). Triple conversion gain may include high conversion gain (HCG), medium conversion gain (MCG), and low conversion gain (LCG).

[0077] When all four DCG transistors (GX1-GX4) are turned on, the electrical signal generated by each of the first to sixteenth photoelectric conversion elements (PD1-PD16) in response to incident light can be output with low conversion gain.

[0078] When the first DCG transistor (GX1) is turned on and the second to fourth DCG transistors (GX2-GX4) are turned off, the electrical signal generated by each of the first to eighth photoelectric conversion elements (PD1-PD8) in response to the incident light can be output using the intermediate conversion gain.

[0079] When the third DCG transistor (GX3) is turned on and the first DCG transistor, the second DCG transistor, and the fourth DCG transistor (GX1, GX2, GX4) are turned off, the electrical signal generated by each of the ninth to sixteenth photoelectric conversion elements (PD1-PD16) in response to the incident light can be output using the intermediate conversion gain.

[0080] When all four DCG transistors (GX1-GX4) are turned off, the electrical signal generated by each of the first to sixteenth photoelectric conversion elements (PD1-PD16) in response to incident light can be output with high conversion gain.

[0081] In the disclosed embodiments, the high conversion gain can be eight times the low conversion gain. The medium conversion gain can be twice the low conversion gain. In this way, the conversion gain ratio of the triple conversion gain can be 1:2:8. However, this disclosure is not limited to this, and the conversion gain ratio can be designed in various ways by adjusting the dimensions of the first DCG transistors to the fourth DCG transistors (GX1-GX4) and the first capacitor CFD1 and the second capacitor CFD2.

[0082] Figure 4 These are examples of some implementation methods based on the disclosed technology. Figure 2 A plan view of an example of the first pixel region 210 shown.

[0083] In the following text, the ellipsis and Figure 3 Some redundant descriptions overlap.

[0084] Reference Figure 3 and Figure 4 The first pixel region 210 may include a first pixel group (GPX1), a second pixel group (GPX2), and a pixel isolation structure 310.

[0085] The pixel isolation structure 310 may include a first pixel isolation structure 311 and a second pixel isolation structure 312.

[0086] The first pixel isolation structure 311 can be arranged in a grid shape along one or more boundaries between pixels. The first pixel isolation structure 311 arranged in a grid shape can define multiple pixels. Each region surrounded by the first pixel isolation structure 311 can constitute a pixel. The first pixel isolation structure 311 can optically isolate adjacent pixels from each other. The first pixel isolation structure 311 can include, for example, an insulating layer (e.g., SiO2, etc.) or a conductive layer (e.g., polysilicon, polysilicon including impurities, etc.).

[0087] The second pixel isolation structure 312 can extend from the first pixel isolation structure 311 toward the interior of each pixel. The second pixel isolation structure 312 can extend from each of the two facing side surfaces of the first pixel isolation structure 311 toward the interior of each pixel. The second pixel isolation structure 312 can reduce crosstalk between two different photoelectric conversion elements disposed within a pixel. The second pixel isolation structure 312 may include, for example, an insulating layer (e.g., SiO2) or a conductive layer (e.g., polysilicon, polysilicon including impurities, etc.).

[0088] The first pixel group (GPX1) may include the first pixel to the fourth pixel (PX1-PX4). The first pixel group (GPX1) may be formed as a structure in which the first pixel to the fourth pixel (PX1-PX4) are arranged in a (2×2) matrix structure.

[0089] Referring to the constituent components included in each of the first to fourth pixels (PX1-PX4), the first pixel (PX1) may include a first transmission gate and a second transmission gate (TXG1, TXG2), a first photoelectric conversion element and a second photoelectric conversion element (PD1, PD2), a ground region 320 and a first floating diffusion region 330.

[0090] Each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) can generate photocharge in response to incident light. The first photoelectric conversion element (PD1) can be spaced apart from the second photoelectric conversion element (PD2). The second pixel isolation structure 312 can be disposed between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2).

[0091] The first transmission gate (TXG1) may include an electrode layer comprising a conductive material (e.g., polysilicon, metal, etc.) and an insulating layer comprising an insulating material (e.g., silicon oxide, etc.). The first transmission gate (TXG1) may receive an operating voltage via a predetermined contact-interconnect (hereinafter referred to as the first transmission transistor contact-interconnect). The first transmission gate (TXG1) may be the gate of the first transmission transistor (TX1). The first transmission gate (TXG1) may overlap with the first photoelectric conversion element (PD1).

[0092] Each of the various gates described below may include an electrode layer comprising a conductive material (e.g., polysilicon, metal, etc.) and an insulating layer comprising an insulating material (e.g., silicon oxide, etc.).

[0093] The second transmission gate (TXG2) may be the gate of the second transmission transistor (TX2). The second transmission gate (TXG2) may receive an operating voltage via a predetermined contact-interconnect (hereinafter referred to as the second transmission transistor contact-interconnect). When an operating voltage is applied to the second transmission gate (TXG2), the photocharge generated and accumulated in the second photoelectric conversion element (PD2) may move to the first floating diffusion region 330. The second transmission gate (TXG2) may overlap with the second photoelectric conversion element (PD2).

[0094] The first floating diffusion region 330 may be adjacent to each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). The first floating diffusion region 330 may store photocharge generated by the first photoelectric conversion element (PD1) and / or the second photoelectric conversion element (PD2), and a voltage corresponding to the stored photocharge may be applied to one or more driving gates (DXG1, DXG2). Each of the plurality of first floating diffusion regions 330 may be arranged to correspond to a photoelectric conversion element and a transmission gate, such that the first floating diffusion region 330 may be arranged adjacent to the transmission gate one by one. For example, one first floating diffusion region 330 may be arranged adjacent to the first transmission gate (TXG1) and another first floating diffusion region 330 may be arranged adjacent to the second transmission gate (TXG2), and these two first floating diffusion regions 330 may be arranged separately from each other. The plurality of first floating diffusion regions 330 may be electrically connected via a single electrical interconnect (hereinafter referred to as the first central electrical interconnect).

[0095] Grounding regions 320 can be arranged between the second pixel isolation structures 312 facing each other. Grounding regions 320 can be regions to which a ground voltage is applied. When a ground voltage is applied to grounding regions 320, the potentials of the components included in the pixel can be stabilized, and, for example, the well capacity of the photoelectric conversion element can be kept constant.

[0096] Each of the second to fourth pixels (PX2-PX4) may also include at least two photoelectric conversion elements, gates of at least two transmission transistors, and at least one floating diffusion region, and the same content as that of the first pixel (PX1) may be applied to each of the second to fourth pixels (PX2-PX4). For example, the second pixel (PX2) may include a third photoelectric conversion element (PD3) and a fourth photoelectric conversion element (PD4), a third transmission gate (TXG3) and a fourth transmission gate (TXG4), and a first floating diffusion region 330. For example, when an operating voltage is applied to the third transmission gate (TXG3), the photocharge generated by the third photoelectric conversion element (PD3) in response to incident light may move to the first floating diffusion region 330.

[0097] In addition, the multiple first floating diffusion regions 330 included in the first to fourth pixels (PX1-PX4) can all be electrically connected through the first central electrical interconnect.

[0098] Referring to the configuration shared by the first to fourth pixels (PX1-PX4), the first pixel (PX1) may include a first driving gate and a second driving gate (DXG1, DXG2), a driving drain region 351, and a driving source region 352. The second pixel (PX2) may include a third driving gate (DXG3), a first reset gate (RXG1), a driving drain region 351, a driving source region 352, a first reset drain region 341, and a first reset source region 342. The third pixel (PX3) may include a first selection gate and a second selection gate (SXG1, SXG2), a selection drain region 371, and a selection source region 372. The fourth pixel (PX4) may include a first DCG gate and a second DCG gate (GXG1, GXG2), a first DCG source region 381, a first DCG drain region 382, ​​a second DCG source region 391, and a second DCG drain region 392.

[0099] Each of the first driving gates to the third driving gates (DXG1-DXG3) can receive a voltage corresponding to the photocharge accumulated in the first floating diffusion region 330. Each of the first driving gates to the third driving gates (DXG1-DXG3) can be electrically connected to the first floating diffusion region 330 via a first central electrical interconnect. When a voltage is applied to the gates (DXG1-DXG3) of the first driving transistors to the third driving transistors, the first driving transistors to the third driving transistors (DX1-DXG3) having gate terminals that receive the operating voltage can amplify the electrical signal to be applied to the first selection transistor and the second selection transistor (SX1, SX2).

[0100] The first driving gate (DXG1) can be the gate of the first driving transistor (DX1). The second driving gate (DXG2) can be the gate of the second driving transistor (DX2). The third driving gate (DXG3) can be the gate of the third driving transistor (DX3). The first driving gate (DXG1) can overlap with the first photoelectric conversion element (PD1). The second driving gate (DXG2) can overlap with the second photoelectric conversion element (PD2). The third driving gate (DXG3) can overlap with the third photoelectric conversion element (PD3).

[0101] The drive drain region 351 can be configured to receive the power supply voltage VDD (see [link]). Figure 3 The driving drain region 351 can have a structure corresponding to the drain terminals of the first to third driving transistors (DX1-DX3). The driving drain region 351 can be adjacent to each of the first and second driving gates (DXG1, DXG2).

[0102] The driving source region 352 can be electrically connected to the selected source region 372 via predetermined electrical interconnects (hereinafter referred to as driving electrical interconnects). The driving source region 352 can serve as the output node of each of the first to third driving transistors (DX1-DX3), and the amplified electrical signal can be output to the source terminals of the selected transistors (SX1 to SX2). The driving source region 352 can be a structure corresponding to the source terminals of the first to third driving transistors (DX1-DX3). The driving source region 352 can be adjacent to each of the first and second driving gates (DXG1, DXG2) and can be spaced apart from the driving drain region 351.

[0103] The first reset gate (RXG1) may be the gate of the first reset transistor (RX1). For example, when an operating voltage is applied to the first reset gate (RXG1) during a pixel reset period, the voltage of the first floating diffusion region 330 can be reset to the power supply voltage (VDD). When a pixel readout period is performed after the voltage of the first floating diffusion region 330 has been reset to the power supply voltage (VDD), the accuracy of the intensity of the pixel signal output in response to the amount of photocharge generated by the photoelectric conversion element can be increased. The first reset gate (RXG1) may overlap with the fourth photoelectric conversion element (PD4).

[0104] The first reset drain region 341 may be configured to receive the power supply voltage VDD (see [reference]). Figure 3 (area).

[0105] The first reset drain region 341 can be configured to correspond to the drain terminal of the first reset transistor (RX1).

[0106] The first reset drain region 341 may be adjacent to the first reset gate (RXG1).

[0107] The first reset source region 342 can be electrically connected to the first floating diffusion region 330 via a first center-current interconnect. The first reset source region 342 can be configured to correspond to the source terminal of the first reset transistor (RX1). The first reset source region 342 can be adjacent to the first reset gate (RXG1).

[0108] The first selection gate (SXG1) can be the gate of the first selection transistor (SX1). The second selection gate (SXG2) can be the gate of the second selection transistor (SX2). The first selection gate (SXG1) can overlap with the fifth photoelectric conversion element (PD5). The second selection gate (SXG2) can overlap with the sixth photoelectric conversion element (PD6). When an operating voltage is applied to the first selection gate (SXG1) and / or the second selection gate (SXG2), the amplified electrical signal can be output to the column bus (CBL) (see...). Figure 3 The amplified electrical signal can be transmitted via the column bus (). Figure 3 The CBL is sent to CDS130 (see Figure 1 ).

[0109] The selected drain region 371 can be electrically connected to the column bus (CBL) via a predetermined electrical interconnect (hereinafter referred to as the selected electrical interconnect) (see [reference]). Figure 3 The selected drain region 371 can be configured to correspond to the drain terminals of the first selected transistor and the second selected transistor (SX1, SX2). The selected drain region 371 can be adjacent to the first selected gate (SXG1) and the second selected gate (SXG2), respectively.

[0110] The selected drain region 371 can be electrically connected to the column bus CBL (see below) via a predetermined electrical interconnect (hereinafter referred to as the selected electrical interconnect). Figure 3 The selected drain region 371 may correspond to the drain terminals of the first selected transistor SX1 and the second selected transistor SX2. Each of the selected drain regions 371 may be adjacent to each of the first selected gate SXG1 and the second selected gate SXG2.

[0111] The selected source region 372 can be electrically connected to the driven source region 352 via a drive interconnect. The selected source region 372 can be configured to correspond to the source terminals of the first selected transistor and the second selected transistor (SX1, SX2). The selected source region 372 can be adjacent to the first selected gate (SXG1) and the second selected gate (SXG2), respectively.

[0112] The first DCG gate (GXG1) may be the gate of the first DCG transistor (GX1). The first DCG gate (GXG1) may overlap with the seventh photoelectric conversion element (PD7). When an operating voltage is applied to the first DCG gate (GXG1), the conversion gain of the first pixel group (GPX1) or the conversion gain of each pixel included in the first pixel group (GPX1) may be adjusted. For example, the conversion gain of the first pixel (PX1) may be adjusted. The first DCG gate (GXG1) may receive the operating voltage through a predetermined electrical interconnect (hereinafter referred to as the first DCG contact-interconnect). The first DCG gate (GXG1) may be arranged from the center of the fourth pixel (PX4) to the sixth pixel (PX6) including the third DCG gate (GXG3).

[0113] The first DCG source region 381 can be electrically connected to the first floating diffusion region 330 via a first central electrical interconnect. The first DCG source region 381 can be arranged adjacent to the first DCG gate (GXG1). The first DCG source region 381 can be a structure corresponding to the source terminal of the first DCG transistor (GX1).

[0114] The first DCG drain region 382 can be electrically connected to the third DCG drain region 482 via a predetermined electrical interconnect (hereinafter referred to as the first DCG electrical interconnect). The first DCG drain region 382 can be electrically connected to the second DCG source region 391 via a predetermined electrical interconnect (hereinafter referred to as the third DCG electrical interconnect). The third DCG electrical interconnect may be spaced apart from the first DCG electrical interconnect or may be in contact with the first DCG electrical interconnect. The first DCG drain region 382 may be a structure corresponding to the drain terminal of the first DCG transistor (GX1). The first DCG drain region 382 may be arranged adjacent to the first DCG gate (GXG1). For example, the first DCG drain region 382 may be arranged to be adjacent to the first DCG gate (GXG1) at a position closer to the sixth pixel (PX6) than the first DCG source region 381. Since the first DCG drain region 382 is located closer to the boundary between the fourth pixel (PX4) and the sixth pixel (PX6) or the boundary between the first pixel group (GPX1) and the second pixel group (GPX2), the length of the first DCG electrical interconnect can be shortened.

[0115] As the length of the DCG electrical interconnect increases, the parasitic resistance and capacitance of the DCG transistor increase, potentially making the DCG transistor's conversion gain value unsuitable because the DCG ratio between low and high conversion gain states may need to be modified. Consequently, due to the shorter length of the first DCG electrical interconnect, the conversion gain value of the DCG transistor can be designed more accurately. For example, when the gates (GXG1) and (GXG3) of the first and third DCG transistors are set to be biased from the center of each pixel along a direction in which the gates (GXG1) and (GXG3) are closer to each other, the length of the first DCG electrical interconnect can be shortened, and a more accurate conversion gain ratio design becomes possible.

[0116] The second DCG gate (GXG2) can be the gate of the second DCG transistor (GX2). The second DCG gate (GXG2) can overlap with the eighth photoelectric conversion element (PD8). When the operating voltages of the first DCG transistor and the second DCG transistor (GX1, GX2) are applied to the first DCG gate and the second DCG gate (GXG1, GXG2), respectively, the conversion gain of the first pixel group (GPX1) or the conversion gain of each pixel included in the first pixel group (GPX1) can be adjusted. For example, the conversion gain of the first pixel (PX1) can be adjusted. The second DCG gate (GXG2) can receive the operating voltage through a predetermined electrical interconnect (hereinafter referred to as the second DCG contact-interconnect). The second DCG gate (GXG2) can be arranged to approach the sixth pixel (PX6) including the fourth DCG gate (GXG4) from the center of the fourth pixel (PX4).

[0117] The second DCG source region 391 can be electrically connected to the first DCG drain region 382 via a third DCG electrical interconnect. The second DCG source region 391 can be arranged adjacent to the second DCG gate (GXG2). The second DCG source region 391 can be configured to correspond to the source terminal of the second DCG transistor (GX2).

[0118] The second DCG drain region 392 can be electrically connected to the fourth DCG drain region 492 via a predetermined electrical interconnect (hereinafter referred to as the second DCG electrical interconnect). The second DCG drain region 392 can be configured to correspond to the drain terminal of the second DCG transistor (GX2). The second DCG drain region 382 can be arranged adjacent to the second DCG gate (GXG2). For example, the second DCG drain region 392 can be arranged to be adjacent to the second DCG gate (GXG2) closer to the sixth pixel (PX6) than the second DCG source region 391. Since the second DCG drain region 392 is positioned closer to the boundary between the fourth pixel (PX4) and the sixth pixel (PX6) or the boundary between the first pixel group (GPX1) and the second pixel group (GPX2), the length of the second DCG electrical interconnect can be shortened.

[0119] The positions of the first selection transistor and the second selection transistor (SX1, SX2), the positions of the first driving transistor to the third driving transistor (DX1-DX3), and the position of the first reset transistor (RX1) in the components included in the first pixel group (GPX1) can be interchanged as needed.

[0120] The second pixel group (GPX2) may include the fifth to eighth pixels (PX5-PX8) and pixel isolation structure 310. The second pixel group (GPX2) may be configured such that the fifth to eighth pixels (PX5-PX8) are arranged in a (2×2) matrix structure.

[0121] In an implementation, the components included in the second pixel group (GPX2) can be arranged symmetrically with respect to the boundary between the first pixel group (GPX1) and the second pixel group (GPX2) and the components included in the first pixel group (GPX1). For example, the first pixel (PX1) can be arranged symmetrically with respect to the seventh pixel (PX7) based on the aforementioned boundary. The second pixel (PX2) can be arranged symmetrically with respect to the eighth pixel (PX8) relative to the aforementioned boundary. The third pixel (PX3) can be arranged symmetrically with respect to the boundary with respect to the fifth pixel (PX5). The fourth pixel (PX4) can be arranged symmetrically with respect to the aforementioned boundary with respect to the sixth pixel (PX6).

[0122] In this document, the aforementioned symmetry between pixels can mean, for example, that the first DCG gate (GXG1) of the fourth pixel (PX4) and the third DCG gate (GXG3) of the sixth pixel (PX6) are positioned symmetrically to each other with respect to the above boundaries.

[0123] In some implementations, in a symmetrical configuration, the symmetry between the constituent components does not need to be mathematically rigorously determined based on whether their distances from the boundaries of the constituent components are exactly equal, and can be adjusted due to variables or constraints in the manufacturing process. Additionally, to reduce the lengths of the first and second DCG electrical interconnects, the aforementioned symmetry may include an arrangement in which the first DCG transistor (GX1) (or the second DCG transistor GX2) and the third DCG transistor (GX3) (or the fourth DCG transistor GX4) belonging to different pixel groups are arranged facing each other relative to the aforementioned boundaries interposed therebetween.

[0124] In the symmetrical arrangement described above, the constituent components (e.g., the first transmission gate TXG1 overlapping with the first pixel PX1 and the thirteenth transmission gate TXG13 overlapping with the seventh pixel PX7) can have substantially the same function and structure. In the following, as representative examples, the fourth pixel (PX4) and the constituent components included in the fourth pixel (PX4), as well as the sixth pixel (PX6) and the constituent components included in the sixth pixel (PX6), will be described in detail.

[0125] The sixth pixel (PX6) may include an eleventh photoelectric conversion element and a twelfth photoelectric conversion element (PD11, PD12), an eleventh transmission gate and a twelfth transmission gate (TXG11, TXG12), a second floating diffusion region 430, a third DCG gate and a fourth DCG gate (GCG3, GCG4), a third DCG source region 481, a third DCG drain region 482, a fourth DCG source region 491 and a fourth DCG drain region 492.

[0126] Each of the eleventh photoelectric conversion element (PD11) and the twelfth photoelectric conversion element (PD12) can generate photocharge in response to incident light. The eleventh photoelectric conversion element (PD11) can be spaced apart from the twelfth photoelectric conversion element (PD12). A second pixel isolation structure 312 can be disposed between the eleventh photoelectric conversion element (PD11) and the twelfth photoelectric conversion element (PD12).

[0127] The eleventh transfer gate (TXG11) can receive the operating voltage via a predetermined contact-interconnect (hereinafter referred to as the eleventh transfer transistor contact-interconnect). When an operating voltage is applied to the gate (TXG11) of the eleventh transfer transistor, the photocharge generated and accumulated in the eleventh photoconversion element (PD11) can move to the second floating diffusion region 430. The eleventh transfer gate (TXG11) can be the gate of the eleventh transfer transistor (TX11).

[0128] The twelfth transfer gate (TXG12) can receive the operating voltage via a predetermined contact-interconnect (hereinafter referred to as the twelfth transfer transistor contact-interconnect). When an operating voltage is applied to the gate (TXG12) of the twelfth transfer transistor, the photocharge generated and accumulated in the twelfth photoconversion element (PD12) can move to the second floating diffusion region 430. The twelfth transfer gate (TXG12) can be the gate of the twelfth transfer transistor (TX12).

[0129] The second floating diffusion region 430 can be arranged adjacent to each of the eleventh transmission gate (TXG11) and the twelfth transmission gate (TXG12). The second floating diffusion region 430 can store photocharge generated by the eleventh photoconversion element (PD11) and / or the twelfth photoconversion element (PD12), and a voltage corresponding to the stored photocharge can be applied to the third driving gate (DXG3) and / or the fourth driving gate (DXG4). Each of the plurality of second floating diffusion regions 430 can be arranged corresponding to one photoconversion element and one transmission gate, such that the second floating diffusion regions 430 can be arranged adjacent to the transmission gates in a one-to-one correspondence. For example, one second floating diffusion region 430 can be arranged adjacent to the eleventh transmission gate (TXG11), and another second floating diffusion region 430 can be arranged adjacent to the twelfth transmission gate (TXG12), and these two floating diffusion regions can be arranged to be isolated from each other. The plurality of second floating diffusion regions 430 can be electrically connected by an electrical interconnect (hereinafter referred to as the second central electrical interconnect).

[0130] The third DCG gate (GXG3) can be the gate of the third DCG transistor (GX3). The third DCG gate (GXG3) can overlap with the eleventh photoelectric conversion element (PD11). When an operating voltage is applied to the third DCG gate (GXG3), the conversion gain of the second pixel group (GPX2) or the conversion gain of each pixel included in the second pixel group (GPX2) can be changed. For example, the conversion gain of the seventh pixel (PX7) can be changed. The third DCG gate (GXG3) can receive the operating voltage through a predetermined electrical interconnect (hereinafter referred to as the third DCG contact-interconnect). The third DCG gate (GXG3) can be arranged closer to the fourth pixel (PX4) including the first DCG gate (GXG1) from the center of the sixth pixel (PX6).

[0131] The third DCG source region 481 can be electrically connected to the second floating diffusion region 430 via the second central electrical interconnect. The third DCG source region 481 can be arranged adjacent to the third DCG gate (GXG3). The third DCG source region 481 can be a structure corresponding to the source terminal of the third DCG transistor (GX3).

[0132] The third DCG drain region 482 can be electrically connected to the first DCG drain region 482 via a predetermined electrical interconnect (hereinafter referred to as the first DCG electrical interconnect). The third DCG drain region 482 can be electrically connected to the fourth DCG source region 491 via a predetermined electrical interconnect (hereinafter referred to as the fourth DCG electrical interconnect). The fourth DCG electrical interconnect can be spaced apart from the first DCG electrical interconnect or can be in contact with the first DCG electrical interconnect. The third DCG drain region 482 can be a structure corresponding to the drain terminal of the third DCG transistor (GX3). The third DCG drain region 482 can be arranged adjacent to the third DCG gate (GXG3). For example, the third DCG drain region 482 can be arranged to be adjacent to the third DCG gate (GXG3) at a position closer to the fourth pixel (PX4) than the third DCG source region 481. Since the third DCG drain region 482 is arranged closer to the boundary between the fourth pixel (PX4) and the sixth pixel (PX6) or the boundary between the first pixel group (GPX1) and the second pixel group (GPX2), the length of the first DCG electrical interconnect can be shortened.

[0133] The fourth DCG gate (GXG4) can be the gate of the fourth DCG transistor (GX4). The fourth DCG gate (GXG4) can overlap with the twelfth photoelectric conversion element (PD12). When the operating voltages of the third and fourth DCG transistors (GX3, GX4) are applied to the third and fourth DCG gates (GXG3, GXG4), the conversion gain of the second pixel group (GPX2) or the conversion gain of each pixel included in the second pixel group (GPX2) can be changed. For example, the conversion gain of the seventh pixel (PX7) can be changed. The fourth DCG gate (GXG4) can receive the operating voltage through a predetermined electrical interconnect (hereinafter referred to as the fourth DCG contact-interconnect). The fourth DCG gate (GXG4) can be arranged closer to the fourth pixel (PX4) including the second DCG gate (GXG2) from the center of the sixth pixel (PX6).

[0134] The fourth DCG source region 491 can be electrically connected to the third DCG drain region 482 via the fourth DCG electrical interconnect. The fourth DCG source region 491 can be arranged adjacent to the fourth DCG gate (GXG4). The fourth DCG source region 491 can be a structure corresponding to the source terminal of the fourth DCG transistor (GX4).

[0135] The fourth DCG drain region 492 can be electrically connected to the second DCG drain region 392 via a predetermined electrical interconnect (hereinafter referred to as the second DCG electrical interconnect). The fourth DCG drain region 492 may be a structure corresponding to the drain terminal of the fourth DCG transistor (GX4). The fourth DCG drain region 492 may be arranged adjacent to the fourth DCG gate (GXG4). For example, the fourth DCG drain region 492 may be arranged to be adjacent to the fourth DCG gate (GXG4) closer to the fourth pixel (PX4) than the fourth DCG source region 491. Since the fourth DCG drain region 492 is set closer to the boundary between the sixth pixel (PX6) and the fourth pixel (PX4) or the boundary between the first pixel group (GP1) and the second pixel group (GP2), the length of the second DCG electrical interconnect can be shortened.

[0136] The pixel array 200 based on the disclosed technology can be repeatedly arranged using eight pixels arranged in a (2×4) matrix structure (shown in the first pixel region 210) as a unit pixel region.

[0137] Figure 5A This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line A-A' is shown.

[0138] Reference Figures 3 to 5A The first cross section 500A may include an electrical interconnect layer 910 and a photoelectric conversion layer 920.

[0139] The photoelectric conversion layer 920 may include a first photoelectric conversion element (PD1), a second photoelectric conversion element (PD2), a second pixel isolation structure 312, a vertical portion (TXG2V) of the gate of a second transmission transistor, a ground region 320, a first floating diffusion region 330, a driving drain region 351, a driving source region 352, and a semiconductor region 921. The photoelectric conversion layer 920 may include a back surface 902 on which light from the outside is incident, and a front surface 901 facing or opposite to the back surface 902.

[0140] When incident light strikes either the first photoelectric conversion element (PD1) or the second photoelectric conversion element (PD2), photocharge can be generated. The generated photocharge can accumulate in each of the photoelectric conversion elements (PD1, PD2). Each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may include a predetermined impurity. For example, each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be a region including impurities of a first conductivity type (e.g., N-type impurities). Each of the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) may be surrounded by a semiconductor region 921.

[0141] The second pixel isolation structure 312 can reduce crosstalk between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2) by optically blocking them. The second pixel isolation structure 312 can be formed by a front-side deep trench isolation (FDTI) process in which trenches are formed from the front surface 901, or by a back-side deep trench isolation (BDTI) process in which trenches are formed from the back surface 902. For example, the second pixel isolation structure 312 can penetrate the photoelectric conversion layer 920.

[0142] When an operating voltage is applied to the gate (TXG2) of the second transmission transistor, the first floating diffusion region 330 can store photocharge moving from the second photoelectric conversion element (PD2). The first floating diffusion region 330 can overlap or contact the gate (TXG2) of the second transmission transistor. The first floating diffusion region 330 can include predetermined impurities. For example, the first floating diffusion region 330 can be a region including impurities of a first conductivity type. The first floating diffusion region 330 can be spaced apart from the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2).

[0143] The drive drain region 351 may contact the power supply contact-interconnect 1351. The drive drain region 351 may overlap with or contact the first drive gate (DXG1). The drive drain region 351 may be spaced apart from the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). The drive drain region 351 may be located near the front surface 901.

[0144] The driving source region 352 may contact the driving electrical interconnect 1352. The driving source region 352 may overlap with or contact the first driving gate (DXG1). The driving source region 352 may be spaced apart from the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). The driving source region 352 may be disposed near the front surface 901. The driving source region 352 and the driving drain region 351 may be disposed at opposite ends of the first driving gate (DXG1).

[0145] Semiconductor region 921 may surround photoelectric conversion elements (PD1, PD2). Semiconductor region 921 may be the remaining region of photoelectric conversion layer 920. Photoelectric conversion layer 920 may surround multiple photoelectric conversion elements (e.g., first photoelectric conversion element PD1, second photoelectric conversion element PD2), various source regions (e.g., source region 352 of driving transistors), various drain regions (e.g., drain region 351 of driving transistors), and pixel isolation structures (e.g., second pixel isolation structure 312). Semiconductor region 921 may be a region including predetermined impurities. For example, semiconductor region 921 may include impurities of a second conductivity type (e.g., P-type impurities).

[0146] Ground region 320 may be disposed near the front surface 901 of photoelectric conversion layer 920 between the second pixel isolation structures 312 facing each other. Ground region 320 may be a region including predetermined impurities. For example, ground region 320 may include impurities of a second conductivity type. Ground region 320 may have a higher concentration of second conductive impurities than semiconductor region 921.

[0147] The vertical portion (TXG2V) of the gate of the second transfer transistor will be described below together with the second transfer transistor (TX2).

[0148] The electrical interconnect layer 910 may include a first driving gate (DXG1), a planar portion of the gate of the second transmission transistor (TXG2P), a second transmission transistor contact-interconnect 1020, a ground contact-interconnect 1320, a first center electrical interconnect 1330, a driving electrical interconnect 1352, a power supply contact-interconnect 1351, and an interlayer insulating layer 911.

[0149] The first driving gate (DXG1) can be disposed on the front surface 901. The gate (DXG1) of the first driving transistor can overlap with the first photoelectric conversion element (PD1). The gate (DXG1) of the first driving transistor can contact the first central electrical interconnect 1330.

[0150] The second transmission gate (TXG2) may include a planar portion (TXG2P) and a vertical portion (TXG2V) of the gate of the second transmission transistor. The planar portion (TXG2P) of the gate of the second transmission transistor may be disposed on the front surface 901. The planar portion (TXG2P) of the gate of the second transmission transistor may overlap with the second photoelectric conversion element (PD2). The vertical portion (TXG2V) of the second transmission transistor may be recessed from the bottom surface of the planar portion (TXG2P) of the gate of the second transmission transistor into the photoelectric conversion layer 920. The second transmission gate (TXG2) may contact the contact-interconnection 1020 of the second transmission transistor.

[0151] The second transmission transistor contact-interconnect 1020 may be an interconnect layer through which the operating voltage is applied to the gate (TXG2) of the second transmission transistor. The second transmission transistor contact-interconnect 1020 may include a conductive material (e.g., a metallic material).

[0152] The first central electrical interconnect 1330 may contact the first floating diffusion region 330. The first central electrical interconnect 1330 may also contact the gate (DXG1) of the first driving transistor. The first central electrical interconnect 1330 can electrically connect the first floating diffusion region 330 to the first driving gate (DXG1). The first central electrical interconnect 1330 may include a conductive material (e.g., a metallic material).

[0153] The drive electrical interconnect 1352 may contact the drive source region 352. The drive electrical interconnect 1352 may electrically connect a selected source region (not shown) to the drive source region 352. The drive electrical interconnect 1352 may include a conductive material (e.g., a metallic material).

[0154] Power contact interconnect 1351 may contact the drive drain region 351. Power contact interconnect 1351 may apply a power supply voltage (VDD) to the drive drain region 351. Power contact interconnect 1351 may include a conductive material (e.g., a metallic material).

[0155] The ground contact-interconnect 1320 can apply a ground voltage to the ground region 320. When a ground voltage is applied to the ground region 320 through the ground contact-interconnect 1320, the voltage in the semiconductor region 921 can become a ground voltage, and the electrical potential of each doped region adjacent to the semiconductor region 921 can remain constant.

[0156] Interlayer insulation 911 can be disposed between multiple interconnects spaced apart in the electrical interconnect layer 910. Interlayer insulation 911 can electrically insulate the multiple interconnects from each other. Interlayer insulation 911 may include insulating material (e.g., oxides, nitrides, etc.).

[0157] Figure 5B This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line B-B' is shown.

[0158] In the following text, the ellipsis and Figure 5A Some redundant descriptions overlap.

[0159] Reference Figures 3 to 5B The second section 500B may include an electrical interconnect layer 910 and a photoelectric conversion layer 920.

[0160] The photoelectric conversion layer 920 may include a seventh photoelectric conversion element (PD7), an eleventh photoelectric conversion element (PD11), a first pixel isolation structure 311, a first DCG source region 381, a first DCG drain region 382, ​​a third DCG source region 481, and a third DCG drain region 482.

[0161] Each of the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11) can generate photocharge in response to incident light. The seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11) can be spaced apart from each other relative to the first pixel isolation structure 311 interposed therebetween. Each of the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11) can be a region including impurities of a first conductivity type.

[0162] The first pixel isolation structure 311 may include a conductive material (e.g., polysilicon or polysilicon including impurities) and an insulating material surrounding the conductive material (e.g., silicon oxide or silicon nitride). In one embodiment, the first pixel isolation structure 311 may be an isolation structure formed by a recess process such as an FDTI process in which the first pixel isolation structure 311 is recessed from the front surface 901 into the photoelectric conversion layer 920. According to another embodiment, the first pixel isolation structure 311 may be an isolation structure formed by a recess process such as a BDTI process in which the first pixel isolation structure 311 is recessed from the back surface 902 into the photoelectric conversion layer 920. The first pixel isolation structure 311 may penetrate the photoelectric conversion layer 920. The first pixel isolation structure 311 can optically isolate the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11) from each other, and thus can reduce crosstalk between the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11).

[0163] The first DCG source region 381 may contact the first central electrical interconnect 1330. The first DCG source region 381 may be disposed near the front surface 901 and may be a region including impurities of a first conductivity type. The first DCG source region 381 may be spaced apart from the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11). The first DCG source region 381 may overlap with or contact the first DCG gate (GXG1).

[0164] The first DCG drain region 382 may contact the first DCG electrical interconnect 1380. For example, the first DCG drain region 382 may directly contact the first DCG electrical interconnect 1380. The first DCG drain region 382 may be disposed near the front surface 901 and may be a region including impurities of a first conductivity type. The first DCG drain region 382 may be spaced apart from the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11). The first DCG drain region 382 may overlap or contact the first DCG gate (GXG1). The first DCG drain region 382 and the first DCG source region 381 may be disposed at opposite ends of the first DCG gate (GXG1).

[0165] The third DCG source region 481 may contact the second central electrical interconnect 1430. The third DCG source region 481 may be disposed near the front surface 901 and may be a region including impurities of the first conductivity type. The third DCG source region 481 may be spaced apart from the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11). The third DCG source region 481 may overlap with or contact the third DCG gate (GXG3).

[0166] The third DCG drain region 482 may contact the first DCG electrical interconnect 1380. For example, the third DCG drain region 482 may directly contact the first DCG electrical interconnect 1380. The third DCG drain region 482 may be disposed near the front surface 901 and may be a region including impurities of the first conductivity type. The third DCG drain region 482 may be spaced apart from the seventh photoelectric conversion element (PD7) and the eleventh photoelectric conversion element (PD11). The third DCG drain region 482 may overlap or contact the third DCG gate (GXG3). The third DCG drain region 482 and the third DCG source region 481 may be disposed at both ends of the third DCG gate (GXG3).

[0167] The electrical interconnect layer 910 may include an interlayer insulating layer 911, a first DCG gate (GXG1), a third DCG gate (GXG3), a first center electrical interconnect 1330, a second center electrical interconnect 1430, a first DCG contact-interconnect 2010, a third DCG contact-interconnect 2030, and a first DCG electrical interconnect 1380.

[0168] The first DCG gate (GXG1) can be disposed on the front surface 901. The first DCG gate (GXG1) can overlap with the seventh photoelectric conversion element (PD7). The gate (GXG1) of the first DCG transistor can contact the first DCG contact-interconnect 2010.

[0169] The third DCG gate (GXG3) can be disposed on the front surface 901. The third DCG gate (GXG3) can overlap with the eleventh photoelectric conversion element (PD11). The gate (GXG3) of the third DCG transistor can contact the third DCG contact-interconnect 2030.

[0170] The first central electrical interconnect 1330 can also contact the first DCG source region 381. The first central electrical interconnect 1330 can electrically connect the first DCG source region 381 to the first floating diffusion region 330.

[0171] The second central electrical interconnect 1430 may also contact the third DCG source region 481. The second central electrical interconnect 1430 can electrically connect the third DCG source region 481 to the second floating diffusion region 430. The second central electrical interconnect 1430 may include a conductive material (e.g., a metallic material).

[0172] The first DCG contact-interconnect 2010 can send an operating voltage to the gate (GXG1) of the first DCG transistor. The first DCG contact-interconnect 2010 may include a conductive material (e.g., a metallic material).

[0173] The third DCG contact-interconnect 2030 can send the operating voltage to the gate (GXG3) of the third DCG transistor. The third DCG contact-interconnect 2030 may include a conductive material (e.g., a metallic material).

[0174] The first DCG electrical interconnect 1380 can electrically connect the drain region 382 of the first DCG transistor to the drain region 482 of the third DCG transistor. For example, the first DCG electrical interconnect 1380 can directly connect the drain region 382 of the first DCG transistor to the drain region 482 of the third DCG transistor. The first DCG electrical interconnect 1380 may include a conductive material (e.g., a metallic material). In some implementations, the first DCG transistor and the third DCG transistor are arranged adjacent to each other, thereby minimizing the length of the first DCG electrical interconnect 1380 connecting them.

[0175] Figure 5C This illustrates some implementations based on the disclosed technology. Figure 4 The cross-sectional view of an example structure cut by line C-C' is shown.

[0176] In the following text, the ellipsis and Figure 5A and Figure 5B Some redundant descriptions overlap.

[0177] Reference Figures 3 to 5C The third section 500C may include an electrical interconnect layer 910 and a photoelectric conversion layer 920.

[0178] The photoelectric conversion layer 920 may include an eighth photoelectric conversion element (PD8), a twelfth photoelectric conversion element (PD12), a first pixel isolation structure 311, a second DCG source region 391, a third DCG drain region 392, a fourth DCG source region 491, and a fourth DCG drain region 492.

[0179] When incident light strikes the eighth photoelectric conversion element (PD8) or the twelfth photoelectric conversion element (PD12), photocharge can be generated. The generated photocharge can accumulate in each of the photoelectric conversion elements (PD8, PD12). The first pixel isolation structure 311 can reduce crosstalk between the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12) by optically blocking them.

[0180] Each of the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12) may include a predetermined impurity. For example, each of the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12) may be a region including an impurity of a first conductivity type.

[0181] The second DCG source region 391 can contact the third DCG electrical interconnect 1391. Although Figure 5C Not shown, but the third DCG electrical interconnect 1391 can connect the first DCG drain region 382 (see Figure 1391). Figure 3 The second DCG source region 391 is electrically connected to the second DCG source region 391. The second DCG source region 391 may be disposed near the front surface 901 and may be a region including impurities of the first conductivity type. The second DCG source region 391 may be spaced apart from the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12). The second DCG source region 391 may overlap or contact the second DCG gate (GXG2).

[0182] The second DCG drain region 392 can contact the second DCG electrical interconnect 1390. For example, the second DCG drain region 392 can directly contact the second DCG electrical interconnect 1390. The second DCG drain region 392 can be disposed near the front surface 901 and can be a region including impurities of the first conductivity type. The second DCG drain region 392 can be spaced apart from the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12). The second DCG drain region 392 can overlap or contact the second DCG gate (GXG2). The second DCG drain region 392 and the second DCG source region 391 can be disposed at opposite ends of the second DCG gate (GXG2).

[0183] The fourth DCG source region 491 may contact the fourth DCG electrical interconnect 1491. The fourth DCG source region 491 may be disposed near the front surface 901 and may be a region including impurities of the first conductivity type. The fourth DCG source region 491 may be spaced apart from the eighth photoelectric conversion element (PD8) and the twelfth photoelectric conversion element (PD12). The fourth DCG source region 491 may overlap with or contact the fourth DCG gate (GXG4).

[0184] The fourth DCG drain region 492 may contact the second DCG electrical interconnect 1390. For example, the fourth DCG drain region 492 may directly contact the second DCG electrical interconnect 1390. The fourth DCG drain region 492 may be disposed near the front surface 901 and may be a region including impurities of the first conductivity type. The fourth DCG drain region 492 may be spaced apart from the eighth photoconverter (PD8) and the twelfth photoconverter (PD12). The fourth DCG drain region 492 may overlap with or contact the fourth DCG gate (GXG4). The fourth DCG drain region 492 and the fourth DCG source region 491 may be disposed at both ends of the fourth DCG gate (GXG4).

[0185] The electrical interconnect layer 910 may include a second DCG gate (GXG2), a fourth DCG gate (GXG4), a second DCG electrical interconnect 1390, a second DCG contact-interconnect 2020, a fourth DCG contact-interconnect 2040, a third DCG electrical interconnect 1391, and a fourth DCG electrical interconnect 1491.

[0186] The second DCG gate (GXG2) can be disposed on the front surface 901. The second DCG gate (GXG2) can overlap with the eighth photoelectric conversion element (PD8). The second DCG gate (GXG2) can contact the second DCG contact-interconnect 2020.

[0187] The fourth DCG gate (GXG4) can be disposed on the front surface 901. The fourth DCG gate (GXG4) can overlap with the twelfth photoelectric conversion element (PD12). The fourth DCG gate (GXG4) can contact the fourth DCG contact-interconnect 2040.

[0188] The second DCG electrical interconnect 1390 can electrically connect the second DCG drain region 392 to the fourth DCG drain region 492. The second DCG electrical interconnect 1390 may include a conductive material (e.g., a metallic material).

[0189] The second DCG contact-interconnect 2020 can send an operating voltage to the second DCG gate (GXG2). The second DCG contact-interconnect 2020 may include a conductive material (e.g., a metallic material).

[0190] The fourth DCG contact-interconnect 2040 can send the operating voltage to the fourth DCG gate (GXG4). The fourth DCG contact-interconnect 2040 may include a conductive material (e.g., a metallic material).

[0191] The third DCG electrical interconnect 1391 can contact the second DCG source region 391. Although Figure 5C Although not shown, the third DCG electrical interconnect 1391 can electrically connect the first DCG drain region 382 to the second DCG source region 391. The third DCG electrical interconnect 1391 may include a conductive material (e.g., a metallic material).

[0192] The fourth DCG electrical interconnect 1491 can contact the fourth DCG source region 491. Although Figure 5C Not shown, but the fourth DCG electrical interconnect 1491 can connect the third DCG drain region 482 (see Figure 1491). Figure 5B It is electrically connected to the fourth DCG source region 491. The fourth DCG electrical interconnect 1491 may include a conductive material (e.g., a metallic material).

[0193] Figure 6 These are examples of some implementation methods based on the disclosed technology. Figure 2 A plan view of another example of the second pixel region 220 shown.

[0194] In the following text, the ellipsis and Figure 4 Some redundant descriptions overlap.

[0195] Reference Figure 2 , Figure 3 , Figure 4 and Figure 6 , Figure 6 The implementation method can be modeled as similar to Figure 3 The circuit diagram is the same as the circuit diagram. Figure 6 The function and materials of the constituent components, including the types of impurities in such materials, etc. Figure 4 The basic components are the same, but the placement of the corresponding components is different.

[0196] The second pixel region 220 may include a pixel isolation structure 610, a third pixel group (GPA), and a fourth pixel group (GPB).

[0197] The pixel isolation structure 610 may include a first pixel isolation structure 611 and a second pixel isolation structure 612.

[0198] The first pixel isolation structure 611 can be with Figure 4 The first pixel isolation structure 311 is basically the same. The first pixel isolation structure 611 can be arranged along the boundary between the first pixel, the third pixel, the fifth pixel and the seventh pixel (PX1, PX3, PX5, PX7) to surround each pixel.

[0199] The second pixel isolation structure 612 may extend from the first pixel isolation structure 611 toward the interior of each pixel on the four side surfaces of each of the pixels (e.g., PX1, PX3, PX5, PX7). The extended second pixel isolation structures 612 may be spaced apart from each other.

[0200] The third pixel group (GPA) may include a first pixel (PX1) and a third pixel (PX3). The first pixel (PX1) and the third pixel (PX3) may be in contact with each other. Although for ease of description... Figure 6 Only the first pixel (PX1) is shown in contact with the third pixel (PX3) in the vertical direction, but the disclosed technology is not limited to this, and it should be noted that other configurations in which the first pixel (PX1) contacts the third pixel (PX3) in the horizontal direction are also possible.

[0201] Referring to the components included in each of the first pixel (PX1) and the third pixel (PX3), the first pixel (PX1) may include a first photoelectric conversion element to a fourth photoelectric conversion element (PD1-PD4), a ground region 620, a first floating diffusion region 630, and a first transmission gate to a fourth transmission gate (TXG1-TXG4). The third pixel (PX3) may include a fifth photoelectric conversion element to an eighth photoelectric conversion element (PD5-PD8), a first floating diffusion region 630, and a fifth transmission gate to an eighth transmission gate (TXG5-TXG8).

[0202] The first to fourth photoelectric conversion elements (PD1-PD4) can be arranged spaced apart from each other. The second pixel isolation structure 612 can be arranged between the first photoelectric conversion element (PD1) and the second photoelectric conversion element (PD2). The second pixel isolation structure 612 can be arranged between the first photoelectric conversion element (PD1) and the third photoelectric conversion element (PD3). The second pixel isolation structure 612 can be arranged between the second photoelectric conversion element (PD2) and the fourth photoelectric conversion element (PD4). The second pixel isolation structure 612 can be arranged between the third photoelectric conversion element (PD3) and the fourth photoelectric conversion element (PD4).

[0203] The fifth to eighth photoelectric conversion elements (PD5-PD8) can also be arranged spaced apart from each other. The second pixel isolation structure 612 can be arranged between adjacent photoelectric conversion elements.

[0204] Grounding area 620 can be with Figure 4 The grounding area 320 is basically the same. The grounding area 620 can be located at the center of the pixel.

[0205] The first floating diffusion region 630 can be arranged adjacent to the gates (TXG1-TXG8) of each of the first to eighth transmission transistors. For example, the first floating diffusion region 630 can be divided into multiple portions and arranged spaced apart from each other. The first floating diffusion region 630 can be arranged in a one-to-one correspondence with the gates (TXG1-TXG8) of the transmission transistors. When the first floating diffusion regions 630 are spaced apart from each other, the first floating diffusion regions 630 can be electrically connected to each other via a first central electrical interconnect (not shown).

[0206] The transmission gates (TXG1-TXG8) can be arranged to overlap with the photoelectric conversion elements (PD1-PD8). For example, the first transmission gate (TXG1) can be arranged to overlap with the first photoelectric conversion element (PD1). The fifth transmission gate (TXG5) can be arranged to overlap with the fifth photoelectric conversion element (PD5). When an operating voltage is applied to each of the transmission gates (TXG1-TXG8), the photocharge accumulated in the photoelectric conversion elements (PD1-PD8) that overlap with the transmission gate configured to receive the operating voltage can move to the first floating diffusion region 630. For example, when an operating voltage is applied to the first transmission gate (TXG1), the photocharge accumulated in the first photoelectric conversion element (PD1) configured to overlap with the first transmission gate (TXG1) can move to the first floating diffusion region 630.

[0207] The functions of the first reset gate (RXG1), the first select gate, the second select gate (SXG1, SXG2), the first drive gate to the third drive gate (DXG1-DXG3), the reset drain region 641, the reset source region 642, the drive drain region 651, the drive source region 652, the select drain region 671, and the select source region 672 can be related to... Figure 4 They have the same function.

[0208] The first select gate (SXG1) may overlap with the first photoelectric conversion element (PD1). The second select gate (SXG2) may overlap with the second photoelectric conversion element (PD2). The select drain region 671 and the select source region 672 may be arranged adjacent to the first select gate (SXG1) and the second select gate (SXG2). The first drive gate (DXG1) may overlap with the third photoelectric conversion element (PD3). The second drive gate (DXG2) may overlap with the fourth photoelectric conversion element (PD4). The third drive gate (DXG3) may overlap with the fifth photoelectric conversion element (PD5). The drive drain region 651 and the drive source region 652 may be arranged adjacent to each of the first to third drive gates (DXG3). The first reset gate (RXG1) may overlap with the sixth photoelectric conversion element (PD6). The reset drain region 641 and the reset source region 642 may be arranged adjacent to the first reset gate (RXG1).

[0209] The first DCG gate and the second DCG gate (GXG1, GXG2), the first DCG source region 681, the first DCG drain region 682, the second DCG source region 791, and the second DCG drain region 692 will be described together with the third DCG gate and the fourth DCG gate (GXG3, GXG4), the third DCG source region 781, the third DCG drain region 782, the fourth DCG source region 791, and the fourth DCG drain region 792.

[0210] The fourth pixel group (GPB) can include a fifth pixel (PX5) and a seventh pixel (PX7). The fifth pixel (PX5) and the seventh pixel (PX7) can be in contact with each other. Although... Figure 6 The illustration shows the seventh pixel (PX7) in vertical contact with the fifth pixel (PX5), but the scope or spirit of the disclosed technology is not limited thereto, and other embodiments in which the seventh pixel (PX7) in horizontal contact with the fifth pixel (PX5) are also possible.

[0211] In some implementations, components included in the third pixel group (GPA) can be vertically symmetrical with components included in the fourth pixel group (GPB) based on the boundary between the third pixel group (GPA) and the fourth pixel group (GPB). For example, a fifth pixel (PX5) can be arranged symmetrically with a third pixel (PX3) based on the above boundary. A first pixel (PX1) can be arranged symmetrically with a seventh pixel (PX7) based on the above boundary. To reduce the length of the first DCG electrical interconnect and the second DCG electrical interconnect, the aforementioned symmetry can include a first DCG transistor (GX1) (or second DCG transistor GX2) and a third DCG transistor (GX3) (or fourth DCG transistor GX4) belonging to different pixel groups being configured to face each other relative to the above boundary interposed therebetween.

[0212] Based on the aforementioned symmetrical arrangement, corresponding components such as the first selection gate SXG1 overlapping with the first pixel PX1 and the third selection gate SXG3 overlapping with the seventh pixel PX7 can have substantially the same function and structure. In the following, as representative examples, the first DCG gate and the second DCG gates (GXG1, GXG2), the first DCG source region and drain region (681, 682), the second DCG source region and drain region (691, 692) of the third pixel (PX3), and the third DCG gate and the fourth DCG gate (GXG3, GXG4), the third DCG source region and drain region (781, 782), and the fourth DCG source region and drain region (791, 792) of the fifth pixel (PX5) will be described in detail.

[0213] The first DCG gate (GXG1) may overlap with the seventh photoelectric conversion element (PD7). The first DCG source region 681 and the first DCG drain region 682 may be arranged at opposite ends of the first DCG gate (GXG1). The first DCG source region 681 may be electrically connected to the first floating diffusion region 630 via a first central electrical interconnect. The first DCG gate (GXG1) may be arranged closer to the fifth pixel (PX5) or boundary relative to the center of the third pixel (PX3). Furthermore, the first DCG gate (GXG1) may be arranged closer to the ninth photoelectric conversion element (PD9) from the center of the seventh photoelectric conversion element (PD7).

[0214] The second DCG gate (GXG2) may overlap with the eighth photoelectric conversion element (PD8). The second DCG source region 691 and the second DCG drain region 692 may be arranged at opposite ends of the second DCG gate (GXG2). The second DCG source region 691 may be electrically connected to the first DCG drain region 682 via a third DCG electrical interconnect. The second DCG gate (GXG2) may be arranged closer to the fifth pixel (PX5) or boundary relative to the center of the third pixel (PX3). Furthermore, the second DCG gate (GXG2) may be arranged closer to the tenth photoelectric conversion element (PD10) from the center of the eighth photoelectric conversion element (PD8).

[0215] The third DCG gate (GXG3) may overlap with the ninth photoelectric conversion element (PD9). The third DCG source region 781 and the third DCG drain region 782 may be arranged at opposite ends of the third DCG gate (GXG3). The third DCG source region 781 may be electrically connected to the second floating diffusion region 730 via a second central electrical interconnect. The third DCG drain region 782 may be electrically connected to the first DCG drain region 682 via a first DCG electrical interconnect. The third DCG gate (GXG3) may be arranged at a position corresponding to the vertical symmetry with the first DCG gate (GXG1) based on the boundary between the third pixel group (GPA) and the fourth pixel group (GPB). The third DCG gate (GXG3) may be arranged closer to the third pixel (PX3) or boundary relative to the center of the fifth pixel (PX5). Furthermore, the third DCG gate (GXG3) may be arranged closer to the seventh photoelectric conversion element (PD7) from the center of the ninth photoelectric conversion element (PD9).

[0216] The fourth DCG gate (GXG4) may overlap with the tenth photoelectric conversion element (PD10). The fourth DCG source region 791 and the fourth DCG drain region 792 may be arranged at both ends of the fourth DCG gate (GXG4). The fourth DCG source region 791 may be electrically connected to the third DCG drain region 782 via a fourth DCG electrical interconnect. The fourth DCG drain region 792 may be electrically connected to the second DCG drain region 692 via a second DCG electrical interconnect. The fourth DCG gate (GXG4) may be arranged at a position corresponding to the vertical symmetry with the second DCG gate (GXG2) based on the boundary between the third pixel group (GPA) and the fourth pixel group (GPB). The fourth DCG gate (GXG4) may be arranged closer to the third pixel (PX3) or boundary relative to the center of the fifth pixel (PX5). Furthermore, the fourth DCG gate (GXG4) may be arranged closer to the eighth photoelectric conversion element (PD8) from the center of the tenth photoelectric conversion element (PD10).

[0217] Figures 3 to 5C The characteristics of the various electrical interconnects described in the text can also be applied to... Figure 6 Examples.

[0218] According to another embodiment of the disclosed technology, the pixel array 200 can be arranged repeatedly with four pixels as a unit pixel region in the same manner as in the second pixel region 220.

[0219] As is evident from the above description, image sensing devices based on some embodiments of the disclosed technology can achieve higher conversion gain by reducing junction capacitance, while simultaneously achieving a more precisely controlled conversion gain ratio.

[0220] The implementation of the disclosed technology can provide various effects that can be directly or indirectly understood through the aforementioned patent documents.

[0221] Although several exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be designed based on the description and / or illustrations in this patent document.

[0222] Cross-references to related applications

[0223] This patent document claims priority and benefit to Korean Patent Application No. 10-2024-0153645, filed on November 1, 2024, the disclosure of which is incorporated herein by reference in its entirety as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: A pixel array of pixels for sensing incident light to capture an image carried by the incident light, wherein the pixel array includes a first pixel group and a second pixel group of pixels, the second pixel group being arranged to one side of and adjacent to the first pixel group. The first pixel group includes a first pixel, and the first pixel includes a first dual-conversion-gain DCG transistor and a second DCG transistor that adjust the capacitance of a first floating diffusion region shared by a plurality of pixels included in the first pixel group. The second pixel group includes a second pixel, and the second pixel includes a third DCG transistor and a fourth DCG transistor for adjusting the capacitance of a second floating diffusion region shared by a plurality of pixels included in the second pixel group. in, The gates of the first DCG transistor and the second DCG transistor are arranged such that the distance between the gates of the first DCG transistor and the second DCG transistor and the second pixel is shorter than the distance between the center of the second pixel and the center of the first pixel, and the gates of the third DCG transistor and the fourth DCG transistor are arranged such that the distance between the gates of the third DCG transistor and the fourth DCG transistor and the first pixel is shorter than the distance between the center of the first pixel and the center of the second pixel.

2. The image sensing device according to claim 1, further comprising: A first dual-conversion-gain DCG electrical interconnect connects the terminals of the first DCG transistor to the terminals of the third DCG transistor. as well as The second DCG electrical interconnect connects the terminals of the second DCG transistor to the terminals of the fourth DCG transistor.

3. The image sensing device according to claim 2, wherein, The first pixel includes: A first photoelectric conversion element and a second photoelectric conversion element, wherein the first photoelectric conversion element and the second photoelectric conversion element generate photocharge in response to incident light, and The second pixel includes: The third and fourth photoelectric conversion elements generate photocharges in response to the incident light.

4. The image sensing device according to claim 3, further comprising: A pixel isolation structure is disposed between the first photoelectric conversion element and the second photoelectric conversion element, and between the third photoelectric conversion element and the fourth photoelectric conversion element.

5. The image sensing device according to claim 3, wherein, The gate of the first DCG transistor overlaps with the first photoelectric conversion element. The gate of the second DCG transistor overlaps with the second photoelectric conversion element. The gate of the third DCG transistor overlaps with the third photoelectric conversion element, and The gate of the fourth DCG transistor overlaps with the fourth photoelectric conversion element.

6. The image sensing device according to claim 3, wherein, The first pixel also includes: A first transfer transistor, which moves photocharge generated by the first photoconversion element to the first floating diffusion region; and The second transmission transistor moves the photocharge generated by the second photoelectric conversion element to the first floating diffusion region, and The second pixel also includes: A third transfer transistor, which moves the photocharge generated by the third photoconversion element to the second floating diffusion region; and The fourth transmission transistor moves the photocharge generated by the fourth photoelectric conversion element to the second floating diffusion region.

7. The image sensing device according to claim 1, wherein, The first pixel group also includes: The first driving transistor amplifies the electrical signal corresponding to the photocharge stored in the first floating diffusion region, and The second pixel group also includes: The second driving transistor amplifies the electrical signal corresponding to the photocharge stored in the second floating diffusion region.

8. The image sensing device according to claim 7, wherein, The first pixel group also includes: The first selection transistor selectively outputs the electrical signal amplified by the first driving transistor, and The second pixel group also includes: The second selection transistor selectively outputs the electrical signal amplified by the second driving transistor.

9. The image sensing device according to claim 1, wherein, The first pixel group includes: The first reset transistor resets the first floating diffusion region, and The second pixel group includes: The second reset transistor resets the second floating diffusion region.

10. The image sensing device according to claim 1, further comprising: A third dual-conversion-gain DCG electrical interconnect connects the terminals of the first DCG transistor to the terminals of the second DCG transistor. as well as A fourth DCG electrical interconnect connects the terminals of the third DCG transistor to the terminals of the fourth DCG transistor.

11. The image sensing device according to claim 1, wherein, The first floating diffusion region is electrically connected to the terminals of the first DCG transistor, and The second floating diffusion region is electrically connected to the terminal of the third DCG transistor.

12. An image sensing device, the image sensing device comprising: The first pixel includes a first photoelectric conversion element and a second photoelectric conversion element that generate photocharge in response to incident light; The second pixel includes a third photoelectric conversion element and a fourth photoelectric conversion element that generate photocharge in response to the incident light, and the second pixel is in contact with the side surface of the first pixel; The third pixel includes a fifth photoelectric conversion element and a sixth photoelectric conversion element that generate photocharge in response to the incident light, and the side surface of the third pixel is in contact with the opposite side surface of the first pixel; as well as A fourth pixel, comprising a seventh photoelectric conversion element and an eighth photoelectric conversion element that generate photocharge in response to the incident light, wherein the fourth pixel is in contact with the opposite side surface of the third pixel. in, The first pixel includes: A first dual-conversion-gain DCG transistor and a second DCG transistor, the first DCG transistor and the second DCG transistor adjusting the conversion gain of the first pixel and the second pixel and arranged such that the distance between the first DCG transistor and the second DCG transistor and the side surface of the third pixel is shorter than the distance between the first DCG transistor and the second DCG transistor and the side surface of the first pixel, and The third pixel includes: A third DCG transistor and a fourth DCG transistor adjust the conversion gain of the third pixel and the fourth pixel and are arranged such that the distance between the third DCG transistor and the fourth DCG transistor and the opposite side surface of the first pixel is shorter than the distance between the third DCG transistor and the fourth DCG transistor and the opposite side surface of the third pixel.

13. The image sensing device according to claim 12, wherein, One terminal of the first DCG transistor and one terminal of the third DCG transistor are electrically connected to each other, and One terminal of the second DCG transistor and one terminal of the fourth DCG transistor are electrically connected to each other.

14. The image sensing device according to claim 13, wherein, The first pixel includes: A first floating diffusion region stores photocharge generated by the first photoelectric conversion element and the second photoelectric conversion element, and The third pixel includes: The second floating diffusion region stores the photocharge generated by the fifth photoelectric conversion element and the sixth photoelectric conversion element.

15. The image sensing device according to claim 14, wherein, The other terminal of the first DCG transistor is electrically connected to the first floating diffusion region, and The other terminal of the third DCG transistor is electrically connected to the second floating diffusion region.

16. The image sensing device according to claim 14, wherein, One terminal of the first DCG transistor is electrically connected to the other terminal of the second DCG transistor, and One terminal of the third DCG transistor is electrically connected to the other terminal of the fourth DCG transistor.

17. The image sensing device according to claim 12, wherein, When all four DCG transistors (first to fourth) are turned off, the first pixel and the second pixel have a high conversion gain that is higher than the intermediate conversion gain. When the first DCG transistor is turned on and the second through fourth DCG transistors are turned off, the first pixel and the second pixel have a medium conversion gain that is higher than the low conversion gain and lower than the high conversion gain. When all four DCG transistors (first to fourth) are turned on, the first pixel and the second pixel have a low conversion gain that is lower than the high conversion gain and the medium conversion gain.

18. The image sensing device according to claim 17, wherein, The intermediate conversion gain is twice the low conversion gain.

19. The image sensing device according to claim 17, wherein, The high conversion gain is eight times that of the low conversion gain.

20. The image sensing device according to claim 17, wherein, When all four DCG transistors (from the first to the fourth) are turned off, the third and fourth pixels have a high conversion gain that is higher than the intermediate conversion gain. When the third DCG transistor is turned on and the first DCG transistor, the second DCG transistor, and the fourth DCG transistor are turned off, the third pixel and the fourth pixel have a medium conversion gain that is higher than the low conversion gain and lower than the high conversion gain. When all four DCG transistors (first to fourth) are turned on, the third pixel and the fourth pixel have a low conversion gain that is lower than the high conversion gain and the medium conversion gain.

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