Semiconductor device

Abstract

A semiconductor device includes: a substrate; a bit line on the substrate and extending in a first direction; a word line extending in a second direction; a first active pattern and a second active pattern between the word lines and spaced apart in a first direction; a unit capacitor on the first active pattern and the second active pattern; and a shield gate located at a horizontal height between the word line and the cell capacitor. Each of the first and second active patterns includes a first dopant region connected to the bit line, a second dopant region connected to the cell capacitor, and a channel region between the first and second dopant regions. The shield gate overlaps the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0156558, filed on November 6, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device. Background Technology

[0003] There is a need for technologies to improve the integration level of semiconductor devices. In the case of two-dimensional semiconductor devices, the integration level is mainly determined by the area occupied by a unit memory cell, and in this respect, the integration level can depend on the level of micropatterning technology.

[0004] Incidentally, micropatterning technology requires expensive equipment. Therefore, although the integration density of two-dimensional semiconductor devices is increasing, it remains limited. Consequently, three-dimensional memory devices with three-dimensionally arranged memory cells have been proposed.

[0005] As the components included in semiconductor memory devices become more integrated and miniaturized, it is important to minimize the interaction between the components included in the semiconductor device in order to improve the operating performance of the semiconductor device. Summary of the Invention

[0006] This disclosure attempts to provide a semiconductor device with improved reliability and productivity.

[0007] A semiconductor device according to an embodiment includes: a substrate; bit lines located on the substrate and extending along a first direction; a plurality of word lines extending along a second direction intersecting the first direction; a first active pattern and a second active pattern located between the plurality of word lines and spaced apart along the first direction; a cell capacitor located on the first active pattern and the second active pattern; and a plurality of shielding gates located at a horizontal height between the plurality of word lines and the cell capacitor, each of the first active pattern and the second active pattern including a first doped region connected to the bit line, a second doped region connected to the cell capacitor, and a channel region located between the first doped region and the second doped region, the plurality of shielding gates overlapping along the first direction with a second doped region of at least one of the first active pattern and the second active pattern.

[0008] A semiconductor device according to an embodiment includes: a substrate including a cell array region and a peripheral circuit region; a bit line located on the cell array region and extending along a first direction; a plurality of word lines extending along a second direction intersecting the first direction; a first active pattern and a second active pattern located on the plurality of word lines and spaced apart in the first direction; a back gate electrode located between the first active pattern and the second active pattern and extending along the second direction; a cell capacitor located on the first active pattern and the second active pattern; and a plurality of shielding gates overlapping at least one of the plurality of word lines and the back gate electrode in a vertical direction intersecting the first direction and the second direction, each of the first active pattern and the second active pattern including a first doped region connected to the bit line, a second doped region connected to the cell capacitor, and a channel region located between the first doped region and the second doped region, and the plurality of shielding gates overlapping a second doped region of at least one of the first active pattern and the second active pattern in the first direction.

[0009] The semiconductor device according to an embodiment includes: a substrate including a cell array region and a peripheral circuit region; a peripheral circuit structure including peripheral circuits located on the substrate and peripheral circuit wiring connected to the peripheral circuits; and a cell structure overlapping the peripheral circuit structure in a vertical direction, wherein the cell structure includes bit lines located on the substrate and extending in a first direction intersecting the vertical direction, a plurality of word lines extending in a second direction intersecting the first direction and the vertical direction, a plurality of active patterns located between the plurality of word lines and spaced apart in the first direction, a back gate electrode located between the plurality of active patterns and extending in the second direction, a cell capacitor located on the plurality of active patterns, a first shielding gate overlapping the back gate electrode in a vertical direction, and a second shielding gate overlapping the plurality of word lines in a vertical direction, wherein each of the plurality of active patterns includes: a first dopant region connected to the bit lines, a second dopant region connected to the cell capacitor, and a channel region located between the first dopant region and the second dopant region, and each of the first shielding gate and the second shielding gate overlaps the second dopant region in the first direction.

[0010] According to an embodiment, since the shielding gate is formed such that it is positioned to overlap with the doped region of the active pattern connected to the capacitor, the gate-induced drain leakage (GIDL) of the memory transistor can be reduced, and the current value of the memory transistor in the on state can be increased. Attached Figure Description

[0011] Figure 1 This is a plan view of a semiconductor device according to an embodiment.

[0012] Figure 2 This is a plan view showing some components of a semiconductor device according to an embodiment.

[0013] Figure 3 It shows Figure 2 A plan view of some of the components.

[0014] Figure 4 It shows along Figure 1 The cross-sectional view taken from lines A-A' and B-B'.

[0015] Figure 5 It shows along Figure 1 The cross-sectional view taken from line C-C'.

[0016] Figure 6 It shows along Figure 1 The cross-sectional view taken from lines D-D' and E-E'.

[0017] Figure 7 yes Figure 5 A magnified view of a portion of region P1.

[0018] Figures 8 to 17 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0019] Figure 18 and Figure 19 This is a plan view illustrating some components of a semiconductor device according to some embodiments.

[0020] Figure 20 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0021] Figure 21 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0022] Figure 22 yes Figure 21 A magnified view of region R1.

[0023] Figure 23 and Figure 24 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0024] Figures 25 to 33 This is a cross-sectional view used to explain the method of manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0025] In the following detailed description, certain embodiments are shown and described by way of example only. The invention can be implemented in various ways and is not limited to the following embodiments.

[0026] The accompanying drawings and description should be considered illustrative rather than restrictive. Throughout the description, the same reference numerals denote the same elements.

[0027] Furthermore, for the sake of understanding and ease of description, the dimensions and thicknesses of each structure shown in the accompanying drawings are arbitrarily illustrated, but the invention is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. Additionally, in the drawings, the thicknesses of some layers and regions are exaggerated for the sake of understanding and ease of description.

[0028] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on another element,” there are no intermediate elements present. Additionally, when an element is on a reference portion, the element is located above or below the reference portion, and this does not necessarily mean that the element is located “above” or “on” the reference portion in a direction opposite to gravity.

[0029] Furthermore, throughout the specification, unless explicitly stated otherwise, the word "comprising" shall be understood to imply the inclusion of the stated element but not the exclusion of any other element.

[0030] Additionally, throughout the instruction manual, when referred to as a "plane," it means the view of the object from above, and when referred to as a "section," it means the view of the cross-section obtained by vertically cutting the object from the side.

[0031] The following will refer to Figures 1 to 7 A semiconductor device according to an embodiment is described.

[0032] Figure 1 This is a plan view of a semiconductor device according to an embodiment. Figure 2 This is a plan view showing some components of a semiconductor device according to an embodiment. Figure 3 It is shown Figure 2 A plan view of some of the components. Figure 4 It shows along Figure 1 The cross-sectional view taken from lines A-A' and B-B'. Figure 5 It shows along Figure 1 The cross-sectional view taken from line C-C'. Figure 6 It shows along Figure 1 The cross-sectional view taken from lines D-D' and E-E'. Figure 7 yes Figure 5 A magnified view of a portion of region P1.

[0033] exist Figure 2 and Figure 3 In this diagram, other components are not shown in order to illustrate the arrangement of some of the components included in the semiconductor device.

[0034] The semiconductor device according to the embodiments may include a plurality of memory cells, the plurality of memory cells including vertical channel transistors (VCTs). However, this is an example, and the semiconductor device according to the embodiments is not limited thereto, and various changes may be made.

[0035] Reference Figures 1 to 7 According to some embodiments, a semiconductor device may include a substrate 100 and a peripheral circuit structure PS and a cell structure CS located on the substrate 100.

[0036] The substrate 100 may include a cell array region CAR and a peripheral circuit region PAR defined around the cell array region CAR. For example, the peripheral circuit region PAR may be adjacent to and surround the cell array region CAR. However, the arrangement relationship between the cell array region CAR and the peripheral circuit region PAR is not limited to this and can be varied.

[0037] In the cell array area CAR, multiple memory cells including memory transistors MT and cell capacitors DSP, word lines WL and bit lines BL connected to them can be set up, and in the peripheral circuit area PAR, multiple contacts 241 and 243 and contact wiring lines CL connected to the components located in the cell array area CAR can be set up.

[0038] A memory cell may include a memory transistor MT and a cell capacitor DSP. Two distinguishable states can be determined based on whether any charge is stored in the cell capacitor DSP, and the cell capacitor DSP can function as a memory element.

[0039] The gate electrode of the memory transistor MT can be connected to the word line WL, the first source / drain of the memory transistor MT can be connected to a terminal of the cell capacitor DSP, and the second source / drain of the memory transistor MT can be connected to the bit line BL. This will be described in detail below.

[0040] The substrate 100 may be a silicon substrate, or may contain silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but is not limited thereto, and various changes may be made to the materials contained in the substrate 100.

[0041] In this embodiment, the peripheral circuit structure PS and the unit structure CS located on the substrate 100 can be positioned to overlap in the vertical direction. For example, the peripheral circuit structure PS and the unit structure CS can be stacked sequentially on the substrate 100. In other words, the unit structure CS can be located on the peripheral circuit structure PS. However, this disclosure is not limited to this, and various changes can be made to the stacking relationship between the unit structure CS and the peripheral circuit structure PS. For example, the unit structure CS can be adjacent to and side by side with the peripheral circuit structure PS in the horizontal direction. As another example, the unit structure CS can be located below the peripheral circuit structure PS to overlap with the peripheral circuit structure in the vertical direction.

[0042] The configuration and structure of the semiconductor device according to the embodiments will be described in detail below.

[0043] An embodiment will be described under the assumption that the unit structure CS is located on the peripheral circuit structure PS.

[0044] The peripheral circuit structure PS can be located on the substrate 100. The peripheral circuit structure PS can be located between the substrate 100 and the unit structure CS.

[0045] The peripheral circuit structure PS can be distributed across the cell array region CAR and the peripheral circuit region PAR of the substrate 100. In other words, a portion of the peripheral circuit structure PS can be located on the cell array region CAR of the substrate 100, and another portion can be located on the peripheral circuit region PAR.

[0046] Although not shown in the diagram, the peripheral circuit structure PS can include a core area and a peripheral area. The core area and the peripheral area can be collectively referred to as the logic area or the peripheral circuit area.

[0047] The core area may include core memory, and the core memory may include core circuitry such as word line drivers, sense amplifiers, row decoders, column decoders, and read / write circuitry (R / W circuitry).

[0048] The peripheral area may include peripheral circuits such as timing registers, address registers, data input registers, data output registers, and data input / output terminals.

[0049] The peripheral circuit structure PS may include peripheral circuitry PC for driving components located in the unit structure CS. For example, the peripheral circuitry PC may include the core circuitry and / or peripheral circuitry mentioned above.

[0050] The peripheral circuit structure PS may include peripheral circuit PC, peripheral circuit contacts PCT1, PCT2 and PCT3, peripheral circuit wiring lines PCL1 and PCL2, peripheral circuit insulation layer 212, first bonding insulation layer 214 and multiple first bonding pads 221.

[0051] The peripheral circuit PC may be located on the substrate 100. The peripheral circuit PC may include, for example, sensing transistors, transmission transistors, driving transistors, etc. However, the type of transistors in the peripheral circuit PC may vary depending on the design of the semiconductor device.

[0052] The peripheral circuit insulating layer 212 may cover the peripheral circuit PC. In other words, the peripheral circuit insulating layer 212 may cover the side surface and top surface of the peripheral circuit PC. The peripheral circuit insulating layer 212 may contain an insulating material. For example, the peripheral circuit insulating layer 212 may contain silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. However, this disclosure is not limited thereto.

[0053] The peripheral circuit contacts PCT1, PCT2 and PCT3, as well as the peripheral circuit wiring lines PCL1 and PCL2, may be located within the peripheral circuit insulation layer 212.

[0054] The first peripheral circuit wiring line PCL1 can be connected to the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring line PCL1 can be connected to at least the source / drain region of the peripheral circuit PC located on one side via the first peripheral circuit contact PCT1. The first peripheral circuit wiring line PCL1 and the second peripheral circuit wiring line PCL2 can be connected via the second peripheral circuit contact PCT2.

[0055] Although the peripheral circuit insulation layer 212 is shown as a single layer in the embodiments in the accompanying drawings, this disclosure is not limited thereto, and the peripheral circuit insulation layer 212 may include multiple layers comprising the same and / or different materials.

[0056] When the peripheral circuit insulation layer 212 comprises multiple layers, at least some of the first peripheral circuit contact PCT1, the second peripheral circuit contact PCT2, the third peripheral circuit contact PCT3, the first peripheral circuit wiring PCL1, the second peripheral circuit wiring PCL2, and the third peripheral circuit wiring PCL3 may be located in substantially the same layer or different layers.

[0057] The first bonding insulating layer 214 may be located on the peripheral circuit insulating layer 212. The first bonding insulating layer 214 may contain an insulating material. For example, the first bonding insulating layer 214 may contain silicon carbonitride, but is not limited thereto. As another example, the first bonding insulating layer 214 may contain at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and silicon nitride.

[0058] The third peripheral circuit contact PCT3 can be located within the peripheral circuit insulating layer 212 and the first bonding insulating layer 214. In other words, a portion of the third peripheral circuit contact PCT3 can be located within the peripheral circuit insulating layer 212, and another portion can be located within the first bonding insulating layer 214.

[0059] Multiple first bonding pads 221 may be located within a first bonding insulating layer 214. The first bonding insulating layer 214 may surround the multiple first bonding pads 221. The first bonding insulating layer 214 may surround the side and bottom surfaces of the first bonding pads 221. The upper surface of the first bonding insulating layer 214 may be located at substantially the same horizontal height as the upper surfaces of the multiple first bonding pads 221, and the first bonding insulating layer 214 may expose the upper surfaces of the multiple first bonding pads 221. The first bonding pads 221 may be connected to a second peripheral circuit wiring line PCL2 via a third peripheral circuit contact PCT3.

[0060] In this embodiment, the peripheral circuit structure PS and the unit structure CS can be semiconductor devices joined by Cu-to-Cu (C2C) wafer bonding. For example, the peripheral circuit structure PS and the unit structure CS can be semiconductor devices joined by a hybrid copper bonding (HCB) method. However, the bonding method of the peripheral circuit structure PS and the unit structure CS is not limited to this and can be modified in various ways.

[0061] Specifically, the peripheral circuit structure PS may include two surfaces that are opposite each other. One of these two surfaces of the peripheral circuit structure PS may be the surface facing the unit structure CS, while the other surface of the peripheral circuit structure PS may be the surface facing the substrate 100.

[0062] Here, one surface of the peripheral circuit structure PS can refer to the front of the peripheral circuit structure PS, while the other surface of the peripheral circuit structure PS can refer to the back of the peripheral circuit structure PS.

[0063] Furthermore, the cell structure CS may include one surface and another surface that are opposite to each other. One surface of the cell structure CS may be the surface facing the peripheral circuit structure PS, while the other surface may be the surface opposite to that surface. Here, one surface of the cell structure CS may refer to the back surface of the cell structure CS, and the other surface of the cell structure CS may refer to the front surface of the cell structure CS.

[0064] In this embodiment, one surface of the peripheral circuit structure PS adjacent to the unit structure CS can be a bonding surface with the unit structure CS. Furthermore, one surface of the unit structure CS adjacent to the peripheral circuit structure PS can be a bonding surface with the peripheral circuit structure PS. In other words, one surface of the peripheral circuit structure PS and one surface of the unit structure CS can be the bonding surfaces of the peripheral circuit structure PS and the unit structure CS. One surface of the peripheral circuit structure PS and one surface of the unit structure CS can constitute the interface between the peripheral circuit structure PS and the unit structure CS.

[0065] Specifically, the unit structure CS may include a second bonding insulating layer 216 that contacts the first bonding insulating layer 214 of the peripheral circuit structure PS. The second bonding insulating layer 216 may contain the same material as the first bonding insulating layer 214 located in the peripheral circuit structure PS, and may be located on the first bonding insulating layer 214.

[0066] Within the second bonding insulating layer 216 located in the unit structure CS, second bonding pads 222 may be disposed. The second bonding insulating layer 216 may surround a plurality of second bonding pads 222. The second bonding insulating layer 216 may surround the side surfaces and the top surface of the second bonding pads 222. The lower surface of the second bonding insulating layer 216 may be located at substantially the same horizontal height as the lower surfaces of the plurality of second bonding pads 222, and the second bonding insulating layer 216 may expose the lower surfaces of the plurality of second bonding pads 222.

[0067] The plurality of second bonding pads 222 located within the second bonding insulating layer 216 can form a metallic bond while in direct contact with the plurality of first bonding pads 221 located within the first bonding insulating layer 214. The upper surfaces of the plurality of first bonding pads 221 and the lower surfaces of the plurality of second bonding pads 222 can be in contact. The plurality of first bonding pads 221 and the plurality of second bonding pads 222 can be located at the interface between the peripheral circuit structure PS and the unit structure CS, and can be in contact with each other.

[0068] Furthermore, the first bonding insulating layer 214 located in the peripheral circuit structure PS and the second bonding insulating layer 216 located in the unit structure CS can contact each other to form a junction insulating layer.

[0069] Therefore, one surface of the unit structure CS and one surface of the peripheral circuit structure PS can be bonded. In other words, a plurality of first bonding pads 221 and a first bonding insulating layer 214 located in the peripheral circuit structure PS can constitute one surface or bonding surface of the peripheral circuit structure PS, and a plurality of second bonding pads 222 and a second bonding insulating layer 216 located in the unit structure CS can constitute one surface or bonding surface of the unit structure CS.

[0070] The first bonding pad 221 of the peripheral circuit structure PS and the second bonding pad 222 of the cell structure CS can be bonded to provide an electrical connection path between the peripheral circuit structure PS and the cell structure CS. For example, cell connection wiring 232 connected to components included in the cell structure CS can be connected to the peripheral circuit PC and / or peripheral circuit wiring PCL1 and PCL2 included in the peripheral circuit structure PS via the first bonding pad 221 and the second bonding pad 222.

[0071] The cell structure CS may include cell connection wiring contacts 231 and cell connection wiring lines 232 located within the second bonding insulating layer 216. Cell connection wiring lines 232 can be connected to components located within the cell structure CS, and cell connection wiring contacts 231 can connect to the second bonding pad 222 and the cell connection wiring lines 232. For example, cell connection wiring lines 232 can be connected to multiple memory cells located within the cell structure CS, including memory transistors MT and cell capacitors DSP, word lines WL and bit lines BTL connected to the memory cells, etc.

[0072] Each of the peripheral circuit contacts PCT1, PCT2, and PCT3 in the peripheral circuit structure PS, and the peripheral circuit wiring lines PCL1 and PCL2, as well as the unit connection wiring contacts 231 and 232 in the unit structure CS, may contain a conductive material. For example, each may contain aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), tantalum (Ta), etc. However, this disclosure is not limited thereto.

[0073] In an embodiment, the cell structure CS may include multiple bit lines BL, multiple word lines WL1 and WL2 located on and extending across the multiple bit lines BL, multiple active patterns AP1 and AP2 located between the multiple word lines WL1 and WL2, a back gate electrode BG located between the multiple active patterns AP1 and AP2 and extending across the multiple bit lines BL, a buried contact BC located on the multiple active patterns AP1 and AP2, a landing pad LP located on the buried contact BC, a cell capacitor DSP located on the landing pad LP, and multiple shielding gates SG located at a horizontal height between the multiple word lines WL1 and WL2 and the cell capacitor DSP and overlapping at least a portion of the active patterns AP1 and AP2 in the horizontal direction.

[0074] The semiconductor device according to an embodiment may include a plurality of bit lines BL. The plurality of bit lines BL may extend parallel to each other in a second direction Y intersecting a first direction X parallel to the substrate 100. The plurality of bit lines BL may be located on the substrate 100 and spaced apart from each other in the first direction X.

[0075] In this embodiment, multiple bit lines BL can extend from the cell array region CAR to the peripheral circuit region PAR in the second direction Y. Therefore, the ends of the bit lines BL can be located in the peripheral circuit regions PAR located on both sides of the cell array region CAR in the second direction Y. The ends of the bit lines BL located in the peripheral circuit regions PAR can be connected to the bit line contact 245.

[0076] Bit line BL may include a polysilicon layer 161, a first metal layer 163, a second metal layer 165, and a bit line capping layer 167.

[0077] The polysilicon layer 161 may comprise polysilicon doped with impurities, and the first metal layer 163 and the second metal layer 165 may comprise conductive materials. For example, the first metal layer 163 may comprise conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and the second metal layer 165 may comprise metals (e.g., tungsten, titanium, tantalum, etc.).

[0078] Furthermore, either the first metal layer 163 or the second metal layer 165 may contain a metal silicide, such as titanium silicide, cobalt silicide, or nickel silicide. However, the materials contained in the first metal layer 163 and the second metal layer 165 are not limited to these and can be varied.

[0079] Bit line capping layer 167 may contain an insulating material, such as silicon nitride or silicon oxynitride.

[0080] In some embodiments, the bit line BL may comprise two-dimensional or three-dimensional materials, and may comprise, for example, graphene as a carbon-based two-dimensional material, carbon nanotubes as a three-dimensional material, or a combination thereof.

[0081] Multiple bit lines BL can be positioned adjacent to the peripheral circuit structure PS. Because multiple bit lines BL are positioned adjacent to the peripheral circuit structure PS, the electrical connection paths between the bit lines BL and the peripheral circuit PC can be reduced.

[0082] The semiconductor device according to the embodiment may further include a shielding pattern SP and a spacer insulating layer 175 located between the peripheral circuit structure PS and the unit structure CS.

[0083] The shielding pattern SP can be located between the peripheral circuit structure PS and the bit line BL. Furthermore, the shielding pattern SP can be located between the bit lines BL and extend in the second direction Y; in other words, the shielding pattern SP can be arranged alternately with the bit line BL in the first direction X.

[0084] The spacer insulating layer 175 may be located on the bit lines BL to conform to them. The spacer insulating layer 175 may cover the side and top surfaces of each of the multiple bit lines BL. The spacer insulating layer 175 may define a gap region between the multiple bit lines BL. The gap region of the spacer insulating layer 175 may extend in a second direction Y to be parallel to the bit lines BL.

[0085] The shielding pattern SP can contain conductive materials. For example, the shielding pattern SP can contain metallic materials such as tungsten (W), titanium (Ti), nickel (Ni), and cobalt (Co). As another example, the shielding pattern SP can include conductive two-dimensional (2D) materials such as graphene. However, the shielding pattern SP is not limited to these.

[0086] The spacer insulation layer 175 may comprise an insulating material. For example, the spacer insulation layer may comprise silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material.

[0087] The shielding pattern SP can be located on the spacer insulation layer 175. The shielding pattern SP can be located within the gap area of ​​the spacer insulation layer 175.

[0088] like Figures 4 to 6 As shown, the shielding pattern SP may include line portions located between adjacent bit lines BL and connection portions of common connecting line portions.

[0089] Specifically, the line portions of the shielding pattern SP can be located between the bit lines BL and within a plurality of gap regions defined by the spacer insulating layer 175. Therefore, the line portions of the shielding pattern SP and the side surfaces of the bit lines BL can be spaced apart with the spacer insulating layer 175 inserted therebetween.

[0090] The connecting portion of the shielding pattern SP can be connected to and integrated with the line portion. The connecting portion of the shielding pattern SP can be located on the line portion to connect the line portions located between adjacent bit lines BL. However, this disclosure is not limited thereto, and in some embodiments, the line portion and the connecting portion of the shielding pattern SP can be formed as separate components.

[0091] like Figure 1 As shown, each line portion of the shielding pattern SP can be located within the cell array region CAR and the peripheral circuit region PAR. In other words, each line portion of the shielding pattern SP can extend from the cell array region CAR to the peripheral circuit region PAR. Therefore, the end of each line portion of the shielding pattern SP can be located within the peripheral circuit region PAR on both sides of the cell array region CAR in the second direction Y.

[0092] Although not shown in the figure, the connecting portion of the shielding pattern SP can extend from the cell array region CAR to the peripheral circuit region PAR. Therefore, the end of the connecting portion of the shielding pattern SP can be located in the peripheral circuit region PAR. The connecting portion of the shielding pattern SP located in the peripheral circuit region PAR can be connected to the shielding pattern contact (not shown in the figure).

[0093] The semiconductor device according to the embodiment may further include a plurality of contact wiring lines CL located in the peripheral circuit area PAR and a contact wiring capping layer 168 covering the contact wiring lines CL.

[0094] Multiple contact wiring lines CL can be located in the peripheral circuit area PAR of the cell structure CS. Multiple contact wiring lines CL can extend in a second direction Y, the same as the extension direction of the bit line BL. Multiple contact wiring lines CL can be located in the peripheral circuit area PAR, spaced apart from each other in a first direction X.

[0095] In this embodiment, the plurality of contact wiring lines CL can be located within the peripheral circuit area PAR on at least one side of the cell array region CAR in the first direction X. For example, a portion of the plurality of contact wiring lines CL can be located within the peripheral circuit area PAR on one side of the cell array region CAR in the first direction X, and another portion can be located within the peripheral circuit area PAR on the other side of the cell array region CAR in the first direction X.

[0096] In this embodiment, each contact wiring line CL may include a first contact wiring layer 162, a second contact wiring layer 164, and a third contact wiring layer 166 stacked sequentially. The contact wiring line CL may be formed simultaneously with the bit line BL in the same process step.

[0097] Therefore, the first contact wiring layer 162 can be formed by the same process as the polysilicon layer 161 for bit line BL, and the second contact wiring layer 164 can be formed by the same process as the first metal layer 163 for bit line BL, and the third contact wiring layer 166 can be formed by the same process as the second metal layer 165.

[0098] Therefore, the first contact wiring layer 162 may contain the same material as the polysilicon layer 161 of the bit line BL, and the second contact wiring layer 164 may contain the same material as the first metal layer 163, and the third contact wiring layer 166 may contain the same material as the second metal layer 165. However, this is just an example, and the contact wiring lines CL may be formed separately from the bit line BL in a separate process step, and at least one of the number of layers and materials constituting the contact wiring lines CL may be varied.

[0099] The semiconductor device according to the embodiment may further include a shielding cover pattern 179 on a shielding pattern SP, a first unit insulating layer 177 between a spacer insulating layer 175 and a second bonding insulating layer 216, a second unit insulating layer 173 on the spacer insulating layer 175, a contact wiring cover layer 168 between a plurality of contact wiring lines CL and the spacer insulating layer 175, and a component isolation layer STI on the second unit insulating layer 173.

[0100] The shielding cover pattern 179 may be located between the shielding pattern SP and the second bonding insulating layer 216 to cover the shielding pattern SP.

[0101] The first unit insulating layer 177 may be located on the second bonding insulating layer 216. The upper surface of the first unit insulating layer 177 may contact the spacer insulating layer 175, and the side surface of the first unit insulating layer 177 may contact the end of the shielding pattern SP and the end of the shielding cover pattern 179.

[0102] The second unit insulation layer 173 may be located on the spacer insulation layer 175.

[0103] like Figure 4 As shown, the second unit insulating layer 173 can contact the side surface of the contact wiring line CL. However, this is an example, and the second unit insulating layer 173 can be positioned separately from the side surface of the contact wiring line CL.

[0104] In addition, such as Figure 5 As shown, the second unit insulating layer 173 can contact and cover the end of the bit line BL. However, this is an example, and the second unit insulating layer 173 can be positioned separately from the end of the bit line BL.

[0105] The contact wiring cover layer 168 may be located on multiple contact wiring lines CL. The contact wiring cover layer 168 may be located between the spacer insulation layer 175 and the multiple contact wiring lines CL.

[0106] The contact wiring capping layer 168 can completely cover multiple contact wiring lines CL. The contact wiring capping layer 168 can cover the lower and side surfaces of the contact wiring lines CL. The contact wiring capping layer 168 can fill the space between multiple contact wiring lines CL positioned separately from each other.

[0107] The component isolation layer STI can be located on the second unit insulating layer 173. A portion of the component isolation layer STI can overlap with the bit line BL in the third direction Z, which is the vertical direction.

[0108] The shielding cap pattern 179, the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. For example, the shielding cap pattern 179 may comprise silicon nitride, and the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI may comprise silicon oxide. However, this is just an example, and the materials contained in each of the shielding cap pattern 179, the first unit insulating layer 177, the second unit insulating layer 173, and the component isolation layer STI can be varied.

[0109] Contact wiring capping layer 168 can be formed simultaneously with bit line capping layer 167 in the same process step and contains the same material as bit line capping layer 167. However, this is an example; bit line capping layer 167 and contact wiring capping layer 168 can be formed separately in separate process steps and contain different materials.

[0110] Multiple active patterns AP1 and AP2 may include multiple first active patterns AP1 and multiple second active patterns AP2 that are separately arranged in the first direction X. The multiple first active patterns AP1 and multiple second active patterns AP2 may be alternately arranged on the bit line BL in the second direction Y.

[0111] The first active pattern AP1 and the second active pattern AP2 can be arranged in two dimensions on a plane along the first direction X and the second direction Y. In other words, the first active pattern AP1 and the second active pattern AP2 can be positioned separately from each other and facing each other in the second direction Y.

[0112] In this embodiment, each of the first active pattern AP1 and the second active pattern AP2 may include a single-crystal semiconductor material. For example, each of the first active pattern AP1 and the second active pattern AP2 may include single-crystal silicon. However, this disclosure is not limited thereto, and various changes can be made to the materials included in the first active pattern AP1 and the second active pattern AP2. For example, the first active pattern AP1 and the second active pattern AP2 may include at least one of polycrystalline semiconductors, oxide semiconductors, and two-dimensional materials. For example, the polycrystalline semiconductor may be polycrystalline silicon. As another example, the oxide semiconductor may be indium gallium zinc oxide (IGZO). As yet another example, the two-dimensional material may be MoS2, WS2, MoSe2, or WSe2.

[0113] Each of the first active pattern AP1 and the second active pattern AP2 may have a length in the first direction X, a width in the second direction Y, and a height in the third direction Z. Each of the first active pattern AP1 and the second active pattern AP2 may include a first surface and a second surface facing each other in the third direction Z.

[0114] Here, the first surface can refer to the surface adjacent to the bit line BL, and the second surface can refer to the surface adjacent to the unit capacitor DSP, which will be described below. In other words, the first surface of the active patterns AP1 and AP2 can correspond to the lower surface, and the second surface can correspond to the upper surface.

[0115] The first and second surfaces of each of the first active pattern AP1 and the second active pattern AP2 may have substantially the same width. Furthermore, the width of the first active pattern AP1 may be substantially the same as the width of the second active pattern AP2. However, this disclosure is not limited thereto; in some embodiments, the first and second surfaces of each of the first active pattern AP1 and the second active pattern AP2 may have different widths. For example, the width of the second surface of each of the first active pattern AP1 and the second active pattern AP2 may be greater than the width of the first surface.

[0116] The following will refer to Figure 7 Describe in detail the first active pattern AP1 and the second active pattern AP2.

[0117] The semiconductor device according to the embodiment may include a plurality of back gate electrodes BG extending between a first active pattern AP1 and a second active pattern AP2 in a direction different from the direction of the bit line BL.

[0118] Multiple back gate electrodes BG can be located between first active patterns AP1 and second active patterns AP2 that are adjacent to each other in the second direction Y, and extend across bit line BL in the first direction X. In other words, multiple back gate electrodes BG can extend across bit line BL in a direction different from the extension direction of the bit line.

[0119] Multiple back gate electrodes BG can be located on the bit line BL and the shielding pattern SP. A first active pattern AP1 can be set on one side of the back gate electrode BG along the second direction Y, and a second active pattern AP2 can be set on the other side of the back gate electrode BG along the second direction Y.

[0120] The thickness of the back gate electrode BG in the third direction Z can be less than the thickness of the first active pattern AP1 and the second active pattern AP2 in the third direction Z. However, this is just an example, and the relationship between the thickness of the back gate electrode BG in the third direction Z and the thicknesses of the first active pattern AP1 and the second active pattern AP2 in the third direction Z can be varied.

[0121] Furthermore, the back gate electrode BG can be located between a pair of adjacent first word lines WL1 and second word lines WL2 in the second direction Y. For example, the first active pattern AP1 can be located between the first word line WL1 (described below) and the back gate electrode BG, and the second active pattern AP2 can be located between the second word line WL2 (described below) and the back gate electrode BG. However, this is just an example, and the arrangement of the first active pattern AP1 and the second active pattern AP2, the first word lines WL1 and the second word lines WL2 (described below), and the back gate electrode BG is not limited to this and can be varied.

[0122] The back gate electrode (BG) may contain a conductive material. For example, the back gate electrode (BG) may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal. However, this is just an example, and the conductive material can be varied.

[0123] During operation of a semiconductor device, the back gate electrode (BG) can receive a negative voltage and increase the threshold voltage of the vertical-channel transistor. In other words, as the vertical-channel transistor is scaled down, the threshold voltage can be reduced, thereby preventing degradation of leakage current characteristics.

[0124] The semiconductor device according to the embodiment may further include a first back gate insulating pattern 111 and a second back gate insulating pattern 117.

[0125] The first back-gate insulating pattern 111 and the second back-gate insulating pattern 117 may be located between the first active pattern AP1 and the second active pattern AP2 that are adjacent to each other in the second direction Y. The first back-gate insulating pattern 111 and the second back-gate insulating pattern 117 may extend in the first direction X to be parallel to the back-gate electrode BG.

[0126] The first back-gate insulating pattern 111 may contact the first active pattern AP1 and the second active pattern AP2. The first back-gate insulating pattern 111 may extend in the third direction Z along the side surface of each of the first active patterns AP1 and the second active patterns AP2 that face each other in the second direction Y.

[0127] Each back gate electrode BG may include a first surface and a second surface opposite to each other in the third direction Z. Here, the first surface of each back gate electrode BG may refer to the surface facing the bit line BL and the shielding pattern SP, and the second surface of each back gate electrode BG may refer to the surface facing the first shielding gate SG1, which will be described below. In other words, the first surface of each back gate electrode BG may correspond to the lower surface of the back gate electrode BG, and the second surface may correspond to the upper surface of the back gate electrode BG.

[0128] The first back gate insulating pattern 111 can extend along the two side surfaces of the back gate electrode BG, and the second back gate insulating pattern 117 can be located between the first surface of the back gate electrode BG and the bit line BL.

[0129] The first back-gate insulating pattern 111 and the second back-gate insulating pattern 117 may contain insulating material. Each of the first back-gate insulating pattern 111 and the second back-gate insulating pattern 117 may contain at least one of silicon oxide, silicon oxynitride, and silicon nitride. However, the materials contained in the first back-gate insulating pattern 111 and the second back-gate insulating pattern 117 are not limited thereto and can be varied.

[0130] Multiple word lines WL1 and WL2 can be located on the bit line BL and the shielding pattern SP. The multiple word lines WL1 and WL2 can include multiple first word lines WL1 and multiple second word lines WL2 extending in a first direction X intersecting with a second direction Y, where the second direction Y is the direction of extension of the bit line BL. The multiple first word lines WL1 and second word lines WL2 can be positioned separately from each other in the second direction Y.

[0131] Multiple first word lines WL1 and multiple second word lines WL2 may overlap with the bit line BL and the shielding pattern SP in the third direction Z. The multiple first word lines WL1 and second word lines WL2 may extend in the third direction Z, intersecting the first direction X and the second direction Y. In other words, the first word lines WL1 and second word lines WL2 may be located between the bit line BL and the second shielding gate SG2, which will be described below, and extend in the third direction Z. A first active pattern AP1 and a second active pattern AP2 may be located between adjacent first word lines WL1 and second word lines WL2 in the second direction Y.

[0132] Although the first word line WL1 and the second word line WL2 are shown in the accompanying drawings to have a rectangular shape in cross-sectional view in the embodiment, the cross-sectional shape of the first word line WL1 and the second word line WL2 is not limited to this and can be varied. For example, each of the first word line WL1 and the second word line WL2 can have an L-shape in cross-sectional view.

[0133] Each of the first word line WL1 and the second word line WL2 may include a first surface and a second surface opposite to each other in the third direction Z. Here, the first surface of each of the first word line WL1 and the second word line WL2 may refer to the surface facing the bit line BL and the shielding pattern SP, and the second surface may refer to the surface facing the second shielding gate SG2, which will be described below. In other words, the first surface of each of the first word line WL1 and the second word line WL2 may correspond to the lower surface, and the second surface may correspond to the upper surface.

[0134] The first word line WL1 and the second word line WL2 may contain conductive materials. For example, the first word line WL1 and the second word line WL2 may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional materials, and metals. However, the conductive materials are not limited to these.

[0135] The semiconductor device according to the embodiment may further include a gate insulating pattern GOX on the side surfaces of word lines WL1 and WL2, a gate isolation pattern 141 between word lines WL1 and WL2, and a gate capping pattern 147 on the first surfaces of word lines WL1 and WL2.

[0136] The gate insulating pattern GOX can contact the first active pattern AP1 and the second active pattern AP2. The gate insulating pattern GOX can extend in the third direction Z along the side surfaces of the first active pattern AP1 and the second active pattern AP2 that face each other in the second direction Y.

[0137] The gate isolation pattern 141 may be located between the first word line WL1 and the second word line WL2, which are spaced apart in the second direction Y. The gate isolation pattern 141 may be located between the gate cap pattern 147 and the second shield cap pattern 145, which will be described below.

[0138] The gate isolation pattern 141 may contact the first word line WL1 and the second word line WL2. The first word line WL1 and the second word line WL2 may be isolated and insulated by the gate isolation pattern 141. The gate isolation pattern 141 may extend in the third direction Z between the first word line WL1 and the second word line WL2.

[0139] Specifically, the gate isolation pattern 141 may include a first surface and a second surface opposite to each other in the third direction Z. The first surface of the gate isolation pattern 141 may refer to the surface facing the gate cap pattern 147, and the second surface may refer to the surface facing the second shield cap pattern 145. In other words, the first surface of the gate isolation pattern 141 may correspond to the lower surface, and the second surface may correspond to the upper surface.

[0140] The first surface and the adjacent side surface of the gate isolation pattern 141 can be covered by the gate capping pattern 147, and the second surface and the adjacent side surface can be covered by the second shielding capping pattern 145.

[0141] The gate cap pattern 147 can be located on the first surfaces of word lines WL1 and WL2. The gate cap pattern 147 can cover the first surfaces of word lines WL1 and WL2.

[0142] The gate insulating pattern (GOX) may comprise silicon oxide, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. For example, the high dielectric constant material may comprise any one or a combination thereof of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but is not limited thereto.

[0143] The gate isolation pattern 141 and the gate cap pattern 147 may comprise any of silicon oxide, silicon nitride, or a combination thereof. For example, the gate isolation pattern 141 may comprise silicon oxide, and the gate cap pattern 147 may comprise silicon nitride. However, this disclosure is not limited thereto.

[0144] Multiple shielded gates SG may overlap with at least some of the first active pattern AP1 and the second active pattern AP2 in a second direction Y, which is a horizontal direction. The multiple shielded gates SG may be located horizontally between word lines WL1 and WL2 and the cell capacitor DSP and / or between the back gate electrode BG and the cell capacitor DSP.

[0145] More specifically, the multiple shielded gates SG may be located at the horizontal height between the upper surfaces of word lines WL1 and WL2 and the lower surface of the buried contact BC, which will be described below, and / or between the upper surface of the back gate electrode BG and the lower surface of the buried contact BC.

[0146] In an embodiment, the plurality of shielding gates SG may include a plurality of first shielding gates SG1 located on the back gate electrode BG and a second shielding gate SG2 located on word lines WL1 and WL2.

[0147] Multiple first shielding gates SG1 can be positioned to overlap with multiple back gate electrodes BG in the third direction Z, and multiple second shielding gates SG2 can be positioned to overlap with each of multiple word lines WL1 and WL2 in the third direction Z.

[0148] The first shielding gate SG1 may extend along the third direction Z on the back gate electrode BG, and the second shielding gate SG2 may extend along the third direction Z on word lines WL1 and WL2.

[0149] Multiple shielding gates SG can be located between first active patterns AP1 and second active patterns AP2 that are adjacent to each other in the second direction Y. The thickness of the multiple shielding gates SG in the third direction Z can be less than the thickness of the first active patterns AP1 and second active patterns AP2 in the third direction Z. Therefore, each shielding gate SG can be positioned to overlap with some portions of the first active patterns AP1 and second active patterns AP2 in the second direction Y.

[0150] A detailed description of the arrangement relationship between the first active pattern AP1, the second active pattern AP2, and the shielding gate SG will be provided below. Figure 7 conduct.

[0151] In an embodiment, in a plan view, the first shielding gate SG1 may have a shape substantially the same as the shape of the back gate electrode BG, and the second shielding gate SG2 may have a shape substantially the same as the shape of the first word line WL1 and the second word line WL2.

[0152] Specifically, such as Figure 2 and Figure 3 As shown, in the embodiment, the first shielding gate SG1, which overlaps with the back gate electrode BG in the third direction Z, can extend in the first direction X and has a rectangular shape in the plan view, similar to the back gate electrode BG.

[0153] Although the accompanying drawings show, in a plan view, the back gate electrode BG and the first shielding gate SG1 in this embodiment completely overlap in the third direction Z, this disclosure is not limited thereto. For example, with Figure 2 Unlike other back gate electrodes, the back gate electrode BG and the first shielding gate SG1 can have different shapes or different areas in the planar view, so that the back gate electrode BG and the first shielding gate SG1 only partially overlap in the third direction Z.

[0154] like Figure 1 and Figure 3 As shown, the first word line WL1 and the second word line WL2 may include gate line portions WL1_B and WL2_B extending in the first direction X, and gate protrusion portions WL1_P and WL2_P extending in the second direction Y from the gate line portions WL1_B and WL2_B.

[0155] Specifically, each first word line WL1 may include: a first gate line portion WL1_B extending in the first direction X, and a first gate protrusion portion WL1_P extending from the first gate line portion WL1_B along the second direction Y and located between adjacent first active patterns AP1 in the first direction X.

[0156] Each second word line WL2 may include: a second gate line portion WL2_B extending in the first direction X, and a second gate protrusion portion WL2_P extending from the second gate line portion WL2_B along the second direction Y and located between adjacent second active patterns AP2 in the first direction X.

[0157] Therefore, in the plan view, each of the first active pattern AP1 and the second active pattern AP2 can be surrounded by the gate line portions WL1_B and WL2_B of the first word line WL1 and the second word line WL2, as well as the gate protrusion portions WL1_P and WL2_P.

[0158] In an embodiment, each second shielding gate SG2 may include: a shielding line portion SG2_B extending in a first direction X, and a shielding protrusion portion SG2_P extending from the shielding line portion SG2_B along a second direction Y and located between adjacent first active patterns AP1 in the first direction X.

[0159] The shielding line portion SG2_B of the second shielding gate SG2 may have a substantially the same planar shape as the gate line portions WL1_B and WL2_B of the individual first word lines WL1 and WL2 described above, and overlaps with them in the third direction Z. Furthermore, the shielding protrusion portion SG2_P of the second shielding gate SG2 may have a substantially the same planar shape as the gate protrusion portions WL1_P and WL2_P of the individual first word lines WL1 and WL2 described above, and overlap with them in the third direction Z.

[0160] Therefore, in the plan view, each of the first active pattern AP1 and the second active pattern AP2 can be surrounded by the shielding line portion SG2_B and the shielding protrusion portion SG2_P of the second shielding gate SG2.

[0161] like Figure 2 and Figure 3 As shown, word lines WL1 and WL2 and the second shielding gate SG2 can completely overlap in the third direction Z in the plan view; however, this disclosure is not limited thereto. For example, with Figure 2 and Figure 3 As shown, word lines WL1 and WL2 and the second shielding gate SG2 can have different shapes or different areas in the plan view, such that they partially overlap in the third direction Z.

[0162] In an embodiment, the shielding gate SG may comprise a conductive material. For example, the first shielding gate SG1 may comprise the same conductive material as the back gate electrode BG, and the second shielding gate SG2 may comprise the same conductive material as the word lines WL1 and WL2. However, the conductive material contained in the shielding gate SG is not limited to this and can be varied. For example, the first shielding gate SG1 may comprise a different conductive material than the back gate electrode BG, and the second shielding gate SG2 may comprise a different conductive material than the word lines WL1 and WL2. As another example, the first shielding gate SG1 and the second shielding gate SG2 may comprise the same material, and the first shielding gate SG1 and the second shielding gate SG2 may comprise a conductive material different from the word lines WL1 and WL2 and the conductive material of the back gate electrode BG.

[0163] Furthermore, in some embodiments, the first shielding gate SG1 may comprise a conductive material having a work function different from that of the back gate electrode BG, and the second shielding gate SG2 may comprise a conductive material having a work function different from that of the word lines WL1 and WL2. For example, each of the first shielding gate SG1 and the second shielding gate SG2 may comprise a conductive material having a higher work function than that of the word lines WL1 and WL2 and the back gate electrode BG.

[0164] As a more specific example, the first shielding gate SG1 and the second shielding gate SG2 may contain one of aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlC, TiAlN, TaCN, TaC, or a combination thereof.

[0165] The semiconductor device according to the embodiment may further include a first shielding isolation pattern 113 located between the back gate electrode BG and the first shielding gate SG1, a first shielding capping pattern 115 located on the first shielding gate SG1, a second shielding isolation pattern 143 located between word lines WL1 and WL2 and the second shielding gate SG2, and a second shielding capping pattern 145 located on the second shielding gate SG2.

[0166] A first shielding isolation pattern 113 may be located between the back gate electrode BG and the first shielding gate SG1, and shall isolate and insulate them. A first shielding capping pattern 115 may be located on the first shielding gate SG1 and shall cover the first shielding gate SG1. The first shielding capping pattern 115 may be located between the first shielding gate SG1 and the contact interlayer insulating layer 271, which will be described below.

[0167] The two side surfaces of each of the first shielding gate SG1, the first shielding isolation pattern 113, and the first shielding cover pattern 115 may be surrounded by the first back gate insulation pattern 111.

[0168] The second shielding isolation pattern 143 may be located between word lines WL1 and WL2 and the second shielding gate SG2, and isolate and insulate them. The second shielding cover pattern 145 may be located on the second shielding gate SG2 and cover the second shielding gate SG2.

[0169] The second shielding cover pattern 145 may cover the upper surface of the gate isolation pattern 141 and its two adjacent side surfaces, which are located at a horizontal height higher than the second shielding gate SG2. The second shielding cover pattern 145 may be located between the second shielding gate SG2 and the buried contact BC, which will be described below, and between the gate isolation pattern 141 and the contact interlayer insulation layer 271, which will be described below.

[0170] The two side surfaces of each of the second shielding gate SG2, the second shielding isolation pattern 143, and the second shielding capping pattern 145 may be surrounded by the gate insulation pattern GOX.

[0171] Each of the first shielding isolation pattern 113, the first shielding cover pattern 115, the second shielding isolation pattern 143, and the second shielding cover pattern 145 may contain an insulating material. For example, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited to these, and various modifications may be made.

[0172] The semiconductor device according to the embodiment may further include a word line contact 241, a second shielding gate contact 243, a bit line contact 245, a first contact via 246 connecting the contact wiring line CL and the back gate electrode BG, and a second contact via 248 connecting the contact wiring line CL and the first shielding gate SG1 in the peripheral circuit area PAR of the cell structure CS.

[0173] In the semiconductor device according to the embodiment, word lines WL1 and WL2 can extend from the cell array region CAR to the peripheral circuit region PAR in a first direction X. Therefore, the ends of word lines WL1 and WL2 can be located in the peripheral circuit region PAR, and word line contacts 241 can be connected around the ends of word lines WL1 and WL2 located in the peripheral circuit region PAR.

[0174] Furthermore, in this embodiment, the second shielding gate SG2 can extend from the cell array region CAR to the peripheral circuit region PAR in the first direction X. Therefore, the end of the second shielding gate SG2 can be located in the peripheral circuit region PAR, and the second shielding gate contact 243 can be connected around the end of the second shielding gate SG2 located in the peripheral circuit region PAR.

[0175] like Figure 1 As shown, in the embodiment, multiple word line contacts 241 and multiple second shielding gate contacts 243 can be located in the peripheral circuit region PAR on both sides of the cell array region CAR in the first direction X.

[0176] Multiple word line contacts 241 and multiple second shielding gate contacts 243 can be arranged to be spaced apart from each other in a plan view along a first direction X. For example, the word line contacts 241 and the second shielding gate contacts 243 can be arranged side by side in the first direction X.

[0177] Multiple word line contacts 241 and multiple second shielding gate contacts 243 can be arranged in a zigzag pattern along the second direction Y. For example, each of the word line contacts 241 and multiple second shielding gate contacts 243 in the first row can be positioned spaced apart from the word line contacts 241 and multiple shielding gate contacts 243 in the second row in a diagonal direction intersecting the first direction X and the second direction Y. However, this is just an example, and the arrangement of the multiple word line contacts 241 and multiple second shielding gate contacts 243 in the plan view can be changed in various ways.

[0178] like Figure 4 As shown, in the embodiment, the extension length of the second word line WL2 in the second direction Y may be different from the extension length of the second shielding gate SG2 in the second direction Y.

[0179] Therefore, the second word line WL2 and the second shielding gate SG2 can have steps and are stacked in a stepped shape in the cross-sectional view. In the cross-sectional view, the end of the second shielding gate SG2 can be positioned to protrude from the end of the second word line WL2 in the first direction X. The second word line WL2 and the second shielding gate SG2 can be stacked in a stepped shape in the cross-sectional view such that the portion of the second shielding gate SG2 on the second word line WL2 does not overlap with the second word line WL2 in the third direction Z.

[0180] like Figure 4 As shown, the end of the second shielding isolation pattern 143 located between the second word line WL2 and the second shielding gate SG2 can be aligned with the end of the second word line WL2 at substantially the same boundary. In other words, the second shielding isolation pattern 143 located between the second word line WL2 and the second shielding gate SG2 can expose the portion of the second shielding gate SG2 positioned to protrude from the end of the second word line WL2 toward one side in the first direction X.

[0181] Furthermore, the second word line WL2 and the second shielding gate SG2, which are stacked in a stepped shape in the cross-sectional view, can be covered by the gate capping pattern 147. In other words, the gate capping pattern 147 can cover the end of the second word line WL2, the end of the second shielding isolation pattern 143, the portion of the second shielding gate SG2 exposed by the second shielding isolation pattern 143, and the end of the second shielding gate SG2.

[0182] Since the second word line WL2 and the second shielding gate SG2 have a stepped shape in the cross-sectional view, the word line contact 241 and the second shielding gate contact 243 can be connected to the second word line WL2 and the second shielding gate SG2 corresponding to the stepped shape, respectively.

[0183] Word line contact 241 can be connected to the lower surface of the second word line WL2, and second shielding gate contact 243 can be connected around the end of the second shielding gate SG2 that does not overlap with the second word line WL2 in the third direction Z.

[0184] One end of the word line contact 241 and the second shielding gate contact 243 can be connected to the second word line WL2 and the second shielding gate SG2, respectively, and their other ends can be connected to the cell connection wiring line 232. However, the connection relationship between the second word line WL2 and the word line contact 241 and / or the comparison result of the second shielding gate SG2 and the second shielding gate contact 243 are not limited to this and can be changed in various ways.

[0185] For example, with Figure 4 Unlike the example shown, the second word line WL2 and the second shielding gate SG2 can extend to have substantially the same length in the first direction X, such that the ends of the second word line WL2 and the second shielding gate SG2 are aligned at substantially the same boundary, and the word line contact 241 can be connected to the lower surface of the second word line WL2, and the second shielding gate contact 243 can pass through the second word line WL2 and the second shielding isolation pattern 143 and be connected to the second shielding gate SG2.

[0186] The word line contact 241 and the second shielding gate contact 243 connected to the cell connection wiring line 232 can be connected to the peripheral circuit wiring lines PCL1 and PCL2 and / or the peripheral circuit PC located in the peripheral circuit structure PS via the cell connection wiring line 232. However, the connection relationship between the second word line WL2 and / or the second shielding gate SG2 and the peripheral circuit structure PS is not limited to this and can be modified in various ways.

[0187] In an embodiment, the second word line WL2 and the second shielding gate SG2 can receive the same voltage via word line contact 241 and the second shielding gate contact 243, respectively. For example, word line contact 241 and the second shielding gate contact 243 can be connected to a driver such that the same voltage can be applied to the second word line WL2 and the second shielding gate SG2. However, this disclosure is not limited thereto.

[0188] For example, word line contact 241 and second shielding gate contact 243 can be connected to a driver, and different voltages can be applied to the second word line WL2 and the second shielding gate SG2 respectively through the operation and / or configuration of the driver.

[0189] When the same voltage is applied to the second word line WL2 and the second shielding gate SG2, the threshold voltage of the memory transistor MT can be adjusted to improve the electrical characteristics of the memory transistor MT because the second shielding gate SG2 contains a conductive material with a higher work function than the second word line WL2 as described above. In other words, because the second shielding gate SG2 contains a material with a higher work function than the second word line WL2, the second shielding gate SG2 can be used together with the second word line WL2 as the gate electrode of the memory transistor MT to adjust the threshold voltage of the memory transistor MT.

[0190] Regarding the second syllable WL2, it has already been referred to Figure 4 The stacking and contact relationships with the second shielding gate SG2 are described. These descriptions are essentially equivalent to those for the first word line WL1 and the second shielding gate SG2, and therefore will not be described in detail.

[0191] According to the embodiments, such as Figure 5 As shown, the extension length of the bit line BL along the second direction Y may differ from the extension length of the shielding pattern SP along the second direction Y. Therefore, the bit line BL may include a portion in the third direction Z, which is the vertical direction, that does not overlap with the shielding pattern SP.

[0192] Bit line contact 245 can be connected around the end of bit line BL that does not overlap with shielding pattern SP in the third direction Z. In other words, bit line contact 245 can be connected to the second metal layer 165 of bit line BL that does not overlap with shielding pattern SP in the third direction Z. One end of bit line contact 245 can be connected to the second metal layer 165 of bit line BL, and the other end can be connected to unit connection wiring line 232.

[0193] Therefore, the bit line contact 245 connected to the unit connection wiring line 232 can be connected to the peripheral circuit wiring lines PCL1 and PCL2 and / or the peripheral circuit PC located in the peripheral circuit structure PS via the first bonding pad 221. However, the connection relationship between the bit line BL and the peripheral circuit structure PS is not limited to this and can be modified in various ways.

[0194] In the semiconductor device according to the embodiment, the back gate electrode BG and the first shielding gate SG1 can extend from the cell array region CAR to the peripheral circuit region PAR in the first direction X.

[0195] Therefore, the back gate electrode BG located in the peripheral circuit region PAR can be connected to the first contact via 246 connected to the contact wiring line CL, and the first shield gate SG1 located in the peripheral circuit region PAR can be connected to the second contact via 248 connected to the contact wiring line CL.

[0196] like Figure 6 As shown, the back gate electrode BG, the first shielding gate SG1, and the ends of the first shielding isolation pattern 113 located between them can be arranged at substantially the same boundary. In other words, the first shielding gate SG1 and the back gate electrode BG can completely overlap in the third direction Z.

[0197] The first contact via 246 can pass through the first contact wiring layer 162 and the second back gate insulation pattern 117 of the contact wiring line CL, thereby connecting any one of the multiple contact wiring lines CL and the back gate electrode BG.

[0198] One end of the first contact via 246 can be connected to the second contact wiring layer 164 of the contact wiring line CL, and the other end can be connected to the lower surface of the back gate electrode BG. For example, the first contact via 246 can be formed simultaneously with the second contact wiring layer 164 of the contact wiring line CL in the same process step, and contains the same material as the second contact wiring layer 164. However, this disclosure is not limited thereto; the first contact via 246 can be formed simultaneously with the first contact wiring layer 162 or the third contact wiring layer 166 in the same process step, and contains the same material as the first contact wiring layer or the third contact wiring layer.

[0199] The second contact via 248 can pass through the first contact wiring layer 162, the second back gate insulation pattern 117, the back gate electrode BG and the first shielding isolation pattern 113, thereby connecting another of the multiple contact wiring lines CL and the first shielding gate SG1.

[0200] One end of the second contact via 248 can be connected to the second contact wiring layer 164 of the contact wiring line CL, and the other end can be connected to the lower surface of the first shield gate SG1 that is in contact with the first shield isolation pattern 113.

[0201] In an embodiment, the second contact via 248 may include a contact conductive pattern 248a and a contact insulating pattern 248b surrounding the contact conductive pattern 248a.

[0202] Specifically, the contact conductive pattern 248a of the second contact via 248 can pass through the first contact wiring layer 162, the second back gate insulation pattern 117, the back gate electrode BG, and the first shielding isolation pattern 113.

[0203] The conductive contact pattern 248a can be formed simultaneously with the second contact wiring layer 164 of the contact wiring line CL in the same process step, and contains the same material as the second contact wiring layer 164. However, this disclosure is not limited thereto; the conductive contact pattern 248a can be formed simultaneously with the first contact wiring layer 162 or the third contact wiring layer 166 in the same process step, and contains the same material as the first contact wiring layer 162 or the third contact wiring layer 166.

[0204] The contact insulating pattern 248b of the second contact via 248 can surround the side surface of the contact conductive pattern 248a. The contact insulating pattern 248b can insulate and isolate the contact conductive pattern 248a from the back gate electrode BG.

[0205] The contact insulation pattern 248b may contain an insulating material. For example, the contact insulation pattern 248b may contain at least one of silicon oxide or silicon nitride. However, the contact insulation pattern is not limited to this.

[0206] The connection relationship between the first contact via 246 and the back gate electrode BG and / or the connection relationship between the second contact via 248 and the first shielding gate SG1 are not limited to the following Figure 6 Those shown, and can be modified in various ways. For example, with reference above. Figure 4 Similar to the second word line WL2 and the second shielding gate SG2 described, the back gate electrode BG and the first shielding gate SG1 can have different extension lengths in the first direction X, thus having a stepped shape in the cross-sectional view.

[0207] Therefore, the first contact via 246 and the second contact via 248 can be connected to the back gate electrode BG and the first shielding gate SG1, which have a stepped shape, respectively. When the back gate electrode BG and the first shielding gate SG1 have a stepped shape in the cross-sectional view, the contact insulation pattern 248b of the second contact via 248 can be omitted.

[0208] The semiconductor device according to the embodiment may further include a back gate contact 242 and a first shielding gate contact 244. The back gate contact 242 connects the cell connection wiring line 232 and the contact wiring line CL connected to the first contact via 246. The first shielding gate contact 244 connects the cell connection wiring line 232 and the contact wiring line CL connected to the second contact via 248. For example, as Figure 1 As shown, the back gate contact 242 and the first shielded gate contact 244 can be connected to the end of the contact wiring line CL located in the peripheral circuit region PAR. However, this disclosure is not limited thereto.

[0209] Therefore, the first shielded gate contact 244 and the back gate contact 242 connected to the unit connection wiring line 232 can be connected to the peripheral circuit wiring lines PCL1 and PCL2 and / or the peripheral circuit PC located in the peripheral circuit structure PS.

[0210] In this embodiment, the same voltage can be applied to each of the back gate electrode BG and the first shielding gate SG1. For example, the back gate contact 242 and the first shielding gate contact 244 described above can be connected to a driver, and the same voltage can be applied to each of the back gate electrode BG and the first shielding gate SG1. However, this disclosure is not limited thereto. For example, the back gate contact 242 and the first shielding gate contact 244 can be connected to a driver, and different voltages can be applied to the back gate electrode BG and the first shielding gate SG1 respectively through the operation and / or configuration of the driver.

[0211] When the same voltage is applied to the back gate electrode BG and the first shielding gate SG1, since the first shielding gate SG1 contains a conductive material with a higher work function than the back gate electrode BG as described above, the threshold voltage of the memory transistor MT can be adjusted to improve the electrical characteristics of the memory transistor MT.

[0212] Furthermore, in embodiments, different voltages can be applied to word lines WL1 and WL2 and the back gate electrode BG via word line contact 241 and back gate contact 242, respectively. However, this disclosure is not limited thereto, and in some embodiments, the same voltage can be applied to each of word lines WL1 and WL2 and the back gate electrode BG.

[0213] The semiconductor device according to the embodiment may further include a contact interlayer insulating layer 271, a pad isolation insulating layer 273, and a contact etch stop layer 275 sequentially stacked on active patterns AP1 and AP2.

[0214] Interlayer contact insulation 271 may be located on active patterns AP1 and AP2. Interlayer contact insulation 271 may cover the first back gate insulation pattern 111, the first shielding cap pattern 115, the second shielding cap pattern 145, and the component isolation layer STI.

[0215] The interlayer insulating layer 271, the pad isolation insulating layer 273, and the contact etch stop layer 275 may comprise silicon oxide, silicon nitride, or a combination thereof. For example, the interlayer insulating layer 271 may comprise silicon oxide, and the pad isolation insulating layer 273 and the contact etch stop layer 275 may comprise silicon nitride. However, this disclosure is not limited thereto.

[0216] In the cell array area CAR of the cell structure CS, buried contacts BC, landing pads LP and cell capacitors DSP can be stacked sequentially.

[0217] The semiconductor device according to an embodiment may include a plurality of buried contacts BC. The plurality of buried contacts BC may pass through a contact interlayer insulating layer 271. The plurality of buried contacts BC may be connected to a first active pattern AP1 and a second active pattern AP2, respectively. Buried contacts BC adjacent to each other may be isolated and insulated from each other by the contact interlayer insulating layer 271.

[0218] Multiple buried contact elements BC can be arranged in a matrix pattern on a plane along a first direction X and a second direction Y. Figure 1 The diagram shows each buried contact BC having a circular shape in a plane; however, this disclosure is not limited thereto, and each buried contact BC may have various shapes in the plan view, such as ellipse, rectangle, square, rhombus and hexagon.

[0219] The buried contact BC may contain a conductive material. For example, the conductive material may contain at least one of doped polycrystalline silicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal.

[0220] The semiconductor device according to an embodiment may include a plurality of landing pads LP. The plurality of landing pads LP may be located on a plurality of buried contacts BC.

[0221] Multiple landing pads (LPs) can be arranged in a matrix along the first direction X and the second direction Y in a plan view. Figure 1 The diagram shows that each landing pad LP has a circular shape in a plane; however, this disclosure is not limited thereto, and each landing pad LP can have various shapes, such as ellipse, rectangle, square, rhombus and hexagon in the plan view.

[0222] A pad isolation insulating layer 273 can be positioned between the landing pads LP. The upper surface of the landing pads LP can be substantially at the same level as the upper surface of the pad isolation insulating layer 273.

[0223] The landing pad (LP) may contain a conductive material. The conductive material may include at least one of, for example, doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal.

[0224] The semiconductor device according to an embodiment may include a plurality of unit capacitor DSPs. The plurality of unit capacitor DSPs may be arranged in a matrix pattern along a first direction X and a second direction Y, such as... Figure 1 As shown.

[0225] Multiple unit capacitors (DSPs) can be located on multiple landing pads (LPs). The multiple unit capacitors (DSPs) can completely or partially overlap with the multiple landing pads (LPs) in a third direction (Z). The multiple unit capacitors (DSPs) can be connected to a first active pattern (AP1) and a second active pattern (AP2), respectively.

[0226] Each unit capacitor DSP may include a first electrode 251, a second electrode 255, and a dielectric film 253 located between the first electrode 251 and the second electrode 255.

[0227] The first electrode 251 may pass through the contact etch stop layer 275 and be connected to the landing pad LP. The first electrode 251 may extend along a third direction Z on the landing pad LP.

[0228] The first electrode 251 may comprise a metal, a conductive metal nitride, or a combination thereof. For example, the first electrode 251 may comprise TiN, Ru, TaN, WN, Pt, Ir, or a combination thereof. However, the material contained in the first electrode 251 is not limited to this and can be varied.

[0229] The dielectric film 253 can extend to conform to the contours of the upper and side surfaces of the first electrode 251. In other words, the dielectric film 253 can cover the side and upper surfaces of the first electrode 251. A portion of the dielectric film 253 can be located on the upper surface of the contact etch stop layer 275. In other words, a portion of the dielectric film 253 can be located between the contact etch stop layer 275 and the second electrode 255.

[0230] The dielectric film 253 may comprise tantalum oxide (Ta2O5), aluminum oxide (Al2O3), titanium oxide (TiO2), or a combination thereof. However, this disclosure is not limited thereto, and the materials contained in the dielectric film 253 can be varied.

[0231] The second electrode 255 may be located on the dielectric film 253. The second electrode 255 may completely cover the first electrode 251. In other words, the second electrode 255 may cover the upper surface and side surface of the first electrode 251.

[0232] The second electrode 255 may contain metallic materials such as W, Ti, Ru, SiGe, etc. For example, the second electrode 255 may contain tungsten (W). However, the material contained in the second electrode 255 is not limited to this and can be varied. For example, the second electrode 255 may contain conductive metal nitrides, metal silicides, or combinations thereof.

[0233] The semiconductor device according to the embodiment may further include a third unit insulating layer 277 and a fourth unit insulating layer 279 sequentially stacked on the contact etch stop layer 275.

[0234] Furthermore, the semiconductor device according to the embodiment may also include a first unit wiring contact 261 and a first unit wiring line 262 located within a third unit insulating layer 277, and a second unit wiring contact 263 and a second unit wiring line 264 located within a fourth unit insulating layer 279.

[0235] The third unit insulating layer 277 can completely cover the unit capacitor DSP. In other words, the third unit insulating layer 277 can cover the top and side surfaces of the unit capacitor DSP.

[0236] The unit capacitor DSP can be connected to the first unit wiring line 262 through the first unit wiring contact 261, and the first unit wiring line 262 can be connected to the second unit wiring line 264 through the second unit wiring contact 263.

[0237] In this embodiment, the first unit wiring line 262 may be wiring subject to an external voltage, or a redistribution layer (RDL) connected to the wiring line subject to the applied voltage. At least a portion of the second unit wiring line 264 may correspond to a power line subject to an external voltage. However, this is just an example, and the functions of the first unit wiring line 262 and the second unit wiring line 264 can be varied.

[0238] The first unit wiring contact 261, the first unit wiring line 262, the second unit wiring contact 263, and the second unit wiring line 264 may contain any metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta), or combinations thereof.

[0239] In the following text, reference will be made to Figure 7 Describe in detail the arrangement of active patterns AP1 and AP2, shielding gate SG, word lines WL1 and WL2, and back gate electrode BG.

[0240] Reference Figure 7 as well as Figure 5 Each of the first active pattern AP1 and the second active pattern AP2 may include a first doped region SDR1 connected to the bit line BL, a second doped region SDR2 connected to the unit capacitor DSP, and a channel region CHR located between the first doped region SDR1 and the second doped region SDR2. The second doped region SDR2 may be connected to the unit capacitor DSP via a buried contact BC and a landing pad LP.

[0241] The first dopant region SDR1 and the second dopant region SDR2 are doped regions within the first active pattern AP1 and the second active pattern AP2, and the dopant concentration in the first dopant region SDR1 and the second dopant region SDR2 can be higher than the dopant concentration in the channel region CHR.

[0242] During operation of the semiconductor device, the first active pattern AP1 and the second active pattern AP2 can be controlled by the first word line WL1 and the second word line WL2, which will be described below, and / or the back gate electrode BG, which will be described below. As described above, in embodiments, when the first active pattern AP1 and the second active pattern AP2 contain single-crystal semiconductor material, the leakage current characteristics of the semiconductor memory device can be improved.

[0243] The first doped region SDR1 and the second doped region SDR2 of the active patterns AP1 and AP2 can correspond to the first source / drain and the second source / drain of the memory transistor MT, and the channel region CHR can correspond to the channel of the memory transistor MT.

[0244] In an embodiment, the thickness of word lines WL1 and WL2 in the third direction Z can be substantially the same as the thickness of the back gate electrode BG in the third direction Z. In other words, the upper and lower surfaces of word lines WL1 and WL2 can be located at horizontal heights substantially the same as the upper and lower surfaces of the back gate electrode BG. However, this disclosure is not limited thereto, and any one or both of the upper and lower surfaces of word lines WL1 and WL2 can be located at horizontal heights different from the upper and lower surfaces of the back gate electrode BG.

[0245] Furthermore, in some embodiments, the thickness of the first word line WL1 and the second word line WL2 in the third direction Z can be less than the thickness of the first active pattern AP1 and the second active pattern AP2 in the third direction Z. However, the relationship between the thickness of the word lines WL1 and WL2 in the third direction Z and the thickness of the back gate electrode BG in the third direction Z, the arrangement relationship between the word lines WL1 and WL2 and the back gate electrode BG, and the relationship between the thickness of the word lines WL1 and WL2 in the third direction Z and the thickness of the active patterns AP1 and AP2 in the third direction Z are not limited to this and can be varied.

[0246] In an embodiment, the shielding gate SG may overlap with at least one second dopant region SDR2 of the active patterns AP1 and AP2 in a second direction Y, which is a horizontal direction. For example, the shielding gate SG may be positioned to overlap with the second dopant region SDR2 of each of the active patterns AP1 and AP2 in a second direction Y, which is a horizontal direction.

[0247] In addition, the shielding gate SG can be located at a horizontal height higher than the channel region CHR so as not to overlap with the channel region CHR in the second direction Y.

[0248] The thickness of the shielding gate SG in the third direction Z can be less than the thickness of the second doped region SDR2 in the third direction Z. Therefore, the shielding gate SG can overlap a portion of the second doped region SDR2 in the second direction Y. In other words, the shielding gate SG can overlap the second doped region SDR2 in a direction intersecting the extension direction of the second doped region SDR2.

[0249] Since the shielding gate SG is positioned to overlap with the second dopant region SDR2 of the active patterns AP1 and AP2 as described above, interference between adjacent second dopant regions SDR2 can be reduced.

[0250] The first shielding isolation pattern 113 may include a first surface and a second surface that face each other in the third direction Z and are in contact with the back gate electrode BG and the first shielding gate SG1, respectively. The second shielding isolation pattern 143 may include a first surface and a second surface that face each other in the third direction Z and are in contact with word lines WL1 and WL2 and the second shielding gate SG2, respectively. Here, the first surface may correspond to the lower surface and the second surface may correspond to the upper surface.

[0251] In an embodiment, the thickness of the first shielding isolation pattern 113 in the third direction Z can be substantially the same as the thickness of the second shielding isolation pattern 143 in the third direction Z.

[0252] Furthermore, the first surface of the first shielding isolation pattern 113 may be substantially at the same horizontal height as the first surface of the second shielding isolation pattern 143, and the second surface of the first shielding isolation pattern 113 may be substantially at the same horizontal height as the second surface of the second shielding isolation pattern 143. However, this disclosure is not limited thereto, and the thickness relationship and / or arrangement relationship of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 can be varied.

[0253] In an embodiment, the first surfaces of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 may be located at a higher horizontal level than the channel region CHR of the active patterns AP1 and AP2. Therefore, the first shielding isolation pattern 113 and the second shielding isolation pattern 143 may not overlap with the channel region CHR in the second direction Y. However, this disclosure is not limited thereto, and some portions of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 may overlap with the channel region CHR in the second direction Y.

[0254] The first shielding gate SG1 may include a first surface SG1_S1 and a second surface SG1_S2 facing each other on the third direction Z and respectively in contact with the first shielding isolation pattern 113 and the first shielding cover pattern 115.

[0255] The two side surfaces (SG1_S1 and SG1_SG2) of the first shielding gate SG1 can contact the first back gate insulating pattern 111. In other words, the two side surfaces (SG1_S1 and SG1_SG2) of the first shielding gate SG1 can face the second doped region SDR2 of the active patterns AP1 and AP2, wherein the first back gate insulating pattern 111 is inserted therebetween.

[0256] The second shielding gate SG2 may include a first surface SG2_S1 and a second surface SG2_S2 facing each other on the third direction Z and in contact with the second shielding isolation pattern 143 and the second shielding cover pattern 145, respectively.

[0257] The second shielding gate SG2 may include a first side surface SG2_S3 and a second side surface SG2_S4 that face each other in the second direction Y.

[0258] The first side surface SG2_S3 of the second shielding gate SG2 located on the first word line WL1 can contact the gate isolation pattern 141, and the second side surface SG2_S4 can contact the gate insulation pattern GOX.

[0259] The first side surface SG2_S3 of the second shielding gate SG2 located on the second word line WL2 can contact the gate insulating pattern GOX, and the second side surface SG2_S4 can contact the gate isolation pattern 141.

[0260] In an embodiment, the first surface SG1_S1 of the first shielding gate SG1 can be positioned at substantially the same horizontal height as the second surface SG2_S2 of the second shielding gate SG2. The second surface SG1_S2 of the second shielding gate SG2 can also be positioned at substantially the same horizontal height as the second surface SG2_S2 of the second shielding gate SG2.

[0261] The second surface SG1_S2 of the first shielding gate SG1 and the second surface SG2_S2 of the second shielding gate SG2 can be located at a horizontal height higher than the upper surface of the gate isolation pattern 141. However, none of the present disclosures are limited thereto, and the thicknesses of word lines WL1 and WL2 in the third direction Z, the thicknesses of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 in the third direction Z, the thickness of the back gate electrode BG in the third direction Z, and the arrangement relationship of the first shielding gate SG1 and the second shielding gate SG2 can be varied.

[0262] The first shielding gate SG1 and the back gate electrode BG may have a first width W1, and the second shielding gate SG2 and word lines WL1 and WL2 may have a second width W2.

[0263] In an embodiment, the first shielding gate SG1 and the back gate electrode BG may have substantially the same first width W1, and each of the second shielding gate SG2 and word lines WL1 and WL2 may have substantially the same second width W2. Here, the first width W1 and the second width W2 may refer to the width in the second direction Y.

[0264] In an embodiment, the first width W1 may be greater than the second width W2. In other words, the width of the first shielding gate SG1 may be greater than the width of the second shielding gate SG2, and the width of the back gate electrode BG may be greater than the widths of the word lines WL1 and WL2. However, this disclosure is not limited thereto, and the first width W1 and the second width W2 may be varied. For example, the first width W1 may be substantially the same as the second width W2. In other words, the width of the back gate electrode BG may be substantially the same as the width of each of the word lines WL1 and WL2, and the width of the first shielding gate SG1 may be substantially the same as the width of the second shielding gate SG2.

[0265] According to the semiconductor device based on the embodiment, since the shielding gate SG is formed between the doped regions of the active patterns AP1 and AP2, the coupling caused by interference between the doped regions of the adjacent active patterns AP1 and AP2 can be improved.

[0266] Furthermore, when a voltage is applied to the shielded gate SG, the current flow of the memory transistor MT in the on-state can be increased, while reducing gate-induced drain leakage in the memory transistor MT, thereby improving the electrical characteristics of the semiconductor device. Therefore, a semiconductor device with improved reliability and productivity can be provided.

[0267] The following will refer to Figures 8 to 24 A semiconductor device according to various embodiments is described. In the following embodiments, components that are the same as those in the above embodiments will be indicated by the same reference numerals, and their redundant descriptions will be omitted or will be brief; rather, their differences from those in the above embodiments will be primarily described.

[0268] Figures 8 to 17 This is a cross-sectional view illustrating a semiconductor device according to some embodiments. Specifically, Figures 8 to 17 This is a partial enlarged view showing regions P2 to P11 according to some embodiments, which correspond to Figure 5 Region P1.

[0269] according to Figure 8 and Figure 9 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in the arrangement of the shielding gate SG.

[0270] according to Figure 8 In the embodiment shown, unlike the semiconductor device according to the above embodiments, the shielding gate SG can be located on word lines WL1 and WL2, and may not be located on the back gate electrode BG. In other words, compared with... Figure 7 The illustrated embodiment differs in that the first shielding gate located on the back gate electrode BG can be omitted (see [reference]). Figure 7 (see attached figure "SG1").

[0271] Furthermore, since the shielding gate SG is omitted on the back gate electrode BG, it is similar to... Figure 7 The illustrated embodiment differs in that the first shielding isolation pattern located on the back gate electrode BG can be omitted (see...). Figure 7 (See attached figure "113").

[0272] In this embodiment, a shielding gate SG can be provided on one side of the second dopant region SDR2 of each of the active patterns AP1 and AP2, and a back gate cover pattern 116 can be provided on the other side.

[0273] Specifically, the back gate capping pattern 116 located on the back gate electrode BG may include a first surface 116_S1 and a second surface 116_S2 facing each other in the third direction Z.

[0274] In this embodiment, the first surface 116_S1 of the back gate cover pattern 116 can contact the back gate electrode BG, and the second surface 116_S2 can contact the interlayer insulating layer 271.

[0275] The thickness of the back gate cover pattern 116 in the third direction Z can be greater than the thickness of the shielding gate SG in the third direction Z. However, this disclosure is not limited thereto, and the relationship between the thickness of the back gate cover pattern 116 in the third direction Z and the thickness of the shielding gate SG in the third direction Z can be varied.

[0276] The shielding gate SG located on word lines WL1 and WL2 may include a first surface SG_S1 and a second surface SG_S2 facing each other on the third direction Z.

[0277] The first surface 116_S1 of the back gate cover pattern 116 may be located at a different horizontal height than the first surface SG_S1 of the shielding gate SG, and the second surface 116_S2 of the back gate cover pattern 116 may be located at a different horizontal height than the second surface SG_S2 of the shielding gate SG. For example, the first surface 116_S1 of the back gate cover pattern 116 may be located at a lower horizontal height than the first surface SG_S1 of the shielding gate SG, and the second surface 116_S2 of the back gate cover pattern 116 may be located at a higher horizontal height than the second surface SG_S2 of the shielding gate SG.

[0278] Furthermore, the first surface 116_S1 of the back gate cover pattern 116 can be located at substantially the same horizontal height as the lower surface of the shielding isolation pattern 140 that contacts the word lines WL1 and WL2. However, this disclosure is not limited to this, and the arrangement relationship between the back gate cover pattern 116 and the shielding gate SG and / or the arrangement relationship between the back gate cover pattern 116 and the shielding isolation pattern 140 can be varied. For example, when the upper surface of the back gate electrode BG is formed at a horizontal height higher than the upper surfaces of the word lines WL1 and WL2, the first surface 116_S1 of the back gate cover pattern 116 can be located at a horizontal height different from the horizontal height of the lower surface of the shielding isolation pattern 140.

[0279] according to Figure 9 In the illustrated embodiment, unlike the semiconductor device according to the embodiments described above, the shielding gate SG may be located on the back gate electrode BG and may not be located on word lines WL1 and WL2. In other words, compared to... Figure 7Unlike the embodiments shown, the second shielding gate located on word lines WL1 and WL2 can be omitted (see...). Figure 7 (see attached figure "SG2").

[0280] Furthermore, since the shielding gate SG is omitted on word lines WL1 and WL2, it is consistent with... Figure 7 The embodiments shown differ in that the second shielding isolation pattern located on word lines WL1 and WL2 may be omitted (see...). Figure 7 (see attached figure "143").

[0281] In this embodiment, a shielding gate SG can be provided on one side of the second dopant region SDR2 of each of the active patterns AP1 and AP2, and a word line capping pattern 146 can be provided on the other side.

[0282] Specifically, the word line cover pattern 146 may include a first surface 146_S1 that contacts the word lines WL1 and WL2 and a second surface 146_S2 that contacts the interlayer insulation layer 271.

[0283] The shielded gate SG located on the back gate electrode BG may include a first surface SG_S1 and a second surface SG_S2 that are opposite to each other in the third direction Z.

[0284] The first surface 146_S1 of the word line capping pattern 146 may be located at a different horizontal height than the first surface SG_S1 of the shielding gate SG, and the second surface 146_S2 of the word line capping pattern 146 may be located at a different horizontal height than the second surface SG_S2 of the shielding gate SG. For example, the first surface 146_S1 of the word line capping pattern 146 may be located at a lower horizontal height than the first surface SG_S1 of the shielding gate SG, and the second surface 146_S2 of the word line capping pattern 146 may be located at a higher horizontal height than the second surface SG_S2 of the shielding gate SG.

[0285] Furthermore, the first surface 146_S1 of the word line capping pattern 146 can be located at a horizontal height substantially the same as the horizontal height of the first surface of the shielding isolation pattern 140 that contacts the back gate electrode BG. However, this disclosure is not limited to this, and the arrangement relationship between the word line capping pattern 146 and the shielding gate SG and / or the arrangement relationship between the word line capping pattern 146 and the shielding isolation pattern 140 can be varied. For example, when the upper surfaces of the word lines WL1 and WL2 are formed at a horizontal height higher than the upper surface of the back gate electrode BG, the first surface 146_S1 of the word line capping pattern 146 can be located at a horizontal height different from the horizontal height of the lower surface of the shielding isolation pattern 140.

[0286] Figure 8and Figure 9 The illustrated embodiment can be the result of forming the shielding gate SG on word lines WL1 and WL2 and the shielding gate SG on the back gate electrode BG by separate processes. In other words, because either the process steps for forming the shielding gate SG on word lines WL1 and WL2 or the process steps for forming the shielding gate SG on the back gate electrode BG are omitted, the result is... Figure 8 and Figure 9 As in the embodiment shown, a shielded gate SG is formed only on word lines WL1 and WL2 or on the back gate electrode BG.

[0287] according to Figure 8 and Figure 9 The semiconductor device of the illustrated embodiment can have substantially the same effects as the semiconductor device according to the above embodiment. In other words, since the shielding gate SG is formed on one side of each of the active patterns AP1 and AP2, coupling caused by interference between the doped regions of the active patterns AP1 and AP2 that are adjacent to each other and in which word lines WL1 and WL2 are inserted, or by interference between the doped regions of the active patterns AP1 and AP2 that are adjacent to each other and in which back gate electrode BG is inserted, can be improved.

[0288] according to Figure 10 and Figure 11 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in that the width of the shielding gate SG is changed.

[0289] Figure 10 The embodiment shown differs from the semiconductor device according to the above embodiments in that the width of the first shielding gate SG1 located on the back gate electrode BG is smaller than the width of the back gate electrode BG, and the width of the second shielding gate SG2 located on the word lines WL1 and WL2 is smaller than the width of each of the word lines WL1 and WL2.

[0290] Specifically, the back gate electrode BG may have a first width W1, and each of the word lines WL1 and WL2 may have a second width W2, the first shielding gate SG1 may have a third width W3, and the second shielding gate SG2 may have a fourth width W4. Here, the first width W1, the second width W2, the third width W3, and the fourth width W4 may refer to the width in the second direction Y.

[0291] In this embodiment, the first width W1 can be greater than the third width W3, and the second width W2 can be greater than the fourth width W4. In other words, the width of the back gate electrode BG can be greater than the width of the first shielding gate SG1, and the width of each of the word lines WL1 and WL2 can be greater than the width of the second shielding gate SG2.

[0292] Furthermore, in this embodiment, the third width W3 can be substantially the same as the fourth width W4. However, the relationship between the third width W3 and the fourth width W4 is not limited to this, but can be changed in various ways. For example, the third width W3 can be greater than or less than the fourth width W4.

[0293] In this embodiment, the first shielding gate SG1 can be completely surrounded by the first shielding cover pattern 115. In other words, the second surface SG1_S2 of the first shielding gate SG1 and the first side surface SG1_S3 and the second side surface SG1_S4 of the first shielding gate SG1 can contact the first shielding cover pattern 115.

[0294] In this embodiment, the first side surface SG2_S3 and the second surface SG2_S2 of the second shielding gate SG2 located on the first word line WL1 can contact the second shielding cover pattern 145, and the second side surface SG2_S4 can contact the gate insulating pattern GOX.

[0295] Furthermore, the first side surface SG2_S3 of the second shielding gate SG2 located on the second word line WL2 can contact the gate insulating pattern GOX, and the second side surface SG2_S4 and the second surface SG2_S2 can contact the second shielding cover pattern 145.

[0296] In this embodiment, the first shielding gate SG1 and the back gate electrode BG may have substantially the same central axis. In other words, the center of the first shielding gate SG1 and the center of the back gate electrode BG may be positioned aligned on substantially the same central axis.

[0297] The second shielding gate SG2 may have a central axis different from the central axis of each of the word lines WL1 and WL2. In other words, the central axis of the second shielding gate SG2 may be shifted from the central axes of the word lines WL1 and WL2 to one side or the other side in the second direction Y, respectively. For example, when the central axis of the second shielding gate SG2 is moved from the central axes of the word lines WL1 and WL2 to one side or the other side in the second direction Y, the second shielding gate SG2 may be positioned closer to the gate isolation pattern 141 or the gate insulation pattern GOX. However, the position on the second shielding gate SG2 is not limited to this and can be changed in various ways. For example, with Figure 10 Unlike other methods, the central axis of the second shielding gate SG2 can be positioned to coincide with the central axes of word lines WL1 and WL2, respectively.

[0298] according to Figure 11 The semiconductor device of the illustrated embodiment and according to Figure 10The semiconductor device in the illustrated embodiment differs in that the widths of the first shielding gate SG1 and the second shielding gate SG2 are different.

[0299] Specifically, refer to Figure 11 The back gate electrode BG and the first shielding gate SG1 can have a first width W1. In other words, the back gate electrode BG and the first shielding gate SG1 can have substantially the same width.

[0300] Each of the word lines WL1 and WL2 may have a second width W2, and the second shielding gate SG2 may have a third width W3. Here, the first width W1, the second width W2, and the third width W3 may refer to the width in the second direction Y.

[0301] In this embodiment, the first width W1 can be greater than the second width W2 and the third width W3, and the second width W2 can be greater than the third width W3. In other words, the width of the back gate electrode BG can be greater than the width of each of the word lines WL1 and WL2, and is substantially the same as the width of the first shielding gate SG1.

[0302] The width of the first shielding gate SG1 can be greater than the width of each of the word lines WL1 and WL2 and the width of the second shielding gate SG2. The width of the second shielding gate SG2 can be less than the width of each of the word lines WL1 and WL2. However, the relationship between the first width W1, the second width W2, and the third width W3 is not limited to this and can be varied. For example, with... Figure 11 Unlike other methods, the width of the first shielding gate SG1 can be smaller than the width of the back gate electrode BG, and the width of the second shielding gate SG2 can be substantially the same as the width of each of the word lines WL1 and WL2. In this case, the width of the first shielding gate SG1 can be smaller or larger than the width of the second shielding gate SG2.

[0303] Figure 10 and Figure 11 The embodiment shown may be the result of forming a shielding gate SG smaller than the width of word lines WL1 and WL2 and / or the width of back gate electrode BG during the process steps of forming a shielding gate SG located on word lines WL1 and WL2 and whose shape is located on back gate electrode BG.

[0304] according to Figure 10 and 11 The semiconductor device of the illustrated embodiment can have substantially the same effects as the semiconductor device according to the above embodiment.

[0305] according to Figures 12 to 14The semiconductor device of the embodiment shown may differ from the semiconductor device according to the above embodiment in that the thickness of the shielding gate SG and / or the shielding isolation patterns 113 and 143 in the third direction Z is changed.

[0306] according to Figure 12 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in that the thickness of the first shielding gate SG1 in the third direction Z and the thickness of the second shielding gate SG2 in the third direction Z are different.

[0307] In this embodiment, the thickness of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 in the third direction Z can be substantially the same.

[0308] In this embodiment, the first shielding gate SG1 may have a first thickness T1, and the second shielding gate SG2 may have a second thickness T2. Here, the first thickness T1 may refer to the thickness of the first shielding gate SG1 in the third direction Z between the first surface SG1_S1 and the second surface SG1_S2, and the second thickness T2 may refer to the thickness of the second shielding gate SG2 in the third direction Z between the first surface SG2_S1 and the second surface SG2_S2.

[0309] In this embodiment, the first thickness T1 may be greater than the second thickness T2. In other words, the thickness of the first shielding gate SG1 may be greater than the thickness of the second shielding gate SG2. However, this disclosure is not limited thereto, and the relationship between the first thickness T1 and the second thickness T2 may be varied. For example, the first thickness T1 may be less than the second thickness T2.

[0310] In this embodiment, the first surface SG1_S1 of the first shielding gate SG1 can be located at substantially the same horizontal height as the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 can be located at a higher horizontal height than the second surface SG2_S2 of the second shielding gate SG2. However, this disclosure is not limited to this, and the relationship between the first shielding gate SG1 and the second shielding gate SG2 can be varied as the thickness of the first shielding gate SG1 and the second shielding gate SG2 changes and / or the thickness of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 changes.

[0311] Figure 13 The semiconductor device of the illustrated embodiment and according to Figure 12 The difference between the semiconductor devices is that the first shielding isolation pattern 113 and the second shielding isolation pattern 143 have different thicknesses in the third direction Z.

[0312] In this embodiment, the first shielding gate SG1 may have a first thickness T1, the second shielding gate SG2 may have a second thickness T2, the first shielding isolation pattern 113 may have a third thickness T3, and the second shielding isolation pattern 143 may have a fourth thickness T4.

[0313] Here, the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 can refer to the thickness in the third direction Z.

[0314] In this embodiment, the first thickness T1 can be substantially the same as the second thickness T2, and the third thickness T3 can be greater than the fourth thickness T4. In other words, the thicknesses of the first shielding gate SG1 and the second shielding gate SG2 can be substantially the same, and the thickness of the first shielding isolation pattern 113 can be greater than the thickness of the second shielding isolation pattern 143.

[0315] Therefore, the first surface of the first shielding isolation pattern 113 can be located at a substantially the same horizontal height as the first surface of the second shielding isolation pattern 143, and the second surface of the first shielding isolation pattern 113 can be located at a higher horizontal height than the second surface of the second shielding isolation pattern 143. Here, the first surface of each of the first shielding isolation pattern 113 and the second shielding isolation pattern 143 can correspond to the lower surface, and the second surface can correspond to the upper surface.

[0316] Furthermore, the first surface SG1_S1 of the first shielding gate SG1 can be located at a higher horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 can be located at a higher horizontal height than the second surface SG2_S2 of the second shielding gate SG2.

[0317] and Figure 13 In some embodiments, the first thickness T1 and the second thickness T2 can be substantially the same, and the third thickness T3 can be less than the fourth thickness T4. The lower surface of the first shielding isolation pattern 113 can be located at substantially the same horizontal height as the lower surface of the second shielding isolation pattern 143, and the upper surface of the first shielding isolation pattern 113 can be located at a lower horizontal height than the upper surface of the second shielding isolation pattern 143.

[0318] Therefore, the first surface SG1_S1 of the first shielding gate SG1 can be located at a lower horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 can be located at a lower horizontal height than the second surface SG2_S2 of the second shielding gate SG2. However, this disclosure is not limited to this, and because the thicknesses of word lines WL1 and WL2 in the third direction Z and / or the thickness of the back gate electrode BG in the third direction Z are different, the relationship between the first shielding isolation pattern 113 and the second shielding isolation pattern 143 and the first shielding gate SG1 and the second shielding gate SG2 can be varied.

[0319] according to Figure 14 The semiconductor device of the illustrated embodiment and according to Figure 13 The semiconductor device in the illustrated embodiment differs in that the first shielding isolation pattern 113 and the second shielding isolation pattern 143 have different thicknesses in the third direction Z, and the first shielding gate SG1 and the second shielding gate SG2 have different thicknesses.

[0320] Reference Figure 14 In this embodiment, the first thickness T1 can be less than the second thickness T2, and the third thickness T3 can be greater than the fourth thickness T4. In other words, the thickness of the first shielding gate SG1 can be less than the thickness of the second shielding gate SG2, and the thickness of the first shielding isolation pattern 113 can be greater than the thickness of the second shielding isolation pattern 143.

[0321] The lower surface of the first shielding isolation pattern 113 may be located at a substantially the same horizontal height as the lower surface of the second shielding isolation pattern 143, and the upper surface of the first shielding isolation pattern 113 may be located at a higher horizontal height than the upper surface of the second shielding isolation pattern 143.

[0322] Furthermore, the first surface SG1_S1 of the first shielding gate SG1 may be located at a higher horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 may be located at a horizontal height substantially the same as the second surface SG2_S2 of the second shielding gate SG2. However, this disclosure is not limited thereto. For example, the first surface SG1_S1 of the first shielding gate SG1 may be located at a higher horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 may be located at a horizontal height different from the second surface SG2_S2 of the second shielding gate SG2.

[0323] Figures 12 to 14The embodiments shown may result in different thicknesses of the shielding gate SG formed on word lines WL1 and WL2 and on the back gate electrode BG.

[0324] according to Figures 13 to 14 The semiconductor device of the illustrated embodiment can have substantially the same effects as the semiconductor device according to the above embodiment.

[0325] according to Figure 15 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in that the arrangement of the second shielding gate SG2 is changed.

[0326] according to Figure 15 The semiconductor device of the embodiment shown differs from the semiconductor device according to the above embodiments in that the width of the second shielding gate SG2 located on word lines WL1 and WL2 is changed.

[0327] Reference Figure 7 The above description of the first shielding gate SG1 can also be applied substantially equivalently to the first shielding gate SG1 according to this embodiment, and therefore will not be described in detail.

[0328] Reference Figure 15 The back gate electrode BG and the first shielding gate SG1 may have a first width W1, each of the word lines WL1 and WL2 may have a second width W2, and the second shielding gate SG2 may have a third width W3. Here, the first width W1, the second width W2, and the third width W3 may refer to the width in the second direction Y.

[0329] In this embodiment, the first width W1 can be greater than the second width W2 and less than the third width W3. In other words, the widths of the back gate electrode BG and the first shielding gate SG1 can be substantially the same, and each of the widths of the back gate electrode BG and the first shielding gate SG1 can be greater than the widths of the word lines WL1 and WL2. Furthermore, the width of the second shielding gate SG2 can be greater than the width of the first shielding gate SG1, the width of the back gate electrode BG, and the width of each of the word lines WL1 and WL2.

[0330] In this embodiment, the second shielding gate SG2 can be positioned to overlap with the first word line WL1 and the second word line WL2 located between the first active pattern AP1 and the second active pattern AP2 in the third direction Z. In other words, the second shielding gate SG2 can be positioned to overlap with multiple word lines WL1 and WL2 in the third direction Z.

[0331] The first surface SG2_S1 of the second shielding gate SG2 can contact the gate isolation pattern 141 and the second shielding isolation pattern 143 located on both sides of the gate isolation pattern 141. The first side surface SG2_S3 and the second side surface SG2_S4 of the second shielding gate SG2 can contact the gate insulating pattern GOX.

[0332] The upper surface of the gate isolation pattern 141 that contacts the first surface SG2_S1 of the second shielding gate SG2 and the upper surface of the second shielding isolation pattern 143 can be located at substantially the same horizontal height.

[0333] In this embodiment, the first surface SG1_S1 of the first shielding gate SG1 can be located at a substantially the same horizontal height as the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 and the second surface SG2_S2 of the second shielding gate SG2 can be located at substantially the same horizontal height. However, the arrangement of the first shielding gate SG1 and the second shielding gate SG2 is not limited to this and can be varied. For example, the first surface SG1_S1 of the first shielding gate SG1 can be located at a substantially the same horizontal height as the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 can be located at a different horizontal height than the second surface SG2_S2 of the second shielding gate SG2. As another example, the first surface SG1_S1 of the first shielding gate SG1 can be located at a different horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 can be located at a substantially the same horizontal height as the second surface SG2_S2 of the second shielding gate SG2. As another example, the first surface SG1_S1 of the first shielding gate SG1 may be located at a different horizontal height than the first surface SG2_S1 of the second shielding gate SG2, and the second surface SG1_S2 of the first shielding gate SG1 may be located at a different horizontal height than the second surface SG2_S2 of the second shielding gate SG2.

[0334] Figure 15 The embodiments shown may be the result of forming the shielding gate SG on word lines WL1 and WL2 and the shielding gate SG on the back gate electrode BG in separate process steps, for example, the width of the first shielding gate SG1 is different from the width of the second shielding gate SG2.

[0335] according to Figure 15 The semiconductor device of the illustrated embodiment can have substantially the same effects as the semiconductor device according to the above embodiment.

[0336] according to Figure 16 and Figure 17 The semiconductor device of the embodiment shown differs from the semiconductor device according to the above embodiment in that the back gate electrode BG is omitted.

[0337] according to Figure 16 The semiconductor device shown in the embodiment, and Figure 7 The embodiments shown are different and may omit the back gate electrode BG, the first back gate insulating pattern 111 and the first shielding isolation pattern 113, and may also include an isolation insulating pattern 150, an isolation capping pattern 170 located between the first active pattern AP1 and the second active pattern AP2, and a first shielding isolation pattern 110 surrounding the side surfaces of the isolation insulating pattern 150 and the isolation capping pattern 170.

[0338] Specifically, refer to Figure 16 On one side of either active pattern AP1 or AP2 in the second direction Y, a first word line WL1 may be provided, and on the other side in the second direction Y, an isolation insulation pattern 150 may be provided. Furthermore, on the other active pattern AP1 or AP2 in the second direction Y, an isolation insulation pattern 150 may be provided, and on the other side in the second direction Y, a second word line WL2 may be provided.

[0339] Therefore, word lines WL1 and WL2 can be located on one side or the other side of active patterns AP1 and AP2.

[0340] The insulating pattern 150 may include a first surface 150_S1 and a second surface 150_S2 that are opposite to each other in a third direction Z. Here, the first surface 150_S1 may correspond to the lower surface of the insulating pattern 150, and the second surface 150_S2 may correspond to the upper surface.

[0341] The first surface 150_S1 of the insulating pattern 150 may be located at a lower horizontal height than the lower surface of the second shielding pattern 143, and the second surface 150_S2 may be located at a substantially the same horizontal height as the upper surface of the second shielding pattern 143. However, this disclosure is not limited thereto, and the second surface 150_S2 of the insulating pattern 150 may be located at a different horizontal height than the upper surface of the second shielding pattern 143.

[0342] In this embodiment, the first shielding gate SG1 may be located on the second surface 150_S2 of the isolation insulating pattern 150, and the second shielding gate SG2 may be located on word lines WL1 and WL2.

[0343] Reference above Figures 7 to 15The description of the first shielding gate SG1 and the second shielding gate SG2 can be applied equally to the first shielding gate SG1 and the second shielding gate SG2 according to this embodiment, and therefore will not be described in detail.

[0344] The isolation cap pattern 170 may be located on the first surface 150_S1 of the isolation insulation pattern 150. The first shielding isolation pattern 110 may extend in the third direction Z along the side surface of each of the sequentially stacked isolation cap pattern 170, isolation insulation pattern 150, first shielding gate SG1 and first shielding cap pattern 115.

[0345] The first shielding isolation pattern 110 may be located between the side surface of each of the sequentially stacked isolation cap pattern 170, isolation insulation pattern 150, first shielding gate SG1 and first shielding cap pattern 115 and the active patterns AP1 and AP2.

[0346] Each of the first shielding isolation pattern 110, the isolation insulation pattern 150, and the isolation cover pattern 170 may contain an insulating material. For example, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited to these, and various modifications may be made.

[0347] according to Figure 17 The semiconductor device shown in the embodiment is Figure 7 The difference in the embodiment shown is that the back gate electrode BG, the first back gate insulating pattern 111, the first shielding isolation pattern 113 and the first shielding gate SG1 located between the first active pattern AP1 and the second active pattern AP2 are omitted, and the first word line WL1 and the second word line WL2 are also included between the first active pattern AP1 and the second active pattern AP2.

[0348] Reference Figure 17 Between each pair of active patterns AP1 and AP2, a first word line WL1 and a second word line WL2 can be set.

[0349] Specifically, a first character line WL1 can be provided on one side of the first active pattern AP1 in the second direction Y, and a second character line WL2 can be provided on the other side in the second direction Y. Furthermore, a first character line WL1 can be provided on one side of the second active pattern AP2 in the second direction Y, and a second character line WL2 can be provided on the other side in the second direction Y.

[0350] Therefore, word lines WL1 and WL2 can be set on both sides of each of the first active pattern AP1 and the second active pattern AP2.

[0351] In this embodiment, multiple shielding gates SG can be located on multiple word lines WL1 and WL2, respectively. The multiple individual shielding gates SG can have substantially the same thickness in the third direction Z and / or substantially the same width in the second direction Y. However, this disclosure is not limited thereto; see also [link to previous section]. Figures 10 to 15 The above description of the shielding gate SG can be used equivalently to the arrangement, width, and thickness relationships of multiple shielding gate SGs, and therefore will not be described in detail.

[0352] exist Figure 17 The diagram shows that two side surfaces of each of the first active pattern AP1 and the second active pattern AP2 overlap with word lines WL1 and WL2; however, the arrangement of the first active pattern AP1, the second active pattern AP2, and the word lines WL1 and WL2 is not limited to this and can be varied.

[0353] and Figure 17 Unlike other embodiments, in some implementations, word lines WL1 and WL2 may surround the side surfaces of each of the first active pattern AP1 and the second active pattern AP2. For example, word lines WL1 and WL2 may be integrally formed and have a ring gate (GAA) structure surrounding the four side surfaces of each of the first active pattern AP1 and the second active pattern AP2.

[0354] When word lines WL1 and WL2 are integrally formed as described above and have a structure that surrounds all side surfaces of each of the first active pattern AP1 and the second active pattern AP2, the shielding isolation pattern 140 located on the first word line WL1 and the second word line WL2 can be integrally formed and have a structure that surrounds all side surfaces of each of the first active pattern AP1 and the second active pattern AP2.

[0355] Furthermore, when word lines WL1 and WL2 are integrally formed as described above and have a structure that surrounds all side surfaces of each of the first active pattern AP1 and the second active pattern AP2, the shielding gate SG located on the first word line WL1 and the second word line WL2 can be integrally formed and have a structure that surrounds all side surfaces of each of the first active pattern AP1 and the second active pattern AP2.

[0356] according to Figure 17 The semiconductor device of the illustrated embodiment can have substantially the same effects as the semiconductor device according to the above embodiment.

[0357] Figure 18 and Figure 19 This is a plan view illustrating a partial configuration of a semiconductor device according to some embodiments. Figure 18 and Figure 19In this document, other components are not shown in order to illustrate the arrangement of some components included in a semiconductor device according to some embodiments.

[0358] according to Figure 18 and Figure 19 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in that the planar shape of the shielding gate SG is changed.

[0359] according to Figure 18 In the embodiment shown, the planar shape of the first shielding gate SG1 can be substantially the same as the planar shape of the back gate electrode BG, and the planar shape of the second shielding gate SG2 can be different from the planar shapes of the word lines WL1 and WL2.

[0360] Specifically, refer to Figure 18 and Figure 3 The planar shape of the first shielding gate SG1 can be substantially the same as the planar shape of the back gate electrode BG. However, this disclosure is not limited thereto. For example, with Figure 18 Unlike other shielding gates, the planar shape of the first shielding gate SG1 can be different from the planar shape of the back gate electrode BG.

[0361] In this embodiment, the planar shapes of the word lines WL1 and WL2 that overlap with the second shielding gate SG2 can be determined according to... Figure 3 The word lines WL1 and WL2 in the illustrated embodiment have substantially the same planar shape. The planar shape of the second shielding gate SG2 may differ from that of the word lines WL1 and WL2.

[0362] Specifically, the second shielding gate SG2 may extend in the first direction X and have a linear shape in the planar view. The planar shape of the second shielding gate SG2 may be substantially the same as the planar shape of the gate line portions WL1_B and WL2_B of each word line WL1 and WL2.

[0363] The second shielding gate SG2 may overlap with a portion of each of the word lines WL1 and WL2 in the third direction Z. In other words, the second shielding gate SG2 may overlap with the gate line portions WL1_B and WL2_B of each word line WL1 and WL2 in the third direction Z, but may not overlap with the gate protrusions WL1_P and WL2_P of each word line WL1 and WL2 in the third direction Z. Therefore, the gate protrusions WL1_P and WL2_P of each word line WL1 and WL2 can be exposed through the second shielding gate SG2.

[0364] exist Figure 18The diagram shows that each of the first shielding gate SG1 and the second shielding gate SG2 has a linear shape in a planar view; however, the planar shapes of the first shielding gate SG1 and the second shielding gate SG2 are not limited to this and can be varied.

[0365] and Figure 18 Unlike other embodiments, in some implementations, at least one of the first shielding gate SG1 and the second shielding gate SG2 may have an island shape in the plan view. For example, the first shielding gate SG1 may have an island shape in the plan view and may be partially located in the region of the back gate electrode BG that overlaps with the active patterns AP1 and AP2 in the second direction Y. As another example, the second shielding gate SG2 may have an island shape in the plan view and may be partially located in the region of the word lines WL1 and WL2 that overlaps with the active patterns AP1 and AP2 in the second direction Y.

[0366] Figure 19 The illustrated embodiments and Figure 2 The difference in the illustrated embodiment is that the shape of the second shielding gate SG2 is changed.

[0367] Reference Figure 19 and Figure 3 In this embodiment, the planar shapes of the word lines WL1 and WL2 that overlap with the second shielding gate SG2 can be determined according to... Figure 3 The word lines WL1 and WL2 in the embodiments shown have substantially the same planar shape.

[0368] In this embodiment, the shielding line portion SG2_B of the second shielding gate SG2 may have substantially the same shape as the gate line portions WL1_B and WL2_B of the individual word lines WL1 and WL2 that overlap with it in the third direction Z.

[0369] In this embodiment, in the plan view, the length of the shielding protrusion SG2_P of the second shielding gate SG2 in the second direction Y can be greater than the length of the gate protrusions WL1_P and WL2_P of each word line WL1 and WL2 in the second direction Y. In other words, in the plan view, the end of the shielding protrusion SG2_P of the second shielding gate SG2 can be positioned to protrude further than the gate protrusions WL1_P and WL2_P of each word line WL1 and WL2 in the second direction Y.

[0370] Therefore, in the plan view, the shielding protrusion SG2_P of the second shielding gate SG2 can be positioned closer to the side surface of the back gate electrode BG and the side surface of the first shielding gate SG1 than the gate protrusions WL1_P and WL2_P of each word line WL1 and WL2.

[0371] exist Figure 19 The diagram shows that the first shielding gate SG1 and the second shielding gate SG2 are positioned separately; however, the planar shapes of the first shielding gate SG1 and the second shielding gate SG2 are not limited to this and can be varied. For example, the first shielding gate SG1 and the second shielding gate SG2 can be formed integrally. For example, the first shielding gate SG1 and the second shielding gate SG2 can be formed integrally when the shielding protrusion SG2_P of the second shielding gate SG2 extends to the side surface of the first shielding gate SG1 in the second direction Y.

[0372] Figure 20 This is a cross-sectional view of a semiconductor device according to some embodiments.

[0373] according to Figure 20 The semiconductor device of the illustrated embodiment differs from the semiconductor device according to the above embodiment in that the stacking structure of the unit structure CS and the peripheral circuit structure PS, as well as the connection method of the unit structure CS and the peripheral circuit structure PS, are changed.

[0374] In this embodiment, the peripheral circuit structure PS can be located on the memory cell structure CS. In other words, the cell structure CS and the peripheral circuit structure PS can be stacked sequentially and positioned to overlap in the third direction Z.

[0375] Specifically, the substrate 100 may include a first surface 100_S1 and a second surface 100_S2 that are opposite to each other in the third direction Z. Here, the first surface 100_S1 may correspond to the lower surface of the substrate 100, and the second surface 100_S2 may correspond to the upper surface of the substrate 100.

[0376] The unit structure CS can be located on the first surface 100_S1 of the substrate 100, and the peripheral circuit structure PS can be located on the second surface 100_S2 of the substrate 100. Therefore, the unit structure CS, the substrate 100, and the peripheral circuit structure PS can be stacked sequentially.

[0377] In this embodiment, the peripheral circuit structure PS may include a first peripheral circuit insulating layer 213 and a second peripheral circuit insulating layer 215 sequentially stacked on the second surface 100_S2 of the substrate 100.

[0378] The peripheral circuit structure PS may include peripheral circuit PC, peripheral circuit contacts PCT1, PCT2 and PCT3, peripheral circuit wiring lines PCL1, PCL2 and PCL3, a first peripheral circuit insulation layer 213 and a second peripheral circuit insulation layer 215.

[0379] In this embodiment, the peripheral circuit PC may be located on the second surface 100_S2 of the substrate 100, and the first peripheral circuit insulating layer 213 may cover the peripheral circuit PC.

[0380] The first peripheral circuit contact PCT1, the second peripheral circuit contact PCT2, the first peripheral circuit wiring PCL1, the second peripheral circuit wiring PCL2, and the third peripheral circuit contact PCT3 may be located within the first peripheral circuit insulation layer 213. The third peripheral circuit wiring PCL3 may be located within the second peripheral circuit insulation layer 215.

[0381] The first peripheral circuit wiring line PCL1 can be connected to the peripheral circuit PC via the first peripheral circuit contact PCT1. The first peripheral circuit wiring line PCL1 and the second peripheral circuit wiring line PCL2 can be connected via the second peripheral circuit contact PCT2. The third peripheral circuit wiring line PCL3 can be connected to the second peripheral circuit wiring line PCL2 via the second peripheral circuit contact PCT2.

[0382] For example, the third peripheral circuit wiring line PCL3 can be an input / output pad used to connect a semiconductor device to an external device. However, this is just an example, and the function of the third peripheral circuit wiring line PCL3 can be varied.

[0383] The materials used for connecting the first peripheral circuit wiring lines to the third peripheral circuit wiring lines PCL1, PCL2 and PCL3 and the first peripheral circuit contact to the third peripheral circuit contact PCT1, PCT2 and PCT3 according to this embodiment are substantially the same as the materials contained in the peripheral circuit wiring lines PCL1 and PCL2 and / or the peripheral circuit contact PCT1 and PCT2 according to the above embodiment, and therefore will not be described further.

[0384] exist Figure 20 The diagram shows a peripheral circuit structure PS including first peripheral circuit wiring lines to third peripheral circuit wiring lines PCL1, PCL2 and PCL3 and first peripheral circuit contacts to third peripheral circuit contacts PCT1, PCT2 and PCT3 for connecting them; however, the number of peripheral circuit wiring lines and peripheral circuit contacts included in the peripheral circuit structure PS and / or their connection relationships can be varied.

[0385] In this embodiment, the unit structure CS may include a unit wiring insulation layer 240 covering the first unit insulation layer 177 and the shielding cover pattern 179, a first unit connection wiring line 233 and a second unit connection wiring line 235 located within the unit wiring insulation layer 240, and a unit connection wiring contact 231 connecting the first unit connection wiring line 233 and the second unit connection wiring line 235.

[0386] According to the semiconductor device based on this embodiment, one surface of the unit structure CS can be positioned as a first surface 100_S1 facing the substrate 100, and the other surface of the peripheral circuit structure PS can be positioned as a second surface 100_S2 facing the substrate 100.

[0387] Here, one surface of the cell structure CS can refer to the back surface of the cell structure CS, and the other surface of the peripheral circuit structure PS can refer to the back surface of the peripheral circuit structure PS. For example, the cell wiring insulating layer 240 can constitute one surface of the cell structure CS, and the first peripheral circuit insulating layer 213 can constitute the other surface of the peripheral circuit structure PS.

[0388] The first unit connection wiring line 233, the second unit connection wiring line 235, and the unit connection wiring contact 231 can be located within the unit wiring insulation layer 240. The first unit connection wiring line 233 can be connected to the second unit connection wiring line 235 through the unit connection wiring contact 231.

[0389] exist Figure 20 The diagram shows a second unit connection wiring line 235 connected to a bit line BL via a bit line contact 245; however, this disclosure is not limited thereto, and the second unit connection wiring line 235 may be connected to other components located in the unit structure CS.

[0390] The unit wiring insulation layer 240 may comprise an insulating material. For example, the unit wiring insulation layer 240 may comprise silicon oxide. The first unit connection wiring line 233, the second unit connection wiring line 235, and the unit connection wiring contact 231 may comprise the same material as the unit connection wiring contact 231 and unit connection wiring line 232 according to the above embodiment.

[0391] exist Figure 20 The diagram shows a unit structure CS including a first unit connection wiring line 233 and a second unit connection wiring line 235, as well as unit connection wiring contacts 231 connecting them; however, the number of unit wiring lines and unit contacts included in the unit structure CS and / or their connection relationships can be varied.

[0392] In addition, Figure 20 The diagram shows that the unit wiring insulation layer 240 is composed of a single layer; however, the present disclosure is not limited thereto, and the unit wiring insulation layer 240 may be composed of multiple layers containing the same material and / or different materials.

[0393] The semiconductor device according to this embodiment may further include a buffer layer 120 located between the substrate 100 and the unit structure CS, a through-hole 180 connecting the unit structure CS and the peripheral circuit structure PS, and a spacer 101 surrounding them.

[0394] The buffer layer 120 may be located between the first surface 100_S1 of the substrate 100 and one surface of the unit structure CS. The buffer layer 120 may contain an insulating material. For example, the insulating material may contain silicon oxide, but is not limited to this, and various modifications may be made.

[0395] In this embodiment, the unit structure CS and the peripheral circuit structure PS can be connected by a single through-hole 180 in a direct engagement manner.

[0396] The via 180 may extend from the peripheral circuit structure PS to the cell structure CS in the third direction Z. The via 180 may be a single via formed such that a portion is located in the cell structure CS and another portion is located in the peripheral circuit structure PS. In other words, the single via 180 may pass through the first peripheral circuit insulating layer 213, the substrate 100, the buffer layer 120, and the cell wiring insulating layer 240.

[0397] The through-hole 180 can connect cell connection wirings 233 and 235 in the cell structure CS, which are connected to multiple memory cells including memory transistors MT and cell capacitors DSP, to peripheral circuit wirings PCL1, PCL2, and PCL3 in the peripheral circuit structure PS, which are connected to peripheral circuits PC. For example, the through-hole 180 can connect a first cell connection wiring 233 in the cell structure CS and a second peripheral circuit wiring PCL2 in the peripheral circuit structure PS.

[0398] exist Figure 20 The diagram shows that one end of the through-hole 180 is connected to the first unit connection wiring line 233, and the other end is connected to the second peripheral circuit wiring line PCL2; however, the connection relationship between the through-hole 180, the unit structure CS, and the peripheral circuit structure PS is not limited to this, but can be changed in various ways.

[0399] Spacer 101 may be located inside substrate 100. Spacer 101 may be located between via 180 and substrate 100, and surround the side surface of via 180 that passes through substrate 100.

[0400] The through-hole component 180 may contain a conductive material. For example, the through-hole component 180 may contain the same conductive material as the conductive material of the first peripheral circuit contacts to the third peripheral circuit contacts PCT1, PCT2 and PCT3 described above.

[0401] Spacer 101 may contain an insulating material. For example, spacer 101 may contain silicon oxide. However, this disclosure is not limited thereto, and the materials contained in each of the through-hole 180 and spacer 101 may be varied.

[0402] and Figure 20 Unlike other embodiments, in some implementations, the cell structure CS and the peripheral circuit structure PS located on the cell structure CS can be joined and coupled using a hybrid copper bonding method, essentially the same as according to Figure 4 The same as that in the semiconductor device of the illustrated embodiment.

[0403] In addition, with Figure 20 In some embodiments, the peripheral circuit structure PS and the unit structure CS can be stacked sequentially on the substrate 100, and the peripheral circuit structure PS and the unit structure CS can be connected by a single through-hole in a direct bonding manner, which is essentially the same as in this embodiment.

[0404] Figure 20 The embodiments shown can have substantially the same effects as the semiconductor devices according to the embodiments described above.

[0405] Figure 21 This is a cross-sectional view of a semiconductor device according to some embodiments. Figure 22 yes Figure 21 A magnified view of region R1.

[0406] Specifically, Figure 21 This is a cross-sectional view showing a substrate 300 of a semiconductor device according to some embodiments and a unit structure CS located on the substrate 300. According to Figure 21 The semiconductor device in the illustrated embodiment may be vertically stacked DRAM (VSDRAM).

[0407] The semiconductor device according to an embodiment may include a plurality of memory cells arranged in three dimensions. The plurality of memory cells may include a memory transistor MT and a cell capacitor DSP. Each of the plurality of memory cells may be connected to a bit line BL and a word line WL. In this embodiment, the two word lines WL may share a back gate electrode BG.

[0408] The semiconductor device according to the embodiments may include a substrate 300 and a cell structure CS located on the substrate 300.

[0409] The cell structure CS may include a substrate 300, a bit line BL extending in a third direction Z perpendicular to the substrate 300, a plurality of active patterns AP connected to the bit line BL and extending in a first direction X parallel to the substrate 300, a pair of word lines WL located on both sides of the plurality of active patterns AP, a back gate electrode BG located between adjacent active patterns AP, a cell capacitor DSP connected to the plurality of active patterns AP, and a plurality of shielding gates SG located at a horizontal height between the word line WL and the cell capacitor DSP and / or at a horizontal height between the back gate electrode BG and the cell capacitor DSP.

[0410] exist Figure 21 The image shows a semiconductor device according to this embodiment including three memory cells that are commonly connected to a bit line BL and stacked on a third direction Z perpendicular to the substrate 300; however, this disclosure is not limited thereto.

[0411] In addition, Figure 21 The diagram illustrates that each stacked structure LS includes a memory cell; however, this disclosure is not limited thereto. For example, each stacked structure LS may also include a memory cell... Figure 21 The memory cell shown has a mirror-symmetric structure. For example, the semiconductor device according to some embodiments may further include... Figure 21 The stacked structure LS shown is a mirror-symmetric stacked structure located on substrate 300. Stacked structure LS and a stacked structure mirror-symmetric to stacked structure LS can form a pair.

[0412] Specifically, the substrate 300 can be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Multiple stacked structures LS can be sequentially stacked on the substrate 300. Each stacked structure LS can constitute a memory cell array of a semiconductor device.

[0413] Despite Figure 21 As shown in the figure, the semiconductor device according to this embodiment may further include a peripheral circuit structure (not shown in the figure), which includes peripheral circuitry for operating a memory cell array.

[0414] The peripheral circuit structure may include wiring electrically connected to the bit line BL and the word line WL, and the wiring may be connected to the peripheral circuit. The peripheral circuit structure may be located on or below the cell structure CS to overlap it in the third direction Z. For example, the cell structure CS and the peripheral circuit structure may be joined and coupled by a hybrid copper bonding method substantially the same as that used in the semiconductor device according to the above embodiments. However, the joining method between the cell structure CS and the peripheral circuit structure is not limited to this. For example, the cell structure CS and the peripheral circuit structure may be connected by a single through-hole in a direct bonding manner, substantially similar to that according to the above embodiments. Figure 20 The semiconductor device of the illustrated embodiment.

[0415] Reference Figure 21 and Figure 22 A bit line BL can be provided on one side of the multiple stacked structures LS. The bit line BL can extend in a third direction Z perpendicular to the substrate 300. The bit line BL can be linear or cylindrical in the third direction Z.

[0416] Each of the multiple stacked structures LS may include an active pattern AP, a pair of word lines WL located on both sides of the active pattern AP in the third direction Z, and a unit capacitor DSP connected to the active pattern AP. The pair of word lines WL may be located on both sides of the active pattern AP in the third direction Z.

[0417] The active pattern AP can extend in a first direction X that is perpendicular to the extension direction of the bit line BL. In other words, the active pattern AP can extend in a first direction X that is parallel to the substrate 300.

[0418] The active patterned AP may include a first doped region SDR1 connected to the bit line BL, a second doped region SDR2 connected to the unit capacitor DSP, and a channel region CHR located between the first doped region SDR1 and the second doped region SDR2. The second doped region SDR2 of the active patterned AP may be connected to the first electrode 351 of the unit capacitor DSP, which will be described below.

[0419] The first dopant region SDR1 and the second dopant region SDR2 of each of the active patterns AP1 and AP2 can correspond to the first source / drain and the second source / drain of the memory transistor MT, and the channel region CHR can correspond to the channel of the memory transistor MT.

[0420] Reference Figure 7 The above description of the active patterned AP can also be applied substantially equivalently to the active patterned AP according to this embodiment, and therefore will not be described in detail.

[0421] The semiconductor device according to this embodiment may further include an interlayer insulating layer 330 located between adjacent stacked structures LS.

[0422] The word line WL, active pattern AP, back gate electrode BG, and unit capacitor DSP included in each stacked structure LS can be located on the interlayer insulating layer 330. The interlayer insulating layer 330 can be located between the substrate 300 and the stacked structure LS located at the bottom.

[0423] The interlayer insulating layer 330 may contain at least one of, for example, silicon nitride, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, or silicon oxynitride containing carbon.

[0424] Multiple word lines WL can extend in a first direction X that is perpendicular to the extension direction of the bit line BL. Multiple word lines WL can also extend in a first direction X that is parallel to the upper surface of the substrate 300.

[0425] The stacked structure LS may include two word lines WL. The stacked structure LS may include a first word line WL1 and a second word line WL2 spaced apart in the third direction Z. Two active patterns AP may be set between the first word line WL1 and the second word line WL2 spaced apart in the third direction Z.

[0426] Each word line WL can be positioned as a channel region CHR corresponding to an active pattern AP. The first word line WL1 can be located on one side of the channel region CHR of any of the multiple active pattern APs positioned adjacent to each other in the third direction Z, and the second word line WL2 can be located on the other side of the channel region CHR of another of the multiple active pattern APs positioned adjacent to each other in the third direction Z.

[0427] The materials contained in the bit line BL and word line WL according to this embodiment are the same as those included in the bit line BL and word line in the semiconductor device according to the above embodiment (see...). Figure 4 The materials contained in the attached figures (“WL1” and “WL2”) are essentially the same and will not be described in detail.

[0428] The semiconductor device according to this embodiment may further include a gate capping pattern 323 located between the bit line BL and the word line WL, and a gate insulating pattern GOX surrounding the side surface of the word line WL and the gate capping pattern 323.

[0429] The gate cap pattern 323 may include an insulating material and insulate the bit line BL and word line WL from each other. For example, the gate cap pattern 323 may include silicon oxide, silicon nitride, or a combination thereof.

[0430] The gate insulating pattern GOX can cover the side surfaces of the gate cap pattern 323 and the word line WL to conform to them.

[0431] The material contained in the gate insulating pattern GOX according to this embodiment is substantially the same as the material contained in the gate insulating pattern GOX included in the semiconductor device according to the above embodiment, and therefore will not be described in detail.

[0432] The stacked structure LS may include a back gate electrode BG. The back gate electrode BG may be located between a first word line WL1 and a second word line WL2. The back gate electrode BG may be located between active patterns AP that are adjacent to each other in the third direction Z. The back gate electrode BG may be positioned to correspond to the channel region CHR of the active pattern AP.

[0433] On one side of the active pattern AP in the third direction Z, a word line WL can be set, and on the other side of the active pattern AP in the third direction Z, a back gate electrode BG can be set. On the two sides of the active pattern AP facing each other in the third direction Z, a word line WL and a back gate electrode BG can be set respectively.

[0434] The material contained in the back gate electrode BG according to this embodiment is substantially the same as the material contained in the back gate electrode BG included in the semiconductor device according to the above embodiment, and will not be described in detail.

[0435] Furthermore, in this embodiment, regarding the arrangement relationship between the word line WL and the back gate electrode BG, and regarding the word line according to the above embodiment (see...), Figure 7 The arrangement of the reference numerals “WL1” and “WL2” in the accompanying drawings and the back gate electrode BG can be applied substantially equivalently, therefore, they will not be described in detail.

[0436] The semiconductor device according to this embodiment may further include a back gate capping pattern 313 located between the bit line BL and the back gate electrode BG, and a back gate insulating pattern 311 surrounding the side surface of the back gate electrode BG and the back gate capping pattern 313.

[0437] The back gate cover pattern 313 may include insulating material and insulate the bit line BL and the back gate electrode BG from each other. The back gate insulation pattern 311 may cover the side surfaces of the back gate cover pattern 313 and the back gate electrode BG to conform to them.

[0438] The back gate insulating pattern 311 and the back gate capping pattern 313 may comprise silicon oxide, silicon nitride, or a combination thereof. However, this disclosure is not limited thereto.

[0439] Multiple shielded gates SG can be located between the word line WL and the cell capacitor DSP, and between the back gate electrode BG and the cell capacitor DSP.

[0440] In this embodiment, the shielding gate SG can overlap with the second doped region SDR2 of at least one of the plurality of active patterns AP in the third direction Z, which is the vertical direction. For example, the shielding gate SG can be positioned to overlap with the second doped region SDR2 of each of the plurality of active patterns AP in the third direction Z, which is the extension direction of the bit line BL. In other words, the shielding gate SG can be positioned to overlap with a portion of the active pattern AP in the third direction Z, which is the extension direction of the bit line BL.

[0441] The plurality of shielding gates SG may include a plurality of first shielding gates SG1 located on the back gate electrode BG and a second shielding gate SG2 located on the word line WL. In other words, the first shielding gates SG1 may be located between the back gate electrode BG and the cell capacitor DSP, and the second shielding gates SG2 may be located between the word line WL and the cell capacitor DSP.

[0442] exist Figure 22 The diagram shows multiple shielded gates SG located between the back gate electrode BG and the cell capacitor DSP, and between the word line WL and the cell capacitor DSP, respectively. However, the arrangement of the multiple shielded gates SG is not limited to this and can be varied. Although not shown in the figure, it can be, for example, arranged according to... Figure 8 and Figure 9 The shielding gates SG in the embodiments shown are arranged in a basically the same manner.

[0443] A back gate insulating pattern 311 may be provided between the first shielding gate SG1 and the back gate electrode BG, and a gate insulating pattern GOX may be provided between the second shielding gate SG2 and the word line WL.

[0444] Each first shielding gate SG1 can be positioned to overlap with the back gate electrode BG in the first direction X, and the second shielding gate SG2 can be positioned to overlap with the word line WL in the first direction X.

[0445] Each first shielding gate SG1 may extend along a first direction X between the back gate electrode BG and the cell capacitor DSP, and the second shielding gate SG2 may extend along the first direction X between the word line WL and the cell capacitor DSP.

[0446] Multiple shielding gates SG can be located between active patterns AP that are adjacent to each other in the third direction Z. The length of each shielding gate SG in the first direction X can be less than the lengths of active patterns AP1 and AP2 in the first direction X.

[0447] The length of the shielding gate SG in the first direction X can be less than the length of the second doped region SDR2 in the first direction X. Therefore, the shielding gate SG can overlap with a portion of the second doped region SDR2 in the third direction Z.

[0448] In addition, the materials, arrangement, width, and thickness relationships of the multiple shielding gates SG, as well as the voltage applied to the multiple shielding gates SG, can be essentially applied using the reference. Figures 7 to 15 The above-described content will therefore not be described in detail.

[0449] The semiconductor device according to this embodiment may further include a first shielding pad pattern 314 and a first shielding isolation pattern 315 located between the back gate electrode BG and the first shielding gate SG1, a first shielding cap pattern 317 located between the first shielding gate SG1 and the unit capacitor DSP, a second shielding pad pattern 324 and a second shielding isolation pattern 325 located between the word line WL and the second shielding gate SG2, and a second shielding cap pattern 327 located between the second shielding gate SG2 and the unit capacitor DSP.

[0450] The first shielding pad pattern 314 may be located between the first shielding gate SG1 and the second doped region SDR2 of the active pattern AP, between the first shielding isolation pattern 315 and the second doped region SDR2 of the active pattern AP, and between the back gate insulating pattern 311 and the first shielding isolation pattern 315. The first shielding pad pattern 314 may extend along the surfaces of the first shielding gate SG1 and the first shielding isolation pattern 315 to conform to them.

[0451] The second shielding pad pattern 324 may be located between the second shielding gate SG2 and the second doped region SDR2 of the active pattern AP, between the second shielding isolation pattern 325 and the second doped region SDR2 of the active pattern AP, and between the gate insulating pattern GOX and the second shielding isolation pattern 325. The second shielding pad pattern 324 may extend along the surfaces of the second shielding gate SG2 and the second shielding isolation pattern 325 to conform to them.

[0452] The first shielding isolation pattern 315 may be located between the first shielding gate SG1 and the first shielding pad pattern 314 that is in contact with the back gate insulating pattern 311, and the second shielding isolation pattern 325 may be located between the second shielding gate SG2 and the second shielding pad pattern 324 that is in contact with the gate insulating pattern GOX.

[0453] The first shielding cover pattern 317 may be located between the first shielding pad pattern 314 and the unit capacitor DSP, and between the first shielding gate SG1 and the unit capacitor DSP. The second shielding cover pattern 327 may be located between the second shielding pad pattern 324 and the unit capacitor DSP, and between the second shielding gate SG2 and the unit capacitor DSP.

[0454] The first shielding gasket pattern 314, the first shielding isolation pattern 315, the first shielding cover pattern 317, the second shielding gasket pattern 324, the second shielding isolation pattern 325, and the second shielding cover pattern 327 may contain an insulating material. For example, the insulating material may contain silicon oxide, silicon nitride, or a combination thereof. However, the insulating material is not limited to this and can be varied.

[0455] The unit capacitor DSP may include a first electrode 351, a second electrode 355, and a dielectric layer 353 inserted between the first electrode 351 and the second electrode 355.

[0456] Regarding the first electrode included in the unit capacitor DSP according to the above embodiments (see...) Figure 4 (See attached figure "251"), second electrode (see) Figure 4 (see attached figure "252") and dielectric layer (see figure) Figure 4 The contents of reference numeral "253" in the accompanying drawings can also be applied substantially equivalently to the first electrode 351, the second electrode 355, and the dielectric layer 353 included in the unit capacitor DSP according to this embodiment, and therefore will not be described in detail.

[0457] The semiconductor device according to this embodiment may further include a first capacitor isolation pattern 341 and a second capacitor isolation pattern 343 located between the first electrodes 351 of the unit capacitor DSP.

[0458] The first capacitor isolation pattern 341 and the second capacitor isolation pattern 343 may be located between the first electrodes 351 of the unit capacitor DSP and stacked alternately along the third direction Z.

[0459] The first capacitor isolation pattern 341 can extend from the interlayer insulating layer 330 along the first direction X, and the second capacitor isolation pattern 343 can extend from the first shielding cover pattern 317 along the first direction X. The first electrode 351 of each unit capacitor DSP can be isolated and insulated by the first capacitor isolation pattern 341 and the second capacitor isolation pattern 343.

[0460] The first capacitor isolation pattern 341 and the second capacitor isolation pattern 343 may comprise an insulating material such as silicon oxide. However, this disclosure is not limited thereto.

[0461] like Figure 22 As shown, the first shielding gate SG1 may have a first thickness T1, the second shielding gate SG2 may have a second thickness T2, the first shielding isolation pattern 315 may have a third thickness T3, and the second shielding isolation pattern 325 may have a fourth thickness T4.

[0462] Here, the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 can refer to the thickness in the first direction X. In other words, the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 can refer to the thickness of the first shielding gate SG1, the second shielding gate SG2, the first shielding isolation pattern 315, and the second shielding isolation pattern 325 in their extension directions, respectively.

[0463] In this embodiment, the first thickness T1 can be substantially the same as the second thickness T2, and the third thickness T3 can be substantially the same as the fourth thickness T4. Furthermore, the first thickness T1 can be greater than the third thickness T3, and the second thickness T2 can be greater than the fourth thickness T4. However, the relationship between the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 can be varied.

[0464] For example, with Figure 22 In some embodiments, the relationship between the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 differs from that in others. Figures 12 to 14 The relationships between the first thickness T1, the second thickness T2, the third thickness T3, and the fourth thickness T4 in the illustrated embodiment can be applied substantially equivalently. Therefore, the arrangement relationships of the first shielding gate SG1, the second shielding gate SG2, the first shielding isolation pattern 315, and the second shielding isolation pattern 325, etc., can be varied.

[0465] In this embodiment, the first shielding gate SG1 may have a first width W1, and the second shielding gate SG2 may have a second width W2. Here, the first width W1 and the second width W2 may refer to the width in the third direction Z.

[0466] In this embodiment, the first width W1 can be greater than the second width W2. Furthermore, the first width W1 can be substantially the same as the width of the back gate electrode BG in the third direction Z, and the second width W2 can be substantially the same as the width of the word line WL in the third direction Z. However, the relationship between the first width W1 and the second width W2, the relationship between the first width W1 and the width of the back gate electrode BG, and the relationship between the second width W2 and the width of the word line WL are not limited to these and can be varied. For example, the first width W1 can be substantially the same as the second width W2.

[0467] Although not shown in the accompanying drawings, as another example, the relationship between the first width W1 and the second width W2 can be substantially equivalently applied according to... Figure 10 and 11 The embodiment shown describes the relationship between the first width W1 and the second width W2.

[0468] Therefore, the arrangement of the shielding gate SG, the back gate electrode BG, and the word line WL, as well as the shape and arrangement of the shielding gate SG, can be changed in various ways.

[0469] Because a shielding gate SG is formed between the doped regions of the active pattern AP connected to the unit capacitor DSP, according to Figure 22 The semiconductor device of the illustrated embodiment may have substantially the same effects as the semiconductor device according to the above embodiment.

[0470] Figure 23 and Figure 24 This is a cross-sectional view illustrating a semiconductor device according to some embodiments. Specifically, Figure 23 and Figure 24 This illustrates the correspondence according to some embodiments. Figure 21 A magnified view of regions R1, R2, and R3.

[0471] according to Figure 23 The semiconductor device of the embodiment shown, and Figure 22 The embodiments shown are different, and the back gate electrode BG, back gate insulation pattern 311 and back gate cap pattern 313 may be omitted, and may further include isolation insulation pattern 350 located between adjacent active patterns AP.

[0472] Specifically, refer to Figure 23 In any of the plurality of active pattern APs, a first word line WL1 can be provided on one side of the third direction Z, and an isolation insulating pattern 350 can be provided on the other side of the third direction Z. Furthermore, in another of the plurality of active pattern APs, an isolation insulating pattern 150 can be provided on one side of the third direction Z, and a second word line WL2 can be provided on the other side of the third direction Z. In other words, according to this embodiment, the word line WL can be located only on one side or the other side of the active pattern AP.

[0473] In this embodiment, the first shielding gate SG1 can be positioned to overlap with the isolation insulating pattern 350 in the first direction X. The second shielding gate SG2 can be positioned to overlap with the word line WL in the first direction X. Although Figure 23 Not shown in the diagram, but the first shielding gate SG1 may be located between the isolation insulating pattern 350 and the unit capacitor (see [reference]). Figure 21 The second shielding gate SG2 can be located between the word line WL and the cell capacitor DSP (as indicated in the attached figure).

[0474] The insulating pattern 350 may include insulating material. For example, the insulating material may include silicon oxide, silicon nitride, silicon oxynitride, etc., but is not limited to these, and can be modified in various ways.

[0475] In addition, regarding the shielding gate SG according to this embodiment, the method according to [the specific embodiment] can be applied substantially equivalently. Figure 16 The contents of the shielding gate SG in the illustrated embodiment will therefore not be described in detail.

[0476] according to Figure 24 The semiconductor device shown in the embodiment is Figure 22The difference in the embodiment shown is that the back gate electrode BG, back gate insulating pattern 311, back gate cap pattern 313, first shielding pad pattern 314, first shielding isolation pattern 315, first shielding gate SG1 and first shielding cap pattern 317 located between adjacent active patterns AP are omitted, and a first word line WL1 and a second word line WL2 are also included between adjacent active patterns AP.

[0477] According to this embodiment, a stacked structure (see...) Figure 22 The reference numeral "LS" in the attached diagram may include four word lines WL.

[0478] Specifically, in a stacked structure LS, a first word line WL1 can be set on one side of the third direction Z of any one of the multiple active pattern APs. A second word line WL2 can be set on the other side of the third direction Z. Furthermore, in another of the multiple active pattern APs, a first word line WL1 can be set on one side of the third direction Z, and a second word line WL2 can be set on the other side of the third direction Z.

[0479] Therefore, word lines WL can be set on both sides of the third direction Z of each of the multiple active pattern APs. In other words, word lines WL can be set on two side surfaces of the multiple active pattern APs that face each other in the third direction Z.

[0480] The semiconductor device according to the embodiment may further include a word line isolation pattern 360, which is located between a plurality of word lines WL and insulates and isolates them.

[0481] The word line isolation pattern 360 can be located between adjacent word lines WL on the third direction Z, and isolate and insulate them. For example, the word line isolation pattern 360 can be located between a first word line WL1 on one side of the third direction Z of any of the plurality of active patterns AP and a second word line WL2 on the other side of the third direction Z of another of the plurality of active patterns AP.

[0482] The word line isolation pattern 360 may include at least one of silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbon nitride, or silicon carbon oxynitride.

[0483] In this embodiment, multiple shielded gates SG can be positioned to connect to multiple word lines WL in a first direction X. Although in Figure 24 Not shown in the diagram, but multiple shielded gates SG can be positioned between the word line WL and the cell capacitor (see [reference]). Figure 21 (The attached figure is labeled "DSP").

[0484] exist Figure 24The diagram shows that two side surfaces of the side surface of each of a plurality of active patterns AP overlap with the word line WL; however, the arrangement relationship between each active pattern AP and the word line WL is not limited to this and can be varied.

[0485] and Figure 24 In some embodiments, word lines WL can surround all side surfaces of each of the plurality of active patterns AP. For example, word lines WL1 and WL2 can be integrally formed and have a ring gate (GAA) structure surrounding the four side surfaces of each of the plurality of active patterns AP.

[0486] When word lines WL1 and WL2 are integrally formed as described above and have a structure surrounding all side surfaces of each active pattern AP, the shielding isolation pattern 140 located on the first word line WL1 and the second word line WL2 can be integrally formed and have a structure surrounding all side surfaces of each active pattern AP.

[0487] Furthermore, when word lines WL1 and WL2 are integrally formed as described above and have a structure surrounding all side surfaces of each active pattern AP, the shielding gate SG located on the first word line WL1 and the second word line WL2 respectively can be integrally formed and have a structure surrounding all side surfaces of each active pattern AP.

[0488] according to Figure 23 The semiconductor device of the illustrated embodiment may have the same characteristics as according to... Figure 16 The semiconductor devices in the illustrated embodiments have essentially the same effect, and according to Figure 24 The semiconductor device of the illustrated embodiment may have the same characteristics as according to... Figure 17 The semiconductor devices in the illustrated embodiments have essentially the same effect.

[0489] The following will refer to Figures 25 to 33 A method for manufacturing a semiconductor device is described. Hereinafter, components identical to those described above will be indicated by the same reference numerals, and will be described only briefly or without unnecessary detail; the main focus will be on their differences from the components described above.

[0490] Figures 25 to 33 This is a cross-sectional view used to explain the method of manufacturing a semiconductor device according to an embodiment.

[0491] Specifically, Figures 25 to 33 This is used to illustrate the various manufacturing process steps in the method for manufacturing a semiconductor device according to the embodiments. Figure 1 The cross-sectional view taken from line C-C'.

[0492] First, refer to Figure 25A buried insulating layer 201 and an active layer 202 can be formed on the sub-substrate 200. The sub-substrate 200, the buried insulating layer 201, and the active layer 202 can be silicon-on-insulator (SOI) substrates.

[0493] The buried insulating layer 201 can be, for example, a buried oxide (BOX) formed by an oxygen implantation isolation (SIMOX) method or a bonding and layer transfer method. As another example, the buried insulating layer 201 can be an insulating layer formed by a chemical vapor deposition method.

[0494] The buried insulating layer 201 may contain, for example, silicon oxide, silicon nitride, silicon oxynitride and / or a low dielectric constant material.

[0495] The active layer 202 can be a single-crystal semiconductor layer. The active layer 202 can be, for example, a single-crystal silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0496] Subsequently, a mask pattern MP can be formed on the active layer 202.

[0497] The mask pattern MP may include a first mask pattern 11 and a second mask pattern 12 stacked in sequence. The second mask pattern 12 may contain a material that is etch-selective to the first mask pattern 11. For example, the first mask pattern 11 may contain silicon oxide and the second mask pattern 12 may contain silicon nitride; however, this disclosure is not limited thereto.

[0498] Subsequently, a component isolation layer (STI) can be formed inside the active layer 202. The component isolation layer STI can be formed inside the active layer 202 in the peripheral circuit area (see [link]). Figure 5 (The attached figure is labeled "PAR").

[0499] A component isolation layer (STI) can be formed by patterning the active layer 202 to create a component isolation trench to expose the buried insulating layer 201, and then filling the component isolation trench with insulating material. When forming the component isolation layer STI, a cell array region can be defined (see...). Figure 5 (The attached image is labeled "CAR").

[0500] Subsequently, the first back gate insulation pattern 111, the back gate electrode BG, the first shielding isolation pattern 113, the first shielding gate SG1, and the first shielding cap pattern 115 can be formed sequentially.

[0501] Specifically, after forming the back gate trench BG_T by removing some portions of the active layer 202 and the mask pattern MP, a first back gate insulation pattern 111 can be formed on the bottom and side surfaces of the back gate trench BG_T.

[0502] Subsequently, the back gate electrode BG can be formed by filling the back gate trench BG_T with the conductive material used to form the back gate electrode BG, and then performing an etchback on a portion of the conductive material. The back gate electrode BG can fill a portion of the back gate trench BG_T.

[0503] Subsequently, the first shielding isolation pattern 113 can be formed on the back gate electrode BG by filling the back gate trench BG_T with the insulating material used to form the first shielding isolation pattern 113 and then performing an etchback on a portion of the insulating material. The first shielding isolation pattern 113 can fill a portion of the back gate trench BG_T left after the formation of the back gate electrode BG.

[0504] Subsequently, the first shielding gate SG1 can be formed on the first shielding isolation pattern 113 by filling the back gate trench BG_T with the conductive material used to form the first shielding gate SG1 and then performing back etch on a portion of the conductive material.

[0505] The thickness of the first shielding gate SG1 in the third direction Z can be less than the thickness of the back gate electrode BG in the third direction Z. The first shielding gate SG1 can fill a portion of the back gate trench BG_T left after forming the first shielding isolation pattern 113.

[0506] Subsequently, the first shielding cover pattern 115 can be formed on the first shielding gate SG1 by filling the back gate trench BG_T with insulating material used to form the first shielding cover pattern 115, and then removing a portion of the insulating material by performing an etch-back process or a planarization process.

[0507] The first shielding capping pattern 115 can fill the remaining portion of the back gate trench BG_T left after the formation of the first shielding gate SG1. The upper surface of the first shielding capping pattern 115 can be substantially at the same horizontal level as the upper surfaces of the mask pattern MP and the component isolation layer STI.

[0508] In some embodiments, prior to forming the first back gate insulation pattern 111, the active layer 202 exposed by the back gate trench BG_T can be doped with impurities by performing a gas phase doping (GPD) process or a plasma doping (PLAD) process.

[0509] Subsequently, referring to Figure 26 as well as Figure 25 By removing some portions of the mask pattern MP, a pair of spacer patterns 121 can be formed on the two side surfaces of the first shielding cover pattern 115 located inside the back gate trench BG_T.

[0510] Specifically, the second mask pattern 12 of the mask pattern MP can be removed, thereby exposing the first mask pattern 11. Therefore, the first shielding cover pattern 115 can have a shape that protrudes from the upper surface of the first mask pattern 11.

[0511] Subsequently, a spacer film (not shown) can be formed along the upper surface of the first mask pattern 11, the side surface of the first back gate insulation pattern 111, and the upper surface of the first shielding cap pattern 115. The spacer film can then be patterned to form the spacer pattern 121. The width of the active pattern can be determined based on the deposition thickness of the spacer film (see...). Figure 27 (See the attached figures labeled "AP1" and "AP2").

[0512] The spacer film may contain an insulating material. The spacer film may contain at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), and silicon carbonitride (SiCN).

[0513] Subsequently, referring to Figure 27 as well as Figure 26 A pair of first active patterns AP1 and second active patterns AP2 can be formed by patterning the active layer 202.

[0514] Specifically, the spacer pattern 121 can be used as an etching mask to pattern the active layer 202. The step of patterning the active layer 202 may include, for example, performing an anisotropic etching process on the active layer 202.

[0515] When the active layer 202 is patterned, a pair of first active patterns AP1 and second active patterns AP2 can be formed on both sides of the back gate electrode BG. The first active patterns AP1 and second active patterns AP2 can be formed on the side surface of the first back gate insulating pattern 111.

[0516] In the process steps of forming the first active pattern AP1 and the second active pattern AP2, when the active layer 202 is removed, the buried insulating layer 201 can be exposed. Although Figure 27 Not shown, but in some embodiments, some portions of the patterned active layer 202 may remain on the side surface of the element isolation layer STI.

[0517] The first active pattern AP1 and the second active pattern AP2, which are adjacent to each other, can define the word line trench WL_T. In other words, the word line trench WL_T can be formed between the first active pattern AP1 and the second active pattern AP2, which are adjacent to each other. The bottom surface of the word line trench WL_T can be defined by the buried insulating layer 201, and the two sidewalls of the word line trench WL_T can be defined by the first active pattern AP1 and the second active pattern AP2.

[0518] Subsequently, referring to Figure 28 and Figure 27 The gate insulating pattern GOX and the word line conductive film PWL for forming word lines can be formed sequentially (see [link]). Figure 31 (See the attached figures labeled "WL1" and "WL2").

[0519] The gate insulating pattern GOX can be formed conformally along the bottom surface and sidewalls of the word line trench WL_T. The gate insulating pattern GOX can be formed conformally along the side surfaces of the first active pattern AP1 and the second active pattern AP2, the top surface of the first back gate insulating pattern 111, the top surface of the first shielding cap pattern 115, the top surface of each spacer pattern 121, and the top surface of the buried insulating layer 201.

[0520] The gate insulating pattern GOX can be formed using at least one of the following methods: chemical oxidation, thermal oxidation, UV oxidation, dual plasma oxidation, physical vapor deposition (PVD), thermochemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD). However, this disclosure is not limited thereto, and the method for forming the gate insulating pattern GOX can be modified in various ways.

[0521] The word line conductive film (PWL) can be formed conformally along the surface of the gate insulating pattern (GOX). The word line conductive film (PWL) can also be formed conformally along the bottom surface and sidewalls of the word line trenches (WL_T).

[0522] The word line conductive film (PWL) may contain a conductive material. For example, the word line conductive film may contain at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, and metal.

[0523] Subsequently, a gate isolation pattern 141 can be formed on the word line conductive film PWL, and then some portions of the word line conductive film PWL can be removed.

[0524] Specifically, the gate isolation pattern 141 can be formed to completely cover the word line conductive film PWL and fill the word line trench WL_T.

[0525] Subsequently, a portion of the gate isolation pattern 141 covering the word line conductive film PWL can be removed, thereby exposing a portion of the word line conductive film PWL. During the process step of removing a portion of the gate isolation pattern 141, a portion of the gate insulating pattern GOX can be exposed.

[0526] Next, an etching process can be performed on the exposed word line conductive film PWL.

[0527] For example, the etching process for the word line conductive film PWL can be a dry etching process.

[0528] An etching process can be performed on the word line conductive film (PWL) until the upper surface of the word line conductive film PWL is substantially at the same horizontal height as the upper surface of the back gate electrode (BG), or at a higher horizontal height than the upper surface of the back gate electrode (BG). However, the invention is not limited thereto, and the horizontal height of the upper surface of the word line conductive film PWL can vary in various ways during the etching process.

[0529] When a portion of the word line conductive film PWL is removed, the remaining word line conductive film PWL may have a generally U-shaped cross-section within the word line trench WL_T. In other words, the removed word line conductive film PWL may be positioned along the bottom surface and sidewalls of the word line trench WL_T and cover a portion of the bottom surface and adjacent side surface of the gate isolation pattern 141.

[0530] like Figure 28 As shown, when the word line conductive film PWL is etched, the upper surface of the word line conductive film PWL can be located at a lower horizontal height than the upper surface of the gate isolation pattern 141.

[0531] Subsequently, referring to Figure 29 Together Figure 28 The second shielding isolation pattern 143 and the second shielding gate SG2 can be sequentially formed on the word line conductive film PWL.

[0532] Specifically, an insulating material for forming the second shielding isolation pattern 143 can be formed to fill the area between the gate isolation pattern 141 and the gate insulating pattern GOX located inside the word line trench WL_T. Then, the second shielding isolation pattern 143 can be formed on the word line conductive film PWL by performing etch-back on a portion of the insulating material.

[0533] In the process step of removing a portion of the second shielding isolation pattern 143, a portion of the gate isolation pattern 141 may also be removed. However, this disclosure is not limited thereto. When the second shielding isolation pattern 143 has high etch selectivity to the gate isolation pattern 141, a portion of the gate isolation pattern 141 may not be removed in the process step of removing a portion of the second shielding isolation pattern 143.

[0534] The second shielding isolation pattern 143 can fill the portion between the gate isolation pattern 141 and the gate insulating pattern GOX left after the word line conductive film PWL is formed.

[0535] The second shielding isolation pattern 143 may be located at a horizontal height substantially the same as that of the first shielding isolation pattern 113 located on the back gate electrode BG. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding isolation pattern 113 and the second shielding isolation pattern 143 may be varied during the process steps of forming the second shielding isolation pattern 143.

[0536] Subsequently, a conductive material for forming the second shielding gate SG2 can be formed to fill the area between the gate isolation pattern 141 and the gate insulation pattern GOX located inside the word line trench WL_T. Then, a portion of the conductive material can be removed so that the second shielding gate SG2 is formed on the second shielding isolation pattern 143.

[0537] The second shielding gate SG2 may fill a portion of the area between the gate insulation pattern GOX and the gate isolation pattern 141 left after the formation of the second shielding isolation pattern 143.

[0538] The second shielding gate SG2 may be located at a horizontal height substantially the same as that of the first shielding gate SG1 located on the back gate electrode BG. However, this disclosure is not limited thereto, and the arrangement relationship between the first shielding gate SG1 and the second shielding gate SG2 may be varied during the process steps of forming the second shielding gate SG2.

[0539] In some embodiments, any one of the process steps for forming the first shielding isolation pattern 113 and the first shielding gate SG1, and the process steps for forming the second shielding isolation pattern 143 and the second shielding gate SG2, may be omitted.

[0540] Subsequently, referring to Figure 30 A second shielding cover pattern 145 can be formed to cover the second shielding gate SG2 and the gate isolation pattern 141.

[0541] Specifically, the second shielding cover pattern 145 can be formed to completely cover the upper surface and side surface of the second shielding gate SG2 and the gate isolation pattern 141 adjacent to the second shielding gate SG2.

[0542] The second shielding cover pattern 145 can fill the word line trench left after forming the word line conductive film PWL, the second shielding isolation pattern 143, and the second shielding gate SG2 (see...). Figure 28 (The attached figure is labeled "WL_T").

[0543] Subsequently, after forming the second shielding cover pattern 145, a planarization process step can be performed. In the planarization process step, the first mask pattern 11 and each spacer pattern 121 located on the first active pattern AP1 and the second active pattern AP2 can be removed, so that the upper surfaces of the first active pattern AP1 and the second active pattern AP2 are exposed.

[0544] In addition, during the planarization process, a portion of the first back gate insulation pattern 111, a portion of the first shielding cover pattern 115, a portion of the gate insulation pattern GOX, a portion of the first active pattern AP1, a portion of the second active pattern AP2, a portion of the second shielding cover pattern 145, and a portion of the component isolation layer STI can be removed together.

[0545] Therefore, the upper surface of the first back gate insulating pattern 111, the upper surface of the first shielding cover pattern 115, the upper surface of the gate insulating pattern GOX, the upper surfaces of the first active pattern AP1 and the second active pattern AP2, the second shielding cover pattern 145, and the upper surface of the element isolation layer STI can be substantially planarized.

[0546] Subsequently, referring to Figure 31 On the upper surface of the first back gate insulating pattern 111, the upper surface of the first shielding cover pattern 115, the upper surface of the gate insulating pattern GOX, the upper surface of the first active pattern AP1 and the second active pattern AP2, the second shielding cover pattern 145 and the upper surface of the element isolation layer STI, a contact interlayer insulating layer 271 including contact holes for exposing the first active pattern AP1 and the second active pattern AP2 can be formed.

[0547] Subsequently, multiple buried contacts BC can be formed inside the contact holes of the interlayer insulation layer 271. The multiple buried contacts BC can be formed on the first active pattern AP1 and the second active pattern AP2.

[0548] Subsequently, a pad isolation insulation layer 273, including pad holes, can be formed on the interlayer insulation layer 271. Then, multiple landing pads LP can be formed within the pad holes of the pad isolation insulation layer 273. The multiple landing pads LP can be formed on multiple buried contacts BC.

[0549] Subsequently, a contact etch stop layer 275 can be formed on the pad isolation insulating layer 273. Then, a first electrode 251, a dielectric film 253 covering the first electrode 251 and connected to multiple landing pads LP, can be sequentially formed through the contact etch stop layer 275 and connected to multiple landing pads LP. The first electrode 251, the dielectric film 253 and the second electrode 255 can constitute a unit capacitor DSP.

[0550] Subsequently, a third unit insulating layer 277 can be formed to completely cover the unit capacitor DSP.

[0551] Subsequently, referring to Figure 32 as well as Figure 31 A post-surface polishing step to remove the sub-substrate 200 can be performed. Removing the sub-substrate 200 may include sequentially performing polishing and etching processes to expose the buried insulating layer 201.

[0552] Subsequently, the buried insulating layer 201 can be removed. When the buried insulating layer 201 is removed, the first active pattern AP1 and the second active pattern AP2, the gate insulating pattern GOX, and the first back gate insulating pattern 111 can be exposed.

[0553] Subsequently, the exposed gate insulating pattern GOX and the first back gate insulating pattern 111 can be removed. This exposes the back gate electrode BG and the word line conductive film PWL.

[0554] Subsequently, a portion of the back gate electrode BG can be removed by performing an etch-back process, and then a second back gate insulation pattern 117 can be formed on the back gate electrode BG.

[0555] Furthermore, a pair of first word lines WL1 and second word lines WL2 can be formed on both sides of the gate isolation pattern 141 by performing an etch-back process or a patterning process for removing a portion of the word line conductive film PWL. Then, a gate capping pattern 147 can be formed to cover the first word lines WL1 and second word lines WL2 as well as the gate isolation pattern 141.

[0556] The process steps for forming the second back gate insulating pattern 117 and the gate cap pattern 147 may include performing a planarization process. Therefore, the first active pattern AP1 and the second active pattern AP2, the first back gate insulating pattern 111, the second back gate insulating pattern 117, the gate insulating pattern GOX, and the gate cap pattern 147 can be substantially planarized.

[0557] Subsequently, a polysilicon layer 161, a first metal layer 163, a second metal layer 165, and a bit line capping layer 167 can be sequentially formed on the active patterns AP1 and AP2. The polysilicon layer 161, the first metal layer 163, the second metal layer 165, and the bit line capping layer 167 can constitute the bit line BL.

[0558] Subsequently, a second unit insulating layer 173 can be formed on the element isolation layer STI. Then, on the bit line BL and the second unit insulating layer 173, a spacer insulating layer 175, a first unit insulating layer 177, a shielding pattern SP, and a shielding cap pattern 179 can be formed sequentially. However, the order in which the bit line BL, the second unit insulating layer 173, the spacer insulating layer 175, the first unit insulating layer 177, the shielding pattern SP, and the shielding cap pattern 179 are formed is not limited to this and can be varied.

[0559] Subsequently, a second bonding insulation layer 216 can be formed on the first unit insulation layer 177 and the shielding cover pattern 179.

[0560] Subsequently, bit line contacts 245 connected to bit line BL can be formed. Then, within the second bonding insulation layer 216, unit connection wiring lines 232 connected to bit line contacts 245, unit connection wiring contacts 231, and second bonding pads 222 can be formed.

[0561] exist Figure 32 The diagram shows that the second bonding insulating layer 216 is a single layer; however, the second bonding insulating layer 216 may have a structure in which multiple layers are stacked, and multiple layers may be formed by separate processes.

[0562] Next, refer to Figure 5 and Figure 33 On the substrate 100, a peripheral circuit structure PS is formed, including peripheral circuit PC, peripheral circuit contacts PCT1, PCT2 and PCT3, peripheral circuit wiring lines PCL1 and PCL2, peripheral circuit insulating layer 212, first bonding insulating layer 214 and first bonding pad 221.

[0563] Subsequently, the first bonding pad 221 and the second bonding pad 222 can be bonded, and the first bonding insulating layer 214 and the second bonding insulating layer 216 can be bonded. Thus, the first bonding pad 221 and the second bonding pad 222 can contact each other to form a metal bond, and the first bonding insulating layer 214 and the second bonding insulating layer 216 can contact each other to form a junction insulating layer.

[0564] Subsequently, within the third unit insulating layer 277, the first unit wiring contact 261 and the first unit wiring line 262 can be formed. Subsequently, on the third unit insulating layer 277, the fourth unit insulating layer 279, the second unit wiring contact 263, and the second unit wiring line 264 can be formed.

[0565] While this disclosure has been described in conjunction with what is now considered to be practical embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Substrate; Bit lines are located on the substrate and extend in a first direction; Multiple letter lines extend in a second direction that intersects with the first direction; The first active pattern and the second active pattern are located between the plurality of word lines and spaced apart in the first direction; A unit capacitor is located on the first active pattern and the second active pattern; as well as Multiple shielding gates are located at a horizontal height between the multiple word lines and the unit capacitor. Each of the first active pattern and the second active pattern includes the following: A first dopant region is connected to the bit line; A second doped region, which is connected to the unit capacitor; and The channel region is located between the first dopant region and the second dopant region, and The plurality of shielding gates overlap with the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.

2. The semiconductor device according to claim 1, wherein: The plurality of shielding gates overlap with the plurality of word lines in a vertical direction that intersects the first direction and the second direction.

3. The semiconductor device according to claim 1, further comprising: A back gate electrode is located between the first active pattern and the second active pattern and extends in the second direction.

4. The semiconductor device according to claim 3, wherein: The plurality of shielding gates includes the following: A first shielding gate overlaps with the back gate electrode in a vertical direction intersecting the first and second directions; as well as The second shielding gate overlaps with the plurality of word lines in the vertical direction.

5. The semiconductor device according to claim 4, wherein: The back gate electrode and the first shielding gate are configured to be applied with different voltages, and The multiple word lines and the second shielding gate are configured to be applied with different voltages.

6. The semiconductor device according to claim 4, wherein: The back gate electrode and the first shielding gate are configured to be applied the same voltage. The multiple word lines and the second shielding gate are configured to be subjected to the same voltage. The first shielding gate has a work function different from that of the back gate electrode, and The second shielding gate has a work function that is different from that of the multiple word lines.

7. The semiconductor device according to claim 1, further comprising: An insulating isolation pattern is located between the first active pattern and the second active pattern. The plurality of shielding gates include the following: A first shielding gate overlaps the insulating pattern in a vertical direction intersecting the first and second directions; and The second shielding gate overlaps with the plurality of word lines in the vertical direction.

8. A semiconductor device, comprising: The substrate includes a unit array region and a peripheral circuit region; Bit lines, which are located on the cell array region and extend in a first direction; Multiple letter lines extend in a second direction that intersects with the first direction; The first active pattern and the second active pattern are located on the plurality of word lines and are spaced apart in the first direction; A back gate electrode is located between the first active pattern and the second active pattern and extends in the second direction; A unit capacitor is located on the first active pattern and the second active pattern; as well as Multiple shielding gates overlap with at least one of the multiple word lines and the back gate electrode in a vertical direction intersecting the first direction and the second direction. Each of the first active pattern and the second active pattern includes the following: A first dopant region is connected to the bit line; A second doped region, which is connected to the unit capacitor; and The channel region is located between the first dopant region and the second dopant region, and The plurality of shielding gates overlap with the second dopant region of at least one of the first active pattern and the second active pattern in the first direction.

9. The semiconductor device according to claim 8, wherein: The plurality of shielding gates includes the following: A first shielding gate overlaps with the back gate electrode in the vertical direction; as well as The second shielding gate overlaps with the plurality of word lines in the vertical direction.

10. The semiconductor device according to claim 9, wherein: The width of the first shielding gate is different from the width of the second shielding gate.

11. The semiconductor device according to claim 9, wherein: The width of the second shielding gate is smaller than the width of each of the plurality of word lines.

12. The semiconductor device according to claim 11, wherein: The width of the first shielding gate is smaller than the width of the back gate electrode.

13. The semiconductor device according to claim 9, wherein: The multiple character lines include first character lines and second character lines that are adjacent to each other, and The second shielding gate overlaps with the first word line and the second word line in the vertical direction.

14. The semiconductor device according to claim 9, wherein: The upper surfaces of the first shielding gate and the second shielding gate are located at different horizontal heights.

15. The semiconductor device according to claim 9, wherein: The thickness of the first shielding gate is different from the thickness of the second shielding gate.

16. The semiconductor device according to claim 9, wherein: In the peripheral circuit region, the ends of the first shielding gate and the back gate electrode are aligned at substantially the same boundary, and The semiconductor device also includes the following: Contact wiring lines, which are located in the peripheral circuit area; A first contact via is connected to the contact wiring and the back gate electrode; and A second contact via is connected to the contact wiring and the first shielding gate, and passes through the back gate electrode.

17. The semiconductor device according to claim 9, wherein: In the peripheral circuit region, the second shielding gate and the plurality of word lines extend at different lengths to have a stepped structure, and The semiconductor device also includes the following: Word line contacts, located in the peripheral circuit area and connected to the plurality of word lines; and The second shielding gate contact is located in the peripheral circuit area and is connected to the second shielding gate on a side further outward than the ends of the plurality of word lines.

18. A semiconductor device, comprising: The substrate includes a unit array region and a peripheral circuit region; The peripheral circuit structure includes peripheral circuits located on the substrate and peripheral circuit wiring lines connected to the peripheral circuits; as well as The unit structure overlaps with the peripheral circuit structure in the vertical direction. The unit structure includes the following: Bit lines are located on the substrate and extend in a first direction intersecting the vertical direction; Multiple character lines extend in a second direction that intersects the first direction and the vertical direction; Multiple active patterns are located between the multiple character lines and spaced apart in the first direction; A back gate electrode, which is located between the plurality of active patterns and extends in the second direction; Unit capacitors, which are located on the plurality of active patterns; A first shielding gate, which overlaps with the back gate electrode in the vertical direction; and The second shielding gate overlaps with the plurality of word lines in the vertical direction. Each of the plurality of active patterns includes the following: A first dopant region is connected to the bit line; A second doped region, which is connected to the unit capacitor; and The channel region is located between the first dopant region and the second dopant region, and Each of the first shielding gate and the second shielding gate overlaps with the second dopant region in the first direction.

19. The semiconductor device according to claim 18, wherein: The peripheral circuit structure also includes a first bonding pad and a first bonding insulating layer surrounding the first bonding pad. The unit structure further includes a second bonding pad and a second bonding insulating layer surrounding the second bonding pad, and The first bonding pad is in contact with the second bonding pad, and the first bonding insulating layer is in contact with the second bonding insulating layer.

20. The semiconductor device of claim 18, wherein: The unit structure also includes memory units and unit connection wiring lines connected to the memory units, and The semiconductor device further includes a through-hole component that connects the peripheral circuit wiring lines and the unit connection wiring lines.

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