Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device includes: a first stack including first material layers and second material layers alternately stacked; a through structure extending through the first stack and including an air gap; and a second laminate below the first laminate and including a key pattern positioned to correspond to the air gap.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices, and more specifically, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed on a single layer on a substrate has reached its limit, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In one embodiment, a semiconductor device may include: a first stack including a first material layer and a second material layer, the first material layer being alternately stacked with the second material layer in a vertical direction; a through structure extending vertically through the first stack and including an air gap; and a second stack located below the first stack and including a bond pattern positioned to overlap with the air gap in a vertical direction.

[0004] In an embodiment, a semiconductor device may include: a stack located in a scribe region and including a first material layer and a second material layer, the first material layer being alternately stacked with the second material layer in a vertical direction; a metal liner extending through the stack in a vertical direction; an insulating liner surrounding the metal liner; an air gap located inside the metal liner; and an interlayer insulating layer overlapping the stack in a vertical direction.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a first laminate on a substrate; forming a first opening extending through the first laminate into the substrate; forming a sacrificial layer in the first opening; forming a second laminate on the first laminate; etching the substrate to expose the sacrificial layer; forming a second opening by removing the sacrificial layer; and forming an air gap in the second opening.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a laminate; forming a contact plug extending through the laminate; forming an opening extending through the laminate; forming an insulating layer inside the opening and over the laminate; forming a hard mask layer on the insulating layer to include a dangling structure in the opening; forming a mask pattern on the hard mask layer; forming a contact hole by etching the insulating layer using the mask pattern as an etch stop, the contact hole exposing the contact plug; forming a via in the contact hole; and forming a metal liner in the opening, the metal liner including an air gap. Attached Figure Description

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0008] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0009] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 5A , Figure 5B and Figure 5C This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment.

[0012] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A as well as Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment.

[0013] Figure 18 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 19 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0015] Various embodiments are directed to semiconductor devices and methods for manufacturing semiconductor devices that have stable structures and improved characteristics.

[0016] In this embodiment, the integration density of the semiconductor device can be improved by stacking memory cells in three dimensions. In this embodiment, a semiconductor device with a stable structure and improved reliability can also be provided.

[0017] The embodiments of the technical concept according to this disclosure will now be described with reference to the accompanying drawings. Terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element. Terms such as "top," "above," "upper," "side," "upper part," "lower part," "row," "column," "inner," and "outer," as well as other terms that imply relative spatial relationships or orientations, are used only for ease of description or reference to the drawings and are not intended to be limiting. Crosshairs running through the drawings illustrate corresponding or similar areas between the drawings and do not indicate material associated with these areas. It should be understood that when an element or layer is referred to as "on another element or layer," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to another element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as "directly on another element or layer," "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers.

[0018] Figures 1A to 1E This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0019] Reference Figures 1A to 1E The semiconductor device may include a first stack ST1, a second stack ST2, a through-structure PS, and a metal pattern 15. The semiconductor device may also include a conductive pattern 19 and an interlayer insulating layer 16. For reference, the number of stacks included in the semiconductor device may vary. The semiconductor device may not include the second stack ST2, or it may include a third stack ST3.

[0020] The first laminate ST1 may include alternating layers of first material 11 and second material 12. In an embodiment, the first material layer 11 and the second material layer 12 may be as follows: Figure 1AThe layers are alternately stacked along the stacking direction. In an embodiment, the stacking direction can be a vertical direction (i.e., the Z direction). In an embodiment, the surface of the first material layer 11 can be formed into a plane by extending it along the horizontal direction (i.e., the X and Y directions). Each of the first material layers 11 may comprise a material with high etch selectivity relative to the second material layer 12. As an example, each of the first material layers 11 may comprise a nitride, while each of the second material layers 12 may comprise an oxide. Each of the first material layers 11 may comprise a conductive material, while each of the second material layers 12 may comprise an insulating material.

[0021] The through-structure PS can be located in the first laminate ST1. The through-structure PS can extend through the first laminate ST1 and can extend in the vertical direction. The through-structure PS can have a tapered cross-section, and its upper width can be smaller than its lower width. The through-structure PS can include an air gap AG. The air gap AG can be an empty space without a material layer. In one embodiment, the air gap AG can be an empty space containing gas. In another embodiment, the air gap AG can be an empty space containing gas, not limited to air. In yet another embodiment, the air gap AG can be an empty space without a material layer and without air. In yet another embodiment, the air gap AG can be an empty space without a material layer and containing gas, which may or may not contain air.

[0022] The second stack ST2 may be located below the first stack ST1. The second stack ST2 may include alternating layers of a third material layer 13 and a fourth material layer 14. As an example, each of the third material layers 13 may comprise a nitride, and each of the fourth material layers 14 may comprise an oxide. Each of the third material layers 13 may comprise a conductive material, and each of the fourth material layers 14 may comprise an insulating material. The third material layer 13 may comprise the same material as the first material layer 11, and the fourth material layer 14 may comprise the same material as the second material layer 12.

[0023] The through-structure PS can be located above the second laminate ST2, and the second laminate ST2 can include a key pattern K positioned corresponding to the through-structure PS. The key pattern K can be located on the surface of the second laminate ST2 and can be a pattern formed by the stacked shapes of the third material layer 13 and the fourth material layer 14. The third material layer 13 and the fourth material layer 14 can be stacked in a shape that is recessed toward the through-structure PS, and the groove in the recessed area can be the key pattern K.

[0024] In one embodiment, the recesses of the third material layer 13 and the fourth material layer 14 forming the bond pattern K can face away from the through structure PS, while the protrusions of the third material layer 13 and the fourth material layer 14 forming the bond pattern can face the through structure PS. In another embodiment, the bond pattern K can be positioned to correspond to the air gap AG by perpendicularly overlapping with the through structure PS, which includes the air gap AG. For example, the bond pattern K is located on the upper surface of the fourth material layer 14, which is furthest from the through structure PS, and is perpendicularly overlapped with the through structure PS.

[0025] Conductive pattern 19 may be located above the first laminate ST1. Interlayer insulating layer 16 may be located above conductive pattern 19. Metal pattern 15 may be located above interlayer insulating layer 16. Interlayer insulating layer 16 may be located between the first laminate ST1 and metal pattern 15. Conductive pattern 19 may include polysilicon. Metal pattern 15 may include tungsten, molybdenum, copper, aluminum, etc. Interlayer insulating layer 16 may include insulating materials such as oxides or nitrides. As an example, interlayer insulating layer 16 may include tetraethyl orthosilicate (TEOS).

[0026] The through-structure PS may include an air gap AG, and may also include a single layer or multiple layers. (See reference...) Figure 1A The through-structure PS may include an insulating liner 17 and an air gap AG located within the insulating liner 17. The air gap AG may be defined by the insulating liner 17, and the inner surface of the insulating liner 17 may be exposed to the air gap AG. The upper surface of the insulating liner 17 may contact the interlayer insulation layer 16, and the insulating liner 17 and the interlayer insulation layer 16 may be integrally connected layers. As an example, the insulating liner 17 and the interlayer insulation layer 16 may be a single layer formed by the same process.

[0027] Reference Figure 1B The through-structure PS may include an insulating bushing 17 and an air gap AG located within the insulating bushing 17. The through-structure PS may protrude from the upper surface of the first laminate ST1 and may penetrate the interlayer insulation layer 16. The upper surface of the through-structure PS may contact the metal pattern 15. The air gap AG may be defined by the insulating bushing 17 and the metal pattern 15. The inner surface of the insulating bushing 17 and the lower surface of the metal pattern 15 may be exposed to the air gap AG. The air gap AG may be sealed by the metal pattern 15.

[0028] Reference Figure 1CThe through-structure PS may include a metal bushing 18, an insulating bushing 17 surrounding the metal bushing 18, and an air gap AG located within the metal bushing 18. The through-structure PS may protrude from the upper surface of the first laminate ST1. The metal bushing 18 may extend vertically through the first laminate ST1 and may protrude from the upper surface of the first laminate ST1. The air gap AG may be defined by the metal bushing 18, and the inner surface of the metal bushing 18 may be exposed to the air gap AG. The metal bushing 18 may contact the metal pattern 15.

[0029] Reference Figure 1D The through-structure PS may include a metal liner 18, an insulating liner 17 surrounding the metal liner 18, and an air gap AG located in the metal liner 18. The air gap AG may be defined by the metal liner 18 and the metal pattern 15, and the inner surface of the metal liner 18 and the lower surface of the metal pattern 15 may be exposed to the air gap AG.

[0030] Reference Figure 1E The through-structure PS may include a metal bushing 18, a first insulating bushing 17A surrounding the metal bushing 18, a second insulating bushing 17B located between the metal bushing 18 and the first insulating bushing 17A, and an air gap AG located within the metal bushing 18. The first insulating bushing 17A and the second insulating bushing 17B may be layers formed by separate processes, and the interface between the layers may be defined or may not be defined. The height of the second insulating bushing 17B may be greater than the height of the first insulating bushing 17A.

[0031] The interlayer insulation layer 16 may include a first interlayer insulation layer 16A and a second interlayer insulation layer 16B. The first interlayer insulation layer 16A and the second interlayer insulation layer 16B may be layers formed by separate processes, and the interfaces between the layers may be defined or may not be defined. The first insulating liner 17A and the first interlayer insulation layer 16A may be formed as a single integral layer, and the second insulating liner 17B and the second interlayer insulation layer 16B may also be single integral layers.

[0032] According to the above structure, the through-structure PS, including the air gap AG, can extend through the first laminate ST1. The second laminate ST2 can include a bond pattern K positioned corresponding to the through-structure PS. The through-structure PS can be located in the scribe zone or at the edge of the semiconductor chip.

[0033] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment.

[0034] Reference Figure 2AThe semiconductor device can be a wafer 20, which can include a chip region CHR and a scriber region SCR. The scriber region SCR is the region where the dicing process is performed and is located between the chip regions CHR. The chip region CHR is the region corresponding to the semiconductor chip. The first stack ST1 and the second stack ST2 described above can be located in the chip region CHR and the scriber region SCR, and the through structure PS can be located in the scriber region SCR.

[0035] Reference Figure 2B The semiconductor device can be a semiconductor chip (CHIP) and can include an internal region C and an edge region EG. The semiconductor chip (CHIP) can include pads (PAD), a first peripheral circuit (PC1), a second peripheral circuit (PC2), and a memory plane (PL) located in the internal region C. The first peripheral circuit (PC1) can include logic circuits, data path circuits, analog circuits, etc., and the second peripheral circuit (PC2) can include page buffers, row decoders, etc. The memory plane (PL) and the second peripheral circuit (PC2) can be vertically stacked.

[0036] Most of the scribing region SCR contained in wafer 20 is lost due to the dicing process, but the scribing region SCR can be retained around the periphery of the chip region CHR. That is, the edge region EG of the semiconductor chip can be the remaining scribing region SCR. The aforementioned through-structure PS can be located in the edge region EG of the semiconductor chip.

[0037] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment. Figure 3A It is a cross-sectional view of the internal regions of a semiconductor chip, and illustrates the cell region (CELL) where the memory cells are located and the peripheral region (PERI) where the peripheral circuits are located. Figure 3B This is a cross-sectional view of the edge of a semiconductor chip. In the following text, content overlapping with the previously described material may be omitted.

[0038] Reference Figure 3A and Figure 3B The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS. The first semiconductor structure S1 may include peripheral circuitry PC (i.e., S1(PC)), and the second semiconductor structure S2 may include a memory cell array CA (i.e., S2(CA)).

[0039] The first semiconductor structure S1 may include a substrate 30, a transistor TR, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The transistor TR may be located inside the semiconductor chip and may belong to the peripheral circuit PC. For example, the transistor TR may belong to logic circuits, data path circuits, analog circuits, page buffers, line decoders, etc. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1 and may include vias, wiring lines, etc. The first interconnect structure IC1 may be electrically connected to the peripheral circuit PC.

[0040] The second semiconductor structure S2 may include a gate structure GST, a channel structure CH, a first stacked layer ST1, a second stacked layer ST2, a source layer S, a second interlayer insulating layer IL2, a second interconnect structure IC2, a third interlayer insulating layer IL3, a third interconnect structure IC3, a passivation layer PB, and a pad PAD. The gate structure GST may be located in the internal region of the semiconductor chip, and the first stacked layer ST1 and the second stacked layer ST2 may be located in the internal region and edge of the semiconductor chip.

[0041] The gate structure GST may include stacked gate lines, which may be source select lines, word lines, or drain select lines. The stacked element ST, the first stacked element ST1, and the second stacked element ST2 may include stacked insulating layers. The gate structure GST and the stacked element ST may be located at heights corresponding to those of the first stacked element ST1 and the second stacked element ST2.

[0042] The source layer S can be located above the gate structure GST. The channel structure CH can extend through the gate structure GST and can be connected to the source layer S. The wiring of the second interconnect structure IC2 connected to the channel structure CH can be a bit line.

[0043] The contact plug CT can be located inside the semiconductor chip or in the peripheral region PERI. The contact plug CT can penetrate the stack-up ST. The second interconnect structure IC2 and the third interconnect structure IC3 can be electrically connected to each other via the contact plug CT. As an example, the contact plug CT can be electrically connected to peripheral circuitry such as page buffers and line decoders.

[0044] The third interlayer insulating layer IL3 can be located above the source layer S. The third interconnect structure IC3 can be located inside the third interlayer insulating layer IL3 and can be electrically connected to the source layer S, contact plug CT, etc.

[0045] The metal pattern ML can be located above the first stack ST1 and the second stack ST2, and can be located within the third interlayer insulating layer IL3. The metal pattern ML can be located at the same height as the wiring included in the third interconnect structure IC3.

[0046] The through-structure PS can extend through the first laminate ST1 and into the third interlayer insulation layer IL3. The through-structure PS can contact the metal pattern ML. The through-structure PS can include a liner 32 and an air gap AG located within the liner 32. The air gap AG can be sealed by the metal pattern ML. The liner 32 can include oxides, metals, etc., and can be a single layer or multiple layers.

[0047] The passivation layer PB may be located above the third interlayer insulating layer IL3. The passivation layer PB may include an oxide layer formed by a high-density plasma (HDP) method. The pads PAD may extend through the passivation layer PB and the third interlayer insulating layer IL3 and may be electrically connected to the third interconnect structure IC3.

[0048] The bonding structure BS can be located between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 can be manufactured separately and can be electrically connected to each other through the bonding structure BS. The memory cell array CA, including the gate structure GST, and the peripheral circuit PC can be electrically connected to each other through the bonding structure BS.

[0049] The bonding structure BS may include a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2. The first bonding layer BL1 and the second bonding layer BL2 may be in contact with each other, and the first bonding pad BP1 and the second bonding pad BP2 may also be in contact with each other. The first bonding layer BL1 and the second bonding layer BL2 may each include SiCN, tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 may be electrically connected to the first interconnect structure IC1, and the second bonding pad BP2 may be electrically connected to the second interconnect structure IC2. The memory cell array CA and the peripheral circuit PC may be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0050] According to an embodiment of the above structure, the through-structure PS can be located at the edge of the semiconductor chip. In an embodiment, compared to the channel structure CH, the through-structure PS can have a larger width in the horizontal direction and / or a larger height in the vertical direction, and can include an air gap AG. In an embodiment, the through-structure PS can contact the metal pattern ML, and the air gap AG can be sealed by the metal pattern ML.

[0051] Figures 4A to 4E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. In the following text, content overlapping with the previously described content may be omitted.

[0052] Reference Figure 4AA first stack ST1 is formed on a substrate 40. The first stack ST1 may include alternating layers of first material layers 41 and second material layers 42. Each of the first material layers 41 may include a material with high etch selectivity relative to the second material layer 42. As an example, each of the first material layers 41 may include an insulating material such as a nitride, while each of the second material layers 42 may include an insulating material such as an oxide. Each of the first material layers 41 may include a conductive material such as polysilicon, tungsten, or molybdenum, while each of the second material layers 42 may include an insulating material such as an oxide.

[0053] Subsequently, a first opening OP1 is formed extending through the first laminate ST1 into the substrate 40. The first opening OP1 may be tapered, and its width at the lower part may be smaller than its width at the upper part. The first opening OP1 may be located in the scribe line region.

[0054] Subsequently, a sacrificial layer 45 is formed in the first opening OP1. The sacrificial layer 45 may be formed conformally along the inner surface of the first opening OP1. The sacrificial layer 45 may comprise a material with high etch selectivity relative to the first material layer 41 and the second material layer 42. As an example, the sacrificial layer 45 may comprise tungsten.

[0055] Subsequently, a second stack ST2 is formed on the first stack ST1. The second stack ST2 may include alternating layers of a third material layer 43 and a fourth material layer 44. Each of the third material layers 43 may comprise a material with high etch selectivity relative to the fourth material layer 44. As an example, each of the third material layers 43 may comprise an insulating material such as a nitride, while each of the fourth material layers 44 may comprise an insulating material such as an oxide. Each of the third material layers 43 may comprise a conductive material such as polysilicon, tungsten, or molybdenum, while each of the fourth material layers 44 may comprise an insulating material such as an oxide.

[0056] The second laminate ST2 can be formed to fill the first opening OP1. The third material layer 43 and the fourth material layer 44 can be formed along the surface of the sacrificial layer 45 and can be stacked in a shape where the third material layer 43 and the fourth material layer 44 are recessed into the first opening OP1. Therefore, the upper surface of the second laminate ST2 can include grooves formed due to the recessed areas, and these grooves can be bond patterns K. Thus, bond patterns K transferred from the first opening OP1 can be formed. As an example, the bond pattern K can be located in the scribe line region and can be used as an alignment key or an overlay key when forming the channel holes. Here, in an embodiment, the alignment key is used to satisfy the minimum conditions for aligning the patterns with each other and can be used to coarsely align the patterns with each other. In an embodiment, the overlay key can be used to finely align the patterns with each other in units of tens of nanometers.

[0057] Reference Figure 4B The substrate 40 is etched to expose the sacrificial layer 45. As an example, the sacrificial layer 45 can be exposed by etching the back surface of the substrate 40 using a grinding process and / or a planarization process. The planarization process can be a chemical mechanical polishing (CMP) process.

[0058] Reference Figure 4C The second opening OP2 is formed by removing the sacrificial layer 45. Metal particles in the second opening OP2 can be removed using a cleaning process. The third material layer 43 and the fourth material layer 44 formed in the second opening OP2 can be etched. In this process, the first material layer 41 and the second material layer 42 can also be partially etched. The second opening OP2 can be substantially the same as or larger than the first opening OP1.

[0059] Subsequently, the remaining substrate 40A can be removed. As an example, substrate 40A can be etched using a wet etching process.

[0060] Reference Figure 4D An insulating layer 46 is formed on the first laminate ST1. The insulating layer 46 may be formed conformally along the surface of the first laminate ST1 including the second opening OP2. The insulating layer 46 may partially fill the second opening OP2. The insulating layer 46 may include an insulating liner 46A formed along the inner surface of the second opening OP2 and an interlayer insulating layer 46B formed above the first laminate ST1.

[0061] Subsequently, a hard mask layer 47 is formed on the insulating layer 46. The hard mask layer 47 can be formed on the first laminate ST1 to have a drooping structure over the insulating substrate 46A. In an embodiment, the hard mask layer 47 can be formed by a deposition method with poor step coverage. In this case, the second opening OP2 can be sealed by the hard mask material deposited on the insulating layer 46 over the first laminate ST1, and a hard mask layer 47 with a drooping structure can be formed.

[0062] Subsequently, a mask pattern 48 can be formed on the hard mask layer 47. The mask pattern 48 can be used to form contact holes in the cell region and / or peripheral region, and can cover the scribe line region. When the mask pattern 48 is formed on the insulating layer 46 without the hard mask layer 47, the mask pattern 48 may be recessed into the second opening, which may result in a step on the upper surface of the mask pattern 48. Therefore, in the embodiment, by sealing the second opening OP2 with the hard mask layer 47 and then forming the mask pattern 48, a stepless mask pattern 48 can be formed.

[0063] Subsequently, the mask pattern 48 can be used as an etching barrier to etch the hard mask layer 47. In this embodiment, because the mask pattern 48, which does not have steps, covers the scribe area, the hard mask layer 47 formed above the second opening OP2 may not be etched during the process of using the mask pattern 48 as an etching barrier to etch the insulating layer 46. Therefore, in this embodiment, etching of the insulating layer 46 in the second opening OP2 can be prevented or mitigated, and abnormal patterns can be prevented or mitigated. Subsequently, the mask pattern 48 and the hard mask layer 47 can be removed, and the second opening OP2 can be reopened.

[0064] Reference Figure 4E A metal pattern 49 is formed above the first laminate ST1. The metal pattern 49 can be formed on the insulating layer 46. The second opening OP2 can be sealed by the metal pattern 49, and an air gap AG can be defined in the second opening OP2. Thus, a through structure PS including an insulating liner 46A and an air gap AG located in the insulating liner 46A can be formed.

[0065] According to the embodiment of the manufacturing method described above, the key pattern K can be formed in the scribe area. In the embodiment, by utilizing the hard mask layer 47 with a drooping structure, the absence of the insulating layer 46 in the second opening OP2 can be prevented or mitigated, and the formation of abnormal patterns can be prevented or mitigated.

[0066] Figures 5A to 5C This is a diagram used to illustrate a method for manufacturing a semiconductor device according to an embodiment. In the following text, content overlapping with the previously described content may be omitted.

[0067] Reference Figure 5A The second opening OP2 can be formed in the first laminate ST1. The first laminate ST1 may include alternating layers of first material 71 and second material 72. The second laminate ST2 may include alternating layers of third material 73 and fourth material 74. The processes for forming the first laminate ST1, the second laminate ST2, and the second opening OP2 can be the same as those described above. Figures 4A to 4C The processes described in the implementation methods are the same.

[0068] Subsequently, a first insulating layer 76 is formed on the first laminate ST1. The first insulating layer 76 may be formed conformally along the surface of the first laminate ST1 including the second opening OP2. The first insulating layer 76 may partially fill the second opening OP2. The first insulating layer 76 may include a first insulating liner 76A formed along the inner surface of the second opening OP2 and a first interlayer insulating layer 76B formed above the first laminate ST1. When the first insulating layer 76 is formed, the width of the uppermost part of the second opening OP2 is a first width W11.

[0069] Reference Figure 5B A second insulating layer 77 is formed on the first insulating layer 76. The second insulating layer 77 may be formed conformally along the surface of the first insulating layer 76. The second insulating layer 77 may partially fill the second opening OP2. The second insulating layer 77 may include a second insulating liner 77A formed inside the second opening OP2 and a second interlayer insulating layer 77B formed above the first laminate ST1. When the second insulating layer 77 is formed, the width of the uppermost part of the second opening OP2 is reduced to a second width W12.

[0070] Subsequently, a mask pattern 75 is formed on the second insulating layer 77. The second opening OP2 can be sealed by the mask pattern 75. The mask pattern 75 can be used to form contact holes in the cell area and / or peripheral area, and can cover the scribing area. Because the uppermost width of the second opening OP2 is reduced to the second width W12 due to the second insulating layer 77, the mask pattern 75 can be formed above the second opening OP2 without steps.

[0071] Subsequently, the mask pattern 75 can be used as an etching barrier to etch the second insulating layer 77 and the first insulating layer 76. This allows contact holes to be formed in the cell region and / or the peripheral region. Because the mask pattern 75, which does not have steps, covers the scribe line area, the first insulating layer 76 and the second insulating layer 77 formed inside the second opening OP2 are not etched. The mask pattern 75 can then be removed, and the second opening OP2 can be reopened.

[0072] Reference Figure 5C A metal insert 78 is formed on the second insulating layer 77. The metal insert 78 can be formed inside the second opening OP2. The second opening OP2 can be sealed by the metal insert 78, and an air gap AG can be defined in the metal insert 78. Through this process, a through structure PS including a first insulating insert 76A, a second insulating insert 77A, a metal insert 78, and an air gap AG can be formed. Subsequently, a metal pattern 79 is formed on the second insulating layer 77.

[0073] According to the embodiment of the manufacturing method described above, by forming a multi-layered insulating liner, the width of the uppermost part of the second opening OP2 can be reduced. Therefore, in the embodiment, even when forming the mask pattern 75 without a hard mask layer, a mask pattern 75 without steps can be formed, and the formation of abnormal patterns can be prevented or mitigated.

[0074] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A as well as Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B This is a diagram used to describe a method for manufacturing a semiconductor device according to an embodiment. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A It is a cross-sectional view of the cell region (CELL) and the peripheral region (PERI), and Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B This is a cross-sectional view of the marked area.

[0075] Reference Figure 6A and Figure 6B A first laminate ST1 is formed on a substrate 50 comprising a cell region (CELL), a peripheral region (PERI), and a scribing region (SCR). The first laminate ST1 may be located within the cell region (CELL), the peripheral region (PERI), and the scribing region (SCR). The first laminate ST1 may include alternating layers of first material 51 and second material 52.

[0076] Subsequently, a first channel hole CHA can be formed extending through the first laminate ST1 into the substrate 50. The first channel hole CHA can be located in the cell region CELL and can have a first width W1 and a first depth D1.

[0077] A first opening OP1 can be formed extending through the first laminate ST1 into the substrate 50. The first opening OP1 can be located in the scribing region SCR and can have a second width W2 greater than the first width W1 and a second depth D2 greater than the first depth D1. As an example, the first opening OP1 can be tapered, and its width at the lower part can be smaller than its width at the upper part. The minimum width of the first opening OP1 can be greater than the first width W1.

[0078] The first channel hole CHA and the first opening OP1 can be formed simultaneously. By simultaneously forming the first opening OP1 with a relatively large width W2 and the first channel hole CHA with a relatively small width W1, the first opening OP1 can be formed at a deeper depth than the first channel hole CHA. The terms "simultaneously" and "at the same time" used in this document to describe the process mean that the process occurs within overlapping time intervals. For example, if the first process occurs within a first time interval, and the second process occurs simultaneously within a second time interval, then the first and second intervals at least partially overlap, such that there exists a time when both the first and second processes occur.

[0079] Subsequently, a sacrificial layer 53 can be formed in the first channel hole CHA. As an example, a sacrificial material layer can be formed on a first laminate ST1 including the first channel hole CHA, and the sacrificial material layer can be planarized to expose the upper surface of the first laminate ST1. Thus, a sacrificial layer 53 filling the first channel hole CHA can be formed. The sacrificial layer 53 may include a material with high etch selectivity relative to the first material layer 51 and the second material layer 52. The sacrificial layer 53 may include tungsten.

[0080] A sacrificial layer 53 can be formed in the first opening OP1. The sacrificial layer 53 can be formed conformally along the inner surface of the first opening OP1. The sacrificial layer 53 can be formed in the first opening OP1 and simultaneously in the first channel hole CHA. Because the size of the first opening OP1 is larger than the size of the first channel hole CHA, the first channel hole CHA can be completely filled by the sacrificial layer 53, while the first opening OP1 can be only partially filled by the sacrificial layer 53.

[0081] Reference Figure 7A and Figure 7BA second laminate ST2 is formed above the first laminate ST1. The second laminate ST2 may include alternating layers of a third material layer 54 and a fourth material layer 55. In the scribe line region SCR, the third material layer 54 and the fourth material layer 55 may be formed in the first opening OP1. The third material layer 54 and the fourth material layer 55 may be laminated along the surface of the sacrificial layer 53. The third material layer 54 and the fourth material layer 55 may be laminated in a shape that is recessed into the first opening OP1, and the upper surface of the second laminate ST2 may include a groove located in the recessed region.

[0082] Subsequently, a hard mask layer 56 can be formed over the second stack ST2, and a mask pattern 57 can be formed over the hard mask layer 56. The mask pattern 57 may include openings located in the cell region CELL and may cover the peripheral region PERI and the scribe line region SCR. When forming the mask pattern 57, a key pattern K can be used as an alignment key or a cover key.

[0083] Subsequently, the mask pattern 57 can be used as an etching stop to etch the hard mask layer 56. Then, the hard mask layer 56 can be used as an etching stop to etch the second stack ST2. This forms a second channel via CHB extending through the second stack ST2. The second channel via CHB can be connected to the first channel via CHA and can expose the sacrificial layer 53. The mask pattern 57 and the hard mask layer 56 can then be removed.

[0084] Reference Figure 8A and Figure 8B A sacrificial layer 58 can be formed in the second channel hole CHB. A sacrificial material layer can be formed on the second stack ST2, and the sacrificial material layer can be planarized to expose the upper surface of the second stack ST2. Thus, a sacrificial layer 58 filling the second channel hole CHB can be formed. The sacrificial layer 58 may include a material with high etch selectivity relative to the third material layer 54 and the fourth material layer 55. The sacrificial layer 58 may include tungsten.

[0085] In the scribe line region SCR, the upper surface of the second laminate ST2 may include a groove, and the sacrificial layer 58 may fill the groove. In an embodiment, the groove may be formed by a recess in a material layer and may be filled with the sacrificial layer 58.

[0086] Reference Figure 9A and Figure 9BThe first via CHA and the second via CHB can be reopened by removing sacrificial layers 53 and 58. Subsequently, a channel structure CH can be formed in the reopened first via CHA and second via CHB. The channel structure CH may include a channel layer, a memory layer surrounding the sidewalls of the channel layer, and an insulating core located within the channel layer. The memory layer may include at least one of a tunneling layer, a data storage layer, and a barrier layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc.

[0087] Subsequently, the first material layer 51 and the third material layer 54 can be replaced by the conductive layer 59. The portions of the first material layer 51 and the third material layer 54 located within the cell region can be replaced by the conductive layer 59. Thus, a gate structure GST comprising alternating layers of conductive layer 59 and a second material layer 52 and a fourth material layer 55 serving as insulating layers can be formed within the cell region. The first material layer 51 of the peripheral region PERI and the scribing region SCR can be retained without being replaced by the conductive layer 59. Thus, a stack ST comprising alternating layers of first material layer 51 and second material layer 52, and alternating layers of third material layer 54 and fourth material layer 55 can be formed within the peripheral region PERI and the scribing region SCR, where all material layers 51, 52, 54, and 55 can be insulating layers.

[0088] Subsequently, a contact plug CT can be formed extending into the substrate 50 through the second stack ST2 and the first stack ST1. The contact plug CT can be formed in the peripheral region PERI. The width of the contact plug CT can be greater than the width of the channel structure CH.

[0089] Subsequently, interconnect structures IC, interlayer insulating layers IL, bonding layers BL, and bonding pads BP can be formed on the second stack ST2. In the cell region CELL, the interconnect structures IC can be connected to the channel structure CH. In the peripheral region PERI, the interconnect structures IC can be electrically connected to the contact plug CT. In the scriber region SCR, the interconnect structures IC can be located above the second stack ST2.

[0090] Reference Figure 10A and Figure 10BA second wafer WF2 is formed, which includes a substrate 60, peripheral circuitry PC, interconnect structure IC electrically connected to the peripheral circuitry PC, interlayer insulating layer IL, bonding layer BL, and bonding pad BP. Subsequently, the first wafer WF1 can be flipped so that the substrate 50 is positioned above the stacked layer ST and the gate structure GST, and the flipped first wafer WF1 and second wafer WF2 can be bonded to each other. Thus, the first wafer WF1, including the gate structure GST, channel structure CH, stacked layer ST, and sacrificial layer 53, and the second wafer WF2, including the peripheral circuitry PC, can be bonded to each other. The interconnect structure ICs of the first wafer WF1 and the second wafer WF2 can be electrically connected to each other via the bonding pad BP.

[0091] Reference Figure 11A and Figure 11B The sacrificial layer 53 is exposed by etching the substrate 50. As an example, the sacrificial layer 53 can be exposed by etching the back surface of the substrate 50 using a polishing process and / or a planarization process. The etched substrate 50A can cover the channel structure CH and not expose the channel structure CH.

[0092] Subsequently, the second opening OP2 is formed by removing the sacrificial layer 53. A portion of the second stack ST2 formed in the first opening OP1 can be etched. In this process, the first stack ST1 can also be partially etched. The size of the second opening OP2 can be equal to or larger than the size of the first opening OP1.

[0093] Subsequently, the remaining substrate 50A is removed. A wet etching process can be used to remove substrate 50A. This exposes the channel structure CH and the contact plug CT. The memory layer of the channel structure CH can then be etched to expose the channel layer, and impurities can be doped into the channel layer.

[0094] Reference Figure 12A and Figure 12B A source conductive layer 61 can be formed above the first stack ST1. The source conductive layer 61 can be formed along the surface of the first stack ST1, including the second opening OP2, using a deposition process. The source conductive layer 61 can include polysilicon. In the cell region (CELL), the source conductive layer 61 can be formed on the gate structure (GST) and can be connected to the channel structure (CH). In the peripheral region (PERI), the source conductive layer 61 can be formed on the first stack ST1 and can be connected to the contact plug (CT). In the slotted region (SCR), the source conductive layer 61 can be formed on the first stack ST1 and can extend along the inner surface of the second opening OP2.

[0095] Reference Figure 13A and Figure 13BThe source layer 61A can be formed by etching the source conductive layer 61. As an example, the source conductive layer 61 can be patterned using a mask pattern. The source layer 61A can be formed in the cell region CELL and can be connected to the channel structure CH. In the peripheral region PERI, the source conductive layer 61 can be removed, exposing the contact plug CT. In the scribe region SCR, a portion of the source conductive layer 61 formed inside the second opening OP2 can be etched, and a conductive pattern 61B can be formed on the upper surface of the first laminate ST1.

[0096] Reference Figure 14A and Figure 14B An insulating layer 62 is formed along the surface of the first laminate ST1, including the second opening OP2. In the cell region (CELL), the insulating layer 62 may be formed over the source layer 61A. In the peripheral region (PERI), the insulating layer 62 may be formed over the first laminate ST1 and may surround a contact plug CT protruding from the surface of the first laminate ST1. In the scriber region (SCR), the insulating layer 62 may be conformally formed along the surface of the conductive pattern 61B and the inner surface of the second opening OP2. The insulating layer 62 may seal the second opening OP2 or may not seal the second opening OP2. The insulating layer 62 may include an insulating material such as an oxide or nitride.

[0097] Subsequently, a hard mask layer 63 is formed over the first stack ST1. The hard mask layer 63 may be formed on the insulating layer 62 and may have a drooping structure over the second opening OP2. The hard mask layer 63 with a drooping structure can be formed by depositing a hard mask material with poor step coverage to seal the second opening OP2. The hard mask layer 63 may include carbon. For reference, it may also refer to the above description. Figure 5B Instead of forming a hard mask layer 63, a second insulating layer is formed on the insulating layer 62.

[0098] Subsequently, a mask pattern 64 can be formed on the hard mask layer 63. The mask pattern 64 may include openings corresponding to the contact plug CT and may cover the cell region and the scribe region SCR. Because the mask pattern 64 is formed on the hard mask layer 63 which has a cantilever structure in the scribe region SCR, the mask pattern 64 may have a flat upper surface.

[0099] Reference Figure 15A and Figure 15BThe hard mask layer 63 is etched using a mask pattern 64 as an etching barrier. Subsequently, the insulating layer 62 can be etched using the etched hard mask layer 63 as an etching barrier to form the contact hole CTH. In the scribing region SCR, in this embodiment, a flat mask pattern 64 has been formed on the hard mask layer 63 with a cantilever structure, thus preventing or mitigating the etching of the insulating layer 62 in the second opening OP2 and preventing or mitigating the formation of abnormal patterns during the formation of the contact hole CTH.

[0100] For reference, when the mask pattern 64 is formed without forming a hard mask layer 63 with a cantilever structure, the mask pattern 64 may be recessed into the second opening OP2, and the upper surface of the mask pattern 64 may have a step. Therefore, during the process of forming the contact hole CTH, the insulating layer 62 inside the second opening OP2 may be etched, and abnormal patterns may form. According to embodiments of the present disclosure, the formation of abnormal patterns can be prevented or reduced.

[0101] Subsequently, the mask pattern 64 and hard mask layer 63 can be removed, and a via conductive layer 65 can be formed over the insulating layer 62. In the peripheral region PERI, the via conductive layer 65 can fill the contact via CTH. In the scribing region SCR, the via conductive layer 65 can be formed on the insulating layer 62 and can extend into the second opening OP2. The second opening OP2 may not be completely filled by the via conductive layer 65. The second opening OP2 may or may not be sealed by the via conductive layer 65. For reference, when the second opening OP2 is sealed by the insulating layer 62, the via conductive layer 65 may not be formed in the second opening OP2. The via conductive layer 65 may include a metal such as tungsten.

[0102] Reference Figure 16A and Figure 16B Via 65A is formed in contact hole CTH by etching via conductive layer 65. Metal insert 65B can be formed in second opening OP2 by etching via conductive layer 65. Via 65A and metal insert 65B can be formed simultaneously. As an example, via 65A and metal insert 65B can be formed by polishing via conductive layer 65 using a planarization process.

[0103] Subsequently, a metal layer 66 is formed over the insulating layer 62. As an example, a deposition process can be used to form the metal layer 66. The metal layer 66 can be located over the metal bushing 65B, and the second opening OP2 can be sealed by the metal layer 66. Thus, an air gap AG can be defined in the second opening OP2.

[0104] Subsequently, a mask pattern 67 can be formed over the metal layer 66. The mask pattern 67 can be used to form metal wiring connected to the via 65A. The mask pattern 67 may include openings exposing the cell region CELL and may cover a portion of the peripheral region PERI and the scribing region SCR.

[0105] Reference Figure 17A and Figure 17B The metal layer 66 is etched using a mask pattern 67 as an etching stop. By etching the metal layer 66, metal wiring lines 66A can be formed in the peripheral region PERI. The metal wiring lines 66A can be electrically connected to vias 65A. By etching the metal layer 66, a metal pattern 66B can be formed in the scribe region SCR. The metal pattern 66B can seal the air gap AG located inside the metal substrate 65B. Thus, a through-structure PS including an insulating layer 62, a metal substrate 65B, and an air gap AG can be formed.

[0106] Subsequently, an interlayer insulation layer 68 can be formed on the metal wiring line 66A and the metal pattern 66B. The interlayer insulation layer 68 may include an insulating material such as an oxide or a nitride.

[0107] According to the embodiment of the above manufacturing method, the manufacturing processes of the cell region (CELL), the peripheral region (PERI), and the scriber region (SCR) can be performed simultaneously. The first channel via (CHA) of the cell region (CELL) and the first opening (OP1) of the scriber region (SCR) can be formed simultaneously. The via (65A) of the peripheral region (PERI) and the metal insert (65B) of the scriber region (SCR) can be formed simultaneously. The metal wiring (66A) of the peripheral region (PERI) and the metal pattern (66B) of the scriber region (SCR) can be formed simultaneously. In this embodiment, because a hard mask layer (63) with a drooping structure is used, the formation of abnormal patterns in the scriber region (SCR) can be prevented or mitigated even when different regions are processed simultaneously.

[0108] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 18 and Figure 19 An illustrative configuration of a semiconductor device to which the above embodiments can be applied is shown.

[0109] Figure 18 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0110] Reference Figure 18 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. Here, the peripheral circuitry PC and the memory cell array CA may be formed on the same substrate.

[0111] The substrate SUB can be made of or comprise a semiconductor material. In embodiments, the semiconductor material can include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Here, group IV semiconductors can include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium (SiGe). Group III-V compound semiconductors can include GaAs, GaN, GaP, GaAsP, GaInAsP, AlAs, AlGa, InP, InSb, or InGaAs. Group II-VI compound semiconductors can include ZnS, ZnO, or CdS.

[0112] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0113] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB can include group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB can include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0114] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In some embodiments, the peripheral circuitry PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, lines, etc.

[0115] A memory cell array (CA) may include memory cells. In one embodiment, the memory cell array (CA) may include memory strings connected between source lines and bit lines, and each memory string may include stacked memory cells. In another embodiment, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0116] Figure 19 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0117] Reference Figure 19The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. Here, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded together. The semiconductor device may also include a support base SP_B.

[0118] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. In an embodiment, after a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC are respectively manufactured, the first wafer and the second wafer can be electrically connected by a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer can be removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0119] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown by selective epitaxial growth (SEG), or a layer formed by metal-induced lateral crystallization (MILC). The support substrate SP_B can be single-crystal, polycrystalline, or amorphous. The support substrate SP_B can include group II, III, IV, V, or VI impurities.

[0120] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded using wafer-to-wafer bonding, chip-to-wafer bonding, chip-to-chip bonding, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals and / or alloys such as copper and aluminum. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0121] For reference, the interconnect structures included in the memory cell array (CA) and / or the peripheral circuitry (PC) can be directly connected without bonding pads. In an embodiment, the bonding layers included in the memory cell array (CA) and the bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, and the interconnect structures included in the memory cell array (CA) and the interconnect structures included in the peripheral circuitry (PC) can be directly connected. Thus, in an embodiment, contact plugs, lines, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0122] Other configurations can be referenced above. Figure 18 The configurations described are the same or similar.

[0123] Furthermore, the semiconductor device may have the aforementioned reference Figure 18 and Figure 19 The described implementation method is a combination of structures, or may have partially modified structures. (Refer to...) Figure 18 and Figure 19 In the described implementation, the positions of the memory cell array CA and the peripheral circuitry PC can be changed. At least one memory cell array CA and / or at least one peripheral circuitry PC can be additionally coupled to a reference. Figure 18 and Figure 19 In the described implementation, a portion of the peripheral circuitry PC may be located within the memory cell array CA.

[0124] While embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely illustrative of embodiments based on the concept of this disclosure, and this disclosure is not limited to the above-described embodiments. Various substitutions, modifications, alterations, and combinations of embodiments can be made by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the appended claims, and it should be understood that such substitutions, modifications, alterations, and combinations fall within the scope of this disclosure.

[0125] Cross-references to related applications

[0126] This application claims priority to Korean Patent Application No. 10-2024-0155194, filed on November 5, 2024, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: The first layer of the stack includes a first material layer and a second material layer, wherein the first material layer and the second material layer are alternately stacked in the vertical direction. A through-structure extending through the first laminate in the vertical direction and including an air gap; and A second laminate, located below the first laminate, includes a key pattern positioned to overlap the air gap in the vertical direction.

2. The semiconductor device according to claim 1, wherein, The through-structure includes: Insulating liners; and The air gap located inside the insulating liner.

3. The semiconductor device according to claim 2, further comprising: A metal pattern that overlaps with the first laminate in the vertical direction; as well as An interlayer insulating layer is located between the first laminate and the metal pattern.

4. The semiconductor device according to claim 3, wherein, The insulating liner and the interlayer insulation layer are a single layer integrally connected.

5. The semiconductor device of claim 3, further comprising a conductive pattern located between the first laminate and the interlayer insulating layer.

6. The semiconductor device according to claim 5, wherein, The conductive pattern comprises polycrystalline silicon.

7. The semiconductor device according to claim 1, wherein, The through-structure includes: Metal liners; An insulating liner surrounding the metal liner; and The air gap located inside the metal liner.

8. The semiconductor device according to claim 7, wherein, The metal liner protrudes from the upper surface of the first laminate.

9. The semiconductor device according to claim 1, wherein, The second laminate includes a third material layer and a fourth material layer, the third material layer being alternately laminated with the fourth material layer in the vertical direction, and the second laminate includes the key pattern on the surface of the second laminate.

10. The semiconductor device according to claim 9, wherein, The third and fourth material layers are stacked in a shape that faces the recess of the through structure, and the key pattern includes grooves located in the recessed region.

11. The semiconductor device according to claim 1, wherein, The width at the upper part of the through structure is smaller than the width at the lower part of the through structure.

12. The semiconductor device according to claim 1, wherein, The through structure is located in the lane marking area.

13. The semiconductor device of claim 1, further comprising: A memory cell array, the memory cell array including a gate structure located at a height corresponding to the first stack and the second stack; Peripheral circuits; as well as A bonding structure that electrically connects the memory cell array to the peripheral circuitry.

14. The semiconductor device of claim 1, further comprising: A gate structure located at a height corresponding to the first stack and the second stack; A source layer, which overlaps with the gate structure in the vertical direction; as well as Metal wiring lines, which are located above the source layer.

15. The semiconductor device of claim 14, further comprising a metal pattern located above the first stack and at a height corresponding to the metal wiring.

16. A semiconductor device, the semiconductor device comprising: A laminate, the laminate being located in a scribing region and comprising a first material layer and a second material layer, the first material layer being alternately laminated with the second material layer in a vertical direction; A metal liner extending through the laminate in the vertical direction; An insulating liner surrounding the metal liner; An air gap, the air gap being located inside the metal liner; as well as An interlayer insulating layer that overlaps with the laminate in the vertical direction.

17. The semiconductor device of claim 16, further comprising a conductive pattern located between the stack and the interlayer insulating layer.

18. The semiconductor device of claim 16, further comprising a metal pattern that overlaps with the interlayer insulating layer in the vertical direction and contacts the air gap or the metal substrate.

19. The semiconductor device according to claim 16, wherein, The insulating liner and the interlayer insulation layer are a single layer integrally connected.

20. A method for manufacturing a semiconductor device, the method comprising the following steps: A first laminate is formed on the substrate; Forming a first opening that extends through the first laminate into the substrate; A sacrificial layer is formed in the first opening; A second layer is formed on the first layer; The substrate is etched to expose the sacrificial layer; The second opening is formed by removing the sacrificial layer; as well as An air gap is formed in the second opening.

21. The method of claim 20, further comprising the step of: A hard mask layer is formed over the first stack including the second opening, the hard mask layer including a droop structure.

22. The method according to claim 21, further comprising the step of: A mask pattern is formed on the hard mask layer, the mask pattern covering the second opening; as well as The mask pattern is used as an etching barrier to etch the hard mask layer.

23. The method of claim 20, wherein, The first opening and the second opening are located in the lane area.

24. The method of claim 20, further comprising forming channel holes in a cell region of the first laminate, in, The first opening is formed simultaneously with the channel hole.

25. The method according to claim 24, wherein, The width of the first opening is greater than the width of the channel hole, and the depth of the first opening is greater than the depth of the channel hole.

26. The method of claim 20, further comprising bonding a first wafer and a second wafer to each other, the first wafer including the first stack, the sacrificial layer and the second stack, and the second wafer including peripheral circuitry.

27. The method of claim 20, further comprising forming an insulating layer in the second opening.

28. The method according to claim 27, wherein, The second opening is sealed by the insulating layer, and the air gap is located inside the insulating layer.

29. The method of claim 27, further comprising forming a metal liner in the second opening.

30. The method according to claim 29, wherein, The second opening is sealed by the metal liner, and the air gap is located inside the metal liner.

31. The method according to claim 20, wherein, The second opening is sealed by forming a metal pattern over the first laminate, and the air gap is formed in the second opening.

32. The method according to claim 20, wherein, The second layer is formed to fill the first opening.

33. The method according to claim 32, wherein, The upper surface of the second laminate includes a key pattern transferred from the first opening.

34. The method according to claim 33, further comprising the following step: A first channel hole is formed in the unit region of the first layer; and The key pattern is used to form a second channel hole, which extends through the second stack and connects to the first channel hole.

35. The method according to claim 32, wherein, In the step of forming the second opening, a cleaning process is used to etch the portion of the second laminate formed in the first opening.

36. The method according to claim 22, further comprising the following steps: A source conductive layer is formed above the first layer stack; and A source layer is formed in the cell region by etching the source conductive layer.

37. The method according to claim 36, wherein, The source conductive layer extends into the second opening, and A conductive pattern is formed in the etched area by etching the portion of the source conductive layer formed in the second opening.

38. The method according to claim 20, further comprising the step of: An insulating layer is formed along the surface of the first laminate, including the second opening; A hard mask layer is formed on the insulating layer; A mask pattern is formed on the hard mask layer; The mask pattern is used as an etching barrier to etch the hard mask layer; Contact holes are formed by etching the insulating layer using the hard mask layer as an etching barrier. as well as A through hole is formed in the contact hole.

39. The method according to claim 38, wherein, The hard mask layer has a drooping structure at the second opening.

40. The method according to claim 39, wherein, The mask pattern covers the second opening.

41. The method according to claim 38, wherein, The steps for forming the via include the following: A via conductive layer is formed in the contact hole and the second opening; The via is formed in the contact hole by etching the via conductive layer; and The metal insert located in the second opening is formed by etching the through-hole conductive layer.

42. The method according to claim 38, further comprising the following step: A metal layer is formed on the insulating layer; Metal wiring is formed by etching the metal layer, and the metal wiring is connected to the via. as well as A metal pattern is formed by etching the metal layer, and the metal pattern defines the air gap in the second opening.

43. The method according to claim 20, further comprising the following step: A first insulating layer is formed along the surface of the first laminate including the second opening; A second insulating layer is formed on the first insulating layer; as well as A mask pattern is formed on the second insulating layer.

44. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming laminated components; Forming a contact plug that penetrates the laminated component; Forming an opening that extends through the laminate; An insulating layer is formed inside the opening and above the laminate; A hard mask layer is formed on the insulating layer to include a hanging structure at the opening; A mask pattern is formed on the hard mask layer; Contact holes are formed by etching the insulating layer using the mask pattern as an etching barrier, and the contact holes expose the contact plugs; A through hole is formed in the contact hole; as well as A metal liner is formed in the opening, the metal liner including an air gap.

45. The method according to claim 44, wherein, The steps for forming the via include the following: A via conductive layer is formed on the insulating layer to fill the contact hole; and The via is formed by polishing the conductive layer of the via.

46. ​​The method according to claim 45, wherein, The via conductive layer extends into the opening, and the metal liner is formed by polishing the via conductive layer.

47. The method of claim 44, further comprising the step of: A metal layer is formed over the insulating layer; as well as Metal wiring is formed by etching the metal layer, and the metal wiring is electrically connected to the via.

48. The method of claim 47, further comprising forming a metal pattern over the opening by etching the metal layer.

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