CMOS three-dimensional memory architecture and preparation method thereof
By adopting a 2FnSnR three-dimensional integrated architecture, using a dual-finger transistor base and a multi-layer stacked 1S1R memory cell design, the problem of leakage current interference in RRAM memory in high-density arrays is solved, achieving high-density and stable storage performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2024-11-07
- Publication Date
- 2026-05-08
AI Technical Summary
Existing planar integrated RRAM memory architectures are susceptible to bypass current interference in high-density memory arrays, leading to read and programming errors. Furthermore, traditional 1T1R MOSFET devices limit the memory density advantage and are difficult to apply to three-dimensional stacked architectures.
Employing a 2FnSnR three-dimensional integrated architecture, multiple 1S1R memory cells are constructed on a dual-finger transistor base and connected in parallel. By combining multi-layer stacking and vertical electrical connections, the signal transmission path is optimized, achieving high-density integration.
It significantly improves storage density and electrical performance, reduces leakage current and crosstalk issues, and supports stable storage operations on larger array sizes.
Smart Images
Figure CN122002811A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor and CMOS hybrid integrated circuit technology, specifically relating to a novel emerging memory architecture that is compatible with existing CMOS processes and integrated with CMOS, and its fabrication method. Background Technology
[0002] With the rapid development of next-generation information technologies such as 5G, artificial intelligence (AI), and the Internet of Things (IoT), massive and diverse data requires efficient storage and processing, leading to a rapid increase in demand for semiconductor memory. In widely used mobile terminal devices (such as wearable devices), embedded storage is evolving towards smaller size and larger capacity. However, non-volatile memories, represented by Flash memory, have encountered miniaturization bottlenecks at the 40nm process node. Planar integrated architectures struggle to further increase storage density, thus failing to meet the high-density storage demands of the mobile internet era. Resistive random access memory (RRAM), as a new type of memory, is considered a key technology for further miniaturization to 22nm and below processes due to its excellent scalability, providing a non-volatile memory solution for 28nm and below processes.
[0003] In RRAM arrays, word lines and bit lines are cross-connected (Crossbar structure). This structure is susceptible to interference from bypass current during reading in high-density memory arrays. Bypass current primarily originates from interference currents in adjacent memory cells, which can lead to read and programming errors. Therefore, in high-density memory arrays, accurately accessing target memory cells while maintaining interference immunity is a major challenge.
[0004] To address the aforementioned issues, a common design is the 1T1R structure, where the transistor (T) acts as a gating unit, effectively shutting off leakage paths. However, in this structure, each memory cell has an area of 6F² (F being the feature size), and the three-terminal design of the MOSFET device limits the high-density advantage of RRAM, making it unsuitable for three-dimensional stacked architectures.
[0005] Another design to address bypass current is the 1S1R structure, where the RRAM is connected to a selector with threshold switching characteristics. The area of each memory cell in this structure is determined by the overlap between word lines and bit lines, with a minimum area of 4F². Furthermore, this design supports multi-layer stacking, reducing the effective area of each memory cell to 4F² / N (where N is the number of stacking layers), thus achieving high-density three-dimensional integration.
[0006] The combination of these two technologies has given rise to the 1TnSnR structure. This structure consists of a MOSFET base connected in parallel with multiple 1S1R memory cells. Compared to the traditional 1T1R structure, 1TnSnR controls multiple memory cells with a single MOSFET, effectively increasing storage density, reducing cell area, and maintaining excellent read / write performance. In terms of three-dimensional integration, 1TnSnR exhibits significant advantages, allowing for the stacking of multiple memory cells, reducing leakage current and crosstalk issues, improving overall stability and storage efficiency, and making it suitable for high-density memory applications such as RRAM. Summary of the Invention
[0007] This invention proposes a three-dimensional integrated architecture based on 2FnSnR and its process implementation method, aiming to further improve the storage density of resistive random access memory (RRAM), phase-change memory (PCRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM), and optimize cell structure and performance. Compared with the 1TnSnR structure, 2FnSnR significantly improves the integration density of memory cells while maintaining excellent electrical performance through the use of biphasic transistors (see SKGupta, SPPark, NNMojumder and K. Roy, "Layout-aware optimization of sttmrams," 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2012, pp. 1455-1458, doi:10.1109 / DATE.2012.6176595.) design and innovative circuit connection methods.
[0008] The three-dimensional memory architecture of this invention constructs one or more 2FnSnR memory cells on a base (hereinafter referred to as a 2F base) containing a two-finger transistor (2F). Each 2FnSnR memory cell includes a two-finger transistor structure and n parallel 1S1R memory cells, which are connected through the common drain of the two-finger transistor. The 1S1R memory cells are composed of a self-selection characteristic structure (S) and a resistive switching structure (R). In this architecture, the two-finger transistor design improves the control capability of the MOSFET, enabling it to maintain stable drive current and read / write characteristics when connected to n 1S1R memory cells.
[0009] Specifically, the 1S1R memory cell is electrically connected through drain lines and bit lines, and each overlapping area of a drain line and a bit line defines a 1S1R memory cell. The functional layer of the 1S1R memory cell can be implemented by superimposing a resistive switching layer and a gating layer or by implementing a self-selection function through a self-selection layer. This is a well-known technology in the art and will not be described in detail here.
[0010] In the 2FnSnR structure of this invention, the dual-finger transistor design enables higher density integration per unit area for each memory cell. According to the 2FnSnR circuit structure design of this invention, the dual-finger transistor effectively distributes the current load, ensuring stable write and read performance. Unlike the traditional single-finger design (1TnSnR), the dual-finger transistor divides the gate width of a transistor into two parallel gate "fingers," each with a width half (1 / 2W) of the original transistor gate width. While maintaining the same driving capability, this design significantly reduces the cell area, thereby improving integration density while optimizing the read / write speed and efficiency of the memory cell.
[0011] The 2F base arranges multiple bi-finger transistors on the xy horizontal plane and stacks 1S1R memory cells in multiple layers in the z direction to form a three-dimensional memory architecture including multiple 2FnSnR memory cells. For each 2FnSnR memory cell in the three-dimensional stack, multiple 1S1R memory cells in the same layer are connected in parallel through horizontal drain lines, while 1S1R memory cells in different layers are vertically electrically connected through interlayer vias. Each layer contains at least one 1S1R memory cell, and multiple layers are stacked to form a high-density three-dimensional memory architecture. One end electrode of the bottom 1S1R memory cell is electrically connected to the drain of the 2F base through contact and vias to ensure that the nSnR structure is isolated from and precisely aligned with the 2F base, thereby optimizing the signal transmission path and maintaining stable electrical performance.
[0012] The 2F base can contain multiple 1S1R memory cells. One electrode of each 1S1R memory cell is electrically connected to the drain of the 2F base, and the other electrode is connected to the corresponding bit line, forming a parallel connection. In this multi-layer stacked structure, the 2F base can simultaneously control the read and write operations of multiple 1S1R memory cells, achieving efficient current control over multiple memory cells. Through multi-layer stacking and a dual-finger transistor structure, the 2FnSnR architecture can provide extremely high storage density, significantly improving the integration and performance of the memory.
[0013] Therefore, the 2FnSnR three-dimensional integrated architecture proposed in this invention can further improve the storage density of new memory such as RRAM while maintaining good driving characteristics and anti-interference capabilities, providing an efficient and stable solution for embedded and stand-alone memory and meeting the needs of high-density storage applications.
[0014] Figure 1 The basic structure of a 2FnSnR memory cell is shown. A 2FnSnR memory cell consists of a dual-finger transistor (2F) and multiple parallel 1S1R memory cells. These parallel 1S1R memory cells can be stacked in multiple layers perpendicular to the 2F base, with each layer containing at least one 1S1R memory cell. The dual-finger transistor employs a common-source, common-drain structure, where a drain line (DL) is led out from the drain, a source line (SL) is led out from the source, and each of the two gates leads out a word line (WL). Multiple bit lines (BL) corresponding to the number of 1S1R memory cells in each layer are also led out. The dual-finger design not only saves area but also allows for greater drive current by setting an appropriate gate width, improving transistor control capability. It maintains stable drive current and read / write performance when multiple 1S1R memory cells are connected in parallel, ensuring the stability of high-density storage and supporting larger array sizes.
[0015] Figure 2 Electrical connection details of the 2FnSnR memory cell array are provided. Multiple bifinite transistors are arranged in an array on the 2F base, with each bifinite transistor forming a 2FnSnR memory cell with n parallel 1S1R memory cells stacked in multiple layers above it. In the y-direction, the bifinite transistors of adjacent 2FnSnR memory cells share a source line (SL); while in the x-direction, the bifinite transistors of adjacent 2FnSnR memory cells share a source line (SL) and a word line (WL). Multiple 1S1R memory cells located on the same layer and aligned along the x-direction share a bit line (BL). During array operation, an operating voltage is applied to the bit line BL corresponding to the selected 1S1R memory cell, and the bifinite transistors on the 2F base are turned on through the word line, making the 1S1R memory cell connected to its drain and source, thus enabling read, write, and erase operations. This method allows access to any memory cell within the array. Correspondingly, multiple BLs can be selected simultaneously or multiple bifinite transistors can be turned on to achieve parallel operation.
[0016] Figure 3 The diagram shows horizontal cross-sectional views of a 3D array of the 2FnSnR architecture at different heights along the z-axis for each layer. Figure A shows a horizontal cross-sectional view of the bifinger transistors, with adjacent bifinger transistors sharing a source line SL in the y-axis and a word line WL in the x-axis. Figure B shows multiple drain lines DL extending along the y-axis, which connect multiple 1S1R memory cells and vias in parallel. The drain lines are connected to the drain terminals of the bifinger transistors on the 2F base vias. Figure C shows multiple bit lines BL extending along the x-axis, which connect multiple 1S1R memory cells in parallel, illustrating the connection structure between the bit lines and the 1S1R memory cells.
[0017] Figure 4 A three-dimensional array structure cross-section of the 2FnSnR architecture is shown. (Example) Figure 4 As shown, the 1S1R memory cells in the same layer are arranged along the x and y directions, and the 1S1R memory cells in adjacent layers are staggered and connected to the drain of the 2F base through a through hole along the z direction.
[0018] This invention also provides a fabrication process for a three-dimensional memory architecture based on the aforementioned 2FnSnR structure, including stacking 1S1R memory cells on a 2F base containing bi-fingered transistors, see [link to documentation]. Figure 5 The preparation steps are as follows:
[0019] S1: Based on CMOS logic technology, the 2F base is fabricated, word lines leading out from the gate of the dual-finger transistor are formed along the x direction, a first insulating dielectric layer is deposited on the 2F base, and then the pattern is formed and vias are set.
[0020] S2: Deposit a second insulating dielectric layer on the first insulating dielectric layer, then visualize the image, deposit a source line in the second insulating dielectric layer along the x direction, and deposit a drain line to bring out the common drain of the 2F base;
[0021] S3: Deposit a third insulating dielectric layer on the second insulating dielectric layer, then visualize it, and open a first through-hole in the third insulating dielectric layer so that it contacts the drain line in the second insulating dielectric layer;
[0022] S4: Deposit a fourth insulating dielectric layer on the third insulating dielectric layer and visualize it. Set a bit line along the x direction on the fourth insulating dielectric layer and set a drain line to contact the first through hole.
[0023] S5: Deposit a fifth insulating dielectric layer on the fourth insulating dielectric layer and visualize it. Form a 1S1R memory cell in the fifth insulating dielectric layer by setting a gate layer and a resistive switching layer or a self-selection layer, and open a second via to make it contact the drain line in the third insulating dielectric layer.
[0024] S6: Deposit a sixth insulating dielectric layer on the fifth insulating dielectric layer and visualize it. Set a bit line along the x direction and a drain line along the y direction on the sixth insulating dielectric layer so that it contacts the second via and all 1S1R memory cells in the fifth insulating dielectric layer to form an electrical parallel connection.
[0025] Repeat steps S5-S6 m times (m ≥ 1). When performing the last step S6, only set the drain line and not the bit line to complete the fabrication of the 3D 2FnSnR structure.
[0026] In this technical solution, after each layer is deposited, a planarization process (CMP) is used.
[0027] In steps S1-S6 above, the insulating dielectric layer is preferably silicon oxide (SiO2) or a low-dielectric-constant material (Low-K dielectric), such as porous SiO2, porous SiCOH, USG (undoped silica), BPSG (borophosphosilicate glass), or one or more combinations thereof, including multilayer structures or mixtures of multilayer materials. The preferred fabrication process is chemical vapor deposition (CVD), including but not limited to APCVD, PECVD, LPCVD, etc., with a dielectric layer thickness of 20-2500 nm. The materials of different insulating dielectric layers can be the same or different.
[0028] In the above process steps, the preferred materials for the source line, drain line, bit line, and word line are vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), aluminum titanium nitride (TiAlN), and aluminum oxide (AlO). x One or more of the following: hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), palladium (Pd), copper (Cu), and their alloys, including multilayer structures or mixtures of multilayer materials, or doped polycrystalline silicon materials, preferably prepared by physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), wherein the thickness of the midline layer and drain layer is 20-2500 nm.
[0029] In the above process step S5, the preferred material for the selection layer or self-selection layer is niobium oxide (NbO). x ), Vanadium oxide (VO) x One or more of these, including multilayer structures or mixtures of multilayer materials, are used. Preferred preparation processes include oxidation or atomic layer deposition (ALD), physical vapor deposition (PVD), or thermal oxidation. Alternatively, the material may be doped, with doping elements preferably being one or more of Al, Cu, Au, Ti, etc. Preferred doping processes are ion implantation (IMP) and co-sputtering (Co-Sputter). Self-selective layers can achieve the functionality of traditional multilayer 1S+1R memory cells in a single thin film, possessing significant application potential. The material composition for preparing the selector layer varies slightly.
[0030] The preferred material for the resistive switching layer is tantalum oxide (TaO). x Titanium oxide (TiO) x) Hafnium oxide (HfO) x Zirconium oxide (ZrO)x ), silicon dioxide (SiO) x (e.g., and alloys thereof), including multilayer structures or mixtures of multilayer materials. Preferred preparation processes include oxidation, physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0031] The preferred materials for vias and through holes in the above process steps are Cu, W, Al, TiN, TaN, titanium tungsten (TiW), and titanium aluminum tungsten (TiAlW), and the preferred preparation processes are electroplating, CVD, and ALD.
[0032] The above-mentioned imaging process includes photolithography and etching techniques, among which the preferred etching processes are dry etching processes such as RIE (Reactive Ion Etching) and ICP (Inductively Coupled Plasma).
[0033] The hyphenated chemical composition notation used herein indicates the elements contained in a particular compound or alloy and is intended to represent all stoichiometry involving the indicated elements. Attached Figure Description
[0034] Figure 1 A schematic diagram of the structure of the 2FnSnR memory cell of the present invention.
[0035] Figure 2 The circuit connection schematic diagram of the 2FnSnR memory cell array of this invention.
[0036] Figure 3 The present invention provides horizontal cross-sectional views of the three-dimensional memory architecture at different heights in the z-direction. A shows a horizontal cross-sectional view of the two-finger transistor on the 2F base, B shows multiple drain lines DL extending along the y-direction, C shows multiple bit lines BL extending along the x-direction, and D is an illustration.
[0037] Figure 4 A longitudinal cross-sectional view of the 2FnSnR array structure of the three-dimensional memory architecture of this invention.
[0038] Figure 5 Flowchart of the 2FnSnR integration process method for the three-dimensional memory architecture of this invention. Detailed Implementation
[0039] The present invention will be further described below with reference to specific embodiments and accompanying drawings.
[0040] The 1S1R memory cell proposed in this embodiment is NbO. x Self-selected layer units, due to NbO x The self-assembly effect of NbO xThe thin film can simultaneously contain both volatile threshold switching regions and non-volatile resistive switching regions, thus enabling NbO... x A single-layer thin film directly achieves the 1S1R function. See also Figure 4 and Figure 5 Prepare a 2FnSnR memory cell array according to the following steps:
[0041] S1: Based on CMOS logic process, the 2F base is fabricated, word lines are set along the x direction, and a 2000nm USG is deposited on the 2F base as the first insulating dielectric layer using atmospheric pressure chemical vapor deposition (APCVD). Then, it is patterned, vias are formed using reactive ion etching (RIE), and W is filled using tungsten chemical vapor deposition (WCVD) to fabricate tungsten plugs.
[0042] S2: A 200nm USG layer is deposited on the first insulating dielectric layer using APCVD process as the second insulating dielectric layer. Then, the image is patterned, and reactive ion etching (RIE) is used to create grooves for source and drain lines. Cu source and drain lines are then deposited.
[0043] S3: A 50nm USG layer is deposited on the second insulating dielectric layer using APCVD process as the third insulating dielectric layer. Then, the image is patterned, a first via is opened using reactive ion etching (RIE), and a 50nm TiN layer is filled using ALD to fill the first via.
[0044] S4: A 50nm USG layer is deposited on the third insulating dielectric layer using APCVD as the fourth insulating dielectric layer. Then, the image is patterned, and grooves for drain lines and multiple bit lines along the x-direction are created using reactive ion etching (RIE). Finally, 50nm TiN is filled using ALD to realize the fabrication of drain lines and bit lines.
[0045] S5: A 50nm USG layer is deposited on the fourth insulating dielectric layer using APCVD as the fifth insulating dielectric layer. Then, the image is patterned, and reactive ion etching (RIE) is used to form the recesses for the 1S1R memory cells and the second vias in the fifth insulating dielectric layer. A 50nm NbO layer is then deposited using ALD. x 1S1R memory cells were fabricated using a self-selected layer, and TiN was used to fill the second via.
[0046] S6: A 50nm USG layer is deposited on the fifth insulating dielectric layer using APCVD process as the sixth insulating dielectric layer. Then, the image is visualized, and a groove is formed along the y-direction and along the x-direction using reactive ion etching (RIE). Finally, a 50nm TiN layer is filled using ALD process to realize the fabrication of the drain line and the bit lines.
[0047] S7: A 50nm USG layer is deposited on the sixth insulating dielectric layer using APCVD as the seventh insulating dielectric layer. Then, the image is patterned, and reactive ion etching (RIE) is used to create the recesses for the 1S1R memory cells and the third via. A 50nm NbO layer is then deposited using ALD. x 1S1R memory cells were fabricated using a self-selected layer, and TiN was used to fill the third via.
[0048] S8: A 50nm USG layer is deposited on the seventh insulating dielectric layer using APCVD process as the eighth insulating dielectric layer. Then, the image is visualized, and a groove for a drain line along the y direction and multiple bit lines along the x direction is formed using reactive ion etching (RIE). The groove is then filled with 50nm TiN using ALD to realize the fabrication of the drain line and bit lines.
[0049] S9: A 50nm USG layer is deposited on the eighth insulating dielectric layer using APCVD as the ninth insulating dielectric layer. Then, the image is patterned, and reactive ion etching (RIE) is used to create the recesses for the 1S1R memory cells and the fourth via. A 50nm NbO layer is then deposited using ALD. x 1S1R memory cells were fabricated using a self-selected layer, and the fourth via was filled with TiN.
[0050] S10: A 50nm USG layer is deposited on the ninth insulating dielectric layer using APCVD process as the tenth insulating dielectric layer. Then, the image is visualized, and a groove for a drain line is formed along the y direction using reactive ion etching (RIE). The groove is then filled with 50nm TiN using ALD to realize the fabrication of the drain line. Finally, the fabrication of the 2FnSnR memory architecture is completed.
[0051] In this embodiment, after each layer is deposited, a planarization process is performed using CMP (Chemical Mechanical Polishing).
[0052] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.
Claims
1. A CMOS three-dimensional memory architecture, comprising constructing one or more 2FnSnR memory cells on a base containing a bifinite transistor, each 2FnSnR memory cell containing a bifinite transistor and n parallel 1S1R memory cells, where n is an integer greater than 1; the bifinite transistor adopts a common source and common drain structure, with a drain line led out from its drain, a source line led out from its source, and a word line led out from each of its two gates; one end electrode of the n 1S1R memory cells is connected to the drain line, and the other end electrode is connected to the corresponding bit line, forming a parallel relationship.
2. The CMOS three-dimensional memory architecture as described in claim 1, characterized in that, The base has multiple bi-finger transistors arranged on the xy horizontal plane and multiple layers of 1S1R memory cells stacked in the z direction. Each layer contains at least one 1S1R memory cell, forming a three-dimensional memory architecture including multiple 2FnSnR memory cells. For each 2FnSnR memory cell, multiple 1S1R memory cells in the same layer are connected in parallel through horizontal drain lines, while 1S1R memory cells in different layers are vertically electrically connected through interlayer vias.
3. The CMOS three-dimensional memory architecture as described in claim 2, characterized in that, Multiple bidigital transistors are arranged in an array on the base. Each bidigital transistor and n parallel 1S1R memory cells stacked in multiple layers above it form a 2FnSnR memory cell. In the y-direction, the bidigital transistors of adjacent 2FnSnR memory cells share a source line. In the x-direction, the bidigital transistors of adjacent 2FnSnR memory cells share a source line and a word line. Multiple 1S1R memory cells located on the same layer and aligned along the x-direction share a bit line.
4. The CMOS three-dimensional memory architecture as described in claim 3, characterized in that, The 1S1R memory cells in the same layer are arranged along the x and y directions, and the 1S1R memory cells in adjacent layers are staggered and connected to the drain of the bi-finger transistor on the base through a via along the z direction.
5. A method for fabricating a CMOS three-dimensional memory architecture according to any one of claims 1 to 4, comprising the following steps: S1: A base containing a dual-finger transistor is fabricated based on CMOS technology, and word lines leading out from the gate of the dual-finger transistor are formed along the x-direction; A first insulating dielectric layer is deposited on the base, then patterned and vias are set; S2: Deposit a second insulating dielectric layer on the first insulating dielectric layer and visualize it. Deposit a source line along the x-direction in the second insulating dielectric layer and deposit a drain line to bring out the drain of the bi-finger transistor on the base. S3: Deposit a third insulating dielectric layer on the second insulating dielectric layer and visualize it, and open a first through hole in the third insulating dielectric layer so that it contacts the drain line in the second insulating dielectric layer; S4: Deposit a fourth insulating dielectric layer on the third insulating dielectric layer and visualize it. Set a bit line along the x direction on the fourth insulating dielectric layer and set a drain line to contact the first through hole. S5: Deposit a fifth insulating dielectric layer on the fourth insulating dielectric layer and visualize it; provide a 1S1R memory cell in the fifth insulating dielectric layer; and open a second through-hole to make it contact the drain line in the third insulating dielectric layer. S6: Deposit a sixth insulating dielectric layer on the fifth insulating dielectric layer and visualize it. Set a bit line along the x direction and a drain line along the y direction on the sixth insulating dielectric layer and make it contact the second via and all 1S1R memory cells in the fifth insulating dielectric layer to form an electrical parallel connection. Repeat steps S5-S6 m times, where m≥1. In the last step S6, only the drain line is set, and the bit line is not set, to complete the fabrication of the CMOS three-dimensional memory architecture.
6. The preparation method according to claim 5, characterized in that, In steps S1-S6, a low dielectric constant material is deposited as an insulating dielectric layer using chemical vapor deposition; after each layer is deposited, a chemical mechanical polishing process is used for planarization.
7. The preparation method according to claim 6, characterized in that, The low dielectric constant material is selected from one or more of SiO2, SiCOH, USG, and BPSG, and the thickness of the deposited insulating dielectric layer is 20-2500 nm.
8. The preparation method according to claim 5, characterized in that, The source lines, drain lines, bit lines, and word lines are made of materials selected from V, Nb, Ru, W, Ta, TaN, Ti, TiN, TiW, Al, TiAlW, TiAlN, and AlO. x The material is selected from one or more of Hf, Ir, Mn, Zn, Pd, and Cu, or doped with polycrystalline silicon; the through-hole and via material is selected from one or more of Cu, W, Al, TiN, TaN, TiW, and TiAlW.
9. The preparation method according to claim 5, characterized in that, In step S5, a 1S1R memory cell is formed by setting a gate layer and a resistive switching layer, or by setting a self-selection layer; the material of the gate layer or the self-selection layer is niobium oxide and / or vanadium oxide. The resistive switching layer is made of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or silicon oxide.
10. The operation method of the CMOS three-dimensional memory architecture according to any one of claims 1 to 4, wherein an operating voltage is applied to the bit line corresponding to the selected 1S1R memory cell, and the dual-finger transistor on the base is turned on through the word line, so that the 1S1R memory cell is connected to the drain and source, thereby realizing read, write and erase operations.