Gallium nitride power device and preparation method thereof

Abstract

The invention discloses a gallium nitride power device and a preparation method of the gallium nitride power device. The gallium nitride power device comprises a substrate; the buffer layer is arranged on one side of the substrate; the channel layer is arranged on the side, away from the substrate, of the buffer layer; the barrier layer is arranged on the side, away from the buffer layer, of the channel layer, and the barrier layer and the channel layer can generate two-dimensional electron gas; the gate structure, the source electrode and the drain electrode are arranged on the side, away from the channel layer, of the barrier layer at intervals, and the source electrode and the drain electrode are located on the two sides of the gate structure; wherein the barrier layer between the gate structure and the drain is provided with a first hollow part, the thickness of the first hollow part is the same as that of the barrier layer, and the first hollow part is etched between the gate and the drain of the barrier layer, so that the current leakage between the gate and the drain can be effectively inhibited, the virtual gate effect is relieved, and the reliability of the device is improved. Current collapse caused by 2DEG electrons captured by an AlGaN barrier layer and a surface defect trap and a channel hot electron effect is improved, and the voltage withstanding performance and the reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a gallium nitride power device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, exhibits significant advantages in characteristics compared to traditional silicon (Si)-based semiconductor materials. Its large bandgap, low intrinsic carrier concentration, and high critical breakdown field strength allow GaN devices to withstand higher applied voltages per unit length of drift region. Furthermore, the AlGaN / GaN heterojunction generates a two-dimensional electron gas (2DEG) with high electron concentration and high migration velocity due to polarization effects, resulting in excellent current handling capabilities and low on-resistance, which contributes to improved overall energy efficiency. These characteristics determine its broad application prospects in power switching devices.

[0003] Currently, although AlGaN / GaN devices have made great progress in microwave and high-power device characteristics, there is still an important constraint, namely the current collapse effect; in addition, the current leakage between the gate and drain is also a problem affecting the gate control capability, device withstand voltage capability and reliability. Summary of the Invention

[0004] The gallium nitride power device and its fabrication method provided in this application effectively suppress current leakage between the gate and drain and improve the current collapse effect, thereby improving the device's withstand voltage performance and reliability.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a gallium nitride power device, including a substrate;

[0006] A buffer layer is disposed on one side of the substrate;

[0007] A channel layer is disposed on the side of the buffer layer opposite to the substrate;

[0008] A barrier layer is disposed on the side of the channel layer opposite to the buffer layer, and the barrier layer and the channel layer can generate a two-dimensional electron gas;

[0009] A gate structure, a source, and a drain are disposed at intervals on the side of the barrier layer away from the channel layer, and the source and the drain are located on opposite sides of the gate structure; wherein, the barrier layer located between the gate structure and the drain has a first cutout portion, the thickness of the first cutout portion is the same as the thickness of the barrier layer, and the thickness direction is the direction from the substrate to the buffer layer.

[0010] In one embodiment, the channel layer located between the gate structure and the drain has a second cutout portion, which is disposed corresponding to the first cutout portion, and the thickness of the second cutout portion is less than or equal to the thickness of the channel layer.

[0011] In one embodiment, the first hollow portion and / or the second hollow portion have an inverted trapezoidal structure.

[0012] In one embodiment, when the thickness of the second cutout is less than the thickness of the channel layer, a carrier high-resistivity layer is included between the buffer layer and the channel layer.

[0013] In one embodiment, the carrier high-resistivity layer is an undoped gallium oxide semiconductor layer.

[0014] In one embodiment, when the thickness of the second cutout is equal to the thickness of the channel layer, a carrier drift layer disposed between the buffer layer and the channel layer is further included.

[0015] In one embodiment, the carrier drift layer is a heavily doped gallium oxide semiconductor layer.

[0016] To solve the above-mentioned technical problems, the second technical solution provided in this application is: a method for fabricating a gallium nitride power device, comprising: providing a substrate;

[0017] A buffer layer is formed on one side of the substrate;

[0018] A channel layer is formed on the side of the buffer layer opposite to the substrate;

[0019] A barrier layer with a first cutout is formed on the side of the communication layer opposite to the buffer layer, which generates a two-dimensional electron gas with the channel layer. The thickness of the first cutout is the same as the thickness of the barrier layer. The barrier layer defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region. The first cutout is located between the gate structure region and the drain region.

[0020] The gate, source, and drain regions on the side of the barrier layer away from the buffer layer are respectively formed as the gate, source, and drain.

[0021] In one embodiment, before forming a barrier layer with a first hollow portion that generates a two-dimensional electron gas with the channel layer on the side of the communication layer opposite to the buffer layer, a second hollow portion is formed in the channel layer, the thickness of the second hollow portion being less than or equal to the thickness of the channel layer, and the second hollow portion being disposed corresponding to the first hollow portion.

[0022] In one embodiment, when the thickness of the second cutout is equal to the thickness of the channel layer, the channel layer is formed on the side of the buffer layer opposite to the substrate before...

[0023] A carrier drift layer is formed on the side of the buffer layer opposite to the substrate.

[0024] The beneficial effects of this application are as follows: Unlike the prior art, this application discloses a gallium nitride (GaN) power device and a method for fabricating the GaN power device. The GaN power device includes a substrate; a buffer layer disposed on one side of the substrate; a channel layer disposed on the side of the buffer layer away from the substrate; a barrier layer disposed on the side of the channel layer away from the buffer layer, and the barrier layer and the channel layer can generate a two-dimensional electron gas; a gate structure, a source, and a drain, which are disposed at intervals on the side of the barrier layer away from the channel layer, and the source and drain are located on opposite sides of the gate structure; wherein the barrier layer located between the gate structure and the drain has a first hollow portion, the thickness of the first hollow portion is the same as the thickness of the barrier layer, and the thickness direction is from the substrate to the buffer layer. By etching the first hollow portion between the gate and the drain of the barrier layer, the current leakage between the gate and drain can be effectively suppressed, the virtual gate effect can be alleviated, the current collapse caused by the trapping of 2DEG electrons by the AlGaN barrier layer and surface defect state traps and the channel hot electron effect can be improved, and the breakdown voltage performance and reliability of the device can be improved. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a gallium nitride power device provided in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the structure of a gallium nitride power device provided in another embodiment of this application;

[0028] Figure 3 This is a schematic diagram of the structure of a gallium nitride power device provided in another embodiment of this application;

[0029] Figure 4 This is a schematic flowchart of a method for fabricating a gallium nitride power device according to an embodiment of this application;

[0030] Figure 5 yes Figure 4 The diagram shows the structure of step S01.

[0031] Figure 6 yes Figure 4 The flowchart of step S02 is shown below;

[0032] Figure 7 yes Figure 4 The diagram shows the structure of step S03.

[0033] Figure 8 yes Figure 4 A schematic diagram of the intermediate structure in step S04 is shown.

[0034] Figure 9 yes Figure 4 A schematic diagram of the intermediate structure in step S04 is shown.

[0035] Figure 10 yes Figure 4 The diagram shows the structure of step S04.

[0036] Figure 11 This is a schematic flowchart of a method for fabricating a gallium nitride power device according to another embodiment of this application; Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0038] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0039] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the stated features. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of components in a specific posture (as shown in the figures). If the specific posture changes, the directional indications also change accordingly. The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or components inherent to these processes, methods, products, or devices.

[0040] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0041] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0042] Gallium nitride-based high electron mobility gallium nitride power devices (GaN HEMTs) have shown great potential in high-efficiency power conversion and high-frequency communication due to their excellent physical properties.

[0043] However, during the operation of gallium nitride (GaN) high-voltage devices, electrons are trapped by traps within GaN itself, leading to increased on-resistance and decreased current density. Current collapse is divided into drain delay and gate delay. The former is generally considered to be related to traps in the GaN buffer layer and barrier layer, and its influence will become smaller with improvements in epitaxial and doping processes. The latter is mainly caused by surface states in the barrier layer, which are related to the polarization charge and band structure of the heterojunction surface. The trapping of electrons by surface states between the gate and drain to form a virtual gate, as well as the trapping of electrons by bulk defects in the AlGaN barrier layer and hot electrons in the channel, are the main mechanisms causing current collapse, especially under high voltage conditions, these mechanisms can cause severe current collapse. In addition, current leakage between the gate and drain is also a problem affecting gate control capability, device withstand voltage capability, and reliability. Under high drain bias electrical stress, the AlGaN barrier layer and surface states trap electrons, and trap-assisted tunneling occurs under a strong electric field. Electrons jump between traps, forming a leakage channel from the drain to the gate.

[0044] To address gate-drain current leakage, current-based technologies primarily employ passivation techniques. By depositing a passivation layer on the AlGaN surface, the number of defect states on the barrier layer surface can be reduced, thereby suppressing surface leakage. To address current collapse effects, field plate structures and passivation techniques are widely used. The basic structure of a field plate involves depositing, photolithography, and etching a dielectric thin film around the gate and source electrodes, extending the gate or source electrode appropriately over the dielectric layer, thus forming a metal-insulator-semiconductor structure around the electrodes.

[0045] Among these techniques, the field plate structure alters the electric field distribution in the depletion layer by changing the curvature of the depletion layer boundary at the gate edge, thereby reducing the peak electric field intensity and improving the device's breakdown voltage. Passivation technology mitigates the current collapse effect by suppressing surface states and reducing leakage current. However, even combining these two techniques, it remains difficult to obtain GaN devices that meet the requirements under high voltage conditions.

[0046] To address the issues of current collapse and gate-drain current leakage in devices, this application provides an alternative solution, specifically a gallium nitride power device and a method for fabricating the gallium nitride power device, to improve current collapse and suppress gate-drain current leakage.

[0047] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the gallium nitride power device provided in the embodiments of this application.

[0048] The gallium nitride power device includes a substrate 10, a buffer layer 20, a channel layer 30, and a barrier layer 40 stacked sequentially. Specifically, the buffer layer 20 is disposed on one side of the substrate 10, the channel layer 30 is disposed on the side of the buffer layer 20 away from the substrate 10, and the barrier layer 40 is disposed on the side of the channel layer 30 away from the buffer layer 20. The gallium nitride power device also includes a drain 50, a source 60, and a gate structure 70.

[0049] The substrate 10 can be made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or sapphire (Al2O3), while the buffer layer 20 can be made of silicon carbide (SiC), aluminum gallium nitride (AlGaN), gallium nitride (GaN), or gallium oxide (Ga2O3). In the embodiments of this application, the substrate 10 is made of sapphire (Al2O3), and the buffer layer 20 is made of gallium oxide (Ga2O3). Since both Ga2O3 and Al2O3 have a corundum structure, the purpose of growing the gallium oxide (Ga2O3) buffer layer on the sapphire (Al2O3) substrate is to reduce the lattice mismatch coefficient, thermal expansion coefficient, and dislocation density, thereby reducing the probability of leakage current channel formation. At the same time, gallium oxide (Ga2O3) material itself has a larger bandgap, lower intrinsic carrier concentration, and higher critical breakdown field strength than GaN, making it more difficult to form leakage current channels, which can suppress current leakage and improve the device's withstand voltage capability. In other embodiments, the substrate 10 may also include a transition layer, such as using an AlGaN material as the transition layer.

[0050] In this embodiment, a two-dimensional electron gas (2DEG) is formed between the interface of the channel layer 30 and the barrier layer 40 to serve as a carrier migration channel for the device. In this embodiment, the material of the channel layer 30 includes GaN, and the material of the barrier layer 40 includes AlGaN.

[0051] The gate structure 70, source 60, and drain 50 are disposed at intervals on the side of the barrier layer 40 away from the substrate 10, and the source 50 and drain 60 are located on opposite sides of the gate structure 70.

[0052] In one embodiment, see further. Figure 1 The gate structure 70 includes a capping layer 71 and a gate 72. The capping layer 71 is disposed between the gate 72 and the barrier layer 40. Taking a gallium nitride power device as an enhancement-mode device as an example, the capping layer 71 serves as a p-type nitride gate layer. The capping layer 71 is also used to deplete the 2DEG under the gate structure 70 to form an enhancement-mode device. Specifically, the material of the capping layer 71 includes, but is not limited to, p-GaN, p-AlGaN, p-InGaN, or p-InAlGaN, etc., and is not limited here.

[0053] In other embodiments, the gate structure 70 may not include the capping layer 71, thereby making the gallium nitride power device a depletion-type device.

[0054] The gate 72, source 60, and drain 50 are formed of conductive metal material and are used for electrical connection with external circuits. In some embodiments, the conductive metal system of the gate 72, source 60, and drain 50 includes, but is not limited to, Ti, Al, Ni, Au, or Ta, as well as alloys or compounds containing the above metal systems.

[0055] The epitaxial layer located between the gate structure 70 and the drain 50 is defined as the cutout region A1. The barrier layer 40 between the gate structure 70 and the drain 50 has a first cutout portion 41, that is, the first cutout portion 41 is located in the cutout region A1, and the thickness of the first cutout portion 41 is the same as the thickness of the barrier layer 41. The thickness direction is from the substrate 10 to the buffer layer 20.

[0056] It is understood that the epitaxial layer in this application includes a buffer layer 20, a channel layer 30, and a barrier layer 40.

[0057] Specifically, on the one hand, under gate bias, the surface states and bulk defects of the barrier layer 40 will trap 2DEG electrons and form a dummy gate between the drain 50 and the gate structure 70. This will cause current leakage and depletion of 2DEG between the gate structure 70 and the drain 50, reducing the current density. On the other hand, under drain bias, the channel is in a high electric field, and 2DEG electrons get enough energy to overflow the channel and accumulate on the surface states of the barrier layer 40 between the gate structure 70 and the drain 50 to form a dummy gate. In this embodiment, the barrier layer 40 has a first cutout portion 41, and the thickness of the first cutout portion 41 is the same as the thickness of the barrier layer 41. That is, the barrier layer 40 in the area where the first cutout portion 41 is located is etched away. The carriers migrate through the channel layer 30, so that the area where the first cutout portion 41 is located will not generate 2EDG due to polarization effect, so that no electrons are captured or overflowed. At the same time, there is no surface state of the barrier layer capturing and releasing electrons and holes, so that there is no negative charge accumulation phenomenon between the gate structure 70 and the drain 50, so that no virtual gate effect is formed, and thus no current collapse is caused. In addition, etching away the area where the first cutout portion 41 of the barrier layer 40 is located can effectively suppress the current leakage between the gate and the drain caused by the carrier drift through the interface state of the barrier layer 40 and the channel layer 30 and the 2DEG channel.

[0058] The virtual gate effect refers to the phenomenon in GaN HEMT devices where, due to the trap effect, leaked electrons fill the traps on the device surface, forming a virtual gate. This virtual gate can affect the depletion region, further depleting electrons in the channel and ultimately leading to current collapse. This application reduces the virtual gate effect between the gate structure 70 and the drain 50, thus improving device stability.

[0059] In one embodiment, reference Figure 2 and Figure 3 The channel layer 40 between the gate structure 70 and the drain 50 has a second cutout portion 31, which is correspondingly disposed to the first cutout portion 41. That is, the second cutout portion 31 is also located in the cutout region A1, and the thickness of the second cutout portion 31 is less than or equal to the thickness of the channel layer 30. In other words, the channel layer 30 in the region where the second cutout portion 31 is located can be completely or only partially etched away. By etching the first cutout portion 41 and the second cutout portion 31 between the gate and the drain, the current leakage between the gate and drain can be effectively suppressed, the virtual gate effect can be alleviated, the current collapse caused by the trapping of 2DEG electrons by the AlGaN barrier layer and surface defect state traps and the channel hot electron effect can be improved, and the breakdown voltage performance and reliability of the device can be improved.

[0060] In one embodiment, the thickness of the channel layer 40 can be in the range of 200 nm, and the thickness of the second cutout portion 31 can be in the range of 50 nm to 200 nm. For example, the thickness of the second cutout portion 31 can be 50 nm, 100 nm, 150 nm, or 200 nm, etc., and is not limited here. It can be set according to the actual situation.

[0061] Specifically, considering that when the first cutout portion 41 is formed in the barrier layer 40 due to process limitations, the barrier layer 40 material will remain on the surface of the channel layer 30, affecting the improvement of device performance, setting the thickness of the second cutout portion 31 to 50nm can avoid the residual barrier layer 40 material on the surface of the channel layer 30.

[0062] Optionally, the thickness of the second cutout portion is 200 nm, meaning that the channel layer 30 in the region where the second cutout portion 31 is located is completely etched away. At the current process level, the channel layer 30 is typically a GaN layer, which has certain defects. When electrons or holes are trapped by defect states, the on-resistance increases, and the accumulation of charge increases the electric field strength, causing the device to break down prematurely. Therefore, completely etching away the region where the second cutout portion 31 is located in the channel layer 30 reduces the probability of premature device breakdown.

[0063] In one implementation, continue to refer to Figure 2 When the thickness of the second cutout portion 31 is less than the thickness of the channel layer 30, such as when the thickness of the channel layer 30 is 200 nm, the thickness of the second cutout portion 31 is 50 nm or 100 nm. The gallium nitride power device also includes a carrier high-resistivity layer 90 disposed between the buffer layer 20 and the channel layer 30. This carrier high-resistivity layer 90 serves to prevent carriers in the channel layer 30 from migrating downwards to the buffer layer 20, thereby suppressing the formation of leakage channels in the buffer layer 20 and improving the device's withstand voltage performance. Optionally, the carrier high-resistivity layer 90 includes α-Ga2O3, β-Ga2O3, ε-Ga2O3, or GaN materials, etc.

[0064] In one embodiment, the carrier high-resistivity layer 90 comprises an undoped gallium oxide semiconductor layer. (e.g., n) - α-Ga2O3, n - β-Ga2O3,n - ε-Ga₂O₃. Due to n - α-Ga2O3 material itself has a larger bandgap, lower intrinsic carrier concentration and higher critical breakdown field strength than GaN. It is difficult to form leakage channels in this material, which can suppress current leakage and improve the withstand voltage of the device.

[0065] Optionally, when the material of the buffer layer 20 includes n - In the case of α-Ga2O3, it is not necessary to form an additional carrier high-resistivity layer 90 between the buffer layer 20 and the channel layer 30 of the gallium nitride power device, as the buffer layer 20 itself can suppress current leakage.

[0066] In one implementation, continue to refer to Figure 3 When the thickness of the second cutout portion 31 is equal to the thickness of the channel layer 30, such as when the thickness of the channel layer 30 is 200 nm, the thickness of the second cutout portion 31 is also 200 nm. The gallium nitride power device also includes a carrier drift layer 80 disposed between the buffer layer 20 and the channel layer 30, which serves as a carrier migration channel. Optionally, the carrier drift layer 80 includes α-Ga2O3, β-Ga2O3, ε-Ga2O3, or GaN materials, etc.

[0067] In one embodiment, the carrier drift layer 80 is a heavily doped gallium oxide semiconductor layer. (e.g., n) + α-Ga2O3, n + β-Ga2O3,n + ε-Ga₂O₃, due to its higher bandgap, can withstand higher voltages, and its high density and few surface defects can improve the device's breakdown voltage. Meanwhile, when the material of the buffer layer 20 includes n... - In α-Ga₂O₃, the n of the carrier drift layer 80 + α-Ga2O3 and buffer layer 20 n - A potential barrier forms at the α-Ga2O3 interface. With high drain bias, the barrier height increases, making it difficult for carriers in the carrier drift layer 80 to move downwards, thus suppressing n. - The formation of leakage channels in the α-Ga2O3 buffer layer can improve the device's withstand voltage performance.

[0068] Optionally, when the material of the buffer layer 20 includes n -In the α-Ga₂O₃ configuration, an additional carrier drift layer 80 does not need to be formed between the buffer layer 20 and the channel layer 30 of the gallium nitride power device. This allows for an increase in the doping concentration of the buffer layer 20 near the channel layer 30, i.e., forming n-type carrier drift layers in the region of the buffer layer 20 near the channel layer 30. + The α-Ga2O3 region allows the buffer layer 20 to be closer to the channel layer 30 in terms of n + The α-Ga2O3 region serves as a migration channel for charge carriers.

[0069] In one embodiment, the second cutout portion 31 and / or the first cutout portion 41 has an inverted trapezoidal structure. Specifically, the width of the second cutout portion 31 and / or the first cutout portion 41 in the gate-to-drain direction gradually increases along the direction away from the substrate 10, and the angle between the two inclined side surfaces of the second cutout portion 31 and / or the first cutout portion 41 and the bottom surface of the second cutout portion 31 and / or the first cutout portion 41 is in the range of 90° to 180°, for example, 91°, 100°, 150° or 179°, to ensure that the second cutout portion 31 and / or the first cutout portion has an inverted trapezoidal shape. By setting the second cutout portion 31 and / or the first cutout portion 41 to an inverted trapezoidal structure, a more uniform film with better step coverage can be obtained on its upper surface when other layers are grown on the second cutout portion 31 and / or the first cutout portion 41.

[0070] Taking into account the difficulty of the process implementation and the subsequent structural growth, the angle between the two inclined sides of the second hollow part 31 and / or the first hollow part 41 and the bottom surface of the second hollow part 31 and / or the first hollow part 41 is 100°-140°.

[0071] In this application, "gradually increasing" means either a linear increase or a stepwise increase.

[0072] Understandably, the trapezoidal cutout has poor step coverage. In particular, if the second cutout 31 is a trapezoidal structure, when an AlGaN barrier layer 40 is formed on it, the AlGaN at the corner of the cutout is thinner than in other areas, and electrons tend to accumulate at the corner, resulting in a higher field strength and easy breakdown. At the same time, the formation of the second cutout 31 of the channel layer 30 mainly adopts dry etching process. Due to process limitations, dry etching cannot etch out a trapezoidal groove.

[0073] It should be noted that the wider the second cutout portion 31 and / or the first cutout portion 41 are, the better, as long as they are located within the cutout area A1.

[0074] In one embodiment, reference Figure 3The gallium nitride power device also includes a passivation layer 100 disposed on the side of the barrier layer 40 facing away from the substrate 10. The passivation layer 100 is beneficial for repairing interface damage of the second cutout portion 31 or the first cutout portion 41. Optionally, the passivation layer may include materials such as SiO2, Si3N4, or Al2O3.

[0075] Specifically, the gallium nitride power device provided in this application, by etching away the barrier layer 40 in the region where the first hollow portion 41 is located, prevents the generation of 2EDG in the region due to polarization effect, thus preventing electrons from being captured or overflowing. At the same time, there is no capture and release of electrons and holes by the surface states of the barrier layer, and no negative charge accumulation phenomenon occurs between the gate structure 70 and the drain 50, thus preventing the formation of a virtual gate effect and preventing current collapse. In addition, etching away the region where the first hollow portion 41 of the barrier layer is located can effectively suppress the current leakage between the gate and the drain caused by carrier drift through the interface states of the barrier layer 40 and the channel layer 30 and the 2DEG channel, thereby effectively suppressing the current leakage between the gate and the drain and improving the current collapse effect, thereby improving the device's withstand voltage performance and reliability.

[0076] Please see Figures 4 to 11 , Figure 4 This is a schematic flowchart illustrating the fabrication method of the gallium nitride power device provided in the embodiments of this application. Figure 5 yes Figure 4 The diagram shown is a structural schematic of step S01. Figure 6 yes Figure 4 The diagram shown is a structural schematic of step S02. Figure 7 yes Figure 4 The diagram shown is a structural schematic of step S03. Figures 8 to 10 yes Figure 4 The diagram shows the structure of step S04. Figure 11 This is a schematic flowchart of a method for fabricating a gallium nitride power device according to another embodiment of this application.

[0077] The method for fabricating gallium nitride (GaN) power devices provided in this application can be used to fabricate the GaN power devices provided in the above embodiments. The method for fabricating GaN power devices provided in this application includes:

[0078] Step S01: Provide substrate 10.

[0079] In one embodiment, the substrate 10 comprises sapphire (Al2O3).

[0080] Step S02: A buffer layer 20 is formed on one side of the substrate 10.

[0081] In one embodiment, the buffer layer 20 comprises gallium oxide (Ga2O3).

[0082] Step S03: Form a channel layer 30 on the side of the buffer layer 20 away from the substrate 10.

[0083] Step S04: A barrier layer 40 is formed on the side of the channel layer 30 away from the buffer layer 20, which generates a two-dimensional electron gas with the channel layer 30 and has a first cutout portion 41. The thickness of the first cutout portion 41 is the same as the thickness of the barrier layer 40. The barrier layer 40 defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region. The first cutout portion 41 is located between the gate structure region and the drain region.

[0084] In one embodiment, the channel layer 30 comprises GaN, and the barrier layer 40 comprises AlGaN.

[0085] Step S05: A gate 72, a source 60, and a drain 50 are formed in the gate structure region, source region, and drain region on the side of the barrier layer 40 away from the buffer layer 20, respectively.

[0086] In one embodiment, a barrier layer 40 is formed on the side of the channel layer 30 opposite to the buffer layer 20, which generates a two-dimensional electron gas with the channel layer 30 and has a first perforation 41, specifically including:

[0087] Step S041: Form a barrier layer 40 on the side of the channel layer 30 away from the buffer layer 20 to generate a two-dimensional electron gas with the channel layer 30;

[0088] Step S042: A capping layer 71 is formed on the side of the barrier layer 40 away from the buffer layer 20 and at a position corresponding to the gate structure region;

[0089] Step S043: A first cutout 41 is formed between the gate structure region and the drain region of the barrier layer 40.

[0090] Specifically, the gate structure 70 includes a capping layer 71 and a gate 72. The capping layer 71 is disposed between the gate 72 and the barrier layer 40. In one embodiment, the material of the capping layer 71 includes p-GaN. In other embodiments, the material of the capping layer 71 may also include p-AlGaN, p-InGaN, or p-InAlGaN, etc., and is not limited here.

[0091] Specifically, such as Figures 5 to 10First, a substrate 10 is formed, then a buffer layer 20 is grown on the substrate, and then a channel layer 30, a barrier layer 40, and a p-GaN layer 701 are epitaxially grown on the substrate by MOCVD. That is, from bottom to top, they are α-Al2O3, α-N-Ga2O3, GaN layer, AlGaN layer, and p-GaN layer. Next, the p-GaN layer other than the gate structure 70 is etched away to form a capping layer 71. Then, the area where the first cutout portion 41 of the barrier layer 40 is located is completely etched away. Finally, the gate 72, source 60, and drain 50 are formed.

[0092] In one embodiment, before forming a barrier layer 40 having a first perforation 41 that generates a two-dimensional electron gas with the channel layer 30 on the side of the communication layer 30 opposite to the buffer layer 20, the method includes:

[0093] Step S031: A second cutout portion 31 is formed in the channel layer 30. The thickness of the second cutout portion 31 is less than or equal to the thickness of the channel layer 30. The barrier layer 40 defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region. The second cutout portion 31 is located between the gate structure region and the drain region.

[0094] Optionally, the second hollowed-out portion 31 is provided correspondingly to the first hollowed-out portion 41.

[0095] Optionally, the second cutout portion 31 and / or the first cutout portion 41 have an inverted trapezoidal structure, so that when other layers are grown on the second cutout portion 31 and / or the first cutout portion 41, a more uniform film with better step coverage can be obtained on its upper surface.

[0096] Specifically, a GaN channel layer 30 is epitaxially grown on Al2O3 / Ga2O3 using MOCVD, consisting of α-Al2O3, α-N-Ga2O3, and GaN layers from bottom to top. Then, an inverted trapezoidal groove is carved into the cutout region A1 of the channel layer 30 using dry etching to form a second cutout portion 31. The depth of the inverted trapezoidal groove is less than or equal to the thickness of the GaN channel layer 30. Next, a barrier layer 40 and a p-GaN layer are epitaxially grown again using MOCVD. First, the p-GaN layer outside the gate structure 70 is etched away to form a capping layer 71. Then, the area containing the first cutout portion 41 of the barrier layer 40 is completely etched away. Finally, the gate 72, source 60, and drain 50 are formed.

[0097] In one embodiment, when the thickness of the second cutout 31 is equal to the thickness of the channel layer 30, before forming the channel layer 30 on the side of the buffer layer 30 facing away from the substrate 10, the following steps are included:

[0098] Step S021: A carrier drift layer 80 is formed on the side of the buffer layer 20 facing away from the substrate 10.

[0099] Optionally, the carrier drift layer 80 is a heavily doped gallium oxide semiconductor layer, such as the carrier drift layer 80 comprising n + α-Ga₂O₃ material. Due to its higher bandgap, Ga₂O₃ can withstand higher voltages, and its high density and few surface defects can improve the device's breakdown voltage. Meanwhile, when the material of the buffer layer 20 includes n... - In α-Ga₂O₃, the n of the carrier drift layer 80 + α-Ga2O3 and buffer layer 20 n - A potential barrier forms at the α-Ga2O3 interface. With high drain bias, the barrier height increases, making it difficult for carriers in the carrier drift layer 80 to move downwards, thus suppressing n. - The formation of leakage channels in the α-Ga2O3 buffer layer can improve the device's withstand voltage performance.

[0100] Specifically, MOCVD is used in Al2O3 / Ga2O3 / n + GaN channel layers 30 are epitaxially grown on α-Ga2O3, i.e., from bottom to top, they are α-Al2O3, α-N-Ga2O3, and n-Ga2O3. + An α-Ga2O3 and GaN layer are formed, and then an inverted trapezoidal groove is carved out in the hollow area A1 of the channel layer 30 by dry etching to form the second hollow portion 31, wherein the depth of the inverted trapezoidal groove is equal to the thickness of the GaN channel layer 30. Next, a barrier layer 40 and a p-GaN layer are grown by MOCVD secondary epitaxy. First, the p-GaN layer other than the gate structure 70 is etched away to form a capping layer 71, and then the area where the first hollow portion 41 of the barrier layer 40 is located is completely etched away. Finally, the gate 72, source 60 and drain 50 are formed.

[0101] In one embodiment, when the thickness of the second cutout 31 is less than the thickness of the channel layer 30, before forming the channel layer 30 on the side of the buffer layer 30 facing away from the substrate 10, the following steps are included:

[0102] Step S022: A carrier high-resistivity layer 90 is formed on the side of the buffer layer 20 away from the substrate 10.

[0103] Optionally, the carrier high-resistivity layer 90 is an undoped gallium oxide semiconductor layer, such as the carrier high-resistivity layer 90 comprising n - α-Ga₂O₃ materials, due to n - α-Ga2O3 material itself has a larger bandgap, lower intrinsic carrier concentration and higher critical breakdown field strength than GaN. It is difficult to form leakage channels in this material, which can suppress current leakage and improve the withstand voltage of the device.

[0104] Specifically, MOCVD is used in Al2O3 / Ga2O3 / n -GaN channel layers 30 are epitaxially grown on α-Ga2O3, i.e., from bottom to top, they are α-Al2O3, α-N-Ga2O3, and n-Ga2O3. - An α-Ga2O3 and GaN layer are formed, and then an inverted trapezoidal groove is carved out in the hollow area A1 of the channel layer 30 by dry etching to form the second hollow portion 31, wherein the depth of the inverted trapezoidal groove is less than the thickness of the GaN channel layer 30. Next, a barrier layer 40 and a p-GaN layer are grown by MOCVD secondary epitaxy. First, the p-GaN layer other than the gate structure 70 is etched away to form a capping layer 71. Then, the area where the first hollow portion 41 of the barrier layer 40 is located is completely etched away. Finally, the gate 72, source 60 and drain 50 are formed.

[0105] In one embodiment, a gate 72, a source 60, and a drain 50 are formed in the gate structure region, source region, and drain region on the side of the barrier layer 40 opposite to the buffer layer 20, respectively, specifically including:

[0106] Step S051: Form a passivation layer 100 on the side of the barrier layer 40 facing away from the substrate 10;

[0107] Step S052: Gate 72, source 60 and drain 50 are formed at the positions corresponding to the gate structure region, source region and drain region of passivation layer 100, respectively.

[0108] Specifically, a substrate 10 is first formed, then a buffer layer 20 is grown on the substrate. Next, a channel layer 30, a barrier layer 40, and a p-GaN layer 701 are epitaxially grown on the substrate via MOCVD, i.e., from bottom to top, they are α-Al₂O₃, α-N-Ga₂O₃, GaN layer, AlGaN layer, and p-GaN layer. Then, the p-GaN layer outside the gate structure 70 is etched away to form a capping layer 71. Next, the area containing the first cutout portion 41 of the barrier layer 40 is completely etched away. Then, materials such as SiO₂, Si₃N₄, or Al₂O₃ are grown as a passivation layer 100 using PECVD, LPCVD, or ALD. Finally, the passivation layer 100 passes through the gate structure region, source region, and drain region of the corresponding barrier layer 40 to form the gate 72, source 60, and drain 50. The passivation layer 100 helps repair interface damage to the second cutout portion 31 or the first cutout portion 41.

[0109] It should be noted that the specific implementation methods for forming the gate 72, source 60 and drain 50 can be found in the prior art.

[0110] Gallium nitride power devices are fabricated using the above method. The barrier layer 40 in the region where the first hollow portion 41 is located is etched away, so that the region where the first hollow portion 41 is located will not generate 2EDG due to polarization effect, thus preventing electrons from being captured or overflowing. At the same time, there is no capture and release of electrons and holes by the surface states of the barrier layer, and no negative charge accumulation phenomenon will occur between the gate structure 70 and the drain 50, thus preventing the formation of a virtual gate effect and preventing current collapse. In addition, the region where the first hollow portion 41 of the barrier layer is etched away can effectively suppress the current leakage between the gate and the drain caused by carrier drift through the interface states of the barrier layer 40 and the channel layer 30 and the 2DEG channel, thereby effectively suppressing the current leakage between the gate and the drain and improving the current collapse effect, thereby improving the device's withstand voltage performance and reliability.

[0111] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A gallium nitride power device, characterized in that, include: Substrate; A buffer layer is disposed on one side of the substrate; A channel layer is disposed on the side of the buffer layer opposite to the substrate; A barrier layer is disposed on the side of the channel layer opposite to the buffer layer, and the barrier layer and the channel layer can generate a two-dimensional electron gas; A gate structure, a source, and a drain are disposed at intervals on the side of the barrier layer away from the channel layer, and the source and the drain are located on opposite sides of the gate structure; wherein, the barrier layer located between the gate structure and the drain has a first cutout portion, the thickness of the first cutout portion is the same as the thickness of the barrier layer, and the thickness direction is the direction from the substrate to the buffer layer.

2. The gallium nitride power device according to claim 1, characterized in that, The channel layer located between the gate structure and the drain has a second cutout portion, which is correspondingly disposed to the first cutout portion, and the thickness of the second cutout portion is less than or equal to the thickness of the channel layer.

3. The gallium nitride power device according to claim 2, characterized in that, The first hollow portion and / or the second hollow portion have an inverted trapezoidal structure.

4. The gallium nitride power device according to claim 2, characterized in that, When the thickness of the second cutout is less than the thickness of the channel layer, a carrier high-resistivity layer is included between the buffer layer and the channel layer.

5. The gallium nitride power device according to claim 4, characterized in that, The carrier high-resistivity layer is an undoped gallium oxide semiconductor layer.

6. The gallium nitride power device according to claim 2, characterized in that, When the thickness of the second hollow portion is equal to the thickness of the channel layer, it also includes a carrier drift layer disposed between the buffer layer and the channel layer.

7. The gallium nitride power device according to claim 5, characterized in that, The carrier drift layer is a heavily doped gallium oxide semiconductor layer.

8. A method for fabricating a gallium nitride power device, used to fabricate the power device as described in claim 1, characterized in that, include: Provide substrate; A buffer layer is formed on one side of the substrate; A channel layer is formed on the side of the buffer layer opposite to the substrate; A barrier layer with a first cutout is formed on the side of the communication layer opposite to the buffer layer, which generates a two-dimensional electron gas with the channel layer. The thickness of the first cutout is the same as the thickness of the barrier layer. The barrier layer defines a gate structure region, a source region, and a drain region, and the source region and the drain region are located on both sides of the gate structure region. The first cutout is located between the gate structure region and the drain region. The gate, source, and drain regions on the side of the barrier layer away from the buffer layer are respectively formed as the gate, source, and drain.

9. The preparation method according to claim 8, characterized in that, Before forming a barrier layer with a first perforation on the side of the communication layer opposite to the buffer layer, which generates a two-dimensional electron gas with the channel layer. A second hollow portion is formed by the channel layer, the thickness of the second hollow portion is less than or equal to the thickness of the channel layer, and the second hollow portion is provided corresponding to the first hollow portion.

10. The preparation method according to claim 9, characterized in that, When the thickness of the second cutout is equal to the thickness of the channel layer, before forming the channel layer on the side of the buffer layer away from the substrate, A carrier drift layer is formed on the side of the buffer layer opposite to the substrate.

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