Bidirectional conduction transistor and preparation method thereof

Abstract

The invention provides a bidirectional conduction transistor and a preparation method thereof, and belongs to the field of power electronics. The transistor comprises a substrate, a semiconductor multilayer body, a first electrode, a second electrode, a first grid control structure and a second grid control structure, the first electrode, the first grid control structure, the second grid control structure and the second electrode are sequentially arranged on the semiconductor multilayer body at intervals in the same direction; the first grid control structure and the second grid control structure each comprise a p-type layer and a grid electrode, and the p-type layers and the grid electrodes are sequentially stacked on the semiconductor multilayer body. According to the embodiment of the invention, bidirectional conduction of the transistor can be realized, and the complexity of circuit layout is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics, and in particular to a bidirectional transistor and its fabrication method. Background Technology

[0002] A high electron mobility transistor (HEMT) is a semiconductor multilayer bulk field-effect transistor. Transistors have advantages such as high electron mobility, high operating frequency, and low noise, and are widely used in various electrical appliances.

[0003] In related technologies, a transistor includes a semiconductor multilayer on a substrate, and a gate, source, and drain on the semiconductor multilayer. In unidirectional switching applications, the roles of the source and drain are fixed. The gate drive circuit pulls the gate voltage up to above the turn-on threshold or down to below the turn-off threshold to control the current flowing from the fixed drain to the fixed source. This drive logic is unidirectional and fixed.

[0004] However, in applications requiring bidirectional switching, two transistors connected in series must be provided with independent and synchronous gate drive signals, which increases the complexity and cost of the drive circuit and makes the circuit layout more complicated. Summary of the Invention

[0005] This disclosure provides a bidirectional transistor and its fabrication method, enabling bidirectional conduction and reducing the complexity of circuit layout. The technical solution is as follows: On one hand, this disclosure provides a transistor comprising: a substrate, a semiconductor multilayer, a first electrode, a second electrode, and a gate control structure, wherein the semiconductor multilayer is located on the surface of the substrate; the gate control structure includes a first gate control structure and a second gate control structure; the first electrode, the first gate control structure, the second gate control structure, and the second electrode are sequentially spaced on the semiconductor multilayer along the same direction; both the first gate control structure and the second gate control structure include a p-type layer and a gate, wherein the p-type layer and the gate are sequentially stacked on the semiconductor multilayer.

[0006] Optionally, the transistor further includes a first semiconductor material layer located between the semiconductor multilayer and the gate structure; the first semiconductor material layer includes a first strip portion, a second strip portion, and a grid portion connecting the first strip portion and the second strip portion.

[0007] Optionally, the first strip portion is located between the first gate structure and the semiconductor multilayer, and the second strip portion is located between the second gate structure and the semiconductor multilayer.

[0008] Optionally, the grid portion includes a plurality of third strip portions and a plurality of fourth strip portions. The plurality of third strip portions are arranged at intervals along a first direction on the semiconductor multilayer, the first direction being the arrangement direction of the first electrode, the first gate control structure, the second gate control structure, and the second electrode. The plurality of fourth strip portions are arranged at intervals along a second direction on the semiconductor multilayer, the second direction intersecting the first direction, and the third strip portions intersecting with each of the fourth strip portions.

[0009] Optionally, each of the fourth strip portions includes a first end and a second end, the first end being connected to the first strip portion and the second end being connected to the second strip portion.

[0010] Optionally, the first semiconductor material layer includes a U-shaped GaN layer.

[0011] Optionally, the p-type layer includes a first p-type GaN layer and a second p-type GaN layer stacked sequentially, wherein the doping concentration of the first p-type GaN layer is lower than that of the second p-type GaN layer.

[0012] Optionally, the orthographic projection of the second p-type GaN layer on the substrate lies within the orthographic projection of the first p-type GaN layer on the substrate.

[0013] Optionally, the transistor further includes a passivation layer comprising portions filling the spaces between the grids of the gate portion.

[0014] Optionally, the first gate control structure and the second gate control structure are arranged symmetrically about the center lines of the first electrode and the second electrode.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The transistor provided in this disclosure utilizes two independent gate-controlled structures on a semiconductor multilayer to switch current paths, enabling the transistor to automatically adjust its source-drain roles according to voltage polarity without the need for additional series devices or synchronous drive signals. In a forward-biased scenario, an external rectifier circuit can activate only the first gate-controlled structure on the left. In this case, the p-type layer of the first gate-controlled structure forms a conductive channel with the gate, while the second gate-controlled structure on the right is in a floating state. The first electrode acts as the source, and the second electrode as the drain, allowing the transistor to conduct current in the forward direction. When a negative bias is applied, the rectifier circuit switches to the second gate-controlled structure on the right, connecting the p-type layer of the second gate-controlled structure to the gate, while the first gate-controlled structure on the left remains floating. The current direction is reversed, with the second electrode becoming the source and the first electrode becoming the drain, resulting in a completely mirror-symmetrical current path for the transistor.

[0016] This time-division multiplexing gate control mechanism ensures that only one gate control structure is conducting at any given time, while the other structure remains floating to avoid interference. The dual-gate control structure design not only retains the low on-resistance characteristic of transistors but also endows them with inherent bidirectional symmetry, completely eliminating the dependence on fixed source and drain terminals. Compared to the dual-transistor series scheme in related technologies, this structure reduces the number of components and wiring complexity. The drive circuit only needs a single signal to adapt to bidirectional requirements, making it particularly suitable for scenarios requiring high-frequency bidirectional switching. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of a transistor provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure; Figure 3 This is a flowchart of a method for fabricating a transistor according to an embodiment of this disclosure.

[0019] The markings in the diagram are explained as follows: 10. Substrate; 20. Semiconductor multilayers; 31. First electrode; 32. Second electrode; 4. Gate control structure; 4a. First gate control structure; 4b. Second gate control structure; 41. p-type layer; 411. First p-type GaN layer; 412. Second p-type GaN layer; 42. Gate; 50. First semiconductor material layer; 51. First strip-shaped part; 52. Second strip-shaped part; 53. Grid section; 531. Third strip section; 532. Fourth strip section; 60. Passivation layer; 70. Buffer layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] Figure 1 This is a top view of a transistor provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure. Figure 2 It is along Figure 1 The cross-sectional view obtained by cutting along section line AA.

[0023] like Figure 1 , 2 As shown, the transistor includes: a substrate 10, a semiconductor multilayer 20, a first electrode 31, a second electrode 32, and a gate structure 4, with the semiconductor multilayer 20 located on the surface of the substrate 10.

[0024] like Figure 1 , 2 As shown, the gate control structure 4 includes a first gate control structure 4a and a second gate control structure 4b. The first electrode 31, the first gate control structure 4a, the second gate control structure 4b and the second electrode 32 are arranged sequentially and spaced apart on the semiconductor multilayer 20 along the same direction.

[0025] like Figure 1 , 2 As shown, both the first gate control structure 4a and the second gate control structure 4b include a p-type layer 41 and a gate 42, which are stacked sequentially on the semiconductor multilayer 20.

[0026] The transistor provided in this embodiment utilizes two independent gate-controlled structures on a semiconductor multilayer 20 to switch current paths, enabling the transistor to automatically adjust its source-drain roles according to voltage polarity without the need for additional series devices or synchronous drive signals. In a forward bias scenario, an external rectifier circuit can activate only the left-side first gate-controlled structure 4a. At this time, the p-type layer 41 of the first gate-controlled structure 4a forms a conduction channel with the gate 42, while the right-side second gate-controlled structure 4b is in a floating state. The first electrode 31 acts as the source, and the second electrode 32 acts as the drain, allowing the transistor to conduct current in the forward direction. When a negative bias is applied, the rectifier circuit switches to the right-side second gate-controlled structure 4b, turning on the p-type layer 41 and gate 42, while the left-side first gate-controlled structure 4a floats. The current direction is reversed, with the second electrode 32 becoming the source and the first electrode 31 becoming the drain, resulting in a completely mirror-symmetrical current path for the transistor.

[0027] This time-division multiplexing gate control mechanism ensures that only one gate control structure is conducting at any given time, while the other structure remains floating to avoid interference. The dual-gate control structure design not only retains the low on-resistance characteristic of transistors but also endows them with inherent bidirectional symmetry, completely eliminating the dependence on fixed source and drain terminals. Compared to the dual-transistor series scheme in related technologies, this structure reduces the number of components and wiring complexity. The drive circuit only needs a single signal to adapt to bidirectional requirements, making it particularly suitable for scenarios requiring high-frequency bidirectional switching.

[0028] Optionally, such as Figure 1 , 2 As shown, the transistor also includes a first semiconductor material layer 50, which is located between the semiconductor multilayer 20 and the gate structure 4; the first semiconductor material layer 50 includes a first strip portion 51, a second strip portion 52, and a grid portion 53 connecting the first strip portion 51 and the second strip portion 52.

[0029] The first strip portion 51 is located between the first gate structure 4a and the semiconductor multilayer 20, and the second strip portion 52 is located between the second gate structure 4b and the semiconductor multilayer 20.

[0030] When the first gate control structure 4a or the second gate control structure 4b is working, the strip-shaped first strip portion 51 or the second strip portion 52 below it serves as the main channel for carrier transmission, while the grid portion 53 becomes the lateral extension region of the electric field, which can effectively disperse the electric field concentration phenomenon at the edge of the gate control structure and reduce the peak electric field intensity.

[0031] Meanwhile, the coordinated layout of the first strip portion 51 and the second strip portion 52 with the gate control structure further optimizes the vertical electric field. The p-type layer 41 of the first gate control / second gate control covers the strip portion. The material properties of the strip portion buffer the direct stress of the gate 42 voltage on the semiconductor multilayer 20, and avoid the electric field distortion caused by the accumulation of interface state charge. This not only improves the reverse blocking voltage of the device, but also enhances the electric field symmetry during bidirectional conduction, providing a more reliable electric field environment for high-power bidirectional switching applications.

[0032] Optionally, such as Figure 1 , 2 As shown, the grid portion 53 includes a plurality of third strip portions 531 and a plurality of fourth strip portions 532, and the plurality of third strip portions 531 are arranged at intervals along the first direction 1a on the semiconductor multilayer body 20.

[0033] Wherein, the first direction 1a is the arrangement direction of the first electrode 31, the first gate structure 4a, the second gate structure 4b, and the second electrode 32.

[0034] like Figure 1 , 2 As shown, a plurality of fourth strip portions 532 are arranged at intervals along the second direction 1b on the semiconductor multilayer body 20, the second direction 1b intersects the first direction 1a, and the third strip portion 531 intersects with each of the fourth strip portions 532.

[0035] Each fourth strip 532 includes a first end and a second end, the first end being connected to the first strip 51 and the second end being connected to the second strip 52.

[0036] In the above implementation, the fourth stripe portion 532 is arranged at intervals along the second direction intersecting the first direction, and intersects with the third stripe portion 531 to form a cross grid. This structure divides the lateral electric field on the surface of the semiconductor multilayer 20 into multiple independent sub-regions. When the device is subjected to a lateral voltage, the stripe layer at the intersection acts as an electric field anchor point, guiding the electric field to be evenly distributed along the grid path, avoiding the edge concentration phenomenon caused by the electric field extending along the long stripe region in a single-direction layout. For example, under high lateral voltage, the grid spacing region provides lateral expansion space for the electric field, which can effectively reduce the peak electric field intensity and directly improve the lateral breakdown voltage.

[0037] Optionally, the first semiconductor material layer 50 includes a u-shaped GaN layer.

[0038] Among them, u-type GaN has high resistivity, high critical breakdown field strength and excellent crystal quality. When used as the base material for strip grid structure, it can suppress interlayer leakage current through high resistivity and avoid unwanted carrier interference with electric field distribution. It can also directly improve the transverse breakdown voltage limit by virtue of high breakdown field strength.

[0039] Meanwhile, the orthogonally intersecting U-shaped GaN strip layers form a composite structure with low conductivity barrier and high field strength carrying capacity. On the one hand, its uniform material properties ensure that the electric field diffuses uniformly along the grid path, eliminating edge concentration; on the other hand, the lattice matching degree with the semiconductor multilayer 20 reduces interface states and avoids electric field distortion. This enables the transistor to maintain a stable electric field environment during bidirectional conduction, achieving both low loss and high reliability.

[0040] Optionally, the p-type layer 41 includes a first p-type GaN layer 411 and a second p-type GaN layer 412 stacked sequentially, wherein the doping concentration of the first p-type GaN layer 411 is lower than that of the second p-type GaN layer 412.

[0041] The p-type layer 41 employs a layered structure of a low-doped first p-type GaN layer 411 and a high-doped second p-type GaN layer 412, which optimizes the gate control electric field and carrier regulation. The low-doped layer has higher resistivity, which buffers the direct impact of the gate voltage 42 on the interface of the semiconductor multilayer 20, disperses the vertical electric field peak, avoids electric field distortion caused by the accumulation of interface state charges, and improves the device's withstand voltage. The high-doped layer provides more hole carriers, enhances the synergistic effect with the gate voltage 42, and enables a faster response to turn-on / turn-off commands, improving gate control sensitivity. The two-layer gradient doping protects the integrity of the semiconductor multilayer 20 and ensures stable channel formation during bidirectional conduction, balancing low conduction loss and high reliability, and providing better gate control performance for high-power bidirectional switches.

[0042] Optionally, both the first p-type GaN layer 411 and the second p-type GaN layer 412 are Mg-doped, and the Mg doping concentration of the first p-type GaN layer 411 is 2 × 10⁻⁶. 17 cm -3 Up to 2×10 18 cm -3 The Mg doping concentration of the second p-type GaN layer 412 is 2 × 10⁻⁶. 18 cm -3 Up to 2×10 19 cm -3 .

[0043] In the above implementation, the first p-type GaN layer 411 and the second p-type GaN layer 412 adopt a gradient concentration design, which can balance electric field control and carrier supply. The low-doped first p-type GaN layer 411 is close to the semiconductor multilayer 20. Its high resistivity suppresses leakage current, buffers the impact of the gate 42 voltage on the interface, disperses the vertical electric field peak, avoids distortion caused by interface state accumulation, and improves the breakdown voltage. The high-doped second p-type GaN layer 412 is close to the gate 42. The sufficient hole concentration enhances the gate control response, quickly forms the conduction channel, and reduces the on-resistance. The above doping concentration range avoids the risk of lattice damage caused by excessive doping, while ensuring hole mobility, making the channel stable and controllable during bidirectional conduction, and balancing low loss and high reliability.

[0044] Optionally, such as Figure 1 , 2 As shown, the orthographic projection of the second p-type GaN layer 412 on the substrate 10 lies within the orthographic projection of the first p-type GaN layer 411 on the substrate 10.

[0045] In this structure, the second p-type GaN layer 412 is orthogonally projected and nested within the first p-type GaN layer 411. The low-doped first p-type GaN layer 411 covers a larger area and, with its high resistivity, uniformly disperses the longitudinal electric field, buffering the impact of the gate voltage 42 on the interface of the semiconductor multilayer 20, suppressing edge electric field concentration, and improving breakdown voltage. The hole supply of the high-doped second p-type GaN layer 412 is concentrated in the effective region, avoiding ineffective edge doping, enhancing gate control response sensitivity, and quickly forming a conduction channel.

[0046] Optionally, such as Figure 2 As shown, the transistor also includes a passivation layer 60 located on the surface of the semiconductor multilayer 20, on the sidewall of the first electrode 31, on the sidewall of the second electrode 32, on the sidewall of the first gate control structure 4a, and on the sidewall of the second gate control structure 4b. The passivation layer 60 includes portions that fill the spaces between the grids of the gate portion 53.

[0047] The passivation layer 60 covers the surface of the semiconductor multilayer 20 and the sidewalls of each electrode and gate structure, which can improve the stability and reliability of the device. It repairs the dangling bonds and interface states on the surface of the semiconductor multilayer 20 through chemical passivation, reduces electric field distortion caused by charge accumulation, and optimizes the electric field symmetry during bidirectional conduction; at the same time, it isolates the sidewalls from external moisture and impurities, and avoids increased leakage current caused by etching residue or oxidation.

[0048] For example, the passivation layer 60 includes at least one of a silicon nitride layer, a silicon oxide layer, and an aluminum oxide layer.

[0049] Optionally, such as Figure 1 , 2 As shown, the first gate control structure 4a and the second gate control structure 4b are arranged symmetrically about the center lines of the first electrode 31 and the second electrode 32.

[0050] The first electrode 31 and the second electrode 32, as well as the first gate control structure 4a and the second gate control structure 4b, are symmetrically arranged about the center point of the line connecting the first electrode 31 and the second electrode 32, achieving an ultimate balance in bidirectional performance. The symmetrical structure ensures that the electric field distribution under positive / negative bias is completely mirrored, guaranteeing that the on-resistance and threshold voltage are highly consistent during forward and reverse conduction, avoiding unidirectional performance degradation, and meeting the stringent symmetry requirements of bidirectional switches.

[0051] Meanwhile, the symmetrical layout simplifies the layout design and process alignment, reducing parameter dispersion caused by structural deviations; it also balances parasitic capacitance and inductance, reducing high-frequency switching losses. This centrally symmetrical design fundamentally ensures the stability of transistors in bidirectional applications.

[0052] Optionally, the semiconductor multilayer 20 may include stacked channel layers and barrier layers.

[0053] For example, the channel layer is a GaN layer. The thickness of the channel layer is 100 nm to 400 nm.

[0054] For example, the barrier layer is an AlGaN layer, wherein the Al content is 0.18 to 0.28. The thickness of the barrier layer is 10 nm to 20 nm.

[0055] Optionally, the substrate 10 can be a silicon carbide substrate 10 or a diamond substrate 10, etc. By providing the substrate 10 on the surface of the channel layer, it is also possible to prevent dangling bonds generated after the GaN channel layer breaks.

[0056] Optionally, In can also be stacked on the barrier layer. 0.52 GaN cap layer, and In 0.52 The thickness of the GaN cap layer ranges from 1 nm to 5 nm.

[0057] By setting In 0.52 The GaN cap layer covers the surface of the AlGaN barrier layer, which can prevent etching or air exposure from forming high-density surface states.

[0058] For example, In 0.52 The GaN cap layer is 3nm thick.

[0059] Optionally, such as Figure 2 As shown, the transistor may also include a buffer layer 70, which is located between the substrate 10 and the semiconductor multilayer 20.

[0060] For example, the buffer layer 70 can be a GaN layer, which can be doped with C, and the doping concentration of C in the GaN layer is 2 × 10⁻⁶. 18 cm -3 Up to 2×10 18 cm -3 .

[0061] Optionally, both the first electrode 31 and the second electrode 32 extend to the channel layer through at least a groove, allowing the first electrode 31 and the second electrode 32 to connect with the channel layer. This increases the contact area between the metal and the semiconductor material, thereby reducing the contact resistance between the first electrode 31, the second electrode 32 and the channel layer.

[0062] Optionally, the gate 42, the first electrode 31, and the second electrode 32 each include multiple stacked metal layers.

[0063] Optionally, the gate 42, the first electrode 31, and the second electrode 32 may each include at least one of the following: a Ti layer, an Al layer, a TaN layer, a TiN layer, and an Au layer.

[0064] The Ti layer, as an adhesion layer, can improve the adhesion between the electrode and the channel layer, and also reduce the contact resistance.

[0065] Among them, the Al layer, as a conductive layer, mainly undertakes the current transmission.

[0066] Among them, the TiN layer and the TaN layer work together to enhance the ability to block the diffusion of metal ions.

[0067] Among them, the Au layer serves as an antioxidant layer. Au's extremely high chemical inertness prevents the outer layer from oxidizing, ensuring long-term reliability.

[0068] For example, the thickness of the Ti layer is 20 nm to 60 nm.

[0069] For example, the thickness of the Ti layer is 20 nm.

[0070] For example, the thickness of the Al layer is 200 nm to 600 nm.

[0071] For example, the thickness of the Al layer is 240 nm.

[0072] For example, the thickness of the TaN layer is 20 nm to 80 nm.

[0073] For example, the thickness of the TaN layer is 50 nm.

[0074] For example, the thickness of the TiN layer is 80 nm to 120 nm.

[0075] For example, the thickness of the TiN layer is 100 nm.

[0076] For example, the thickness of the Au layer is 20 nm to 80 nm.

[0077] For example, the thickness of the Au layer is 50 nm.

[0078] For example, the gate 42, the first electrode 31 and the second electrode 32 may each include a Ti layer, an Al layer and a Ti layer stacked sequentially.

[0079] The first Ti layer has a thickness of 20 nm, the Al layer has a thickness of 240 nm, and the second Ti layer has a thickness of 100 nm.

[0080] Figure 3This is a flowchart illustrating a method for fabricating a transistor according to an embodiment of this disclosure. For example... Figure 3 As shown, the preparation method includes: S11: Forming a semiconductor multilayer on a substrate.

[0081] For example, the substrate is a silicon carbide substrate or a diamond substrate.

[0082] S12: Form a first electrode, a second electrode, a first gate structure, and a second gate structure on a semiconductor multilayer.

[0083] The first electrode, the first gate control structure, the second gate control structure, and the second electrode are arranged sequentially and spaced apart on the semiconductor multilayer in the same direction. Both the first gate control structure and the second gate control structure include a p-type layer and a gate, which are stacked sequentially on the semiconductor multilayer.

[0084] The transistor fabricated using this method utilizes two independent gate-controlled structures on a semiconductor multilayer, switching current paths to allow the transistor to automatically adjust its source-drain roles based on voltage polarity, eliminating the need for additional series devices or synchronous drive signals. Under forward bias, an external rectifier circuit can activate only the first gate-controlled structure on the left. In this case, the p-type layer of the first gate-controlled structure forms a conductive channel with the gate, while the second gate-controlled structure on the right is in a floating state. The first electrode acts as the source, and the second electrode as the drain, allowing the transistor to conduct current in the forward direction. When a negative bias is applied, the rectifier circuit switches to the second gate-controlled structure on the right, connecting the p-type layer to the gate, while the first gate-controlled structure on the left remains floating. The current direction is reversed, with the second electrode becoming the source and the first electrode becoming the drain, resulting in a perfectly mirror-symmetrical current path for the transistor.

[0085] This time-division multiplexing gate control mechanism ensures that only one gate control structure is conducting at any given time, while the other structure remains floating to avoid interference. The dual-gate control structure design not only retains the low on-resistance characteristic of transistors but also endows them with inherent bidirectional symmetry, completely eliminating the dependence on fixed source and drain terminals. Compared to the dual-transistor series scheme in related technologies, this structure reduces the number of components and wiring complexity. The drive circuit only needs a single signal to adapt to bidirectional requirements, making it particularly suitable for scenarios requiring high-frequency bidirectional switching.

[0086] Step S11 may include the following steps: The first step is to form an AlN nucleation layer on the substrate.

[0087] Specifically, this can include growing an AlN nucleation layer using MOCVD (Metal-organic Chemical Vapor Deposition). The main purpose of growing an AlN nucleation layer is to solve the lattice and thermal mismatch problem in heteroepitaxial growth and to provide a foundation for subsequent high-quality nitride epitaxy.

[0088] The second step is to form a buffer layer on the AlN nucleation layer.

[0089] The buffer layer can be a GaN layer, which can be doped with C, and the C doping concentration in the GaN layer is 2 × 10⁻⁶. 18 cm -3 Up to 2×10 18 cm -3 .

[0090] The third step involves sequentially growing a channel layer and a barrier layer on the buffer layer to form a semiconductor multilayer.

[0091] Optionally, the channel layer is a GaN layer. The thickness of the channel layer is from 100 nm to 400 nm.

[0092] Optionally, the barrier layer is an AlGaN layer, wherein the Al content is 0.18 to 0.28. The thickness of the barrier layer is 10 nm to 20 nm.

[0093] The fourth step is to form a cap layer on the barrier layer.

[0094] The cap layer can be In 0.52 GaN cap layer. For example, In 0.52 The GaN cap layer is 3nm thick.

[0095] The following steps may also be included before step S12: First, a U-shaped GaN layer is grown on the surface of a semiconductor multilayer using metal-organic chemical vapor deposition (MOCVD) to obtain a first stripe portion 51, a second stripe portion 52, and a grid portion 53.

[0096] Among them, the high resistivity and high breakdown field strength of U-type GaN can optimize the electric field distribution and suppress leakage current, laying the foundation for bidirectional withstand voltage.

[0097] The grid portion 53 includes a plurality of third strip portions 531 and a plurality of fourth strip portions 532, and the plurality of third strip portions 531 are arranged at intervals along the first direction 1a on the semiconductor multilayer body 20.

[0098] Wherein, the first direction 1a is the arrangement direction of the first electrode 31, the first gate structure 4a, the second gate structure 4b, and the second electrode 32.

[0099] likeFigure 1 , 2 As shown, a plurality of fourth strip portions 532 are arranged at intervals along the second direction 1b on the semiconductor multilayer body 20, the second direction 1b intersects the first direction 1a, and the third strip portion 531 and the fourth strip portion 532 intersect.

[0100] Each fourth strip 532 includes a first end and a second end, the first end being connected to the first strip 51 and the second end being connected to the second strip 52.

[0101] Then, a first p-type GaN layer is grown on the first semiconductor material layer.

[0102] The thickness of the first p-type GaN layer is 20 nm to 50 nm, and the Mg doping of the first p-type GaN layer is 2 × 10⁻⁶. 17 cm -3 Up to 2×10 18 cm -3 Low-doping design improves resistivity, buffers the impact of gate voltage on the semiconductor multilayer interface, and disperses the peak value of the longitudinal electric field; uniform doping ensures hole mobility, avoids interface state accumulation, and protects the integrity of the semiconductor multilayer.

[0103] Next, a second p-type GaN layer is grown on the first p-type GaN layer.

[0104] The thickness of the second p-type GaN layer is 20 nm to 50 nm, and the Mg doping of the second p-type GaN layer is 2 × 10⁻⁶. 18 cm -3 Up to 2×10 19 cm -3 High doping provides ample hole carriers, enhancing gate control response speed and rapidly forming conduction channels; the concentration range avoids the risk of lattice damage, ensuring coordinated control with the upper gate and reducing on-resistance.

[0105] Then, TiN is deposited as a mask layer, the metal contact area is defined and etched by photolithography, and SiO2 dielectric layer is deposited after resist removal; the gate area is defined by photolithography again, and the second p-type GaN layer is etched with SiO2 as a mask until it is completely removed. After resist removal, SiO2 is removed by wet etching.

[0106] Next, the first p-type GaN layer is defined by photolithography, and the patterning is completed by reactive ion etching. The etching angle is strictly controlled at 85±5° to ensure that the etching selectivity is greater than 5 and that there is no material loss at the bottom.

[0107] Step S12 may include the following steps: First, a first electrode and a second electrode are formed on the semiconductor multilayer.

[0108] For example, both the first electrode and the second electrode may include a Ti layer, an Al layer and a Ti layer stacked sequentially.

[0109] The first Ti layer has a thickness of 20 nm, the Al layer has a thickness of 240 nm, and the second Ti layer has a thickness of 100 nm.

[0110] Next, a gate is formed on the second p-type GaN layer.

[0111] For example, the gate may include a Ti layer, an Al layer and a Ti layer stacked sequentially.

[0112] The first Ti layer has a thickness of 20 nm, the Al layer has a thickness of 240 nm, and the second Ti layer has a thickness of 100 nm.

[0113] After forming each electrode, it is annealed in a nitrogen atmosphere at a temperature of 570℃ for 180 seconds to activate the metal-semiconductor contact, reduce contact resistance, and ensure bidirectional conductivity.

[0114] Finally, a passivation layer was uniformly deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD), with the thickness controlled between 100 nm and 300 nm.

[0115] The passivation layer completely covers the surface of the semiconductor multilayer and extends along the sidewalls of the first electrode, the second electrode, the first gate structure, and the second gate structure, forming a seamless encapsulation. By passivating the surface dangling bonds and smoothing the sidewall curvature, it suppresses edge electric field concentration, isolates moisture and impurities from corrosion, and significantly improves the long-term stability and bidirectional conduction reliability of the device.

[0116] For example, the passivation layer includes at least one of a silicon nitride layer, a silicon oxide layer, and an aluminum oxide layer.

[0117] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A transistor, characterized in that, The transistor includes: a substrate (10), a semiconductor multilayer (20), a first electrode (31), a second electrode (32), and a gate structure (4), wherein the semiconductor multilayer (20) is located on the surface of the substrate (10); The gate control structure (4) includes a first gate control structure (4a) and a second gate control structure (4b). The first electrode (31), the first gate structure (4a), the second gate structure (4b) and the second electrode (32) are arranged sequentially and spaced apart on the semiconductor multilayer (20) in the same direction; Both the first gate control structure (4a) and the second gate control structure (4b) include a p-type layer (41) and a gate (42), which are stacked sequentially on the semiconductor multilayer (20).

2. The transistor according to claim 1, characterized in that, The transistor further includes a first semiconductor material layer (50), which is located between the semiconductor multilayer (20) and the gate structure (4); the first semiconductor material layer (50) includes a first strip (51), a second strip (52), and a grid (53) connecting the first strip (51) and the second strip (52).

3. The transistor according to claim 2, characterized in that, The first strip (51) is located between the first gate structure (4a) and the semiconductor multilayer (20), and the second strip (52) is located between the second gate structure (4b) and the semiconductor multilayer (20).

4. The transistor according to claim 3, characterized in that, The grid portion (53) includes a plurality of third strip portions (531) and a plurality of fourth strip portions (532). The plurality of third strip portions (531) are arranged at intervals along a first direction (1a) on the semiconductor multilayer body (20). The first direction (1a) is the arrangement direction of the first electrode (31), the first gate control structure (4a), the second gate control structure (4b) and the second electrode (32). The plurality of fourth strip portions (532) are arranged at intervals along a second direction (1b) on the semiconductor multilayer (20), the second direction (1b) intersecting the first direction (1a), and the third strip portion (531) intersecting each of the fourth strip portions (532).

5. The transistor according to claim 4, characterized in that, Each of the fourth strip (532) includes a first end and a second end, the first end being connected to the first strip (51) and the second end being connected to the second strip (52).

6. The transistor according to any one of claims 2 to 5, characterized in that, The first semiconductor material layer (50) includes a u-shaped GaN layer.

7. The transistor according to any one of claims 2 to 5, characterized in that, The p-type layer (41) includes a first p-type GaN layer (411) and a second p-type GaN layer (412) stacked sequentially, wherein the doping concentration of the first p-type GaN layer (411) is lower than that of the second p-type GaN layer (412).

8. The transistor according to claim 7, characterized in that, The orthographic projection of the second p-type GaN layer (412) on the substrate (10) lies within the orthographic projection of the first p-type GaN layer (411) on the substrate (10).

9. The transistor according to claim 7, characterized in that, The transistor also includes a passivation layer (60) that includes portions between the grids of the gate portion (53).

10. The transistor according to any one of claims 1 to 6, characterized in that, The first gate control structure (4a) and the second gate control structure (4b) are arranged symmetrically about the center lines of the first electrode (31) and the second electrode (32).

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