Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes a support substrate; and the channel layer is parallel to a top surface of the supporting substrate, extends along a first direction, and sequentially comprises a drain electrode, a channel and a source electrode along the first direction. A top surface of the channel is offset less than three times its root mean square roughness.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 941,106 (i.e., priority date "November 8, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a horizontal channel layer and a method of manufacturing a semiconductor device having a horizontal channel layer. Background Technology

[0003] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the ever-increasing demands for computing power. However, various problems arise during this shrinkage process, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of the "prior art" in this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a support substrate; and a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction. A top surface of the channel deviates from its root mean square roughness by less than three times.

[0006] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate; forming a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction; conformally forming an interface insulating layer covering the channel layer; and performing a first heat treatment on the channel layer and the interface insulating layer. The top surface of the channel layer deviates from its root mean square roughness by less than three times.

[0007] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate; forming a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction; conformally forming a word line dielectric layer covering the channel layer; and performing a second heat treatment on the channel layer and the word line dielectric layer. A top surface of the channel deviates from its root mean square roughness by less than three times.

[0008] Due to the design of the semiconductor device disclosed herein, the surface roughness (or interface roughness) of the channel layer can be improved and the stress in the channel layer can be reduced by employing heat treatment. Therefore, the performance of the semiconductor device can be improved. Furthermore, by employing a thicker word line dielectric layer composed of an inner word line dielectric layer and an outer word line dielectric layer, gate-induced drain leakage current can be reduced. Therefore, the performance of the semiconductor device (such as hold time) can be improved. In addition, the outer word line dielectric layer, comprising a high-dielectric-constant dielectric material, can improve the drain current of the semiconductor device.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 The flowchart illustrates a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0013] Figure 3 For illustration purposes, this shows an example along... Figure 2 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0014] Figure 4 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0015] Figure 5 For illustration purposes, this shows an example along... Figure 4 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0016] Figure 6 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0017] Figure 7 For illustration purposes, this shows an example along... Figure 6 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0018] Figure 8 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0019] Figure 9 For illustration purposes, this shows an example along... Figure 8 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0020] Figure 10 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0021] Figure 11 For illustration purposes, this shows an example along... Figure 10 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0022] Figure 12 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0023] Figure 13 For illustration purposes, this shows an example along... Figure 12 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0024] Figure 14 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0025] Figure 15 and Figure 16 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 14 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0026] Figure 17 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0027] Figure 18 and Figure 19 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 17 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0028] Figure 20For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0029] Figures 21 to 26 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 20 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0030] Figure 27 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0031] Figure 28 For illustration purposes, this shows an example along... Figure 27 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0032] Figure 29 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0033] Figure 30 For illustration purposes, this shows an example along... Figure 29 Schematic cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'.

[0034] Figure 31 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0035] Figure 32 and Figure 33 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 31 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0036] Figure 34 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0037] Figure 35 For illustration purposes, this shows an example along... Figure 34 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0038] Figure 36 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0039] Figure 37 and Figure 38 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 36The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'.

[0040] Figure 39 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0041] Figure 40 and Figure 41 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 39 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0042] Figure 42 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0043] Figure 43 For illustration purposes, this shows an example along... Figure 42 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0044] Figure 44 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0045] Figure 45 and Figure 46 For illustrative purposes, this diagram illustrates part of the process for manufacturing a semiconductor device. Figure 44 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0046] Figure 47 For illustrative purposes, a top view of an intermediate semiconductor device according to another embodiment of the present disclosure is shown.

[0047] Figure 48 For illustration purposes, this shows an example along... Figure 47 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0048] Figure 49 For illustrative purposes, a top view of an intermediate semiconductor device according to another embodiment of the present disclosure is shown.

[0049] Figures 50 to 54 For illustrative purposes, this diagram illustrates a portion of the process for manufacturing a semiconductor device according to another embodiment. Figure 49 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0050] The reference numerals in the attached figures are explained as follows:

[0051] 1A: Semiconductor device

[0052] 1B: Semiconductor Device

[0053] 10: Method

[0054] 111: Bottom Barrier Layer

[0055] 111TS: Top Surface

[0056] 113: Top dielectric layer

[0057] 113SW: Sidewall

[0058] 113TS: Top Surface

[0059] 115: Isolation Dielectric Layer

[0060] 115TS: Top Surface

[0061] 117: Node Overlay

[0062] 117TS: Top Surface

[0063] 119: Channel-filled dielectric layer

[0064] 119SW: Sidewall

[0065] 119TS: Top Surface

[0066] 121: Interlayer dielectric

[0067] 121TS: Top Surface

[0068] 130: Storage Node Structure

[0069] 131: First electrode

[0070] 133: Node dielectric layer

[0071] 135: Second electrode

[0072] 150: Channel Layer

[0073] 151: Channel

[0074] 151BS: Bottom Surface

[0075] 151SW: Sidewall

[0076] 151TS: Top Surface

[0077] 153: Source Extreme

[0078] 155: Drain

[0079] 159: Interface insulating layer

[0080] 159TS: Top Surface

[0081] 170: Character Line Structure

[0082] 171: Internal word line dielectric layer

[0083] 171TS: Top Surface

[0084] 173: External word line dielectric layer

[0085] 173TS: Top Surface

[0086] 175: Conductive layer for word lines

[0087] 175TS: Top Surface

[0088] 177: Word line overlay

[0089] 177TS: Top Surface

[0090] 179: Word line dielectric layer

[0091] 179TS: Top Surface

[0092] 190: Bit line

[0093] 190TS: Top Surface

[0094] 210: Storage Node Area

[0095] 220: Passage Area

[0096] 221: First source / drain region

[0097] 223: Second source / drain region

[0098] 230: Character line area

[0099] 231: Area 1

[0100] 233: Second Area

[0101] 240: Bit line area

[0102] 250: Isolation Zone

[0103] 260: Active region

[0104] 311: Sacrifice Layer

[0105] 313: Channel Material

[0106] 411: Isolation Light Shield

[0107] 413: Node Exposure Mask

[0108] 415: Channel Exposure Mask

[0109] 417: Text line exposure mask

[0110] 419: Area Exposure Mask

[0111] 421: Bitline Exposure Mask

[0112] 511: Vertical opening

[0113] 513: Vertical opening

[0114] 515: Vertical opening

[0115] 517: Vertical opening

[0116] 521: Vertical opening

[0117] 610: Support substrate

[0118] 610TS: Top Surface

[0119] A-A': line

[0120] B-B': Line

[0121] C-C': Line

[0122] D1: Dimensions

[0123] DT: Size

[0124] D-D': Line

[0125] E1: Arrow

[0126] E-E': line

[0127] F-F': Line

[0128] S11: Steps

[0129] S13: Steps

[0130] S15: Steps

[0131] S17: Steps

[0132] S19: Steps

[0133] S21: Steps

[0134] SP1: Space

[0135] SP2: Space

[0136] T1: Thickness

[0137] T2: Thickness

[0138] T3: Thickness

[0139] TK1: Thickness

[0140] TK2: Thickness

[0141] TR1: First level

[0142] TR2: Second level

[0143] X: Direction

[0144] Y: direction

[0145] Z: Direction Detailed Implementation

[0146] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0147] Terms such as “an embodiment,” “an embodiment,” “an exemplary embodiment,” “another embodiment,” and “another embodiment” refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase “in an embodiment” does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0148] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0149] Figure 1 The flowchart illustrates a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 3 For illustration purposes, this shows an example along... Figure 2 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'. Figure 4 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown.

[0150] Figure 5 For illustration purposes, this shows an example along... Figure 4The cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'. Figure 6 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 7 For illustration purposes, this shows an example along... Figure 6 The cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'.

[0151] Reference Figures 1 to 7 In step S11, a supporting substrate 610 is provided, and a bottom stop layer 111, a sacrificial layer 311 and a top dielectric layer 113 are sequentially stacked on the supporting substrate 610. Multiple isolation dielectric layers 115 are formed through the top dielectric layer 113 and the sacrificial layer 311 to define multiple isolation regions 250 and multiple active regions 260 of the supporting substrate 610.

[0152] Reference Figure 2 and Figure 3 The support substrate 610 includes a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In some embodiments, the support substrate 610 includes a non-semiconductor substrate. In some embodiments, the support substrate 610 includes a glass substrate, a plastic substrate, a ceramic substrate, or a conductive substrate. The glass substrate includes soda-lime glass, alkali-free glass, or fused silica. The plastic substrate includes polyethylene terephthalate, polyimide, or polycarbonate. The conductive substrate includes metal foil. In some embodiments, the support substrate 610 includes an insulating substrate.

[0153] From a top view, the support substrate 610 and the space above it are divided into different regions. Each region includes a portion of the support substrate 610 and the corresponding space above its top surface 610TS. Each region comprises a rectangular area whose long axis is aligned along the X or Y direction (referred to as the region along the X or Y direction). It should be noted that these regions are defined for illustrative purposes only and they may not be entirely distinct. For example, the region along the X direction and the region along the Y direction may partially overlap. Furthermore, an element (or feature) within (in or located on) a region may be described as the region of that element.

[0154] In some embodiments, the support substrate 610 sequentially includes a memory node region 210, a channel region 220, a word line region 230, and a bit line region 240 along the Y direction, all extending along the X direction. The channel region 220 sequentially includes a first source / drain region 221, a word line region 230, and a second source / drain region 223 along the Y direction.

[0155] Furthermore, the support substrate 610 includes multiple isolation regions 250 and active regions 260, both extending along the Y direction and alternately arranged along the X direction. Different portions of each isolation region 250 partially overlap with the memory node region 210, channel region 220, word line region 230, and bit line region 240, respectively. Different portions of each active region 260 partially overlap with the memory node region 210, channel region 220, word line region 230, and bit line region 240, respectively.

[0156] For the sake of brevity, clarity and ease of description, only an isolation region 250 and an active region 260 will be described.

[0157] Reference Figure 2 and Figure 3A bottom barrier layer 111 is formed on the support substrate 610. In some embodiments, the bottom barrier layer 111 is formed of, for example, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbide, silicon oxide, boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or other suitable insulating materials. In some embodiments, the bottom barrier layer 111 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0158] In some embodiments, the support substrate 610 serves as an etching stop layer. In some embodiments, the bottom stop layer 111 is optional when the support substrate 610 is formed of a material having etching selectivity in subsequent etching processes.

[0159] Reference Figure 2 and Figure 3 A sacrificial layer 311 is formed on the bottom barrier layer 111. A top dielectric layer 113 is formed on the sacrificial layer 311. In some embodiments, the sacrificial layer 311 is formed of a material having etch selectivity for the top dielectric layer 113. In some embodiments, the sacrificial layer 311 is formed of a material having etch selectivity for both the top dielectric layer 113 and the bottom barrier layer 111. In some embodiments, the sacrificial layer 311 is formed of, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, or an oxide-based semiconductor. In some embodiments, the sacrificial layer 311 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0160] In some embodiments, the top dielectric layer 113 is formed of a material having etch selectivity for the sacrificial layer 311. In some embodiments, the top dielectric layer 113 is formed of a material having etch selectivity for both the sacrificial layer 311 and the bottom barrier layer 111. In some embodiments, the top dielectric layer 113 and the bottom barrier layer 111 are formed of the same material. In some embodiments, the top dielectric layer 113 and the bottom barrier layer 111 are formed of different materials. In some embodiments, the top dielectric layer 113 is formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, or other suitable insulating materials. In some embodiments, the top dielectric layer 113 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0161] Reference Figure 2 and Figure 3 An isolation photomask 411 is formed on the top dielectric layer 113. In some embodiments, the isolation photomask 411 is a photoresist layer. The isolation photomask 411 includes a pattern that partially exposes the isolation region 250. Specifically, the overlapping region (or part) between the isolation region 250 and the storage node region 210, and the overlapping region between the isolation region 250 and the channel region 220 are exposed by the isolation photomask 411.

[0162] Reference Figure 4 and Figure 5 Multiple vertical openings 511 are formed by removing the exposed top dielectric layer 113 and bottom sacrificial layer 311 through an etching process (also known as an isolation etching process). Specifically, the top dielectric layer 113 and sacrificial layer 311 are removed through an etching process from the overlapping regions between the isolation region 250 and the memory node region 210, and from the overlapping regions between the isolation region 250 and the channel region 220, thereby forming multiple vertical openings 511. The multiple vertical openings 511 separate the top dielectric layer 113 and the bottom sacrificial layer 311 located in multiple active regions 260. In some embodiments, the bottom barrier layer 111 located in / or in the aforementioned overlapping regions is removed. After forming the vertical openings 511, the isolation photomask 411 is removed.

[0163] In some embodiments, the isolation etching process is an anisotropic etching process. In some embodiments, the isolation etching process includes multiple stages, each stage providing a customized etching chemical composition to selectively remove the target layer.

[0164] For the sake of brevity, clarity and ease of description, only an isolation dielectric layer 115 will be described.

[0165] Reference Figure 6 and Figure 7An isolation dielectric layer 115 is formed in a vertical opening 511. A planarization process, such as chemical mechanical polishing, is performed until the top surface 113TS of the top dielectric layer 113 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. From a top view, the isolation dielectric layer 115 is located in the overlapping region between the isolation region 250 and the memory node region 210, and in the overlapping region between the isolation region 250 and the channel region 220. The isolation dielectric layer 115 separates the top dielectric layer 113 and the bottom sacrificial layer 311 located in a plurality of active regions 260. From a cross-sectional view, the isolation dielectric layer 115 penetrates the top dielectric layer 113 and the sacrificial layer 311. In some embodiments, the top surface 113TS of the top dielectric layer 113 and the top surface 115TS of the isolation dielectric layer 115 are substantially coplanar.

[0166] In some embodiments, the isolation dielectric layer 115 is formed of a material having etch selectivity for the top dielectric layer 113. In some embodiments, the isolation dielectric layer 115 is formed of a material having etch selectivity for the sacrificial layer 311. In some embodiments, the isolation dielectric layer 115 is formed of a material having etch selectivity for the bottom barrier layer 111. In some embodiments, the isolation dielectric layer 115 is formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, or other suitable insulating materials. In some embodiments, the isolation dielectric layer 115 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0167] Figure 8 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 9 For illustration purposes, this shows an example along... Figure 8 The cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'. Figure 10 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 11 For illustration purposes, this shows an example along... Figure 10 The cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'. Figure 12 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 13 For illustration purposes, this shows an example along... Figure 12 The cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'. Figure 14 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 15 and Figure 16 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 14 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', and E-E'.

[0168] Reference Figure 1 and Figures 8 to 16 In step S13, a storage node structure 130 is formed in the storage node region 210 of the support substrate 610 by selectively removing the sacrificial layer 311 of the storage node region 210, and a node cover layer 117 is formed on the storage node structure 130.

[0169] Reference Figure 8 and Figure 9 A node exposure mask 413 is formed on the top dielectric layer 113 and the isolation dielectric layer 115. In some embodiments, the node exposure mask 413 is a photoresist layer. The node exposure mask 413 includes a pattern that partially exposes the memory node region 210. Specifically, the top dielectric layer 113 (located as indicated by arrow E1) away from the channel region 220 is exposed, and the isolation dielectric layer 115 (located as indicated by arrow E1) furthest from the channel region 220 is fully exposed. The isolation dielectric layer 115 in the memory node region 210 is partially exposed, while the node exposure mask 413 shields the isolation dielectric layer 115 in the channel region 220.

[0170] Reference Figure 10 and Figure 11 The exposed top dielectric layer 113, bottom sacrificial layer 311, and exposed isolation dielectric layer 115 are removed by performing an etching process (also known as a node-exposing etching process) to form a vertical opening 513. Specifically, the top dielectric layer 113 and bottom sacrificial layer 311 located away from the channel region 220 (as indicated by arrow E1) are removed, exposing the sacrificial layer 311 in the overlapping region of the active region 260 and the memory node region 210. The isolation dielectric layer 115 furthest from the channel region 220 (as indicated by arrow E1) is also removed. The remaining isolation dielectric layer 115 in the memory node region 210 is partially removed. The vertical opening 513 divides the isolation dielectric layer 115 in the memory node region 210 into two portions extending along the Y direction. However, the isolation dielectric layer 115 in the memory node region 210 continues to separate adjacent active regions 260.

[0171] In some embodiments, the node exposure etching process is an anisotropic etching process. In some embodiments, the node exposure etching process includes multiple stages, each stage providing customized etching chemicals to selectively remove the target layer. After forming the vertical opening 513, the node exposure mask 413 is removed.

[0172] Reference Figure 12 and Figure 13 The sacrificial layer 311 in the storage node region 210 is selectively removed to form a space SP1. The sacrificial layer 311 in the channel region 220 is exposed through the space SP1. In some embodiments, the sacrificial layer 311 is removed by an isotropic etching process.

[0173] Subsequently, a storage node structure 130 is formed in the space SP1 and the vertical opening 513. In some embodiments, the storage node structure 130 is or includes a storage element capable of storing data. In some embodiments, the storage node structure 130 is a storage element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistive element including a phase change material. In this disclosure, the storage node structure 130 is a capacitor.

[0174] Reference Figure 14 and Figure 15 A first electrode 131 is conventionally formed in the space SP1 and the vertical opening 513. In some embodiments, the first electrode 131 is formed of, for example, tungsten (W), cobalt (Co), zirconium (Zr), tantalum (Ta), titanium (Ti), aluminum (Al), ruthenium (Ru), copper (Cu), metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, the first electrode 131 is formed by, for example, atomic layer deposition or other suitable deposition processes.

[0175] Reference Figure 14 and Figure 15 A node dielectric layer 133 is conformally formed on the first electrode 131. In some embodiments, the node dielectric layer 133 is formed of, for example, silicon oxide, silicon nitride, a high dielectric constant dielectric material, or other suitable dielectric material. In some embodiments, the node dielectric layer 133 is formed by, for example, atomic layer deposition or other suitable deposition processes.

[0176] Reference Figure 14 and Figure 15A second electrode 135 is formed to fill space SP1 and vertical opening 513. A planarization process, such as chemical mechanical polishing, is performed until the top dielectric layer 113 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the second electrode 135 is formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the second electrode 135 is formed by, for example, atomic layer deposition or other suitable deposition processes. The first electrode 131, node dielectric layer 133, and second electrode 135 together configure the storage node structure 130. The node dielectric layer 133 electrically isolates the first electrode 131 and the second electrode 135. The first electrode 131 contacts the sacrificial layer 311 in the overlapping region between the active region 260 and the channel region 220.

[0177] Reference Figure 16 A node capping layer 117 is formed on the top dielectric layer 113, the isolation dielectric layer 115, and the storage node structure 130. In some embodiments, the node capping layer 117 is formed of a material having etch selectivity for the bottom barrier layer 111. In some embodiments, the node capping layer 117 is formed of a material having etch selectivity for the top dielectric layer 113. In some embodiments, the node capping layer 117 is formed of a material having etch selectivity for the isolation dielectric layer 115. In some embodiments, the node capping layer 117 is formed of a material having etch selectivity for the sacrificial layer 311. In some embodiments, the node capping layer 117 is formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon carbide oxycarbide, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon carbide boron nitride, or other suitable insulating materials. In some embodiments, the node capping layer 117 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0178] It should be noted that, for clarity, node overlay 117 is not shown in the top view.

[0179] Figure 17 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 18 and Figure 19 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 17 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', and E-E'. Figure 20 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figures 21 to 26 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 20The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', and E-E'.

[0180] Reference Figure 1 and Figures 17 to 24 In step S15, a plurality of channel layers 150 are formed in the overlapping area between the plurality of active regions 260 and the channel region 220 of the adjacent storage node region 210.

[0181] Reference Figure 17 and Figure 18 A channel exposure mask 415 is formed on the node cover layer 117. In some embodiments, the channel exposure mask 415 is a photoresist layer. The channel exposure mask 415 includes a pattern that fully exposes the channel region 220.

[0182] Reference Figure 19 The pattern of the channel exposure mask 415 is transferred to the node capping layer 117 via an etching process. In some embodiments, the etching process is an anisotropic etching process. After the etching process, the isolation dielectric layer 115 and the top dielectric layer 113 in the channel region 220 are exposed. In some embodiments, the channel exposure mask 415 is removed after pattern transfer. In some embodiments, the channel exposure mask 415 is removed after the vertical opening 515, which will be described later, is formed.

[0183] Reference Figure 20 and Figure 21 Multiple vertical openings 515 are formed by selectively removing the isolation dielectric layer 115 in the channel region 220 using an etching process (also known as a first-channel exposure etching process). The sacrificial layer 311 in the channel region 220 is exposed through these multiple vertical openings 515.

[0184] Reference Figure 22 Multiple spaces SP2 are formed by selectively removing the sacrificial layer 311 in the channel region 220. Specifically, the multiple spaces SP2 are located in the overlapping region of the multiple active regions 260 and the channel region 220. The multiple spaces SP2 communicate with the multiple vertical openings 515. In some embodiments, the removal of the sacrificial layer 311 is achieved through an etching process such as a selective isotropic etching process.

[0185] Reference Figure 23 A channel material 313 layer is formed to completely fill the plurality of vertical openings 515 and the plurality of spaces SP2. In some embodiments, the channel material 313 includes doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium.

[0186] In some embodiments, channel material 313 comprises a semiconductor oxide (also referred to herein as "oxide semiconductor" or "oxide semiconductor material"). The semiconductor oxide includes any suitable composition; and in some embodiments may include one or more indium (In), zinc (Zn), tin (Sn), and gallium (Ga). Examples of oxide semiconductor materials and / or compositions used herein include one or more indium, zinc, tin, and gallium, such as ZnO. x SnO2, Zn x O y N, Mg x Zn y O z In x Zn y O z In x Zn y O z In x Ga y Zn z O a In x Ga y Si z O a Zr x In y Zn z O a Hf x In y Zn z O a Sn x In y Zn z O a Al x Sn y In z Zn a O b Si x In y Zn z O a Zn x Sn y O z Al x Zn y Sn z O a Ga x Zn y Sn z O a and Zr x Zn y Sn z O a Materials, etc.

[0187] In some embodiments, the channel material 313 comprises a two-dimensional (2D) material. The two-dimensional material includes any suitable composition; and in some embodiments, the two-dimensional material comprises one or more transition metal dichalcogenides, including molybdenum disulfide, molybdenum diselenide, molybdenum ditelluride, tungsten sulfide, and tungsten selenide. In some embodiments, the channel material 313 is formed by, for example, atomic layer deposition or other suitable deposition processes.

[0188] In some embodiments, the channel material 313 includes composite materials, such as indium gallium zinc oxide or indium zinc oxide.

[0189] Reference Figure 24 An etching process (also known as a second-channel exposure etching process) is performed to remove channel material 313 from the overlapping areas between channel region 220 and the plurality of isolation regions 250. The channel material 313 formed on the node capping layer 117 is removed during the second-channel exposure etching process. In some embodiments, the second-channel exposure etching process is an anisotropic etching process.

[0190] The remaining channel material 313 in the overlapping region between channel region 220 and multiple active regions 260 is referred to as the multiple channel layers 150. Each channel layer 150 is parallel to the top surface 610TS of the support substrate 610 and extends along the Y direction. Each channel layer 150 includes a channel 151, a source 153, and a drain 155. Channel 151 is located in the overlapping region of word line region 230 and active region 260. Source 153 and drain 155 are located at opposite ends of channel 151. Drain 155 is located in the overlapping region of first source / drain region 221 and active region 260. Drain 155 is disposed between channel 151 and memory node structure 130 and contacts memory node structure 130. Source 153 is located in the overlapping region of second source / drain region 223 and active region 260.

[0191] Reference Figure 1 and Figure 25 and Figure 26 In step S17, a plurality of interface insulating layers 159 are conformally formed to cover the plurality of channel layers 150, and a first heat treatment is performed.

[0192] Reference Figure 25The top dielectric layer 113 in the channel region 220 is removed by an etching process (also known as a third-channel exposure etching process). In some embodiments, the third-channel exposure etching process is an anisotropic etching process. After the third-channel exposure etching process, the channel layer 150 is exposed through a vertical opening 515.

[0193] In some embodiments, the bottom barrier layer 111 is also removed during the third channel exposure etching process. In this case, the bottom surface of the channel layer 150 may also be exposed.

[0194] Reference Figure 26 An oxidation process is performed to form an interface insulating layer 159 covering the channel layer 150 and exposing the channel material 313. In some embodiments, the oxidation process is performed in a temperature range of about 700 degrees Celsius to about 1100 degrees Celsius. In some embodiments, the oxidation process is performed using a dry or wet technique. In a dry technique, the oxidation step may be performed, for example, by heating in an oxygen environment. Figure 25 The intermediate semiconductor device shown is used to perform this process. In wet technology, the oxidation process can be performed, for example, by heating in an environment containing water vapor. Figure 25 The intermediate semiconductor device shown is used to perform this. In some embodiments, in both dry and wet processes, the oxidizing environment also contains hydrochloric acid.

[0195] In some embodiments, a first heat treatment is performed after the interface insulating layer 159 is formed. In some embodiments, the first heat treatment is performed at a temperature above 1000 degrees Celsius, or between about 1100 degrees Celsius and about 1200 degrees Celsius. In some embodiments, the first heat treatment is performed in a non-oxidizing environment, which includes argon (Ar), nitrogen (N), hydrogen (H), or a mixture of these gases. In some embodiments, the first heat treatment is performed in a vacuum.

[0196] In some embodiments, the first heat treatment is a rapid thermal annealing process. In some embodiments, the rapid thermal annealing process is performed at a temperature between approximately 1000°C and approximately 1400°C, or between approximately 1100°C and approximately 1250°C. In some embodiments, the rapid thermal annealing process is performed for approximately 1 second to approximately 60 seconds. In some embodiments, the rapid thermal annealing process is performed in an environment of a selected gas. In some embodiments, the selected gas is an inert gas. In some embodiments, the selected gas is argon.

[0197] After the first heat treatment, the surface roughness (or interface roughness) of the channel layer 150 (or interface insulating layer 159) can be improved. For example, the top surface 151TS (or surface) of the channel layer 150 may not deviate more than three times its root mean square roughness, more than twice its root mean square roughness, or more than once its root mean square roughness. The top surface 159TS (or surface) of the interface insulating layer 159 may not deviate more than three times its root mean square roughness, more than twice its root mean square roughness, or more than once its root mean square roughness.

[0198] In some embodiments, a first heat treatment is performed prior to the formation of the interface insulating layer 159.

[0199] It should be noted that, for clarity, the interface insulating layer 159 is not shown in the top view.

[0200] Figure 27 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 28 For illustration purposes, this shows an example along... Figure 27 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'. Figure 29 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 30 For illustration purposes, this shows an example along... Figure 29 Schematic cross-sectional views obtained from lines A-A', B-B', C-C', D-D', and E-E'. Figure 31 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 32 and Figure 33 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 31 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', and E-E'. Figure 34 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 35 For illustration purposes, this shows an example along... Figure 34 The cross-sectional views obtained by the lines A-A', B-B', C-C', D-D', and E-E'. Figure 36 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 37 and Figure 38 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 36 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', and E-E'.

[0201] Reference Figure 1 and Figures 27 to 38 In step S19, multiple channels 151 of multiple channel layers 150 are exposed, multiple word line dielectric layers 179 covering multiple channels 151 are conformally formed, a second heat treatment is performed, a word line conductive layer 175 is formed around the multiple word line dielectric layers 179 and a word line structure 170 is configured, and a word line cover layer 177 covering the word line structure 170 is formed.

[0202] Reference Figure 27 and Figure 28 A channel-filling dielectric layer 119 is formed to completely fill the vertical opening 515. A planarization process, such as chemical mechanical polishing, is performed until the top surface 117TS of the node capping layer 117 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the top surface 119TS of the channel-filling dielectric layer 119 and the top surface 117TS of the node capping layer 117 are substantially coplanar. In some embodiments, the channel-filling dielectric layer 119 is formed of a material having etch selectivity to the interface insulating layer 159. In some embodiments, the channel-filling dielectric layer 119 is formed of a material having etch selectivity to the top dielectric layer 113. In some embodiments, the channel-filling dielectric layer 119 is formed of a material having etch selectivity to the bottom barrier layer 111. In some embodiments, the channel-filling dielectric layer 119 is formed of a material having etch selectivity to the channel material 313. In some embodiments, the channel-filling dielectric layer 119 is formed of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbide, or other suitable insulating material. In some embodiments, the channel-filled dielectric layer 119 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0203] Reference Figure 29 and Figure 30 A word line exposure mask 417 is formed on the node cover layer 117 and the channel fill dielectric layer 119. In some embodiments, the word line exposure mask 417 is a photoresist layer. The word line exposure mask 417 includes a pattern that fully exposes the word line region 230. The first source / drain region 221, the second source / drain region 223, the memory node region 210, and the bit line region 240 remain shielded.

[0204] Reference Figure 31 and Figure 32 Vertical openings 517 are formed by removing exposed channels and filling dielectric layer 119 using an etching process. Interface insulating layer 159 in word line region 230 is exposed through the vertical openings 517. In some embodiments, the etching process is an anisotropic etching process.

[0205] Reference Figure 33 An etching process is used to selectively remove the interface insulating layer 159 in the word line region 230. After removing the interface insulating layer 159, the channel 151 is exposed through the vertical opening 517. The interface insulating layer 159 still covers the source 153 and the drain 155. In some embodiments, the etching process is an anisotropic etching process. After the channel 151 is exposed, the word line exposure mask 417 is removed.

[0206] In some embodiments, the bottom blocking layer 111 in the word line region 230 is also removed to expose the bottom surface 151BS of the channel 151.

[0207] Reference Figure 34 and Figure 35 The word line dielectric layer 179 conformally forms a cover channel 151. In some embodiments, the word line dielectric layer 179 is formed by an oxidation process. In some embodiments, the oxidation process is performed in a temperature range of approximately 700 degrees Celsius to approximately 1100 degrees Celsius. In some embodiments, the oxidation process is performed using a dry technique or a wet technique. In a dry technique, for example, by heating in an oxygen environment... Figure 33 The intermediate semiconductor device shown is used to perform the oxidation step. In wet processes, this is achieved, for example, by heating in an environment containing water vapor. Figure 33 The intermediate semiconductor device shown is used to perform the oxidation process. In some embodiments, in both dry and wet processes, the oxidation environment also contains hydrochloric acid.

[0208] In some embodiments, the thickness TK1 of the word line dielectric layer 179 and the thickness TK2 of the interface insulating layer 159 are substantially the same. In some embodiments, the thickness TK1 of the word line dielectric layer 179 and the thickness TK2 of the interface insulating layer 159 are different.

[0209] In some embodiments, the word line dielectric layer 179 and the interface insulating layer 159 are formed of the same material. In some embodiments, the word line dielectric layer 179 and the interface insulating layer 159 are formed of different materials. In some embodiments, the word line dielectric layer 179 is formed by a deposition process such as atomic layer deposition. In some embodiments, the word line dielectric layer 179 includes silicon oxide, a high dielectric constant dielectric material, or other suitable dielectric material.

[0210] Reference Figure 35 A second heat treatment is then performed. In some embodiments, the second heat treatment is performed at a temperature above 1000 degrees Celsius, or about 1100 degrees Celsius and about 1200 degrees Celsius. In some embodiments, the second heat treatment is performed in a non-oxidizing environment, which may include argon, nitrogen, hydrogen, or mixtures of these gases. In some embodiments, the second heat treatment is performed in a vacuum.

[0211] In some embodiments, the second heat treatment is a rapid thermal annealing process. In some embodiments, the rapid thermal annealing process is performed at a temperature of approximately 1000°C to approximately 1400°C or approximately 1100°C to approximately 1250°C. In some embodiments, the rapid thermal annealing process may be performed for approximately 1 second to approximately 60 seconds. In some embodiments, the rapid thermal annealing process is performed in an environment of a selected gas. In some embodiments, the selected gas is an inert gas. In some embodiments, the selected gas is argon.

[0212] After the second heat treatment, the surface roughness of channel 151 (or word line dielectric layer 179) can be improved. For example, the top surface 151TS (or surface) of channel 151 may not deviate more than three times, more than twice, or more than one times its root mean square roughness. The top surface 179TS (or surface) of word line dielectric layer 179 may not deviate more than three times, more than twice, or more than one times its root mean square roughness.

[0213] In some embodiments, a second heat treatment is performed before forming the word line dielectric layer 179.

[0214] Reference Figure 36 and Figure 37 A word line conductive layer 175 is formed to completely fill the vertical opening 517 and cover the word line dielectric layer 179. A planarization process, such as chemical mechanical polishing, is then performed until the top surface 117TS of the node capping layer 117 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the top surface 175TS of the word line conductive layer 175 and the top surface 117TS of the node capping layer 117 are substantially coplanar. In some embodiments, the word line conductive layer 175 is formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0215] Multiple word line dielectric layers 179 and word line conductive layers 175 are configured together in a word line structure 170. The word line structure 170 is located in the word line region 230 and along the X direction.

[0216] Reference Figure 38 A word line capping layer 177 is formed on the word line structure 170, the node capping layer 117, and the channel filling dielectric layer 119. In some embodiments, the word line capping layer 177 is formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, or other suitable insulating materials. In some embodiments, the word line capping layer 177 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0217] It should be noted that, for clarity, the text overlay 177 is not shown in the top view.

[0218] Figure 39 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 40 and Figure 41 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 39 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', E-E', and F-F'. Figure 42 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 43 For illustration purposes, this shows an example along... Figure 42 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'. Figure 44 For illustrative purposes, a top view of an intermediate semiconductor device according to an embodiment of the present disclosure is shown. Figure 45 and Figure 46 For illustrative purposes, a portion of the process for manufacturing semiconductor device 1A is shown below. Figure 44 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0219] Reference Figure 1 and Figures 39 to 46 In step S21, multiple bit lines 190 are formed to electrically connect multiple sources 153 of multiple channel layers 150.

[0220] Reference Figure 39 and Figure 40 A bit line exposure mask 421 is formed on the word line overlay layer 177. In some embodiments, the bit line exposure mask 421 is a photoresist layer and includes a pattern that exposes the bit line region 240.

[0221] Reference Figure 41 A vertical opening 521 is formed in the bit line region 240 through an etching process to expose the bottom barrier layer 111 (or support substrate 610) within the bit line region 240. The source 153, located in the overlapping area between the second source / drain region 223 and the active region 260, is exposed through the vertical opening 521.

[0222] Reference Figure 42 and Figure 43An interlayer dielectric 121 is formed to fill the vertical opening 521. A planarization process, such as chemical mechanical polishing, is performed until the top surface 177TS of the word line overlay 177 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. The top surface 177TS of the word line overlay 177 and the top surface 121TS of the interlayer dielectric 121 are substantially coplanar. In some embodiments, the interlayer dielectric 121 is formed of, for example, silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbide, or other suitable insulating materials. In some embodiments, the interlayer dielectric 121 is formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0223] Reference Figure 44 and Figure 45 A plurality of bit lines 190 are formed in the overlapping region of bit line region 240 and a plurality of active regions 260. The plurality of bit lines 190 are formed by removing the interlayer dielectric 121 in the overlapping region of bit line region 240 and a plurality of active regions 260 to form an opening (not shown) in the bottom barrier layer 111 (or support substrate 610) exposing the aforementioned overlapping region. Subsequently, a conductive material is deposited to fill the opening. A planarization process, such as chemical mechanical polishing, is performed until the top surface 177TS of word line capping layer 177 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. The top surface 190TS of bit line 190 and the top surface 177TS of word line capping layer 177 are substantially coplanar. In some embodiments, the conductive material is, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0224] Reference Figure 46 The first level TR1 is configured by a top dielectric layer 113, a memory node structure 130, a channel layer 150, a word line structure 170, a node cover layer 117, a channel fill dielectric layer 119, a word line cover layer 177, an interlayer dielectric 121, and a bit line 190. This is achieved through methods such as... Figures 2 to 46 The process shown forms a second layer, TR2, that is identical to the first layer, TR1, in terms of components and configuration. By repeating this process, additional layers can be built, thus forming a three-dimensional (3D) memory.

[0225] By employing heat treatment, the surface roughness (or interface roughness) of the channel layer 150 can be improved, and the stress in the channel layer 150 can be reduced. Therefore, the performance of the device 1A can be improved.

[0226] Figure 47For illustrative purposes, a top view of an intermediate semiconductor device according to another embodiment of the present disclosure is shown. Figure 48 For illustration purposes, this shows an example along... Figure 47 The cross-sectional views obtained by lines A-A', B-B', C-C', D-D', E-E', and F-F'. Figure 49 For illustrative purposes, a top view of an intermediate semiconductor device according to another embodiment of the present disclosure is shown. Figures 50 to 54 For illustrative purposes, this diagram illustrates a portion of the process for manufacturing semiconductor device 1B according to another embodiment. Figure 49 The cross-sectional views obtained along lines A-A', B-B', C-C', D-D', E-E', and F-F'.

[0227] Reference Figure 47 and Figure 48 Using similar Figures 2 to 33 The process shown is used to manufacture intermediate devices. Word line regions 230 sequentially include a first region 231 and a second region 233 along the Y direction. An inner word line dielectric layer 171 is conformally formed on the top surface 117TS of the node cover layer 117, the top surface 119TS and sidewalls 119SW of the channel-filling dielectric layer 119, the top surface 111TS of the bottom barrier layer 111, and the top surface 151TS and sidewalls 151SW of the channel 151. In some embodiments, the inner word line dielectric layer 171 is formed of, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. High dielectric constant dielectric materials include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the internal word line dielectric layer 171 is formed, for example, by atomic layer deposition.

[0228] It should be noted that, for clarity, the internal word line dielectric layer 171 is not shown in the top view.

[0229] In some embodiments, after forming the internal word line dielectric layer 171, a heat treatment (also known as a third heat treatment) is performed, the procedure of which is similar to... Figure 35 The second heat treatment shown will not be described again here. After heat treatment, the surface roughness of the channel layer 150 (or the internal word line dielectric layer 171) can be improved. For example, the top surface 171TS (or surface) of the internal word line dielectric layer 171 may not deviate more than three times its root mean square roughness, more than twice its root mean square roughness, or more than one time its root mean square roughness.

[0230] Reference Figure 49 and Figure 50 ,exist Figure 48 A region exposure mask 419 is formed on the intermediate device shown. In some embodiments, the region exposure mask 419 includes a pattern that exposes a second region 233 of the support substrate 610, the second region 233 being adjacent to a second source / drain region 223. Specifically, the internal word line dielectric layer 171 in the second region 233 is exposed. The first region 231, the first source / drain region 221, the second source / drain region 223, the memory node region 210, and the bit line region 240 are masked.

[0231] Reference Figure 51 An etching process is performed to remove the exposed internal word line dielectric layer 171. After the etching process, the channels 151 in the second region 233 are exposed, while the internal word line dielectric layer 171 still covers the channels 151 in the first region 231. In some embodiments, the internal word line dielectric layer 171 formed on the sidewalls 113SW of the top dielectric layer 113 and the sidewalls 119SW of the channel-filling dielectric layer 119 is removed. In some embodiments, the etching process is an anisotropic etching process. After the etching process, the area exposure mask 419 is removed.

[0232] Reference Figure 52 An outer word line dielectric layer 173 is conformally formed on the top surface 111TS of the inner word line dielectric layer 171, the bottom barrier layer 111, and the top surface 151TS of the channel 151 in the second region 233. In some embodiments, the inner word line dielectric layer 171 and the outer word line dielectric layer 173 are formed of the same material. In some embodiments, the inner word line dielectric layer 171 and the outer word line dielectric layer 173 are formed of different materials. In some embodiments, the outer word line dielectric layer 173 is formed of, for example, a high dielectric constant dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the outer word line dielectric layer 173 is formed by, for example, atomic layer deposition.

[0233] In detail, after the external word line dielectric layer 173 is deposited, only the external word line dielectric layer 173 may cover the channel 151 in the second region 233, while the stack including the internal word line dielectric layer 171 (which directly contacts the channel 151 in the first region 231) and the external word line dielectric layer 173 may cover the channel 151 in the first region 231.

[0234] In some embodiments, after the outer word line dielectric layer 173 is formed, a heat treatment (also known as a fourth heat treatment) is performed, the procedure of which is similar to... Figure 35 The second heat treatment shown will not be described again here. After heat treatment, the surface roughness of the channel layer 150 (or the outer word line dielectric layer 173) can be improved. For example, the top surface 173TS (or surface) of the outer word line dielectric layer 173 may not deviate more than three times its root mean square roughness, more than twice its root mean square roughness, or more than one time its root mean square roughness.

[0235] It should be noted that, for clarity, the outer word line dielectric layer 173 is not shown in the top view.

[0236] Reference Figure 53 A word line conductive layer 175 is formed to completely fill the vertical opening 517 and cover the outer word line dielectric layer 173. A planarization process, such as chemical mechanical polishing, is then performed until the top surface 117TS of the node capping layer 117 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. In other words, the word line conductive layer 175 surrounds the inner word line dielectric layer 171 and the outer word line dielectric layer 173, while directly contacting the outer word line dielectric layer 173. In some embodiments, the top surface 175TS of the word line conductive layer 175 and the top surface 117TS of the node capping layer 117 are substantially coplanar. In some embodiments, the word line conductive layer 175 is formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0237] An inner word line dielectric layer 171, an outer word line dielectric layer 173, and a word line conductive layer 175 are configured together to form a word line structure 170. The word line structure 170 is located in the word line region 230 and extends along the X direction.

[0238] In some embodiments, the ratio of the size D1 (or length) of the first region 231 to the size DT (or the sum of the first region 231 and the second region 233) of the word line region 230 is between about 0.15 and about 0.85, between about 0.20 and about 0.75, between about 0.30 and about 0.60, or about 0.50.

[0239] In some embodiments, the thickness T1 of the inner word line dielectric layer 171 and the thickness T2 of the outer word line dielectric layer 173 are substantially the same. In some embodiments, the thickness T1 of the inner word line dielectric layer 171 is less than the thickness T2 of the outer word line dielectric layer 173. In some embodiments, the thickness T1 of the inner word line dielectric layer 171 is greater than the thickness T2 of the outer word line dielectric layer 173.

[0240] In some embodiments, the ratio of the thickness T2 of the outer word line dielectric layer 173 to the thickness T3 of the stack of the inner word line dielectric layer 171 and the outer word line dielectric layer 173 is between about 0.16 and about 0.50 or between about 0.20 and 0.45.

[0241] In some embodiments, the dielectric layer of the word line structure 170 is referred to as a stepped dielectric layer due to the thickness difference between the outer word line dielectric layer 173 and the stack of the inner word line dielectric layer 171 and the outer word line dielectric layer 173.

[0242] Reference Figure 54 Using similar Figures 38 to 45 The procedure described forms word line overlay 177, interlayer dielectric 121 and bit line 190, the description of which will not be repeated here.

[0243] By employing a thicker word line dielectric layer consisting of an inner word line dielectric layer 171 and an outer word line dielectric layer 173, gate-induced drain leakage current can be reduced. Therefore, the performance of the semiconductor device 1B (such as hold time) can be improved. Furthermore, the outer word line dielectric layer 173, comprising a high-dielectric-constant dielectric material, can improve the drain current of the semiconductor device 1B.

[0244] One embodiment of this disclosure provides a semiconductor device including a support substrate; and a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction. A top surface of the channel deviates from its root mean square roughness by less than three times.

[0245] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate; forming a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction; conformally forming an interface insulating layer covering the channel layer; and performing a first heat treatment on the channel layer and the interface insulating layer. A top surface of the channel layer deviates from its root mean square roughness by less than three times.

[0246] Another embodiment of this disclosure provides a method of manufacturing a semiconductor device, including providing a support substrate; forming a channel layer parallel to a top surface of the support substrate, extending along a first direction, and sequentially including a drain, a channel, and a source along the first direction; conformally forming a word line dielectric layer covering the channel layer; and performing a second heat treatment on the channel layer and the word line dielectric layer. A top surface of the channel deviates from its root mean square roughness by less than three times.

[0247] Due to the design of the semiconductor device disclosed herein, the surface roughness (or interface roughness) of the channel layer 150 can be improved by employing heat treatment, and the stress in the channel layer 150 can be reduced. Therefore, the performance of the semiconductor device 1A can be improved. Furthermore, by employing a thicker word line dielectric layer composed of an inner word line dielectric layer 171 and an outer word line dielectric layer 173, gate-induced drain leakage current can be reduced. Therefore, the performance (such as hold time) of the semiconductor device 1B can be improved. Moreover, the outer word line dielectric layer 173, comprising a high-dielectric-constant dielectric material, can improve the drain current of the semiconductor device 1B.

[0248] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0249] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: One supporting substrate; as well as A channel layer is positioned parallel to a top surface of the supporting substrate, extends along a first direction, and sequentially includes a drain, a channel, and a source along the first direction. One of the top surfaces of the channel deviates from its root mean square roughness by less than three times.

2. The semiconductor device of claim 1, further comprising a line structure positioned parallel to the top surface of the support substrate, extending along a second direction perpendicular to the first direction, and surrounding the channel.

3. The semiconductor device of claim 2, wherein the word line structure includes a word line dielectric layer surrounding the channel and a word line conductive layer surrounding the word line dielectric layer.

4. The semiconductor device of claim 3, further comprising a memory node structure that contacts the drain.

5. The semiconductor device of claim 4, further comprising a bit line contacting the source electrode.

6. The semiconductor device of claim 5 further includes a plurality of interface insulating layers respectively covering the source and the drain.

7. The semiconductor device of claim 6, wherein the thickness of the word line dielectric layer and the thickness of the plurality of interface insulating layers are substantially the same.

8. The semiconductor device of claim 6, wherein the thickness of the word line dielectric layer is different from the thickness of the plurality of interface insulating layers.

9. The semiconductor device of claim 6, further comprising a word line overlay layer covering the word line structure.

10. The semiconductor device of claim 9, wherein a top surface of the word line overlay and a top surface of the bit line are substantially coplanar.

11. The semiconductor device of claim 10, further comprising a node overlay positioned between the word line overlay and the memory node structure.

12. The semiconductor device of claim 11, further comprising a channel-filled dielectric layer positioned between the plurality of interface insulating layers and the word line overlay layer.

13. The semiconductor device of claim 12, wherein a top surface of the channel-filled dielectric layer and a top surface of the node capping layer are substantially coplanar.

14. The semiconductor device of claim 13, wherein the plurality of interface insulating layers and the word line dielectric layer comprise the same material.

15. The semiconductor device of claim 13, wherein the plurality of interface insulating layers and the word line dielectric layer comprise different materials.

16. A method of manufacturing a semiconductor device, comprising: Provide a support substrate; A channel layer is formed that is parallel to the top surface of the support substrate, extends along a first direction, and sequentially includes a drain, a channel, and a source along the first direction. A conformal insulating layer is formed to cover the channel layer; as well as A first heat treatment is performed on the channel layer and the interface insulating layer. One of the top surfaces of the channel layer deviates from its root mean square roughness by less than three times.

17. The method of manufacturing a semiconductor device as claimed in claim 16, wherein the first heat treatment is performed at a temperature above 1000°C.

18. The method of manufacturing a semiconductor device as claimed in claim 16, wherein the first heat treatment is performed in a non-oxidizing environment.

19. The method of manufacturing a semiconductor device as claimed in claim 18, wherein the non-oxidizing environment comprises argon, nitrogen, hydrogen, or a combination thereof.

20. The method of manufacturing a semiconductor device as claimed in claim 16, wherein the first heat treatment is a rapid thermal annealing process.

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