Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device may include: a substrate; a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to an upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode includes a material different from a material of the external gate electrode.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] In semiconductor devices such as fin field-effect transistors (FinFETs), the channel can be formed as a fin shape protruding vertically from the substrate, and the gate electrode can surround three sides of the channel. Semiconductor devices with such a three-dimensional shape can exhibit high performance and achieve high integration density.

[0003] The information disclosed in this background section was already known to the inventor or derived from the embodiments of this application before or during the implementation of the embodiments, or it is technical information obtained during the implementation of the embodiments. Therefore, it may contain information that does not constitute prior art already known to the public. Summary of the Invention

[0004] A semiconductor device and its manufacturing method are provided.

[0005] Additional aspects will be set forth in part in the description which follows, and will also be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor device includes: a substrate; a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to the upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode comprises a material different from that of the external gate electrode.

[0007] The material of the internal gate electrode can be etch-selective relative to the external gate electrode.

[0008] The materials of the internal gate electrode and the external gate electrode may include at least one of metal, metal nitride, metal oxide and doped polysilicon.

[0009] The external gate electrode may include a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.

[0010] The channel layer may include group IV semiconductors, group III-V compound semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductors, quantum dots, or organic semiconductors.

[0011] The internal gate electrode may include: an internal conductive layer, comprising a material different from that of the external gate electrode; and a barrier layer on the upper surface and the lower surface of the internal conductive layer.

[0012] According to one aspect of this disclosure, a semiconductor device includes: a substrate; a first unit device on the substrate; and a second unit device on the substrate and spaced apart from the first unit device, wherein each of the first unit device and the second unit device may include: a channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to the upper surface of the substrate; an external gate electrode on a first side surface of the channel layer, a second side surface of the channel layer opposite to the first side surface, and an upper surface of the channel layer; and an internal gate electrode contacting a lower surface of the channel layer, wherein the internal gate electrode comprises a material different from that of the external gate electrode.

[0013] The material of the internal gate electrode in each of the first and second unit devices can be etch-selective relative to the external gate electrode.

[0014] In a second direction perpendicular to the first direction, the thickness of the external gate electrode of the first unit device is different from the thickness of the external gate electrode of the second unit device.

[0015] The external gate electrode of each of the first unit device and the second unit device may include a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.

[0016] In a second direction perpendicular to the first direction, the thickness of the first conductive layer of the first unit device is different from the thickness of the first conductive layer of the second unit device.

[0017] The materials of the internal gate electrode and the external gate electrode of each of the first and second unit devices may include at least one of metal, metal nitride, metal oxide and doped polysilicon.

[0018] The channel layer of each of the first and second unit devices may include group IV semiconductors, group III-V compound semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductors, quantum dots, or organic semiconductors.

[0019] The internal gate electrode of each of the first and second unit devices may include: an internal conductive layer, comprising a material different from that of the external gate electrode; and a barrier layer on the upper surface and the lower surface of the internal conductive layer.

[0020] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: forming a first channel layer and a second channel layer extending in a first direction perpendicular to the upper surface of the substrate on a substrate; forming a first through-hole in a lower portion of the first channel layer and a second through-hole in a lower portion of the second channel layer; forming a first internal gate electrode filling the first through-hole and a second internal gate electrode filling the second through-hole; forming a first external gate material layer on the substrate, the first external gate material layer covering the first channel layer, the first internal gate electrode, the second channel layer and the second internal gate electrode; and selectively etching away the covering of the first external gate material layer. The region of the first channel layer and the first internal gate electrode; and the formation of a second external gate material layer on the first channel layer, the first internal gate electrode, and the first external gate material layer covering the second channel layer and the second internal gate electrode, wherein the first external gate material layer and the second external gate material layer form the first external gate electrode on the first channel layer and the first internal gate electrode, and the second external gate material layer forms the second external gate electrode on the second channel layer and the second internal gate electrode, and wherein the first internal gate electrode includes a material different from the material of the first external gate electrode, and the second internal gate electrode includes a material different from the material of the second external gate electrode.

[0021] The thickness of the second external gate electrode can be different from the thickness of the first external gate electrode.

[0022] The first through hole and the second through hole can be formed in a second direction perpendicular to the first direction.

[0023] Forming the first internal gate electrode and the second internal gate electrode may include: forming an internal gate material layer in each of the first channel layer and the second channel layer to fill the first via and the second via; and partially etching and removing the internal gate material layer such that the internal gate material layer remains only in the first via and the second via.

[0024] The inner gate material layer may include a material that has etch selectivity relative to the first outer gate material layer.

[0025] The first internal gate electrode may include a first internal conductive layer and a barrier layer. The first internal conductive layer includes a material different from that of the first external gate electrode. The barrier layer is located on the upper surface and the lower surface of the first internal conductive layer. The second internal gate electrode may include a second internal conductive layer and a barrier layer. The second internal conductive layer includes a material different from that of the second external gate electrode. The barrier layer is located on the upper surface and the lower surface of the second internal conductive layer. Attached Figure Description

[0026] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0027] Figure 1 It is a perspective view of a semiconductor device according to one or more embodiments;

[0028] Figure 2 It is based on one or more implementation methods along Figure 1 A cross-sectional view of the semiconductor device taken by line I-I';

[0029] Figure 3 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0030] Figure 4 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0031] Figure 5 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0032] Figure 6 It is a cross-sectional view of a semiconductor device according to one or more embodiments;

[0033] Figures 7A to 7G This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to one or more embodiments;

[0034] Figures 8A to 8C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example; and

[0035] Figures 9A to 9H This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0036] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments will be described below only with reference to the accompanying drawings to illustrate various aspects.

[0037] For ease of explanation and clarity, the dimensions of each component in the accompanying drawings may be exaggerated. Since the embodiments described below are illustrative, other modifications can be made to the embodiments.

[0038] When a component is disposed "above" or "on top of" another component, the component may include not only components that directly contact the upper / lower / left / right side of the other component, but also components disposed in a non-contact manner above / below / left / right of the other component. As used herein, the singular forms "a," "an," and "the" also include the plural forms, unless the context clearly indicates otherwise. Furthermore, throughout the specification, unless otherwise described, when a portion "includes" an element, it may further include another element without excluding the presence of other elements.

[0039] Furthermore, unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Implementation is not limited to the described order of steps.

[0040] Furthermore, terms such as “…part,” “…unit,” “…module” and “…block” as stated in this disclosure may refer to a unit that processes at least one function or operation, and the unit may be implemented by hardware, software or a combination of hardware and software.

[0041] Furthermore, the connecting lines or connectors shown in the various figures are intended to represent functional relationships and / or physical or logical connections between various components. It should be noted that many alternative or additional functional relationships, physical connections, or logical connections may exist in actual devices.

[0042] Unless otherwise required, any and all examples or language (such as "as in") provided herein are intended only to better explain this disclosure and do not impose any limitation on the scope of this disclosure.

[0043] As used here, when following an element in a column, expressions such as "at least one of..." modify the entire column of elements, not individual elements within that column. For example, the expression "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0044] It will be understood that when a component or layer is referred to as being "above," "over," "on," "below," "below," "under," "connected to," or "linked to" another component or layer, it can be directly above, directly above, directly on, directly below, directly below, directly connected to, or directly linked to the other component or layer, or there can be intermediate components or layers. In contrast, when a component is referred to as being "directly above," "directly above," "directly on," "directly below," "directly below," "directly connected to," or "directly linked to" another component or layer, there are no intermediate components or layers.

[0045] Figure 1 It is a perspective view of a semiconductor device according to one or more embodiments. Figure 2 It is based on one or more implementation methods along Figure 1 A cross-sectional view of semiconductor device 100 taken by line I-I'. Figure 1 and Figure 2 The semiconductor device 100 shown may be a fin field-effect transistor (FinFET).

[0046] Reference Figure 1 and Figure 2 A substrate 110 is provided. The substrate 110 may include various materials. For example, the substrate 110 may include a semiconductor material layer 111. The semiconductor material layer 111 may include group IV semiconductors (such as Si, Ge, SiGe, etc.) or group III-V compound semiconductors. Furthermore, the semiconductor material layer 111 may include, for example, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors. However, the implementation is not limited thereto. The semiconductor material layer 111 may include p-type dopants or n-type dopants. The substrate 110 may further include an insulating material layer 112. The insulating material layer 112 may include, for example, silicon oxide, but the implementation is not limited thereto.

[0047] Although the above description shows that substrate 110 includes a semiconductor material layer 111 and an insulating material layer 112, substrate 110 can include various materials. For example, substrate 110 can include a glass substrate or a silicon-on-insulator (SOI) substrate.

[0048] A channel layer 120 is disposed on a substrate 110. The channel layer 120 may have a fin shape protruding from the upper surface of the substrate 110. The channel layer 120 has a length along the x-axis, a width along the y-axis, and a height along the z-axis.

[0049] A portion of the channel layer 120 (on opposite sides of the channel layer 120 in the longitudinal direction (x-axis direction)) may be a source 121 and a drain 122, and the intermediate portion of the channel layer 120 between the source 121 and the drain 122 may be a channel. The channel layer 120 may include a semiconductor material. The channel layer 120 may include, for example, the semiconductor material forming the substrate 110. However, the implementation is not limited thereto. The channel layer 120 may include, for example, a group IV semiconductor (such as Si, Ge, SiGe, etc.) or a group III-V compound semiconductor. The channel layer 120 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxide-oxygen nitride semiconductor, a 2D semiconductor material, a quantum dot, or an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, the 2D semiconductor material may include, for example, a transition metal dichalcogenide (TMD), and the quantum dot may include colloidal quantum dots (QD), nanocrystal structures, etc. However, the implementation is not limited thereto. The channel layer 120 may further include a dopant. Dopants can include p-type dopants or n-type dopants.

[0050] Gate electrode 130 is provided to surround a channel formed in channel layer 120. Gate electrode 130 is provided to surround four sides of channel layer 120. Gate electrode 130 may include an outer gate electrode 131 and an inner gate electrode 132. Outer gate electrode 131 may be provided to cover the upper surface of channel layer 120 and the opposite side surfaces of channel layer 120 in the width direction of channel layer 120. Inner gate electrode 132 may be provided to cover the lower surface of channel layer 120 from below (e.g., the upper surface of inner gate electrode 132 may contact the lower surface of channel layer 120). Inner gate electrode 132 may be provided between the lower surface of channel layer 120 and the upper surface of substrate 110. Gate insulating layer may be provided between outer gate electrode 131 and channel layer 120 and between inner gate electrode 132 and channel layer 120.

[0051] The external gate electrode 131 may comprise, for example, a metal, a metal nitride, a metal oxide, or a combination thereof. Metals may include, for example, ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), platinum (Pt), etc. Metal nitrides may include, for example, titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), etc. Metal oxides may include, for example, platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO3), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), lanthanum strontium cobalt oxide ((La,Sr)CoO3), etc. The external gate electrode 131 may comprise highly doped polycrystalline silicon. The external gate electrode 131 may have a single material layer. As described below, the external gate electrode 131 may have a stacked structure of multiple material layers.

[0052] The internal gate electrode 132 may comprise a heterogeneous material different from the external gate electrode 131. Specifically, the internal gate electrode 132 may comprise a material with etch selectivity relative to the external gate electrode 131. Like the external gate electrode 131, the internal gate electrode 132 may comprise, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon. However, embodiments are not limited thereto.

[0053] According to one or more embodiments, since the outer gate electrode 131 is provided to cover the opposite side surface and the upper surface of the channel layer 120, and the inner gate electrode 132 is provided to cover the lower surface of the channel layer 120, a semiconductor device 100 in which the gate electrode 130 surrounds the four sides of the channel layer 120 can be realized. Accordingly, since the inner gate electrode 132 is provided on the lower surface of the channel layer 120 (i.e., the inner gate electrode 132 covers the remaining portion of the channel layer 120 not covered by the outer gate electrode 131), leakage current occurring from the lower surface of the channel layer 120 can be additionally controlled. Due to the fin shape of the channel layer 120, the inner gate electrode 132 on the lower surface of the channel layer 120 has a smaller impact on the channel layer 120 compared to the outer gate electrode 131; therefore, a stable threshold voltage can be achieved even when the inner gate electrode 132 is formed of a heterogeneous material different from the outer gate electrode 131. Furthermore, similar to the semiconductor manufacturing process described below, by forming the internal gate electrode 132 with a material that has etch selectivity relative to the external gate electrode 131, it is possible to prevent organic material from the etch mask from remaining between the substrate 110 and the channel layer 120.

[0054] Figure 3 It is a cross-sectional view of a semiconductor device 200 according to one or more embodiments. Figure 3The semiconductor device 200 shown may be a FinFET array including multiple FinFETs. Figure 3 An example of a semiconductor device 200 including two FinFETs is shown. The following description primarily focuses on the differences from the embodiments described above.

[0055] Reference Figure 3 The semiconductor device 200 may include a first unit device 250a and a second unit device 250b spaced apart from each other on the substrate 110. Each of the first unit device 250a and the second unit device 250b may be a FinFET. The first unit device 250a and the second unit device 250b may be configured to have different threshold voltages from each other.

[0056] The first unit device 250a may include a first channel layer 220a disposed on a substrate 110 and a first gate electrode 230 provided surrounding the first channel layer 220a. The first gate electrode 230 may include a first external gate electrode 231a disposed on the opposite side surface and the upper surface of the first channel layer 220a, and a first internal gate electrode 232a disposed on the lower surface of the first channel layer 220a. Because the substrate 110, the first channel layer 220a, the first external gate electrode 231a, and the first internal gate electrode 232a are... Figure 2 The substrate 110, channel layer 120, external gate electrode 131 and internal gate electrode 132 shown are the same, so their description is omitted.

[0057] The second unit device 250b may include a second channel layer 220b disposed on a substrate 110 and a second gate electrode 240 provided to cover the second channel layer 220b. The second gate electrode 240 may include a second external gate electrode 231b and a second internal gate electrode 232b. The second external gate electrode 231b is disposed on opposite side surfaces and the upper surface of the second channel layer 220b, and the second internal gate electrode 232b is disposed on the lower surface of the second channel layer 220b. The second channel layer 220b and the second internal gate electrode 232b are identical to the first channel layer 220a and the first internal gate electrode 232a, respectively. The second external gate electrode 231b may include the same material as the first external gate electrode 231a.

[0058] In a cross-sectional view through the y-axis, the second external gate electrode 231b can have a different thickness than the first external gate electrode 231a. For example, the second external gate electrode 231b can be formed to have a greater thickness than the first external gate electrode 231a. Accordingly, since the first external gate electrode 231a and the second external gate electrode 231b have different thicknesses, and the elemental material capable of adjusting the work function diffuses into the first external gate electrode 231a and the second external gate electrode 231b, the first external gate electrode 231a and the second external gate electrode 231b can be configured to have different threshold voltages.

[0059] Figure 4 This is a cross-sectional view of a semiconductor device 300 according to one or more embodiments. Descriptions of those aspects that are the same as or similar to those described above may be omitted.

[0060] Reference Figure 4 The first unit device 350a may include a first channel layer 320a disposed on a substrate 110 and a first gate electrode 330 provided to surround the first channel layer 320a. The first gate electrode 330 may include a first external gate electrode 331a and a first internal gate electrode 332a, with the first external gate electrode 331a disposed on opposite side surfaces and the upper surface of the first channel layer 320a, and the first internal gate electrode 332a disposed on the lower surface of the first channel layer 320a. The first external gate electrode 331a may include a first conductive layer 331a' disposed on the first channel layer 320a and a second conductive layer 331a'' disposed on the first conductive layer 331a'. The first conductive layer 331a' of the first external gate electrode 331a may be... Figure 3 The first external gate electrode 231a is the same. The second conductive layer 331a'' of the first external gate electrode 331a may include a different material than the first conductive layer 331a' of the first external gate electrode 331a.

[0061] The second unit device 350b may include a second channel layer 320b disposed on the substrate 110 and a second gate electrode 340 provided to surround the second channel layer 320b. The second gate electrode 340 may include a second external gate electrode 331b and a second internal gate electrode 332b. The second external gate electrode 331b is disposed on the opposite side surface and the upper surface of the second channel layer 320b, and the second internal gate electrode 332b is disposed on the lower surface of the second channel layer 320b. The second channel layer 320b and the second internal gate electrode 332b are the same as the first channel layer 320a and the first internal gate electrode 332a, respectively.

[0062] The second external gate electrode 331b may include a first conductive layer 331b' disposed on the second channel layer 320b and a second conductive layer 331b'' disposed on the first conductive layer 331b'. The first conductive layer 331b' of the second external gate electrode 331b may be connected to... Figure 3 The second external gate electrode 231b is the same. Therefore, the first conductive layer 331b' of the second external gate electrode 331b can have a different thickness than the first conductive layer 331a' of the first external gate electrode 331a.

[0063] The second conductive layer 331b'' of the second external gate electrode 331b is the same as the second conductive layer 331a'' of the first external gate electrode 331a. Therefore, the second conductive layer 331b'' of the second external gate electrode 331b can have the same thickness as the second conductive layer 331a'' of the first external gate electrode 331a. The second conductive layer 331b'' of the second external gate electrode 331b can include a material different from the first conductive layer 331b' of the second external gate electrode 331b. The second conductive layer 331a'' of the first external gate electrode 331a and the second conductive layer 331b'' of the second external gate electrode 331b can each include a material capable of adjusting the work function (e.g., Al).

[0064] In one or more embodiments, the first conductive layer 331a' of the first external gate electrode 331a and the first conductive layer 331b' of the second external gate electrode 331b can be formed with different thicknesses, and the second conductive layers 331a'' and 331b'' of the first external gate electrode 331a and 331b'' can be formed with the same thickness. When an element capable of adjusting the work function in the second conductive layers 331a'' and 331b'' diffuses into each of the first conductive layers 331a' of the first external gate electrode 331a and 331b'' of the second external gate electrode 331b, the first external gate 331a and the second external gate 331b can be configured to have different threshold voltages due to the thickness difference between the first conductive layers 331a' and 331b'.

[0065] Figure 5 It is a cross-sectional view of a semiconductor device 400 according to one or more embodiments. Figure 5 The semiconductor device 400 shown may be a FinFET. Descriptions of the same or similar aspects as described above may be omitted.

[0066] Reference Figure 5A channel layer 420 is disposed on the substrate 110. The channel layer 420 may have a fin shape protruding from the upper surface of the substrate 110. The channel layer 420 has a length along the x-axis, a width along the y-axis, and a height along the z-axis. The channel layer 420 may include a semiconductor material. The channel layer 420 may include, for example, a group IV semiconductor (such as Si, Ge, SiGe, etc.) or a group III-V compound semiconductor. The channel layer 420 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxide-oxygen nitride semiconductor, a 2D semiconductor material, a quantum dot, or an organic semiconductor. However, the implementation is not limited thereto. The channel layer 420 may further include a p-type dopant or an n-type dopant.

[0067] A gate electrode 450 may be provided surrounding the channel layer 420. The gate electrode 450 may be provided surrounding four sides of the channel layer 420. The gate electrode 450 may include an outer gate electrode 431 and an inner gate electrode 432. The outer gate electrode 431 may be provided to cover the upper surface of the channel layer 420 and the opposite side surface of the channel layer 420. The inner gate electrode 432 may be provided to cover the lower surface of the channel layer 420. The inner gate electrode 432 may be disposed between the lower surface of the channel layer 420 and the upper surface of the substrate 110. A gate insulating layer may be disposed between the outer gate electrode 431 and the channel layer 420, and between the inner gate electrode 432 and the channel layer 420.

[0068] The external gate electrode 431 may include, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon. The external gate electrode 431 may have a single material layer. Alternatively, the external gate electrode 431 may have a stacked structure of multiple material layers.

[0069] The internal gate electrode 432 may include an internal conductive layer 432' and a barrier layer 432'' disposed on each of the upper and lower surfaces of the internal conductive layer 432'. The internal conductive layer 432' may include a heterogeneous material different from that of the external gate electrode 431. Specifically, the internal conductive layer 432' may include a material with etch selectivity relative to the external gate electrode 431. Like the external gate electrode 431, the internal conductive layer 432' may include, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon. However, embodiments are not limited thereto.

[0070] The barrier layer 432'' may include a material that prevents the material in the inner conductive layer 432' from diffusing to the outside. The barrier layer 432'' may include a material different from the inner conductive layer 432'. The barrier layer 432'' may include a material different from or the same as the outer gate electrode 431. For example, when the inner conductive layer 432' includes W, the barrier layer 432'' may include TiN. However, the implementation is not limited to this.

[0071] Figure 6 It is a cross-sectional view of a semiconductor device 500 according to one or more embodiments. Figure 6 The semiconductor device 500 shown may be a FinFET array including multiple FinFETs. Figure 6 An example of a semiconductor device 500 comprising two FinFETs is shown. Descriptions of aspects that are the same as or similar to those described above may be omitted.

[0072] Reference Figure 6 The semiconductor device 500 may include a first unit device 550a and a second unit device 550b spaced apart from each other on the substrate 110. Each of the first unit device 550a and the second unit device 550b may be a FinFET. The first unit device 550a and the second unit device 550b may be configured to have different threshold voltages from each other.

[0073] The first unit device 550a may include a first channel layer 520a disposed on a substrate 110 and a first gate electrode 530 provided around the first channel layer 520a. The first gate electrode 530 may include a first external gate electrode 531a and a first internal gate electrode 532a, the first external gate electrode 531a being disposed on an opposite side surface and an upper surface of the first channel layer 520a, and the first internal gate electrode 532a being disposed on a lower surface of the first channel layer 520a. The first internal gate electrode 532a may include a first internal conductive layer 532a' and a first barrier layer 532a'' disposed on each of the upper and lower surfaces of the first internal conductive layer 532a'. The first channel layer 520a, the first external gate electrode 531a, and the first internal gate electrode 532a may be connected to... Figure 5 The channel layer 420, the outer gate electrode 431, and the inner gate electrode 432 shown are the same.

[0074] The second unit device 550b may include a second channel layer 520b disposed on a substrate 110 and a second gate electrode 540 provided around the second channel layer 520b. The second gate electrode 540 may include a second external gate electrode 531b and a second internal gate electrode 532b, the second external gate electrode 531b being disposed on opposite side surfaces and the upper surface of the second channel layer 520b, and the second internal gate electrode being disposed on the lower surface of the second channel layer 520b. The second internal gate electrode 532b may include a second internal conductive layer 532b' and a second barrier layer 532b'' disposed on each of the upper and lower surfaces of the second internal conductive layer 532b'. The second channel layer 520b and the second internal gate electrode 532b are identical to the first channel layer 520a and the first internal gate electrode 532a, respectively. The second external gate electrode 531b may include the same material as the first external gate electrode 531a.

[0075] The second external gate electrode 531b can have a different thickness than the first external gate electrode 531a. For example, the second external gate electrode 531b can be formed to have a thicker thickness than the first external gate electrode 531a. Accordingly, since the first external gate electrode 531a and the second external gate electrode 531b are formed to have different thicknesses, and the elemental material with adjustable work function can diffuse into the first external gate electrode 531a and the second external gate electrode 531b, the first external gate electrode 531a and the second external gate electrode 531b can be configured to have different threshold voltages. Figure 4 As shown in the examples, the first external gate electrode 531a and the second external gate electrode 531b may each include a first conductive layer and a second conductive layer disposed on the first conductive layer.

[0076] Figures 7A to 7G This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Figures 7A to 7G Manufacturing Figure 3 An example of a method for the semiconductor device 200 shown.

[0077] Reference Figure 7A The first channel layer 220a and the second channel layer 220b are formed on the substrate 110 and extend vertically. The substrate 110 may include a semiconductor material layer 111. The semiconductor material layer 111 may include a group IV semiconductor (such as Si, Ge, SiGe, etc.) or a group III-V compound semiconductor. Furthermore, the semiconductor material layer 111 may include, for example, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, or organic semiconductors. However, the implementation is not limited thereto. The semiconductor material layer 111 may include p-type dopant or n-type dopant. The substrate 110 may further include an insulating material layer 112. The insulating material layer 112 may include, for example, silicon oxide, etc., but the implementation is not limited thereto.

[0078] The first channel layer 220a and the second channel layer 220b can each be formed as a fin shape protruding from the upper surface of the substrate 110. The first channel layer 220a and the second channel layer 220b can include the same material as the semiconductor material layer 111 of the substrate 110. For example, the first channel layer 220a and the second channel layer 220b can each include a group IV semiconductor (such as Si, Ge, SiGe, etc.) or a group III-V compound semiconductor. Furthermore, the first channel layer 220a and the second channel layer 220b can each include, for example, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, or organic semiconductors. The first channel layer 220a and the second channel layer 220b can each include a p-type dopant or an n-type dopant. The first channel layer 220a and the second channel layer 220b can be formed by etching the semiconductor material layer 111 forming the substrate 110 into a certain shape.

[0079] Next, a first through-hole h1 and a second through-hole h2 are formed in the first channel layer 220a and the second channel layer 220b, respectively. The first through-hole h1 and the second through-hole h2 can be formed in a direction parallel to the surface of the substrate 110 (y-axis direction) by penetrating the first channel layer 220a and the second channel layer 220b, respectively. The first through-hole h1 can be formed between the upper surface of the substrate 110 and the lower surface of the first channel layer 220a, and the second through-hole h2 can be formed between the upper surface of the substrate 110 and the lower surface of the second channel layer 220b.

[0080] Reference Figure 7B An internal gate material layer 232' is formed on the first channel layer 220a, the second channel layer 220b, and the substrate 110 to fill the first through-hole h1 and the second through-hole h2. The internal gate material layer 232' may include, for example, a metal, a metal nitride, a metal oxide, or a combination thereof. Metals may include, for example, Ru, Ti, Ta, Nb, Ir, Mo, W, Pt, etc. Metal nitrides may include, for example, TiN, TaN, NbN, MoN, CoN, WN, etc. Metal oxides may include, for example, PtO, IrO2, RuO2, SrRuO3, (Ba,Sr)RuO3, CaRuO3, (La,Sr)CoO3, etc. The internal gate material layer 232' may include highly doped polysilicon. The internal gate material layer 232' may include a material with etch selectivity relative to the first external gate material layer 231' described below.

[0081] Reference Figure 7CThe internal gate material layer 232' is partially etched, leaving only inside the first through-hole h1 and the second through-hole h2. Therefore, a first internal gate electrode 232a can be formed to fill the first through-hole h1, and a second internal gate electrode 232b can be formed to fill the second through-hole h2.

[0082] Reference Figure 7D A first external gate material layer 231' is formed to cover the first channel layer 220a, the first internal gate electrode 232a, the second channel layer 220b, and the second internal gate electrode 232b. The first external gate material layer 231' may include a material different from the internal gate material layer 232'. Specifically, the first external gate material layer 231' may include a material with etch selectivity relative to the internal gate material layer 232'. The first external gate material layer 231' may include, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon. However, embodiments are not limited thereto.

[0083] Reference Figure 7E The first external gate material layer 231' covering the first channel layer 220a and the first internal gate electrode 232a is selectively etched and removed. Specifically, an etching mask M is formed by patterning to cover the first external gate material layer 231' formed on the second channel layer 220b and the second internal gate electrode 232b. The etching mask M may include, for example, silicon-based or carbon-based organic materials, but the implementation is not limited thereto. Next, the first external gate material layer 231' covering the first channel layer 220a and the first internal gate electrode 232a is selectively etched using the etching mask M. Next, referring to… Figure 7F Remove the etch mask M formed on the first external gate material layer 231' covering the second channel layer 220b and the second internal gate electrode 232b.

[0084] Reference Figure 7G A second external gate material layer 700 is formed to cover Figure 7FThe structure shown is illustrated. The second external gate material layer 700 may include the same material as the first external gate material layer 231'. The second external gate material layer 700 may be formed to cover the first channel layer 220a and the first internal gate electrode 232a, as well as the first external gate material layer 231' formed on the second channel layer 220b and the second internal gate electrode 232b. The second external gate material layer 700 covering the first channel layer 220a and the first internal gate electrode 232a may be the first external gate electrode 231a. Both the first external gate material layer 231' and the second external gate material layer 700 covering the second channel layer 220b and the second internal gate electrode 232b may be formed as the second external gate electrode 231b. Therefore, the second external gate electrode 231b may be formed to have a thicker thickness than the first external gate electrode 231a. Accordingly, a semiconductor device 200 including a first unit device 250a and a second unit device 250b arranged separately from each other on the substrate 110 can be manufactured. An additional conductive layer (not shown) comprising an elemental material for adjusting the work function may be formed on the first external gate electrode 231a and the second external gate electrode 231b.

[0085] Figures 8A to 8C This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example. Figures 8A to 8C This illustrates an example of a problem that may arise when the internal gate electrode and the external gate electrode are formed as the same gate material layer in a semiconductor device manufacturing process.

[0086] Reference Figure 8A The first channel layer 1220a and the second channel layer 1220b are each formed in a fin shape extending vertically from the substrate 1110. Then, a first through-hole and a second through-hole are formed in the first channel layer 1220a and the second channel layer 1220b, respectively. Next, a gate material layer 31' is formed on the first channel layer 1220a, the second channel layer 1220b, and the substrate 1110. The gate material layer 31' can be formed around the four sides of each of the first channel layer 1220a and the second channel layer 1220b. Although the gate material layer 31' is formed to fill the first and second through-holes, it is possible to form a gap between the substrate 1110 and the gate material layer 31' formed on the lower surface of each of the first channel layer 1220a and the second channel layer 1220b during this process.

[0087] Reference Figure 8BThe gate material layer 31' on the first channel layer 1220a is selectively etched and removed. Specifically, an etching mask 1M is patterned to cover the gate material layer 31' formed on the second channel layer 1220b. The etching mask 1M may include, for example, silicon-based or carbon-based organic materials, but the implementation is not limited thereto. Next, the gate material layer 31' covering the first channel layer 1220a is selectively etched using the etching mask 1M.

[0088] Reference Figure 8C The etch mask 1M formed on the gate material layer 31' covering the second channel layer 1220b is removed. However, during the removal of the etch mask 1M, a problem may arise in which the organic material M' of the etch mask 1M, which fills the gap between the gate material layer 31' formed on the lower surface of the second channel layer 1220b and the substrate 1110, remains unchanged.

[0089] Figures 9A to 9H This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Figures 9A to 9H Manufacturing Figure 6 An example of a method for the semiconductor device 500 shown.

[0090] Reference Figure 9A The first channel layer 520a and the second channel layer 520b are each formed in a fin shape extending vertically from the substrate 110. Then, a first through-hole and a second through-hole are formed in the first channel layer 520a and the second channel layer 520b, respectively. The first through-hole and the second through-hole can be formed in a direction parallel to the surface of the substrate 110 by penetrating the first channel layer 520a and the second channel layer 520b, respectively. Next, a barrier material layer 532' is formed on the surfaces of the first channel layer 520a and the second channel layer 520b and on the upper surface of the substrate 110. The barrier material layer 532' can be formed around the four sides of each of the first channel layer 520a and the second channel layer 520b and cover the upper surface of the substrate 110. The barrier material layer 532' may include an internal conductive material layer (as described below) that prevents... Figure 9B The material diffused in 532'' of the middle.

[0091] Reference Figure 9BAn internal conductive material layer 532'' is formed on a barrier material layer 532' formed on a first channel layer 520a, a second channel layer 520b, and a substrate 110. The internal conductive material layer 532'' may include a material different from the barrier material layer 532'. Furthermore, the internal conductive material layer 532'' may include a material with etch selectivity relative to the first external gate material layer 531' described below. The internal conductive material layer 532'' may include, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon.

[0092] The internal conductive material layer 532'' can be formed to fill the region between the first channel layer 520a and the second channel layer 520b and the substrate 110. Therefore, the gap between the first channel layer 520a and the second channel layer 520b and the substrate 110 can be filled by the internal conductive material layer 532'' and the barrier material layer 532' formed on the upper and lower surfaces of the internal conductive material layer 532''.

[0093] Reference Figure 9C Partial etching of the internal conductive material layer 532'' is performed, so that the internal conductive material layer 532'' remains only between the first channel layer 520a and the second channel layer 520b and the substrate 110, becoming the first internal conductive layer 532a' and the second internal conductive layer 532b'.

[0094] Next, refer to Figure 9D The barrier material layer 532' is partially etched, leaving it only between the first channel layer 520a and the second channel layer 520b and the substrate 110. During this process, the first internal conductive layer 532a' and the second internal conductive layer 532b' may be partially etched. Therefore, the first internal gate electrode 532a can be formed between the lower surface of the first channel layer 520a and the upper surface of the substrate 110. The first internal gate electrode 532a may include the first internal conductive layer 532a' and a first barrier layer 532a'' disposed on each of the upper and lower surfaces of the first internal conductive layer 532a'. The second internal gate electrode 532b can be formed between the lower surface of the second channel layer 520b and the upper surface of the substrate 110. The second internal gate electrode 532b may include the second internal conductive layer 532b' and a second barrier layer 532b'' disposed on each of the upper and lower surfaces of the second internal conductive layer 532b'.

[0095] Reference Figure 9EA first external gate material layer 531' is formed to cover the first channel layer 520a, the first internal gate electrode 532a, the second channel layer 520b, and the second internal gate electrode 532b. The first external gate material layer 531' may include a material different from the internal conductive material layer 532'' described above. Specifically, the first external gate material layer 531' may include a material with etch selectivity relative to the internal conductive material layer 532''. The first external gate material layer 531' may include, for example, a metal, a metal nitride, a metal oxide, a combination thereof, or highly doped polysilicon. However, embodiments are not limited thereto.

[0096] Reference Figure 9F The first external gate material layer 531' covering the first channel layer 520a and the first internal gate electrode 532a is selectively etched and removed. Specifically, an etching mask M is patterned to cover the first external gate material layer 531' formed on the second channel layer 520b and the second internal gate electrode 532b. The etching mask M may include, for example, silicon-based or carbon-based organic materials, but the implementation is not limited thereto. Next, the first external gate material layer 531' covering the first channel layer 520a and the first internal gate electrode 532a is selectively etched using the etching mask M. Next, refer to... Figure 9G Remove the etch mask M formed on the first external gate material layer 531' covering the second channel layer 520b and the second internal gate electrode 532b.

[0097] Reference Figure 9H A second external gate material layer 900 is formed to cover Figure 9G The structure shown is illustrated. The second external gate material layer 900 may include the same material as the first external gate material layer 531'. The second external gate material layer 900 may be formed to cover the first channel layer 520a and the first internal gate electrode 532a, as well as the first external gate material layer 531' formed on the second channel layer 520b and the second internal gate electrode 532b. The second external gate material layer 900 covering the first channel layer 520a and the first internal gate electrode 532a may be the first external gate electrode 531a. Both the first external gate material layer 531' and the second external gate material layer 900 covering the second channel layer 520b and the second internal gate electrode 532b may be formed as the second external gate electrode 531b. Therefore, the second external gate electrode 531b may be formed to have a thicker thickness than the first external gate electrode 531a. Accordingly, a semiconductor device 500 including a first unit device 550a and a second unit device 550b arranged separately from each other on the substrate 110 can be manufactured. A conductive layer (not shown) comprising an elemental material for adjusting the work function may be additionally formed on the first external gate electrode 531a and the second external gate electrode 531b.

[0098] According to one or more embodiments described above, since the external gate electrode is provided to cover the opposite side surface and the upper surface of the channel layer, while the internal gate electrode is provided to cover the lower surface of the channel layer, a semiconductor device in which the gate electrode surrounds the four sides of the channel layer can be realized. Accordingly, since the internal gate electrode is arranged on the lower surface of the channel layer in addition to the external gate electrode, leakage current generated from the lower surface of the channel layer can be additionally controlled. Due to the fin shape of the channel layer, the internal gate electrode on the lower surface of the channel layer has a smaller impact on the channel layer compared to the external gate electrode; therefore, a stable threshold voltage can be achieved even when the internal gate electrode is formed of a heterogeneous material different from the external gate electrode. Furthermore, in the semiconductor manufacturing process, since the internal gate electrode is formed of a material with etch selectivity relative to the external gate electrode, organic material from the etching mask can be prevented from remaining between the substrate and the channel layer.

[0099] Each implementation described above is not excluded from being associated with one or more features of another example, nor is it excluded from being associated with another implementation provided herein or not provided herein but consistent with this disclosure.

[0100] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

[0101] This application is based on and claims priority to Korean Patent Application No. 10-2024-0156884, filed on November 7, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Substrate; A channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to the upper surface of the substrate; External gate electrode, on the first side surface of the channel layer, the second side surface of the channel layer opposite to the first side surface, and the upper surface of the channel layer; as well as The internal gate electrode contacts the lower surface of the channel layer. The internal gate electrode is made of a material different from that of the external gate electrode.

2. The semiconductor device according to claim 1, wherein, The material of the inner gate electrode has etch selectivity relative to the outer gate electrode.

3. The semiconductor device according to claim 1, wherein, The material of the inner gate electrode and the material of the outer gate electrode include at least one of metal, metal nitride, metal oxide and doped polycrystalline silicon.

4. The semiconductor device according to claim 1, wherein, The external gate electrode includes a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.

5. The semiconductor device according to claim 1, wherein, The channel layer includes group IV semiconductors, group III-V compound semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductors, quantum dots, or organic semiconductors.

6. The semiconductor device according to claim 1, wherein, The internal gate electrode includes: An internal conductive layer comprising a material different from the material of the external gate electrode; and A barrier layer is located on the upper surface and the lower surface of the inner conductive layer.

7. A semiconductor device, comprising: Substrate; The first unit device is on the substrate; as well as The second unit device is located on the substrate and spaced apart from the first unit device. Each of the first unit device and the second unit device includes: A channel layer having a fin shape and protruding from the substrate in a first direction perpendicular to the upper surface of the substrate; External gate electrodes are located on the first side surface of the channel layer, the second side surface of the channel layer opposite to the first side surface, and the upper surface of the channel layer; and The internal gate electrode contacts the lower surface of the channel layer, and The internal gate electrode is made of a material different from that of the external gate electrode.

8. The semiconductor device according to claim 7, wherein, The material of the internal gate electrode of each of the first and second unit devices has etch selectivity relative to the external gate electrode.

9. The semiconductor device according to claim 7, wherein, In a second direction perpendicular to the first direction, the thickness of the external gate electrode of the first unit device is different from the thickness of the external gate electrode of the second unit device.

10. The semiconductor device according to claim 7, wherein, The external gate electrode of each of the first unit device and the second unit device includes a first conductive layer on the channel layer and a second conductive layer on the first conductive layer.

11. The semiconductor device according to claim 10, wherein, In a second direction perpendicular to the first direction, the thickness of the first conductive layer of the first unit device is different from the thickness of the first conductive layer of the second unit device.

12. The semiconductor device according to claim 7, wherein, The material of the inner gate electrode of each of the first unit device and the second unit device and the material of the outer gate electrode include at least one of metal, metal nitride, metal oxide and doped polysilicon.

13. The semiconductor device according to claim 7, wherein, The channel layer of each of the first and second unit devices comprises a group IV semiconductor, a group III-V compound semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional semiconductor, a quantum dot, or an organic semiconductor.

14. The semiconductor device according to claim 7, wherein, The internal gate electrode of each of the first unit device and the second unit device includes: An internal conductive layer comprising a material different from the material of the external gate electrode; and A barrier layer is located on the upper surface and the lower surface of the inner conductive layer.

15. A method for manufacturing a semiconductor device, the method comprising: A first trench layer and a second trench layer are formed on the substrate in a first direction perpendicular to the upper surface of the substrate; A first through hole is formed in the lower portion of the first channel layer and a second through hole is formed in the lower portion of the second channel layer; A first internal gate electrode filling the first through-hole and a second internal gate electrode filling the second through-hole are formed; A first external gate material layer is formed on the substrate, the first external gate material layer covering the first channel layer, the first internal gate electrode, the second channel layer and the second internal gate electrode; Selectively etch and remove the area of ​​the first external gate material layer covering the first channel layer and the first internal gate electrode; as well as A second external gate material layer is formed on the first channel layer, the first internal gate electrode, and the first external gate material layer covering the second channel layer and the second internal gate electrode. The first external gate material layer and the second external gate material layer form a first external gate electrode on the first channel layer and the first internal gate electrode, and the second external gate material layer forms a second external gate electrode on the second channel layer and the second internal gate electrode. Wherein, the first internal gate electrode is made of a material different from that of the first external gate electrode, and the second internal gate electrode is made of a material different from that of the second external gate electrode.

16. The method according to claim 15, wherein, The thickness of the second external gate electrode is different from the thickness of the first external gate electrode.

17. The method according to claim 15, wherein, The first through hole and the second through hole are formed in a second direction perpendicular to the first direction.

18. The method according to claim 15, wherein, Forming the first internal gate electrode and the second internal gate electrode includes: An internal gate material layer is formed in each of the first channel layer and the second channel layer to fill the first through-hole and the second through-hole; and The internal gate material layer is partially etched and removed so that it remains only in the first and second vias.

19. The method according to claim 18, wherein, The inner gate material layer includes a material that has etch selectivity relative to the first outer gate material layer.

20. The method of claim 15, wherein, The first internal gate electrode includes a first internal conductive layer and a barrier layer. The first internal conductive layer includes a material different from that of the first external gate electrode. The barrier layer is located on the upper surface and the lower surface of the first internal conductive layer. The second internal gate electrode includes a second internal conductive layer and a barrier layer. The second internal conductive layer includes a material different from the material of the second external gate electrode. The barrier layer is located on the upper surface and the lower surface of the second internal conductive layer.

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