Oxide semiconductor thin film transistor

Abstract

The invention relates to an oxide semiconductor thin film transistor. The oxide semiconductor thin film transistor includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer connected to the source electrode and the drain electrode, and a gate insulating film between the gate electrode and the oxide semiconductor layer in a stacking direction. The oxide semiconductor layer includes a channel region. The gate insulating film includes a metal oxide film and a first insulating film made of silicon nitride and / or silicon oxynitride. A portion of the first insulating film is provided between the metal oxide film and the oxide semiconductor layer. In a plan view, at least a portion of a first end of the metal oxide film is located on the channel region and faces any one of the source electrode and the drain electrode.

Description

Technical Field

[0001] This invention relates to oxide semiconductor thin-film transistors. Background Technology

[0002] Thin-film transistors (TFTs) are used in various fields, such as display devices and radiation sensors. TFTs with active layers made of oxide semiconductors, such as InGaZnO (IGZO), can achieve high mobility despite their amorphous structure. However, controlling their threshold voltage is difficult because the added donors and acceptors make it hard to control the Fermi energy. Summary of the Invention

[0003] A technique is needed to control the threshold voltage of oxide semiconductor TFTs.

[0004] An oxide semiconductor thin-film transistor according to one aspect of the present invention includes a gate electrode, a source electrode, a drain electrode, an oxide semiconductor layer connected to the source electrode and the drain electrode, and a gate insulating film located between the gate electrode and the oxide semiconductor layer in a stacking direction. The oxide semiconductor layer includes a channel region. The gate insulating film includes a metal oxide film and a first insulating film made of silicon nitride and / or silicon oxynitride. A portion of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer. In a plan view, at least a portion of a first end of the metal oxide film is located on the channel region and faces either the source electrode or the drain electrode.

[0005] One aspect of the present invention is the ability to control the threshold voltage of an oxide semiconductor TFT.

[0006] It should be understood that the above general description and the following detailed description are exemplary and explanatory, and do not limit the invention. Attached Figure Description

[0007] Figure 1 An X-ray sensor is shown.

[0008] Figure 2 The cross-sectional structure of the pixels of an X-ray sensor is shown.

[0009] Figure 3 This is a cross-sectional view schematically illustrating an example configuration of an oxide semiconductor TFT having a gate insulating film made of a SiNx / SiOx / SiNx laminate.

[0010] Figure 4A It is an energy band diagram used to illustrate the movement of charge carriers when an oxide semiconductor TFT is irradiated with X-rays.

[0011] Figure 4BThis is another band diagram used to illustrate the movement of charge carriers when an oxide semiconductor TFT is irradiated with X-rays.

[0012] Figure 5 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT in one embodiment of the present invention.

[0013] Figure 6 It is a plan view schematically showing the positional relationship between the silicon oxide film, the channel region, and some other components in an oxide semiconductor TFT.

[0014] Figure 7A Schematic illustration when Figure 5 and Figure 6 The oxide semiconductor TFT in the illustrated embodiment exhibits a charge state when it is supplied with a gate bias voltage and irradiated by radioactive rays.

[0015] Figure 7B This is a schematic diagram illustrating the negative offset of the threshold voltage.

[0016] Figure 8A Schematic illustration when Figure 5 and Figure 6 Another charge state that occurs when the oxide semiconductor TFT in the illustrated embodiment is supplied with a gate bias and irradiated with radioactive rays.

[0017] Figure 8B This is a schematic diagram illustrating the positive offset of the threshold voltage.

[0018] Figure 9 A graph is provided showing the relationship between the intensity of the electric field generated by planar charges of different areas and the distance from the planar charges.

[0019] Figure 10 This is a cross-sectional view schematically illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0020] Figure 11 It is shown schematically. Figure 10 The diagram shows the positional relationship between the silicon oxide film, the channel region, and some other components in an oxide semiconductor TFT.

[0021] Figure 12 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0022] Figure 13 It is shown schematically. Figure 12 The diagram shows the positional relationship between the silicon oxide film, the channel region, and some other components in an oxide semiconductor TFT.

[0023] Figure 14A The diagram shows a planar charge extending infinitely in both the positive and negative directions along the Y-axis and in the positive direction along the X-axis.

[0024] Figure 14B express Figure 14A The intensity of the Z-axis component of the electric field produced by a plane charge at different coordinates (x, z).

[0025] Figure 15 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0026] Figure 16 It is shown schematically. Figure 15 The diagram shows the positional relationship between the silicon oxide film, the channel region, and some other components in an oxide semiconductor TFT.

[0027] Figure 17 This is a plan view schematically illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0028] Figure 18 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0029] Figure 19 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT in another embodiment of the present invention.

[0030] Figure 20A This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0031] Figure 20B This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0032] Figure 20C This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0033] Figure 20D This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0034] Figure 20E This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0035] Figure 20F This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0036] Figure 20G This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0037] Figure 20HThis illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0038] Figure 20I This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0039] Figure 20J This illustrates one step in a method for manufacturing an oxide semiconductor TFT.

[0040] Figure 21A This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0041] Figure 21B This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0042] Figure 21C This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0043] Figure 21D This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0044] Figure 21E This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0045] Figure 21F This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0046] Figure 21G This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0047] Figure 21H This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0048] Figure 21I This illustrates a step in another manufacturing method for an oxide semiconductor TFT.

[0049] Figure 21J This illustrates a step in another manufacturing method for an oxide semiconductor TFT. Detailed Implementation

[0050] In the following description, embodiments will be illustrated with reference to the accompanying drawings. These embodiments are merely examples of implementing the invention and do not limit the scope of the invention. For clarity of understanding, the dimensions or shapes of some elements in the drawings may be exaggerated.

[0051] The oxide semiconductor thin-film transistor (TFT) in the embodiments of the present invention is suitable for various devices, such as display devices and radiation sensors. Figure 1 An X-ray sensor 10 is shown as an example of a device that can employ an oxide semiconductor TFT according to an embodiment of the present invention. For example, the X-ray sensor 10 is an image sensor for imaging X-rays that pass through an object.

[0052] X-ray sensor 10 includes a pixel matrix 101, a scanning circuit 170, and a detector circuit 150. The pixel matrix 101 includes pixels 102 arranged in a matrix. The pixel matrix 101 is fabricated on a substrate 100. The substrate 100 is an insulating substrate (e.g., a glass substrate or a resin substrate).

[0053] Pixel 102 is positioned at the intersection of multiple signal lines 106 and multiple gate lines (scan lines) 105. Figure 1 In this configuration, signal lines 106 are arranged to extend vertically and are horizontally spaced apart, while gate lines 105 are arranged to extend horizontally and are vertically spaced apart. Each pixel 102 is connected to a bias line 107. Figure 1 In this configuration, multiple offset lines 107 are set to extend vertically and be horizontally spaced apart from each other. Figure 1 In the figure, only one pixel, one signal line, one gate line and one bias line are provided with reference numerals 102, 106, 105 and 107 respectively.

[0054] Each signal line 106 is connected to a different pixel column. Each gate line 105 is connected to a different pixel row. Signal lines 106 are connected to detector circuit 150, and gate lines 105 are connected to scan circuit 170. Each bias line 107 is connected to a common bias line 108. A bias potential is supplied to the pad 109 of the common bias line 108.

[0055] Each pixel 102 includes a photodiode 103 as a photoelectric conversion element and a TFT 104 as a switching element. In the TFT 104, the gate is connected to a gate line 105; one of the source / drain terminals is connected to a signal line 106; and the other of the source / drain terminal is connected to the cathode of the photodiode 103. Figure 1 In the example, the anode of photodiode 103 is connected to bias line 107.

[0056] Figure 1 In the configuration example, TFT 104 is of n-type conductivity. TFT 104 can have different conductivity types. In this embodiment, TFT 104 is an oxide semiconductor TFT. Oxide semiconductor TFTs exhibit good switching characteristics.

[0057] The X-ray sensor 10 reads the signal from the pixel 102 by extracting a signal charge stored in the photodiode 103, which is proportional to the X-ray irradiation dose, to the outside. The signal charge can be extracted by turning on the TFT 104 in the pixel 102. Specifically, when light enters the photodiode 103, a signal charge is generated and stored in the photodiode 103.

[0058] The scanning circuit 170 selects gate lines 105 one by one to apply pulses to turn on TFT 104. The anode terminal of photodiode 103 is connected to bias line 107, and signal line 106 is supplied with a reference potential by detector circuit 150. Therefore, photodiode 103 is charged with the difference voltage between the bias potential of bias line 107 and the reference potential. This difference voltage is determined such that the cathode potential is higher than the anode potential to reverse bias photodiode 103.

[0059] The charge required to recharge photodiode 103 to its reverse bias voltage depends on the amount of light incident on photodiode 103. Detector circuit 150 reads the signal charge by integrating the current flowing during the recharging of photodiode 103 to its reverse bias voltage.

[0060] Due to the incident light and the dark leakage current present even when the photodiode 103 is not illuminated, the charge stored in the photodiode 103 inevitably decreases. Therefore, in the TFT 104 during signal charge readout operation, the voltage at the terminal connected to the signal line 106 is equal to or higher than the voltage at the terminal connected to the photodiode 103. That is, when detecting signal charge, the terminal connected to the signal line 106 is the drain, and the terminal connected to the photodiode 103 is the source.

[0061] Figure 2 The cross-sectional structure of the pixel is shown. In the following description, the side of the test object placed relative to the X-ray sensor 10 is defined as the front side. Figure 2 In the image, the side opposite to the substrate 100, relative to the photodiode (PD) 103, is the front side. In the positional relationship between the pixel components, the side closer to the substrate 100 is called the lower side, and the opposite side is called the upper side.

[0062] The TFT 104 and photodiode 103 included in the pixel both have multilayer structures. The TFT 104 includes a gate electrode 202 disposed above a substrate 100 having insulating properties, a gate insulating film 203 disposed above the gate electrode 202, and an oxide semiconductor layer 204 disposed above the gate insulating film 203. As will be described later, the gate insulating film 203 comprises a multilayer insulating film of different materials.

[0063] Figure 2The TFT 104 has a bottom gate structure; the gate electrode 202 is located below the oxide semiconductor layer 204. The TFT 104 also includes one source electrode / drain electrode 205 and the other source electrode / drain electrode 206 above the gate insulating film 203. The source electrodes / drain electrodes 205 and 206 are respectively connected to the oxide semiconductor layer 204. Each of the source electrodes / drain electrodes 205 and 206 is in contact with the side surface and a portion of the top surface of the island-shaped oxide semiconductor layer 204.

[0064] Depending on the flow of charge carriers, one of the source / drain electrodes 205 and 206 is the source electrode, and the other is the drain electrode. When detecting the charge of the photodiode 103, electrode 205 is the drain electrode, and electrode 206 is the source electrode. Therefore, in the following description, electrode 205 will be referred to as the drain electrode, and electrode 206 as the source electrode.

[0065] A gate insulating film 203 is provided to cover the entire gate electrode 202. The gate insulating film 203 is disposed between the gate electrode 202 and the oxide semiconductor layer 204, between the gate electrode 202 and the drain electrode 205, and between the gate electrode 202 and the source electrode 206.

[0066] A first interlayer insulating layer 207 is provided to cover the entire TFT 104. Specifically, the first interlayer insulating layer 207 covers the top surface of the oxide semiconductor layer 204, the top surface of the drain electrode 205, and the top surface of the source electrode 206.

[0067] The substrate 100 may be made of glass or resin. The gate electrode 202 is a conductor and may be made of metal or doped silicon. The gate insulating film 203 has a multilayer structure. The gate insulating film 203 may include an insulating film made of oxide and another insulating film made of nitride or oxynitride. Details of the gate insulating film 203 will be described later.

[0068] The oxide semiconductor used for the oxide semiconductor layer 204 is an oxide semiconductor comprising at least one of In, Ga, and Zn, such as amorphous InGaZnO (a-InGaZnO) or microcrystalline InGaZnO. Other oxide semiconductors, such as a-InSnZnO and a-InGaZnSnO, may also be used. The examples described below primarily employ amorphous InGaZnO or microcrystalline InGaZnO (which may also be referred to as IGZO below).

[0069] The drain electrode 205 and source electrode 206 are conductors and may be made of metals such as Mo, Ti, Al, or Cr, their alloys, or a stacked structure of these metals or alloys. The first interlayer insulating layer 207 is an inorganic or organic insulator. Although Figure 2The TFT 104 in the figure has a bottom gate structure, but the TFT 104 can also have a top gate structure or a dual gate structure including a top gate and a bottom gate.

[0070] The photodiode 103 is disposed above the first interlayer insulating layer 207. Figure 2 An example of photodiode 103 is a PIN diode. A PIN diode has a thick depletion layer in its film thickness to allow for efficient light detection. Photodiode 103 comprises a stacked semiconductor sandwiched between a lower electrode 208 and an upper electrode 212 above a first interlayer insulating layer 207. The lower electrode 208 is connected to the source electrode 206 of the TFT 104 through an interconnect region in a via 221 of the first interlayer insulating layer 207.

[0071] The lower electrode 208 is a conductor and may be made of a metal such as Cr, Mo, or Al, an alloy thereof, or a stacked structure of these metals or alloys. The upper electrode 212 is a transparent electrode that transmits light from the scintillator 216 and may be made of, for example, ITO.

[0072] The photodiode 103 includes an n-type amorphous silicon layer 209 above the lower electrode 208, an intrinsic amorphous silicon layer 210 above the n-type amorphous silicon layer 209, and a p-type amorphous silicon layer 211 above the intrinsic amorphous silicon layer 210. An upper electrode 212 is disposed above the p-type amorphous silicon layer 211. The light to be detected enters the photodiode 103 from above the upper electrode 212 (p-type amorphous silicon layer 211).

[0073] A second interlayer insulating layer 213 is provided to cover the photodiode 103. Specifically, the second interlayer insulating layer 213 is provided on a portion of the first interlayer insulating layer 207 and above the upper electrode 212. The second interlayer insulating layer 213 is an inorganic or organic insulator.

[0074] A bias line 107 is disposed above the second interlayer insulating layer 213. The bias line 107 is connected to the upper electrode 212 through an interconnection region disposed in a through-hole 222 of the second interlayer insulating layer 213. The bias line 107 is a conductor and may be made of a metal such as Mo, Ti or Al, an alloy thereof, or a stacked structure of such metals or alloys.

[0075] A passivation layer 215 is provided to cover the bias line 107 and the interlayer insulating layer 213. The passivation layer 215 covers the entire pixel matrix 101. The passivation layer 215 is an inorganic or organic insulator. A scintillator 216 is disposed above the passivation layer 215.

[0076] Scintillator 216 covers the entire pixel matrix 101. Scintillator 216 emits light by being excited by radioactive rays. Specifically, scintillator 216 converts received X-rays into light with a wavelength detectable by photodiode 103. Photodiode 103 stores signal charge depending on the amount of light from scintillator 216.

[0077] The following describes the configuration of an oxide semiconductor TFT according to one embodiment of the present invention. The oxide semiconductor TFT of this embodiment can be applied to devices other than the X-ray sensor described above, such as display devices.

[0078] TFTs with active layers made of oxide semiconductors, such as InGaZnO (IGZO), can achieve high mobility despite their amorphous structure. However, controlling their threshold voltage is difficult because the added donors and acceptors make it hard to control the Fermi energy.

[0079] The inventors investigated a method for controlling the threshold voltage of an oxide semiconductor TFT by configuring the gate insulating film as a SiNx / SiOx / SiNx stacked film and irradiating the TFT with light of energy greater than the band gap of the gate insulating film while the gate voltage is supplied, so that the interface of the three layers stores the required charge. The threshold voltage of the TFT can be controlled by controlling the potential at the oxide semiconductor interface through the electric field generated by the charge (see, for example, U.S. Application No. 18 / 781,161).

[0080] Specifically, when an oxide semiconductor is irradiated with high-energy X-rays, pairs of holes (h) and electrons (e) are photoexcited and generated. When a negative voltage is applied between the source and gate of the TFT, holes in the oxide semiconductor transition to the interface with the SiNx gate insulating film and are trapped in the interface state, resulting in a threshold voltage shift. When a positive voltage is applied between the source and gate, electrons induced in the channel are trapped in the SiNx interface with the gate insulating film, resulting in a threshold voltage shift.

[0081] These threshold voltage offsets can be reduced by configuring the gate insulating film as a three-layer structure with SiNx / SiOx / SiNx. Depending on the polarity of the voltage applied between the source and the gate, charges of different polarities are collected at two interfaces within the gate insulating film to counteract the electric field generated by the charges trapped at the interface of the oxide semiconductor layer and the electric field generated by the collected charges.

[0082] Figure 3This is a schematic cross-sectional view illustrating an example configuration of an oxide semiconductor TFT having a gate insulating film made of a SiNx / SiOx / SiNx laminate. The oxide semiconductor TFT 500 includes a gate electrode 502, a gate insulating film 503 above the gate electrode 502, and an oxide semiconductor layer 504 above the gate insulating film 503. An interlayer insulating film 507 is provided to cover the entire oxide semiconductor TFT 500.

[0083] The gate insulating film 503 has a three-layer structure consisting of a lower silicon nitride (SiNx) film 511, a silicon oxide (SiOx) film 512 above the lower silicon nitride film 511, and an upper silicon nitride film 513 above the silicon oxide film 512. The lower silicon nitride (SiNx) film 511, the silicon oxide (SiOx) film 512, and the upper silicon nitride film 513 are respectively the lower region, the middle region, and the upper region of the gate insulating film 503.

[0084] The silicon oxide film 512, serving as an intermediate insulating layer, is in contact with and has interfaces with the lower silicon nitride film 511 and the upper silicon nitride film 513. In the gate insulating film 503, the lower silicon nitride film 511 has an interface with the gate electrode 502, and the upper silicon nitride film 513 has an interface with the oxide semiconductor layer 504.

[0085] The oxide semiconductor TFT 500 has a bottom gate structure; the gate electrode 502 is located lower than the oxide semiconductor layer 504. The oxide semiconductor TFT 500 also includes source / drain electrodes 505 and 506 above the gate insulating film 503. Each of the source / drain electrodes 505 and 506 is connected to the oxide semiconductor layer 504.

[0086] Figure 4A and Figure 4B It is an energy band diagram used to illustrate the movement of charge carriers when an oxide semiconductor TFT is irradiated with X-rays. Figure 4A The band structure diagram 592 shows the electronic energy levels of the gate electrode 502, lower silicon nitride film 511, silicon oxide film 512, upper silicon nitride film 513, and oxide semiconductor layer 504 when a positive gate voltage is applied to the oxide semiconductor TFT 500 irradiated by X-rays. In this diagram, Ec represents the lower edge of the conduction band of the oxide semiconductor layer 504, lower silicon nitride film 511, silicon oxide film 512, and upper silicon nitride film 513; Ev represents the upper edge of the valence band of the oxide semiconductor layer 504, lower silicon nitride film 511, silicon oxide film 512, and upper silicon nitride film 513; and Ef represents the Fermi level of the gate electrode (metal layer) 502.

[0087] Electrons (e) generated by X-rays in the lower silicon nitride film 511 are trapped in the electron trap level of the lower silicon nitride film 511. Holes (h) generated in the lower silicon nitride film 511 are trapped in the hole trap level of the lower silicon nitride film 511.

[0088] Similarly, electrons (e) generated by X-rays in the upper silicon nitride film 513 are trapped in the electron trap level of the upper silicon nitride film 513. Holes (h) generated in the upper silicon nitride film 513 are trapped in the hole trap level of the upper silicon nitride film 513.

[0089] Electrons (e) generated by X-rays in the silicon oxide film 512 move to the lower silicon nitride film 511, which has a lower energy level, and are trapped in the electron trapping energy level of the lower silicon nitride film 511. Holes (h) generated in the silicon oxide film 512 are trapped in the hole trapping energy level of the silicon oxide film 512. Therefore, positive charges are stored near the interface between the silicon oxide film 512 and the upper silicon nitride film 513.

[0090] Due to the positive gate voltage, electrons (e) generated by X-rays in the oxide semiconductor layer 504 move to the vicinity of the interface between the upper silicon nitride film 513 and the oxide semiconductor layer 504 and are trapped there. The negative charge of the trapped electrons and the positive charge stored near the interface between the silicon oxide film 512 and the upper silicon nitride film 513 cancel each other out, thereby reducing the potential change of the oxide semiconductor layer 504 and suppressing the shift in the Vg-Id characteristic of the oxide semiconductor TFT 500.

[0091] Figure 4B The band structure diagram 593 shows the electronic energy levels of the gate electrode 502, lower silicon nitride film 511, silicon oxide film 512, upper silicon nitride film 513, and oxide semiconductor layer 504 when a negative gate voltage is applied to the oxide semiconductor TFT 500 irradiated by X-rays. The reference numerals Ec, Ev, and Ef, as well as the band gaps of silicon oxide, silicon nitride, and oxide semiconductor, are the same as those in band structure diagram 592.

[0092] Electrons (e) and holes (h) generated by X-rays in the lower silicon nitride film 511 are trapped in the electron trap level and hole trap level in the lower silicon nitride film 511, respectively.

[0093] Similarly, electrons (e) generated by X-rays in the upper silicon nitride film 513 are trapped in the electron trap level of the upper silicon nitride film 513. Holes (h) generated in the upper silicon nitride film 513 are trapped in the hole trap level of the upper silicon nitride film 513.

[0094] Electrons (e) generated by X-rays in the silicon oxide film 512 move to the upper silicon nitride film 513, which has a lower energy level, and are trapped in the electron trapping energy level of the upper silicon nitride film 513. Therefore, negative charges are stored near the interface between the silicon oxide film 512 and the upper silicon nitride film 513. Holes (h) generated in the silicon oxide film 512 are trapped in the hole trapping energy level of the silicon oxide film 512.

[0095] Due to the negative gate voltage, holes (h) generated by X-rays in the oxide semiconductor layer 504 move to the vicinity of the interface between the upper silicon nitride film 513 and the oxide semiconductor layer 504 and are trapped there. The positive charge of the trapped holes and the negative charge stored near the interface between the silicon oxide film 512 and the upper silicon nitride film 513 cancel each other out, thereby reducing the potential change of the oxide semiconductor layer 504 and suppressing the shift in the Vg-Id characteristic of the oxide semiconductor TFT 500.

[0096] Further research by the inventors revealed a more efficient method for controlling the threshold voltage of an oxide semiconductor TFT. This method involves reducing the area of ​​the silicon oxide film spaced apart from the oxide semiconductor layer in the stacking direction of the multilayer gate insulating film. Consequently, the dependence of the electric field strength generated by the trapped charge on distance increases, thereby achieving a greater difference in strength between the electric fields of positive and negative charges at the location of the oxide semiconductor layer.

[0097] In one embodiment of the present invention, a portion (first insulating film) of the gate insulating film of an oxide semiconductor TFT is fabricated using silicon nitride and / or silicon oxynitride, and small island-shaped (isolated) metal oxide films (insulating films) are embedded in the gate insulating film to overlap with the channel region in the stacking direction. The metal oxide films may be made of, for example, silicon oxide and / or aluminum oxide.

[0098] The charge is distributed at the interface between the metal oxide film and the silicon nitride or silicon oxynitride film. Therefore, a small area of ​​metal oxide film will generate a small area of ​​planar charge. Consequently, the electric field generated by the charge near the oxide semiconductor layer and the electric field generated by the charge far away from the oxide semiconductor layer have a large difference in intensity.

[0099] To shift the threshold voltage positively, the control applies a voltage between the source and gate, causing the charge near the oxide semiconductor layer to have a negative polarity (by applying a voltage to the gate that is negative relative to the source potential), and irradiates the TFT with light (e.g., X-rays) with energy greater than the band gap of the metal oxide film. To shift the threshold voltage negatively, the control applies a voltage to the gate that is positive relative to the source potential, and irradiates the TFT with the aforementioned high-energy light.

[0100] Figure 5This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT 300 according to an embodiment of the present invention. The oxide semiconductor TFT 300 can be used as... Figure 1 and Figure 2 The TFT 104 shown is illustrated. It should be noted that for... Figure 2 and Figure 5 Components that share the same reference numerals in the accompanying drawings, refer to... Figure 2 The provided description is applicable Figure 5 Components in.

[0101] The oxide semiconductor TFT 300 includes a gate electrode 302, a gate insulating film 303 above the gate electrode 302, and an oxide semiconductor layer 304 above the gate insulating film 303. An interlayer insulating layer 307 is provided to cover the entire oxide semiconductor TFT 300.

[0102] The gate insulating film 303 has a multilayer structure and consists of a silicon nitride (SiNx) film 311 and isolated island-like silicon oxide (SiOx) films 312 embedded in the silicon nitride film 311. The silicon oxide film 312 is surrounded by the silicon nitride film 311, and its entire surface is in contact with the silicon nitride film 311, forming an interface with the silicon nitride film 311. A portion of the silicon nitride film 311 is located between the silicon oxide film 312 and the oxide semiconductor layer 304, with the silicon oxide film 312 spaced apart from the oxide semiconductor layer 304. Another portion of the silicon nitride film 311 is located between the silicon oxide film 312 and the gate electrode 302, with the silicon oxide film 312 spaced apart from the gate electrode 302.

[0103] The oxide semiconductor layer 304 includes a drain region 342, a source region 343, and a channel region 341 therebetween. The drain region 342 and the source region 343 have a lower resistance than the channel region 341. The drain region 342 and the source region 343 can be generated by exposing the oxide semiconductor layer to hydrogen plasma or fluorine plasma to reduce its resistance. At least a portion of the drain region 342 is in contact with a drain electrode 305. At least a portion of the source region 343 is in contact with a source electrode 306.

[0104] The size of the channel region 341 can be defined by the channel width and the channel length. The channel length is the distance from the boundary between the source region 343 and the channel region 341 to the boundary between the drain region 342 and the channel region 341. The channel width is the dimension of the channel in the direction perpendicular to the channel length.

[0105] exist Figure 5 In the plan view of the configuration example, the entire silicon oxide film 312 is located on the channel region 341; its area is smaller than the area of ​​the channel region 341.

[0106] Figure 6It is a plan view schematically showing the positional relationship between the silicon oxide film 312, the channel region 341, and some other components. Figure 6 The entire area is filled with a silicon nitride film 311. Figure 6 In the diagram, the source region 343, the drain region 342, and the channel region 341 between them are represented by arrowed lines. The arrows indicate the length direction of the channel, and the direction perpendicular to them is the width direction of the channel.

[0107] like Figure 6 As shown in the plan view, the area of ​​the silicon oxide film 312 is smaller than the area of ​​the channel region 341, and the entire silicon oxide film 312 is located on (and included in) the channel region 341. Figure 6 In the plan view, the entire left (side), right (side), upper (side), and lower (side) ends of the silicon oxide film 312 are located on (included in) the channel region 341. The left and right ends are opposite ends in the channel length direction (horizontal direction), and the upper and lower ends are opposite ends in the channel width direction (vertical direction).

[0108] The right end of the silicon oxide film 312 faces the source electrode 306 (and source region 343). The left end of the silicon oxide film 312 faces the drain electrode 305 (and drain region 342). The entire right end of the silicon oxide film 312 facing the source electrode 306 (and source region 343) lies on the channel region 341. The entire left end of the silicon oxide film 312 facing the drain electrode 305 (and drain region 342) lies on the channel region 341. At least a portion of the right or left end may be located outside the channel region 341 (it does not need to be located on the channel region 341).

[0109] exist Figure 6 In one configuration example, the distance LR between the right end of the silicon oxide film 312 and one end of the source electrode 306 (minimum distance) is equal to the distance LL between the left end of the silicon oxide film 312 and one end of the drain electrode 305 (minimum distance). In another configuration example, these distances LR and LL can be different. The centroid of the silicon oxide film 312 coincides with the centroid of the channel region 341. In another configuration example, these centroids do not need to coincide. Although Figure 5 and Figure 6 The silicon oxide film 312 in the example has a cuboid shape, but there are no particular restrictions on the shape of the silicon oxide film 312.

[0110] Figure 7A and Figure 8A Each schematically shows when Figure 5 and Figure 6 The charge state that occurs when the oxide semiconductor TFT300 in the illustrated embodiment is supplied with a gate bias and irradiated by radioactive rays. Figure 7A and Figure 8A Each schematically illustrates the state of charge generated in response to irradiation by radioactive rays (e.g., X-rays of 500 Gy or higher) when a voltage is applied between the gate electrode 302 and the source electrode 306.

[0111] Figure 7A The diagram illustrates a state where a voltage positive relative to the potential of the source electrode 306 is applied to the gate electrode 302. Under the influence of radioactive rays, electrons (-) and holes (+) are excited and generated in the silicon oxide film 312. Due to the electric field between the gate electrode 302 and the source electrode 306, holes accumulate at the interface between the top surface of the silicon oxide film 312 (the surface facing the oxide semiconductor layer 304) and the silicon nitride film 311, while electrons accumulate at the interface between the bottom surface of the silicon oxide film 312 (the surface facing the gate electrode 302) and the silicon nitride film 311.

[0112] Figure 8A The diagram illustrates a state where a voltage negative relative to the potential of the source electrode 306 is applied to the gate electrode 302. Under the influence of radioactive rays, electrons (-) and holes (+) are excited and generated in the silicon oxide film 312. Due to the electric field between the gate electrode 302 and the source electrode 306, electrons accumulate at the interface between the top surface of the silicon oxide film 312 (the surface facing the oxide semiconductor layer 304) and the silicon nitride film 311, while holes accumulate at the interface between the bottom surface of the silicon oxide film 312 (the surface facing the gate electrode 302) and the silicon nitride film 311.

[0113] exist Figure 7A and Figure 8A In each state, the distance between electrons and the oxide semiconductor layer 304 is different from the distance between holes and the oxide semiconductor layer 304. Specifically, in Figure 7A In this state, the distance between holes and the oxide semiconductor layer 304 is smaller than the distance between electrons and the oxide semiconductor layer 304. Figure 8A In this state, the distance between electrons and oxide semiconductor layer 304 is smaller than the distance between holes and oxide semiconductor layer 304.

[0114] exist Figure 7A In this state, the holes accumulate closer to the oxide semiconductor layer 304 than the electrons. Therefore, a positive electric field is generated at the interface of the oxide semiconductor layer 304 to cause the threshold voltage to shift negatively. Figure 7B This is a schematic diagram illustrating the negative shift of the threshold voltage. The horizontal axis represents the gate-source voltage, and the vertical axis represents the drain current. Figure 8A In this state, the electrons accumulate closer to the oxide semiconductor layer 304 than the holes. Therefore, a negative electric field is generated at the interface of the oxide semiconductor layer 304 to cause the threshold voltage to shift in the positive direction. Figure 8BThis is a schematic diagram illustrating the positive shift of the threshold voltage. The horizontal axis represents the gate-source voltage, and the vertical axis represents the drain current.

[0115] After the radioactive radiation and voltage application are stopped, it can be maintained Figure 7A and Figure 8A The threshold voltage of the oxide semiconductor layer 304 can be positively or negatively controlled based on its charge state. To effectively control the threshold voltage of the oxide semiconductor layer 304, it is important to generate a strong positive or negative electric field at the interface between the oxide semiconductor layer 304 and the silicon nitride film 311.

[0116] The electric field of the oxide semiconductor layer 304 is caused by the difference between the distance from electrons to the oxide semiconductor layer 304 and the distance from holes to the oxide semiconductor layer 304. (See reference...) Figure 5 and Figure 6 The silicon oxide film 312 in one embodiment of the present invention has a small area. This configuration achieves a large intensity difference between the electric fields of electrons and holes, thereby providing an effective electric field for controlling the threshold voltage of the oxide semiconductor layer 304. This phenomenon is explained below.

[0117] According to electromagnetic theory, the intensity of the electric field produced by a charge distributed on a plane along the normal to the plane increases with distance from the plane as the area of ​​the plane decreases. This can be understood from the fact that the intensity of the electric field produced by a planar charge with an infinitely large area does not depend on the distance from the plane, but the intensity of the electric field of a small planar charge, which can be considered as a point charge, depends on z. -2 , where z represents the distance from the plane.

[0118] Since the charge distribution is on the interface between the silicon oxide film 312 and the silicon nitride film 311, a planar charge with a small area can be generated by reducing the size of the silicon oxide film 312. Therefore, the electric field generated by the charge near the oxide semiconductor layer 304 and the electric field generated by the charge away from the oxide semiconductor layer 304 have a large intensity difference. Therefore, to shift the threshold voltage positively, the control should apply a voltage between the source and gate such that the charge near the oxide semiconductor layer is negative, and the TFT should be irradiated with high-energy light. Conversely, to shift the threshold voltage negatively, the control should apply a voltage between the source and gate such that the charge near the oxide semiconductor layer is positive, and the TFT should be irradiated with high-energy light.

[0119] Reference Figure 9 Describe the effect of reducing the area of ​​the silicon oxide film 312. Figure 9A graph is provided showing the relationship between the intensity of the electric field generated by planar charges of different areas and the distance from the planar charges. These relationships are based on theoretical calculations, assuming each plane has a circular shape and a constant charge density. The horizontal axis of the graph represents the distance from the planar charges (nm), and the vertical axis represents the electric field strength (AU).

[0120] Line 905 shows the relationship between the electric field strength and distance for a circular planar charge with a radius of 100 μm. Line 906 shows the relationship between the electric field strength and distance for a circular planar charge with a radius of 10 μm. Line 907 shows the relationship between the electric field strength and distance for a circular planar charge with a radius of 5 μm. Line 908 shows the relationship between the electric field strength and distance for a circular planar charge with a radius of 2 μm.

[0121] As from Figure 9 As the diagram illustrates, when a planar charge has a small area, the difference in distance from the planar charge will result in a large difference in electric field strength. Assuming the silicon oxide film 312 has a thickness of approximately 400 nm and the distance between the top surface of the silicon oxide film 312 and the lower surface of the oxide semiconductor layer 304 is approximately 10 nm, then for a silicon oxide film 312 with a radius of 100 μm, the difference in intensity between the electric field generated by electrons and the electric field generated by holes is relatively small. In contrast, for a silicon oxide film 312 with a radius of 2 μm, the difference in intensity between the electric field generated by electrons and the electric field generated by holes is relatively large. Therefore, the oxide semiconductor layer 304 can provide a stronger electric field through the charges near the oxide semiconductor layer.

[0122] The configuration of oxide semiconductor TFTs in some other embodiments of the present invention is described below. Figure 10 This is a schematic cross-sectional view illustrating the configuration of an oxide semiconductor TFT 400 according to an embodiment of the present invention. Figure 11 It is shown schematically. Figure 10 A plan view showing the positional relationship between the silicon oxide film 402, the channel region 341, and some other components in the oxide semiconductor TFT 400.

[0123] The following mainly describes and Figure 5 and Figure 6 The differences between the configuration examples in [the document / reference] and [the examples in the document / reference]. For those with [the same / previous] configuration examples, [the following is likely related to configuration examples]. Figure 5 and Figure 6 The components with the same reference numerals as those described in the figures are applicable to the description provided for the oxide semiconductor TFT 300. Compared to the silicon oxide film 312 of the oxide semiconductor TFT 300, the silicon oxide film 402 is closer to the source electrode 306 than the drain electrode 305.

[0124] Reference Figure 11The distance (minimum distance) LR between the right end of the silicon oxide film 402 and one end of the source electrode 306 is shorter than the distance (minimum distance) LL between the left end of the silicon oxide film 402 and one end of the drain electrode 305. In the plan view, the distance (minimum distance) between the centroid of the silicon oxide film 402 and that end of the source electrode 306 is shorter than the distance (minimum distance) between the centroid and that end of the drain electrode 305.

[0125] The silicon oxide film 402 has an isolated island-like shape within the silicon nitride film 311, and its entire area in the plan view lies within the channel region 341. In other words, in the plan view, the silicon oxide film 402 has an area smaller than that of the channel region 341. Figure 10 As shown, each of the regions between the silicon oxide film 402 and the oxide semiconductor layer 304, and between the silicon oxide film 402 and the gate electrode 302, is filled with a portion of the silicon nitride film 311.

[0126] The threshold voltage of an oxide semiconductor depends more on the potential of the region closer to the source electrode. Therefore, the silicon oxide film 402, which is positioned closer to the source electrode 306 than the drain electrode 305, can achieve a larger threshold voltage offset.

[0127] Figure 12 This is a cross-sectional view schematically illustrating the configuration of an oxide semiconductor TFT 420 according to another embodiment of the present invention. Figure 13 It is shown schematically. Figure 12 A plan view showing the positional relationship between the silicon oxide film 422, the channel region 341, and some other components in the oxide semiconductor TFT 420.

[0128] The following mainly describes and Figure 5 and Figure 6 The differences between the configuration examples in [the document / reference] and [the examples in the document / reference]. For those with [the same / previous] configuration examples, [the following is likely related to configuration examples]. Figure 5 and Figure 6 The components with the same reference numerals as those described in the figures are applicable to the description provided for the oxide semiconductor TFT 300. Compared to the silicon oxide film 312 of the oxide semiconductor TFT 300, in the plan view, a portion of the silicon oxide film 422 is located outside the channel region 341. Specifically, in the plan view, the source-side region of the silicon oxide film 422 does not overlap with the channel region 341. In the plan view, the source-side region of the silicon oxide film 422 overlaps with the source region 343 and / or the source electrode 306.

[0129] Reference Figure 13In the plan view, the drain-side end 423 of the silicon oxide film 422 faces the drain electrode 305. In the plan view, the entire drain-side end 423 is located on the channel region 341. The distance LS1 between the drain-side end 423 and one end of the source electrode 306 is shorter than the distance LD1 between the drain-side end 423 and one end of the drain electrode 305.

[0130] By positioning the drain-side end 423 of the silicon oxide film 422 closer to the source electrode 306 rather than the drain electrode 305, a larger threshold voltage offset is achieved. (Refer to...) Figure 14A and Figure 14B Describe the effect.

[0131] Figure 14A The diagram shows a planar charge 580 extending infinitely in both the positive and negative directions of the Y-axis and along the positive direction of the X-axis. Figure 14B Indicates by Figure 14A The diagram shows the intensity of the Z-axis component of the electric field generated by the planar charge 580 at different coordinates (x, z). The horizontal axis represents the distance along the X-axis from the end of the planar charge to the center (the value at the x-coordinate), and the vertical axis represents the intensity of the Z-axis component of the electric field. Point 0 on the horizontal axis corresponds to the position of the end of the planar charge 580.

[0132] Curve 581 represents the electric field intensity change at a z-coordinate of 500 nm, and curve 582 represents the electric field intensity change at a z-coordinate of 10 nm. As can be understood from the comparison between curves 581 and 582, the difference in electric field intensity between different z-coordinates is greater closer to the end of the planar charge. The end 423 of the silicon oxide film 422 is positioned closer to the source electrode 306 than the drain electrode 305, which can generate a large difference in the electric field intensity between vertically separated electrons and holes in the stacking direction in the region of the oxide semiconductor layer near the source electrode, thereby achieving effective threshold voltage control.

[0133] Figure 15 This is a cross-sectional view schematically illustrating the configuration of an oxide semiconductor TFT 440 in another embodiment of the present invention. Figure 16 It is shown schematically. Figure 15 A plan view showing the positional relationship between the silicon oxide film 442, the channel region 341, and some other components in the oxide semiconductor TFT 440.

[0134] The following mainly describes and Figure 5 and Figure 6 The differences between the configuration examples in [the document / reference] and [the examples in the document / reference]. For those with [the same / previous] configuration examples, [the following is likely related to configuration examples]. Figure 5 and Figure 6The components with the same reference numerals as those described in the figures are applicable to the description provided for the oxide semiconductor TFT 300. Compared to the silicon oxide film 312 of the oxide semiconductor TFT 300, in the plan view, a portion of the silicon oxide film 442 is located outside the channel region 341. Specifically, in the plan view, the drain-side region of the silicon oxide film 442 does not overlap with the channel region 341. In the plan view, the drain-side region of the silicon oxide film 442 overlaps with the drain region 342 and / or the drain electrode 305.

[0135] Reference Figure 16 In the plan view, the source-side end 443 of the silicon oxide film 442 faces the source electrode 306. In the plan view, the entire source-side end 443 lies on the channel region 341. The distance LS2 between the source-side end 443 and one end of the source electrode 306 is shorter than the distance LD2 between the source-side end 443 and one end of the drain electrode 305. (See reference...) Figure 14A and Figure 14B The source-side end 443 of the silicon oxide film 442 is located closer to the source electrode 306 than to the drain electrode 305, thereby achieving a larger threshold voltage offset.

[0136] In reference Figure 13 In the described structure of the oxide semiconductor TFT, the distance LS1 between the drain-side end 423 and one end of the source electrode 306 can be equal to or longer than the distance LD1 between the drain-side end 423 and one end of the drain electrode 305. (Refer to...) Figure 16 In the structure of the oxide semiconductor TFT described, the distance LS2 between the source side end 443 and one end of the source electrode 306 can also be equal to or longer than the distance LD2 between the source side end 443 and one end of the drain electrode 305.

[0137] Figure 17 This is a plan view schematically illustrating the configuration of an oxide semiconductor TFT 460 according to another embodiment of the present invention. The main description is related to... Figure 6 The configuration examples differ from those in the plan view. In the plan view, a portion of the silicon oxide film 462 is not located on the channel region 341; these portions are located outside the channel region 341. The ends of the silicon oxide film 462 in the channel width direction, or... Figure 17 The upper end 463 and the lower end 464 are located outside the channel region 341 in the plan view.

[0138] Therefore, a portion of the source-side end 465 of the silicon oxide film 462 is located on the channel region 341, while the remaining portion is located outside the channel region 341. Similarly, a portion of the drain-side end 466 of the silicon oxide film 462 is located on the channel region 341, while the remaining portion is located outside the channel region 341. The threshold voltage of the oxide semiconductor TFT 460 can be effectively controlled as in other embodiments of the oxide semiconductor TFT.

[0139] and Figure 5 and Figure 6 Like the oxide semiconductor TFT 300 described herein, each of the regions between the silicon oxide film 462 and the oxide semiconductor layer 304, and between the silicon oxide film 462 and the gate electrode 302, is filled with a portion of the silicon nitride film.

[0140] Although both ends of the silicon oxide film 462 in the channel width direction are located outside the channel region 341, in a plan view, one end can be located on the channel region 341 and the other end can be located outside the channel region 341. (Refer to...) Figure 17 The described configuration, or the configuration in which the ends of the silicon oxide film in the channel width direction are located outside the channel region 341 in the plan view, is applicable to reference. Figures 10 to 13 , Figure 15 and Figure 16 The configuration example described.

[0141] As mentioned above, in reference Figures 5 to 17 In the described oxide semiconductor TFT, in a planar view, at least a portion of the end facing the source electrode or drain electrode is located on the channel region.

[0142] Figure 18 and Figure 19 This is a cross-sectional view schematically illustrating the configuration of an oxide semiconductor TFT 480 according to another embodiment of the present invention. (See reference...) Figure 5 and Figure 6 Compared to the described oxide semiconductor TFT 300, the difference in this oxide semiconductor TFT 480 lies in the position of the silicon oxide film in the stacking direction; all other components are the same. Specifically, the silicon oxide film 482 is in direct contact with the gate electrode 302 and has an interface with the gate electrode 302.

[0143] Figure 18 and Figure 19 Each schematically illustrates the charge state that occurs when an oxide semiconductor TFT 480 is subjected to a gate bias and irradiated with radioactive rays. Figure 18 This illustrates the state in which a voltage is applied to the gate electrode 302 that is positive relative to the potential of the source electrode 306. Figure 19The diagram illustrates a state where the gate electrode 302 is subjected to a voltage negative relative to the source electrode 306. In either state, the oxide semiconductor layer 304 is susceptible to an electric field generated by charges trapped at the interface between the silicon nitride film 311 and the silicon oxide film 482 facing the oxide semiconductor layer 304. The silicon oxide film may also be compared with a reference... Figures 10 to 17 The gate electrode in the described oxide semiconductor TFT is in direct contact.

[0144] In reference Figures 5 to 19 In the described oxide semiconductor TFT, the metal oxide film in the gate insulating film can be made of a material different from silicon oxide. For example, aluminum oxide can be used instead of silicon oxide. Furthermore, the insulating film, exemplified by silicon nitride film 311, is not particularly limited in material; for example, silicon oxynitride can be used. In other examples, a stacked structure of silicon nitride film and silicon oxynitride film or multiple layers of silicon nitride film can replace silicon nitride film 311.

[0145] For example, a lower layer made of silicon nitride or silicon oxynitride can be disposed between the metal oxide film and the bottom gate electrode, and an upper layer made of silicon nitride or silicon oxynitride can be disposed between the metal oxide film and the oxide semiconductor layer. There is no particular limitation on the number of insulating film layers surrounding the metal oxide film. The metal oxide film can also have a single-layer or multi-layer structure.

[0146] In one embodiment of the present invention, the oxide semiconductor TFT may have a top gate electrode, instead of the reference one. Figures 5 to 19 The bottom gate electrode is described. The gate insulating film between the top gate electrode and the oxide semiconductor layer can have the following characteristics as shown in the reference. Figures 5 to 19 The various structures described above.

[0147] In another embodiment of the present invention, the oxide semiconductor TFT may have both a top gate electrode and a bottom gate electrode. The top gate insulating film between the top gate electrode and the oxide semiconductor layer, and the bottom gate insulating film between the bottom gate electrode and the oxide semiconductor layer, may have the structure of a gate insulating film as described in the foregoing embodiments.

[0148] In reference Figures 5 to 19 In the described oxide semiconductor TFT, the source electrode and drain electrode are disposed above the oxide semiconductor layer (above the oxide semiconductor layer). In another configuration example, the source electrode and drain electrode may be disposed below the oxide semiconductor layer (below the oxide semiconductor layer).

[0149] The following describes some examples of methods for manufacturing the gate insulating film of an oxide semiconductor TFT, and more specifically, the gate insulating film of an oxide semiconductor TFT. Examples of methods to be described produce a gate insulating film with a structure in which an isolated silicon oxide film is embedded within a silicon nitride insulating film. Other components can be produced by well-known methods, and therefore their description is omitted herein. The film of each component can be formed, patterned, etched, and / or removed using any well-known method.

[0150] Reference Figures 20A to 20J Describe the first manufacturing method. (Refer to...) Figure 20A This method involves depositing a gate metal film 602 on a substrate 601, patterning the gate metal film 602, depositing a silicon nitride film 603 above the gate metal film 602, and patterning a photoresist 604. Next, referring to... Figure 20B This method etches the silicon nitride film 603 to the desired depth within the openings of the photoresist 604. Next, refer to... Figure 20C This method removes photoresist 604.

[0151] Next, refer to Figure 20D This method involves depositing a silicon oxide film 605 and patterning a photoresist 606. Next, referring to... Figure 20E This method involves etching a silicon oxide film 605 within the openings of the photoresist 606. Next, refer to... Figure 20F This method removes photoresist 606. Next, refer to... Figure 20G The method involves depositing a silicon nitride film 607 over a silicon oxide film 605 over the entire region of the TFT.

[0152] Next, refer to Figure 20H This method involves depositing an oxide semiconductor film 609 and patterning a photoresist 610. The stacked structure of silicon nitride films 603 and 607 is indicated by reference numeral 608. Next, referring to... Figure 20I This method etches the oxide semiconductor film 609. Next, refer to... Figure 20J This method removes photoresist 610.

[0153] Reference Figures 21A to 21J A second manufacturing method is described. This method is more complex than the first manufacturing method, but it improves the thickness uniformity of the gate insulating film. (See reference...) Figure 21A The method involves depositing a gate metal film 632 on a substrate 631, patterning the gate metal film 632, depositing a silicon nitride film 633 and an etch stop layer 634 above the gate metal film 632, and patterning the photoresist 635.

[0154] Next, refer to Figure 21B This method etches the etch stop layer 634. Next, refer to... Figure 21C This method uses the etch stop layer 634 as a mask to etch the silicon nitride film 633. Next, refer to... Figure 21D The method involves depositing a silicon oxide film 636 over the entire etch stop layer 634.

[0155] Next, refer to Figure 21E This method etches the silicon oxide film 636 until the silicon oxide above the etch stop layer 634 is removed. During this process, the etch stop layer 634 prevents over-etching of the silicon nitride film 633. Next, refer to... Figure 21F This method removes the etch stop layer 634. Next, refer to... Figure 21G The method deposits a silicon nitride film 637 over the silicon oxide film 636 over the entire region of the TFT.

[0156] Next, refer to Figure 21H The stacked structure of silicon nitride films 633 and 637 is indicated by reference numeral 638. The method involves depositing an oxide semiconductor film 639 over the silicon nitride 638, depositing photoresist 640 over the oxide semiconductor film 639, and patterning the photoresist 640. Next, referring to… Figure 21I This method etches the oxide semiconductor film 639. Next, refer to... Figure 21J This method removes 640 photoresist.

[0157] As described above, embodiments of the present invention have been presented; however, the present invention is not limited to the embodiments described above. Those skilled in the art can readily modify, add to, or transform the components of the above embodiments within the scope of the present invention. A portion of the configuration of one embodiment can be replaced by the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. An oxide semiconductor thin-film transistor, comprising: Gate electrode; Source electrode; Drain electrode; An oxide semiconductor layer connected to the source electrode and the drain electrode; as well as A gate insulating film located between the gate electrode and the oxide semiconductor layer in the stacking direction; The oxide semiconductor layer includes a channel region. The gate insulating film includes: Metal oxide films; and The first insulating film is made of silicon nitride and / or silicon oxynitride. Wherein, a portion of the first insulating film is disposed between the metal oxide film and the oxide semiconductor layer, and In the plan view, at least a portion of the first end of the metal oxide film is located on the channel region and faces either the source electrode or the drain electrode.

2. The oxide semiconductor thin-film transistor according to claim 1, wherein, The minimum distance between the first end and the source electrode is shorter than the minimum distance between the first end and the drain electrode.

3. The oxide semiconductor thin-film transistor according to claim 2, in, In the plan view, the first end faces the source electrode. In the plan view, the metal oxide film includes a second end facing the drain electrode, and In the plan view, at least a portion of the second end is located on the channel region.

4. The oxide semiconductor thin-film transistor according to claim 1, in, The metal oxide film has an island-like shape. In the plan view, the area of ​​the metal oxide film is smaller than the area of ​​the channel region, and In the plan view, the entire metal oxide film is located on the channel region.

5. The oxide semiconductor thin-film transistor according to claim 1 or 4, wherein, The entire surface of the metal oxide film is surrounded by the first insulating film.

6. The oxide semiconductor thin-film transistor according to claim 5, wherein, In the plan view, the minimum distance between the centroid of the metal oxide film and the source electrode is shorter than the minimum distance between the centroid of the metal oxide film and the drain electrode.

7. The oxide semiconductor thin-film transistor according to claim 1, wherein, The metal oxide film has an interface with the gate electrode.

8. The oxide semiconductor thin-film transistor according to claim 1, wherein, The metal oxide film is made of silicon oxide, and the first insulating film is made of silicon nitride.

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