Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate, and forming an epitaxial layer on the substrate; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; etching the amorphous carbon layer to form an opening for exposing the polycrystalline silicon layer by taking the patterned photoresist layer as a mask; and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. The method can shorten the processing time and reduce the preparation cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Technology

[0002] In the fabrication of semiconductor structures, P-type or N-type doped regions need to be formed in the epitaxial layer. Generally, a multilayer dielectric structure is used as a barrier layer, typically consisting of three or more layers. The multilayer dielectric structure is then etched stepwise to define the implantation regions. Subsequently, ion implantation is performed on the epitaxial layer using the multilayer dielectric structure as a barrier layer to form P-type or N-type doped regions. However, forming a multilayer dielectric structure requires multiple film growth processes, and stepwise etching of the multilayer dielectric structure requires multiple etching processes, resulting in a long process cycle and high fabrication costs. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating semiconductor structures, thereby shortening the process time and reducing the fabrication cost.

[0004] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] A substrate is provided on which an epitaxial layer is formed;

[0006] A polycrystalline silicon layer and an amorphous carbon layer are sequentially formed on the epitaxial layer from bottom to top;

[0007] A patterned photoresist layer is formed on the amorphous carbon layer;

[0008] Using a patterned photoresist layer as a mask, the amorphous carbon layer is etched to form openings exposing the polysilicon layer; and,

[0009] An ion implantation process is performed to form a doped region in the epitaxial layer below the bottom of the opening.

[0010] Optionally, the thickness of the amorphous carbon layer is greater than the thickness of the polycrystalline silicon layer.

[0011] Optionally, the thickness of the amorphous carbon layer is 1.8 μm to 2.2 μm.

[0012] Optionally, the thickness of the polycrystalline silicon layer is 0.45μm to 0.55μm.

[0013] Optionally, the polycrystalline silicon layer is an undoped polycrystalline silicon layer.

[0014] Optionally, when etching the amorphous carbon layer to form an opening exposing the polysilicon layer, a portion of the polysilicon layer is simultaneously etched so that the opening extends into the polysilicon layer.

[0015] Optionally, the thickness of the etched polysilicon layer is 8 nm to 12 nm.

[0016] Optionally, after etching the amorphous carbon layer to form an opening exposing the polysilicon layer, the patterned photoresist layer is removed.

[0017] Optionally, the depth of the doped region is less than the thickness of the epitaxial layer.

[0018] Optionally, the doping type of the doped region is P-type or N-type.

[0019] The semiconductor structure fabrication method provided by this invention includes: providing a substrate on which an epitaxial layer is formed; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; using the patterned photoresist layer as a mask, etching the amorphous carbon layer to form an opening exposing the polycrystalline silicon layer; and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. This invention requires only two film growth steps, namely, sequentially forming a polycrystalline silicon layer and an amorphous carbon layer, thus saving film growth steps, and only requires one etching step, namely etching the amorphous carbon layer to form the opening exposing the polycrystalline silicon layer, thus saving etching steps, thereby shortening the process time and reducing the fabrication cost. Attached Figure Description

[0020] Figures 1-5 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor structure.

[0021] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0022] Figures 7-10 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0023] in, Figures 1-5 The attached figures are labeled as follows:

[0024] 10-Substrate; 20-Epipolar layer; 31-First oxide layer; 32-Polysilicon layer; 33-Second oxide layer; 40-Patterned photoresist layer; 50-Opening; 60-Doped region.

[0025] Figures 7-10 The attached figures are labeled as follows:

[0026] 100 - Substrate; 200 - Epitaxial layer; 310 - Polycrystalline silicon layer; 320 - Amorphous carbon layer; 400 - Patterned photoresist layer; 500 - Opening; 600 - Doped region. Detailed Implementation

[0027] Figures 1-5 This is a cross-sectional schematic diagram of a corresponding step in a semiconductor structure fabrication method. Please refer to it. Figure 1 A substrate 10 is provided, on which an epitaxial layer 20 is formed. Then, a first oxide layer 31, a polysilicon layer 32, and a second oxide layer 33 are sequentially formed on the epitaxial layer 20. The process involves three film growth steps, wherein the thickness of the polysilicon layer 32 is greater than the thickness of the first oxide layer 31 and the second oxide layer 33, and the polysilicon layer 32 serves as the main barrier layer.

[0028] Please refer to Figure 2 A photoresist layer is formed on the second oxide layer 33, and a patterned photoresist layer 40 is obtained by exposure and development; please refer to Figure 3 Using the patterned photoresist layer 40 as a mask, the second oxide layer 33 is etched to form an opening 50 exposing the polysilicon layer 32; please refer to Figure 4 Using the patterned photoresist layer 40 as a mask, the polysilicon layer 32 is etched so that the bottom of the opening 50 extends to the surface of the first oxide layer 31, that is, the opening 50 exposes the first oxide layer 31. This etching process utilizes two etching steps, and then the patterned photoresist layer 40 is removed.

[0029] Please refer to Figure 5 A polysilicon layer 32 and a second oxide layer 33 are used as barrier layers, with the polysilicon layer 32 being the primary barrier layer. Due to the relatively thick thickness of the polysilicon layer 32 and its lattice structure providing good barrier properties, ions entering the polysilicon layer 32 are trapped within it and do not enter the epitaxial layer 20. An ion implantation process (the direction of the dashed arrow in the figure indicates the ion implantation direction) is performed to form a P-type or N-type doped region 60 in the epitaxial layer 20 below the bottom of the opening 50. The above preparation method utilizes three film growth processes and two etching processes, resulting in a long process cycle, high preparation cost, and making it difficult to simplify the process and reduce costs.

[0030] Based on this, the present invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate on which an epitaxial layer is formed; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; using the patterned photoresist layer as a mask, etching the amorphous carbon layer to form an opening exposing the polycrystalline silicon layer; and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. The present invention requires only two film growth steps, namely, sequentially forming a polycrystalline silicon layer and an amorphous carbon layer, thus saving film growth steps, and only requires one etching step, namely etching the amorphous carbon layer to form the opening exposing the polycrystalline silicon layer, thus saving etching steps, thereby shortening the process time and reducing the fabrication cost.

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The accompanying drawings are all in a very simplified form and are not drawn to scale, only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures; in particular, different proportions are sometimes used because different drawings need to show different focuses.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] Figure 6 This is a flowchart illustrating the method for fabricating the semiconductor structure provided in this embodiment. Please refer to... Figure 6 This embodiment provides a method for fabricating a semiconductor structure, including:

[0036] Step S1: Provide a substrate on which an epitaxial layer is formed;

[0037] Step S2: A polycrystalline silicon layer and an amorphous carbon layer are formed sequentially from bottom to top on the epitaxial layer;

[0038] Step S3: Form a patterned photoresist layer on the amorphous carbon layer;

[0039] Step S4: Using the patterned photoresist layer as a mask, etch the amorphous carbon layer to form an opening that exposes the polysilicon layer;

[0040] Step S5: Perform an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening.

[0041] Figures 7-10 This is a cross-sectional schematic diagram of a corresponding step in the semiconductor structure fabrication method provided in this embodiment. The following is in conjunction with… Figures 7-10 The method for fabricating the semiconductor structure provided in this embodiment will be described in detail.

[0042] Please refer to Figure 7 Step S1: Provide a substrate 100, preferably a silicon carbide substrate, but not limited to this. An epitaxial layer 200 is epitaxially grown on the substrate 100, and the material of the epitaxial layer 200 can be silicon carbide, gallium nitride, etc.

[0043] Please continue to refer to this. Figure 7 Step S2 involves sequentially forming a polycrystalline silicon layer 310 and an amorphous carbon layer 320 on the epitaxial layer 200 from bottom to top. Specifically, the polycrystalline silicon layer 310 is first formed on the epitaxial layer 200. The polycrystalline silicon layer 310 is an undoped polycrystalline silicon layer, which can buffer the penetration of ion impact forces into the epitaxial layer 200, allowing ions to remain within the epitaxial layer 200. Then, the amorphous carbon layer 320 is formed on the polycrystalline silicon layer 310. The amorphous carbon layer 320 acts as the main barrier layer, blocking ion implantation in the non-implanted regions, thus preventing ion implantation in these regions. Forming the polycrystalline silicon layer 310 and the amorphous carbon layer 320 requires two film growth processes, which saves film growth steps compared to conventional methods. In this embodiment, since the interior of the amorphous carbon layer 320 is a disordered amorphous solid, and the polycrystalline silicon layer 310 is formed by countless grains with different lattice orientations spliced ​​together by disordered grain boundaries, the amorphous carbon layer 320 can be formed on the polycrystalline silicon layer 310; and since the interior of the amorphous carbon layer 320 is a disordered amorphous solid, it can play a good blocking role.

[0044] In this embodiment, the thicknesses of the polysilicon layer 310 and the amorphous carbon layer 320 need to be specifically set. If the polysilicon layer 310 is too thick, ions will have difficulty penetrating it or the ion implantation depth will be insufficient. If the amorphous carbon layer 320 is too thick, it will easily collapse. Since the amorphous carbon layer 320 acts as a barrier in the non-implanted ion region, while the polysilicon layer 310 acts as a buffer against ion impact, the amorphous carbon layer 320 is relatively thick, while the polysilicon layer 310 is relatively thin, with the amorphous carbon layer 320 being thicker than the polysilicon layer 310. In this embodiment, the thickness of the amorphous carbon layer 320 is preferably 1.8 μm to 2.2 μm, and the thickness of the polysilicon layer 310 is preferably 0.45 μm to 0.55 μm, but may vary slightly above or below these ranges.

[0045] Please refer to Figure 8 Step S3: A patterned photoresist layer 400 is formed on the amorphous carbon layer 320. Specifically, a photoresist layer is formed on the amorphous carbon layer 320, and then the patterned photoresist layer 400 is obtained by exposure and development. The patterned photoresist layer 400 exposes part of the surface of the amorphous carbon layer 320 to define the ion implantation region.

[0046] Please refer to Figure 9 Step S4: Using the patterned photoresist layer 400 as a mask, the amorphous carbon layer 320 is etched to form an opening 500 exposing the polysilicon layer 310. While etching the amorphous carbon layer 320 to form the opening, a portion of the polysilicon layer 310 is simultaneously etched so that the bottom of the opening 500 extends into the polysilicon layer 310. This is over-etching to ensure complete etching of the amorphous carbon layer 320. Care should be taken to avoid excessive etching of the polysilicon layer 310, which would result in a thinner polysilicon layer 310 at the bottom of the opening 500, thus affecting the buffering effect of the polysilicon layer 310 on ions. Etching the amorphous carbon layer 320 to form the opening 500 exposing the polysilicon layer 310 requires one etching step, saving etching steps compared to conventional methods. In this embodiment, the thickness d of the etched polysilicon layer 310 can be 8nm to 12nm, for example, 10nm, but is not limited to this. After etching, the patterned photoresist layer 400 is removed.

[0047] Please refer to Figure 9Step S5: Perform an ion implantation process to form a doped region 600 in the epitaxial layer 200 below the bottom of the opening 500. During ion implantation (the direction of the dashed arrow in the figure indicates the ion implantation direction), the amorphous carbon layer 320 acts as a barrier layer in the non-implanted region, preventing ions from being implanted into the epitaxial layer 200. The opening 500 region corresponds to the ion implantation region, where ions can penetrate the polysilicon layer 310 and implant into the epitaxial layer. The polysilicon layer 310 also acts as a buffer against ion impact, preventing ions from implanting into the substrate 100. This allows for the selective formation of the doped region 600 in the epitaxial layer 200. The depth of the doped region 600 is less than the thickness of the epitaxial layer 200, and the doping type of the doped region 600 can be P-type or N-type. The depth of the doped region 600 is determined based on the thickness of the polysilicon layer 310, and appropriate ion implantation parameters, such as doping energy and doping dose, are matched accordingly.

[0048] In summary, the semiconductor structure fabrication method provided by this invention includes: providing a substrate on which an epitaxial layer is formed; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; using the patterned photoresist layer as a mask, etching the amorphous carbon layer to form an opening exposing the polycrystalline silicon layer; and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. This invention requires only two film growth steps, namely, sequentially forming a polycrystalline silicon layer and an amorphous carbon layer, thus saving film growth steps, and only requires one etching step, namely etching the amorphous carbon layer to form the opening exposing the polycrystalline silicon layer, thus saving etching steps, thereby shortening the process time and reducing the fabrication cost.

[0049] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which an epitaxial layer is formed; A polycrystalline silicon layer and an amorphous carbon layer are sequentially formed on the epitaxial layer from bottom to top; A patterned photoresist layer is formed on the amorphous carbon layer; Using a patterned photoresist layer as a mask, the amorphous carbon layer is etched to form an opening that exposes the polysilicon layer; as well as, An ion implantation process is performed to form a doped region in the epitaxial layer below the bottom of the opening.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The thickness of the amorphous carbon layer is greater than the thickness of the polycrystalline silicon layer.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The thickness of the amorphous carbon layer is 1.8 μm to 2.2 μm.

4. The method for preparing a semiconductor structure as described in claim 2, characterized in that, The thickness of the polycrystalline silicon layer is 0.45μm to 0.55μm.

5. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The polycrystalline silicon layer is an undoped polycrystalline silicon layer.

6. The method for preparing a semiconductor structure as described in claim 1, characterized in that, When etching the amorphous carbon layer to form an opening that exposes the polysilicon layer, a portion of the polysilicon layer is simultaneously etched so that the opening extends into the polysilicon layer.

7. The method for preparing a semiconductor structure as described in claim 6, characterized in that, The thickness of the etched polysilicon layer is 8nm to 12nm.

8. The method for preparing a semiconductor structure as described in claim 1, characterized in that, After etching the amorphous carbon layer to form an opening that exposes the polysilicon layer, the patterned photoresist layer is removed.

9. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The depth of the doped region is less than the thickness of the epitaxial layer.

10. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The doping type of the doped region is P-type or N-type.

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