Semiconductor device

Abstract

A semiconductor device is provided with a drift layer (11) of a first conductivity type, a body layer (13) of a second conductivity type, a lower surface electrode (28), a gate wiring (21) connected to a gate electrode (20), a gate insulating film (19), and an upper surface electrode (26). A depletion region (16) of the first conductivity type, which is depleted in a state in which an applied voltage between the lower surface electrode and the upper surface electrode is 0 V, is formed in a portion of a surface layer portion on the upper surface side of the body layer, said portion being located below the gate wiring. The depletion region is formed at a lower portion of at least a portion of an end portion of the gate wiring. An upper surface of the body layer is exposed from the depletion region at a lower portion of at least a portion of a portion of the gate wiring inside the end portion.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Semiconductor devices such as MOSFETs are configured such that a body layer is stacked on the upper surface of a drift layer, a drain electrode is formed on the lower surface of the drift layer, and a gate wiring and a source electrode are formed on the upper surface of the body layer. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0003] In such a semiconductor device, during recovery, displacement current flows to the body layer through the PN junction capacitance between the drift layer and the body layer. At this time, due to the path resistance of the body layer, the potential of the body layer rises, creating a potential difference between the gate wiring and the body layer. If this potential difference becomes large, a high electric field is applied to the gate insulating film formed between the body layer and the gate wiring, which can easily lead to breakdown.

[0004] The semiconductor device described in Patent Document 1 includes a MOSFET element comprising a p-type body layer stacked on the upper surface of an n-type drift layer, wherein a p-type body layer is formed on the upper surface side layer of the body layer in such a manner as to be in contact with the gate insulating film. + Type area.

[0005] p + The type region is formed in the entire area below the gate wiring in the surface portion of the body layer. Additionally, p + The type region is connected to the source potential by n + The p-type region covers the sides and lower surface, and the p-type region and p-type region of the body layer + Type region is n + Type separation. This configuration suppresses displacement current towards p. + Invasion of the type region, inhibited by p + The breakdown of the gate insulating film caused by the potential rise in the type region.

[0006] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2021-125638 Summary of the Invention

[0007] In the semiconductor device described in Patent Document 1, at p + Type region and n + In the lower part of the p-type region, the p-type region is thinner than other parts of the p-type region, therefore the path resistance of the displacement current in the p-type region is larger than in other parts. Therefore, if the entire surface layer of the body layer below the gate wiring is formed into a p-type region... + Type region and n+ In the high-resistance region, the path resistance increases, causing a localized temperature rise during recovery, which poses a risk of component breakdown.

[0008] In view of the above points, the object of this disclosure is to provide a semiconductor device capable of improving recovery breakdown tolerance.

[0009] To achieve the above objectives, according to one aspect of the present invention, a semiconductor device includes: a drift layer of a first conductivity type; a body layer of a second conductivity type stacked on the upper surface of the drift layer; a lower surface electrode formed on the lower surface side of the drift layer; a gate wiring formed on the upper surface side of the body layer and connected to the gate electrode; a gate insulating film formed between the upper surface of the body layer and the gate wiring; and an upper surface electrode formed on the upper surface side of the body layer. A depletion region of the first conductivity type is formed in the lower portion of the surface layer portion on the upper surface side of the body layer, where it is depleted when a voltage of 0V is applied between the lower surface electrode and the upper surface electrode. The depletion region is formed in the lower portion of at least a portion of the ends of the gate wiring, and in the lower portion of at least a portion of the portion of the gate wiring that is inward from the ends, the upper surface of the body layer is exposed from the depletion region.

[0010] The depletion region is less susceptible to potential rise caused by displacement current flowing through the body layer. Therefore, if a depletion region is formed at the bottom of the gate wiring, the electric field applied to the gate insulating film is reduced. Near the end of the gate wiring, compared to the area near the inner portion of the end, the gate insulating film is more susceptible to a higher electric field, leading to breakdown. Therefore, by forming a depletion region at the bottom of at least a portion of the end of the gate wiring, breakdown of the gate insulating film can be suppressed. Furthermore, by configuring the upper surface of the body layer to expose from the depletion region at the bottom of at least a portion of the inner portion of the gate wiring, the increase in path resistance at the bottom of this inner portion can be suppressed, thereby suppressing device breakdown caused by temperature rise.

[0011] This can improve recovery breakdown resistance. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0013] Figure 2 yes Figure 1 A magnified view of the area near the depletion region.

[0014] Figure 3 It is a top view of the body layers.

[0015] Figure 4A It is a cross-sectional view showing the manufacturing process of a semiconductor device.

[0016] Figure 4B It means to continue Figure 4A A cross-sectional view of the manufacturing process of a semiconductor device.

[0017] Figure 4C It means to continue Figure 4B A cross-sectional view of the manufacturing process of a semiconductor device.

[0018] Figure 4D It means to continue Figure 4C A cross-sectional view of the manufacturing process of a semiconductor device.

[0019] Figure 5 This is a sectional view of a comparative example.

[0020] Figure 6 This is a cross-sectional view showing the path resistance of the first embodiment.

[0021] Figure 7 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0022] Figure 8 This is a cross-sectional view of the semiconductor device according to the third embodiment.

[0023] Figure 9 This is a top view of the body layer in the fourth embodiment.

[0024] Figure 10 This is a top view of the body layer in the fourth embodiment.

[0025] Figure 11 This is a top view of the body layer in other embodiments.

[0026] Figure 12 This is a top view of the body layer in other embodiments. Detailed Implementation

[0027] Hereinafter, embodiments of the present disclosure will be described based on the accompanying drawings. Furthermore, in the following embodiments, the same or equivalent parts will be described using the same reference numerals.

[0028] (First Implementation) The first embodiment will be described. Figure 1 The semiconductor device 1 shown in this embodiment includes a MOSFET element. The region in the semiconductor device 1 that operates as a MOSFET element is designated as the active region 2, and the other regions are designated as the non-active region 3. In this embodiment, the MOSFET element included in the semiconductor device 1 will be described as an n-channel element with n-type as the first conductivity type and p-type as the second conductivity type.

[0029] Semiconductor device 1 includes a substrate 10. The substrate 10 is made of n-type SiC (silicon carbide). An n-type drift layer 11 is formed on the upper surface of the substrate 10.

[0030] Let the direction parallel to the upper surface of layer 13 (described later) be the x-direction. Let the direction perpendicular to the upper surface of layer 13, i.e., the thickness direction of layer 13, be the y-direction. Let the direction parallel to the upper surface of layer 13 and perpendicular to the x-direction be the z-direction.

[0031] The drift layer 11 is configured to function as an electric field mitigation layer. Specifically, a plurality of linear p-type pillar regions 12 extending in the z-direction are formed on the surface portion of the upper surface of the drift layer 11, and the surface portion of the drift layer 11 is configured as an SJ (Super Junction) structure in which n-type regions and p-type pillar regions 12 are alternately arranged in the x-direction.

[0032] A bulk layer 13 doped with p-type impurities is stacked on the upper surface of the drift layer 11. An n-type region 14 and a p-type impurity are formed on the surface portion of the upper surface of the bulk layer 13. + Type 15, Depletion Zone 16.

[0033] n-type region 14 forms in active region 2, and depletion region 16 forms in non-active region 3. p + A portion of region 15 is formed in active region 2, and the rest is formed in non-active region 3. (The last part, "p," appears to be a typo and can be omitted.) + The portion of region 15 formed in active region 2 is designated as p. + Type region 15a, the portion formed in the non-active region 3 is designated as p. + Type 15b.

[0034] A trench 17 is formed in the active region 2, with a through-body layer 13 and an n-type region 14 extending into the interior of the drift layer 11. The n-type region 14 is disposed on both sides of the trench 17 in the x-direction.

[0035] p + Region 15 is a region where the concentration of p-type impurities is higher than that of p-type column region 12 and bulk layer 13. + Type 15a is formed to connect with type n-14 from the side opposite to trench 17. That is, p + Type 15a includes a portion that connects to an n-type region 14 located on one side of the x-direction relative to the trench 17 in the x-direction from one side and a portion that connects to an n-type region 14 located on the other side of the x-direction relative to the trench 17 from the other side of the x-direction.

[0036] p +Type region 15b is a contact portion connecting body layer 13 to source electrode 26 (described later), and is disposed between active region 2 and depletion region 16. Depletion region 16 is disposed at the lower part of the end of the first gate wiring 21 (described later). Depletion region 16 is a region where the n-type impurity concentration is lower than that of substrate 10, drift layer 11, and n-type region 14. Depletion region 16 is formed to deplete when a voltage of 0V is applied between drain electrode 28 (described later) and source electrode 26.

[0037] A field insulating film 18 composed of SiO2 (silicon oxide) is stacked on the upper surface of the body layer 13 included in the non-active region 3. The upper surface of the depletion region 16 is covered by the field insulating film 18. A gate insulating film 19 composed of SiO2 is stacked on the upper surface of the field insulating film 18 and on the upper surface of the body layer 13 exposed from the field insulating film 18. The gate insulating film 19 is also formed inside the trench 17, and the walls and bottom surface of the trench 17 are covered by the gate insulating film 19.

[0038] A gate electrode 20 is formed by filling the interior of trench 17 with polysilicon (Poly-Si). The gate electrode 20 is insulated from the drift layer 11, the body layer 13, and the n-type region 14 by a gate insulating film 19. A first gate wiring 21 made of Poly-Si is formed on the upper surface of the gate insulating film 19. The first gate wiring 21 is a lead used to connect the gate electrode 20 to the second gate wiring 27 (described later), and is connected to the gate electrode 20 in portions not shown. An interlayer insulating film 22 made of SiO2 is formed on the upper surfaces of the gate insulating film 19, the gate electrode 20, and the first gate wiring 21.

[0039] In the active region 2, a through-gate insulating film 19 and an interlayer insulating film 22 are formed, thereby making the n-type region 14 and the p-type region 15... + The groove 23 is exposed on the upper surface of the part that is connected to the type region 15a.

[0040] In the non-active region 3, a through-field insulating film 18, a gate insulating film 19, and an interlayer insulating film 22 are formed to enable p + The trench 24 is exposed on the upper surface of the type region 15b. The trench 25 is exposed on the upper surface of the first gate wiring 21 due to the formation of a through interlayer insulating film 22 in the non-active region 3.

[0041] An Al-Si (aluminum-silicon) layer is formed on the upper surface of the interlayer insulating film 22, and this Al-Si layer constitutes the source electrode 26 and the second gate wiring 27. The source electrode 26 is equivalent to the upper surface electrode. A recess is formed between the source electrode 26 and the second gate wiring 27, exposing the upper surface of the interlayer insulating film 22, and the source electrode 26 is electrically insulated from the second gate wiring 27. In addition to being formed on the upper surface of the interlayer insulating film 22, the source electrode 26 is also formed inside the trenches 23 and 24, and is connected to the n-type region 14 and p-type region 27. + Connect areas 15a and 15b.

[0042] The second gate wiring 27 is formed not only on the upper surface of the interlayer insulating film 22 but also inside the trench 25, and is connected to the first gate wiring 21. The gate electrode 20 is connected to a pad (not shown) via the first gate wiring 21 and the second gate wiring 27. A drain electrode 28 made of Al-Si is stacked on the lower surface of the substrate 10. The drain electrode 28 corresponds to the lower surface electrode.

[0043] Details of the configuration of the depletion region 16 are explained. The depletion region 16 is formed at the lower part of at least a portion of the end of the first gate wiring 21. In addition, the depletion region 16 is not formed at the lower part of at least a portion of the portion of the first gate wiring 21 that is inside the end. At the lower part of at least a portion of the portion of the first gate wiring 21 that is inside the end, the upper surface of the body layer 13 is exposed from the depletion region 16.

[0044] In this embodiment, the depletion region 16 is formed in Figure 2 , Figure 3 The location shown. Figure 3 Region Re1 represents the portion of body layer 13 opposite to the first gate wiring 21. Additionally, in Figure 2 The diagram only shows a portion of the first gate wiring 21. Figure 3 In the middle, the layers 13 and Figure 2 The portion opposite to a part of the first gate wiring 21 shown is illustrated as region Re1.

[0045] Specifically, the first gate wiring 21 includes a rectangular portion with the z-direction as its long side and the x-direction as its short side, and a portion connecting this rectangular portion to the gate electrode 20. Furthermore, in Figure 2 In the diagram, only the rectangular portion of the first gate wiring 21 is shown. Figure 3 In the diagram, the part opposite to the rectangular part is illustrated as region Re1.

[0046] In the x-direction, the portions of both ends of the first gate wiring 21 relative to the center of the first gate wiring 21 are located at the p-direction. + The end opposite to the type region 15b is designated as the first end 21a, and the center portion of the first gate wiring 21 is located at p. + The end on the same side as the type region 15b is designated as the second end 21b. For example... Figure 3 As shown, the depletion region 16 is a straight-line region extending in the z-direction along the first end 21a and the second end 21b.

[0047] Specify the dimensions of the depletion region 16. For example... Figure 2As shown, the depletion region 16 protrudes outward from the end of the first gate wiring 21 in the x direction. The width of the protruding portion in the x direction is designated as X1. In addition, a part of the depletion region 16 overlaps with the first gate wiring 21 in the x direction. The width of the overlapping portion in the x direction is designated as X2. The width of the first gate wiring 21 in the x direction is designated as X3.

[0048] As described later, breakdown of the field insulating film 18 and the gate insulating film 19 is suppressed by the depletion region 16. To obtain this effect, it is preferable that 0 < X1 < 5 μm and 0 < X2 < X3. In addition, the conditions for these X1 and X2 are not necessary. For example, X1 can be 0, X1 can be ≥5 μm, or X2 can be 0. In addition, the sizes of the depletion region 16 under the first end portion 21a and the depletion region 16 under the second end portion 21b can also be different.

[0049] In addition, the width of the depletion region 16 in the y direction is designated as Y1, and the width of the body layer 13 in the y direction is designated as Y2, and 0 < Y1 < Y2 is set.

[0050] Use Figures 4A-4D The manufacturing method of the semiconductor device 1 will be described. In addition, in Figures 4A-4D the illustration of the active region 2 and the substrate 10 is omitted. In the process shown in Figure 4A an n-type substrate 10 made of SiC is prepared, and a drift layer 11 made of SiC is epitaxially grown on the upper surface of the substrate 10. Then, a p-type pillar region 12 is formed by ion implantation into the drift layer 11. Furthermore, a body layer 13 is formed by ion implantation.

[0051] In Figure 4B the process shown, an n-type region 14, a p + -type region 15, and a depletion region 16 are formed by ion implantation into the body layer 13. In addition, the formation of the n-type region 14, the p + -type region 15, and the depletion region 16 can be performed in any order. When forming the depletion region 16, the film formation conditions and the ion implantation conditions are set so that the donor density N D satisfies Equation 4. Thus, when the voltage applied between the drain electrode 28 and the source electrode 26 is 0 V, the depletion region 16 is depleted. After forming the n-type region 14, the p + -type region 15, and the depletion region 16, a trench 17 is formed by etching.

[0052] In Figure 4C the process shown, in the non-active region 3, by thermal oxidation on the body layer 13, p +The upper surfaces of the type region 15b and the depletion region 16 form a field insulating film 18. Then, on the upper surface of the body layer 13 exposed from the field insulating film 18, the upper surface of the n-type region 14, the upper surface of the p + type region 15a, the wall surface and the bottom surface of the trench 17, and the upper surface of the field insulating film 18, a gate insulating film 19 is formed by thermal oxidation. Then, by CVD (Chemical Vapor Deposition), a gate electrode 20 is formed inside the trench 17, and a first gate wiring 21 is formed on the upper surface of the gate insulating film 19.

[0053] In Figure 4D the process shown, an interlayer insulating film 22 is formed by thermal oxidation on the upper surfaces of the gate insulating film 19, the gate electrode 20, and the first gate wiring 21. Then, trenches 23, 24, and 25 are formed by etching. In Figure 4D the process shown, a source electrode 26 and a second gate wiring 27 are formed on the upper surface side of the substrate 10 by sputtering, and a drain electrode 28 is formed on the lower surface of the substrate 10, thereby forming Figure 1 the semiconductor device 1 shown.

[0054] Explain the conditions for depletion of the depletion region 16. In Figure 4B the process shown, depletion occurs from the body layer 13 toward the center of the portion that becomes the depletion region 16. Let the width of the depleted region in the direction from the body layer 13 toward the center of the depletion region 16 be W depl,n . In the case of forming a horizontally long depletion region 16, that is, when X1 + X2 > Y1, if W depl,n ≥ Y1, the entire depletion region 16 is depleted. Additionally, in the case of forming a vertically long depletion region 16, that is, when X1 + X2 < Y1, if W depl,n ≥ (X1 + X2) / 2, the entire depletion region 16 is depleted.

[0055] The width W depl,n is represented by Equation 1. ε SiC is the dielectric constant of SiC, ψ bi is the built-in potential of the depletion region 16, q is the elementary charge, N A is the acceptor density of the body layer 13, and N D is the donor density of the depletion region 16.

[0056] [Equation 1] When N D << N A , Equation 1 can be transformed into Equation 2.

[0057] [Equation 2] According to equation 2, the donor density N D As shown in equation 3.

[0058] [Number 3] Therefore, the width W required to exhaust the entire exhaustion region 16 depl,n Let W be the name of the project. depl,n1 At that time, the donor density N D The range is shown in equation 4.

[0059] [Number 4] The operation of semiconductor device 1 will be explained. In semiconductor device 1, if a gate voltage of a threshold voltage or higher is applied to the gate electrode 20, an inversion layer is formed in the body layer 13 near the trench 17, and the drain-source current flows according to the voltage between the drain electrode 28 and the source electrode 26. Furthermore, when the gate voltage is less than the threshold voltage, an inversion layer is not formed, and no drain-source current flows.

[0060] During the recovery operation when semiconductor device 1 is turned off, displacement current flows to body layer 13 via the PN junction capacitance between drift layer 11 and body layer 13. The displacement current flows between body layer 13 and p... + The voltage is transferred from the type region 15b to the source electrode 26. At this time, due to the path resistance of the body layer 13, the potential of the body layer 13 rises, and a potential difference is generated between the first gate wiring 21 and the body layer 13.

[0061] Specifically, if the potential difference generated between the first gate wiring 21 and the body layer 13 is denoted as ΔV, the current flowing in the body layer 13 is denoted as I, and the path resistance of the body layer 13 is denoted as Rs, then ΔV = I·Rs. If the displacement current is denoted as Id and the recovery current is denoted as Irr, then I = Id + Irr. When Irr = 0, I = Id. If the PN junction capacitance between the drift layer 11 and the body layer 13 is denoted as C, and the time derivative of the voltage between the drain electrode 28 and the source electrode 26 is denoted as dV / dt, then Id = C·(dV / dt).

[0062] If the potential difference ΔV increases, a high electric field is applied to the field insulating film 18 and the gate insulating film 19, which can easily lead to breakdown. To suppress this situation, for example, Figure 5 As shown, considering the lower part of the first gate wiring 21, n is formed on the surface of the body layer 13. + Type 30, in n + p is formed on the surface of type 30 + Type 31. p + Type 31 through n+ The type region 30 is separated from the body layer 13. This configuration suppresses displacement current to p. + The intrusion of the type region 31 can suppress the application of a high electric field to the field insulating film 18 and the gate insulating film 19.

[0063] However, in n + Type 30 and p + In the lower part of the type region 31, the body layer 13 is thinner than other parts. In the current path indicated by arrow A1, the resistance R1 of the body layer 13 in the lower part of the gate wiring 21 is greater than the resistance R2 of the body layer 13 in other parts. Therefore, as Figure 5 As shown, if n is formed entirely in the region below the first gate wiring 21 in the surface layer of body layer 13... + Type 30 and p + In type 31, the part with large path resistance becomes larger, thus posing a risk of component breakdown due to heat generation.

[0064] In this embodiment, a depletion region 16 is formed at the lower part of the end of the first gate wiring 21. The depletion region 16 is depleted when the applied voltage between the drain electrode 28 and the source electrode 26 is 0V, so it is not easily affected by the potential rise of the body layer 13. Near the depletion region 16, the electric field applied to the field insulating film 18 and the gate insulating film 19 is reduced.

[0065] Near the end of the first gate wiring 21, the field insulating film 18 and the gate insulating film 19 are more susceptible to being subjected to a high electric field compared to the area closer to the inside of the end of the first gate wiring 21, making them prone to breakdown. Therefore, by forming a depletion region 16 at the lower part of the end of the first gate wiring 21, the breakdown of the field insulating film 18 and the gate insulating film 19 can be effectively suppressed.

[0066] Furthermore, in the lower portion of the first gate wiring 21 that is more inward than the end, no depletion region 16 is formed, and the upper surface of the body layer 13 is exposed from the depletion region 16 and in contact with the field insulating film 18. That is, the body layer 13 in the portion more inward than the end of region Re1 has the same thickness as the body layer 13 in the portion that is farther away from region Re1 and depletion region 16 in the x direction.

[0067] Figure 6The resistance R3 of the body layer 13 at the lower part of the depletion region 16 shown is greater than the resistance R4 of the body layer 13 in the region located outside the first gate wiring 21 in the x-direction. However, in this embodiment, the depletion region 16 is formed at the lower part of the end of the first gate wiring 21, and a portion in which the depletion region 16 is not formed is provided at the lower part of at least a portion of the portion inside the end of the first gate wiring 21. As a result, in this portion, the resistance R5 of the body layer 13 decreases to the same extent as the resistance R4. Therefore, it is possible to suppress the increase in path resistance and suppress component breakdown caused by temperature rise.

[0068] As explained above, in this embodiment, a depletion region 16 is formed at the lower part of the first gate wiring 21, which depletes when a voltage of 0V is applied between the drain electrode 28 and the source electrode 26. Furthermore, the depletion region 16 is formed at the lower part of at least a portion of the ends of the first gate wiring 21, and at the lower part of at least a portion of the portion of the first gate wiring 21 that is closer to the inside of the ends, the upper surface of the body layer 13 is exposed from the depletion region 16. This suppresses breakdown of the field insulating film 18 and the gate insulating film 19 caused by the application of an electric field, and suppresses device breakdown caused by temperature rise, thereby improving the recovery breakdown tolerance of the semiconductor device 1.

[0069] In addition, Figure 5 In the configuration shown, p + The side and bottom surfaces of type 31 need to be n + The 30-type region is covered, thus the size restrictions in the x, y, and z directions become strict, potentially reducing the degree of freedom in layout. In this embodiment, the depletion region 16 is n... - Type region, therefore, with the use of n + Type 30 and p + Compared to the layered structure of type 31, there are fewer size restrictions and greater freedom in layout.

[0070] (Second Implementation) The second embodiment will be described. This embodiment differs from the first embodiment in that the configuration of the depletion region 16 is changed; otherwise, it is the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0071] like Figure 7 As shown, in this embodiment, the depletion region 16 is not formed at the lower part of the second end 21b, but only at the lower part of the first end 21a. In the body layer 13, the distance from p connected to the source electrode 26... + The potential tends to rise in regions far from p, therefore, the potential in regions far from p is more likely to rise. +The field insulating film 18 and the gate insulating film 19 are particularly susceptible to being subjected to high electric fields at the lower part of the first end 21a, which is far from the type region 15b. In this regard, by forming the depletion region 16 only at the lower part of the first end 21a, the breakdown of the field insulating film 18 and the gate insulating film 19 can be effectively suppressed, and the path resistance at the lower part of the second end 21b is reduced to further suppress the device breakdown caused by temperature rise.

[0072] This embodiment can achieve the same effects as the first embodiment from the same configuration and operation.

[0073] Furthermore, the following effects can be obtained according to the above embodiments.

[0074] (1) The depletion region 16 is formed only in the lower part of the first end 21a and the second end 21b. As a result, the breakdown of the field insulating film 18 and the gate insulating film 19 can be suppressed, and the path resistance of the lower part of the second end 21b is reduced, thereby further suppressing the device breakdown caused by temperature rise.

[0075] (Third Implementation) The third embodiment will be described. This embodiment differs from the first embodiment in that the configuration of the depletion region 16 is changed; otherwise, it is the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0076] like Figure 8 As shown, in this embodiment, the depletion region 16 is not formed at the lower part of the first end 21a, but only at the lower part of the second end 21b. The displacement current is concentrated according to the layout of the various parts of the semiconductor device 1, thereby increasing the current at the p-th electrode connected to the source electrode 26. + In the lower part of the second end 21b near the type region 15b, the field insulating film 18 and the gate insulating film 19 are easily broken down. In this case, by forming the depletion region 16 only in the lower part of the second end 21b, the breakdown of the field insulating film 18 and the gate insulating film 19 can be suppressed, and the path resistance in the lower part of the first end 21a is reduced to further suppress the device breakdown caused by temperature rise.

[0077] This embodiment can achieve the same effects as the first embodiment from the same configuration and operation.

[0078] Furthermore, the following effects can be obtained according to the above embodiments.

[0079] (1) The depletion region 16 is formed only at the lower part of the second end 21b in the first end 21a and the second end 21b. As a result, the breakdown of the field insulating film 18 and the gate insulating film 19 can be suppressed, and the path resistance at the lower part of the first end 21a is reduced, thereby further suppressing the device breakdown caused by temperature rise.

[0080] (Fourth Implementation) The fourth embodiment will be described. This embodiment differs from the first embodiment in that the shape of the depletion region 16 is changed; otherwise, it is the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.

[0081] In this embodiment, the depletion region 16 formed along the first end 21a and the second end 21b is divided into multiple segments. Specifically, as shown below... Figure 9 As shown, the portion formed at the corner of region Re1 in the depletion region 16 is separated from the straight portion extending in the z direction along the end of region Re1.

[0082] In the current path indicated by arrow A2, the body layer 13 is thicker than the path through the lower part of the depletion region 16, and the path resistance of the body layer 13 is smaller, thus further suppressing component breakdown caused by temperature rise.

[0083] In addition, Figure 9 In this context, the depletion region 16 is divided between the corner portion formed in region Re1 and the straight portion, but the straight portion can be further divided into multiple parts. For example, as... Figure 10 As shown, the straight section of the depletion region 16 can also be divided into two at its central part. Figure 10 Similarly, in the configuration shown, in the current path indicated by arrow A3, the path resistance of body layer 13 is smaller than that of the path through the lower part of depletion region 16, thus further suppressing component breakdown caused by temperature rise.

[0084] Furthermore, the lower part of the corner of the first gate wiring 21 is more prone to breakdown of the field insulating film 18 and the gate insulating film 19 due to the potential rise of the body layer 13 compared to other parts. Therefore, the depletion region 16 can be formed only at the corner of region Re1, and the upper surface of the body layer 13 is exposed from the depletion region 16 and in contact with the field insulating film 18 at the straight portion at the end of region Re1. This further suppresses device breakdown caused by temperature rise.

[0085] In the device design of semiconductor device 1, the position and width of the gap in depletion region 16 can be adjusted by taking into account the magnitude of the electric field applied to field insulating film 18 and gate insulating film 19 and the temperature rise of bulk layer 13.

[0086] This embodiment can achieve the same effects as the first embodiment from the same configuration and operation.

[0087] Furthermore, the following effects can be obtained according to the above embodiments.

[0088] (1) The depletion region 16 is formed along the end of the first gate wiring 21 and is divided into a plurality of regions. This further suppresses component breakdown caused by temperature rise.

[0089] (Other implementation methods) Furthermore, this disclosure is not limited to the embodiments described above, and appropriate modifications are possible. Additionally, the embodiments described above are not unrelated to each other and can be appropriately combined, except in cases where they are clearly incompatible. Furthermore, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential, except where they are specifically stated to be necessary or where they are clearly considered necessary in principle. Furthermore, in each of the above embodiments, when referring to the number, value, quantity, range, etc., of the constituent elements of the embodiment, the number is not limited to that specific number, except where it is specifically stated to be necessary or where it is clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when referring to the shape, positional relationship, etc., of the constituent elements, the shape, positional relationship, etc., is not limited to that shape, positional relationship, etc., except where it is specifically stated or where it is limited to a specific shape, positional relationship in principle.

[0090] For example, such as Figure 11 As shown, the fourth embodiment can also be combined with the second embodiment. Figure 11 In the configuration shown, the path resistance of body layer 13 is lower in the current path indicated by arrow A4, which further suppresses temperature rise compared to the second embodiment. Additionally, as... Figure 12 As shown, the fourth embodiment can also be combined with the third embodiment. Figure 12 In the configuration shown, the path resistance of the body layer 13 is lower in the current path indicated by arrow A5, which can further suppress the temperature rise compared to the third embodiment.

[0091] Alternatively, a depletion region 16 may be formed in the lower portion of a portion of the first gate wiring 21 that is inward from the end of the first gate wiring 21. Alternatively, the depletion region 16 may be formed entirely in the lower portion of the end of the first gate wiring 21. For example, in addition to the lower portions of the first end 21a and the second end 21b, the depletion region 16 may be formed in a rectangular frame shape along the lower portions of both ends of the first gate wiring 21 in the z-direction. Alternatively, the depletion region 16 may be entirely undepleted. For example, an undepleted region may exist in the center of the depletion region 16.

[0092] Furthermore, while the above embodiments have described the case where the semiconductor device 1 has a MOSFET element, the semiconductor device 1 may also have a JFET (Junction Field Effect Transistor) element or an IGBT (Insulated Gate Bipolar Transistor) element. Additionally, an SJ structure may not be formed in the drift layer 11.

[0093] Furthermore, in the above embodiments, n-type is designated as the first conductivity type and p-type as the second conductivity type. However, this disclosure can also be applied to p-channel elements where p-type is designated as the first conductivity type and n-type as the second conductivity type.

Claims

1. A semiconductor device, characterized in that, have: The drift layer of the first conductivity type; A second conductive body layer is stacked on the upper surface of the drift layer; The lower surface electrode is formed on the lower surface side of the drift layer; Gate wiring is formed on the upper surface side of the body layer and connected to the gate electrode; A gate insulating film is formed between the upper surface of the body layer and the gate wiring; as well as The upper surface electrode is formed on the upper surface side of the body layer. In the portion of the surface layer located below the gate wiring on the upper surface side of the body layer, a depletion region of the first conductivity type is formed, which is depleted when a voltage of 0V is applied between the lower surface electrode and the upper surface electrode. The depletion region is formed at the lower part of at least a portion of the end of the gate wiring. At least a portion of the lower part of the portion of the gate wiring that is inside the end, the upper surface of the body layer is exposed from the depletion region.

2. The semiconductor device according to claim 1, characterized in that, In a direction parallel to the upper surface of the body layer, Let the width of the portion of the depletion region that protrudes from the end of the gate wiring toward the outside of the gate wiring be X1. Set to 0 <X1<5μm。 3. The semiconductor device according to claim 1, characterized in that, In a direction parallel to the upper surface of the body layer, The width of the portion of the depletion region that overlaps with the gate wiring is set to X2. Set the width of the gate wiring to X3. Set to 0 <X2<X3。 4. The semiconductor device according to claim 1, characterized in that, Set the thickness of the depletion region to Y1. The thickness of the body layer is set to Y2. Set to 0 <Y1<Y2。 5. The semiconductor device according to any one of claims 1 to 4, characterized in that, Let the acceptor density of the body layer be N. A , Set the donor density of the depletion region to N. D , Let the dielectric constant of SiC be ε SiC , Let the built-in potential of the depletion region be ψ. bi , Let the elementary charge be q. Let W be the width of the depleted region in the direction from the body layer toward the center of the depleted region. depl,n , The width W required to deplete the entire depletion region depl,n Let W be the name of the project. depl,n1 , Satisfying the following equation 4 [Number 4] 。 6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The upper surface electrode is in contact with the contact portion formed on the surface portion of the body layer inside the trench through which the gate insulating film passes. In a direction parallel to the upper surface of the body layer, The end of the gate wiring located on the opposite side of the contact portion relative to the center of the gate wiring is designated as the first end, and the end located on the same side as the contact portion relative to the center of the gate wiring is designated as the second end. The depletion zone is formed only at the lower part of the first end, which is the first end and the second end.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, The upper surface electrode is in contact with the contact portion formed on the surface portion of the body layer inside the trench through which the gate insulating film passes. In a direction parallel to the upper surface of the body layer, The end of the gate wiring located on the opposite side of the contact portion relative to the center of the gate wiring is designated as the first end, and the end located on the same side as the contact portion relative to the center of the gate wiring is designated as the second end. The depletion zone is formed only at the lower part of the second end, which is the first end and the second end.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, The depletion region is formed along the end of the gate wiring and is divided into multiple parts.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first conductivity type is n-type. The second conductivity type is p-type.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first conductivity type is p-type. The second conductivity type is n-type.

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