Semiconductor device

Abstract

There is provided a semiconductor device including: a lower sheet structure including a plurality of first lower semiconductor layers and a plurality of second lower semiconductor layers alternately stacked; an upper sheet structure including a plurality of first upper semiconductor layers and a plurality of second upper semiconductor layers alternately stacked on the lower sheet structure; a lower semiconductor pattern on at least one side of the lower sheet structure; an upper semiconductor pattern on at least one side of the upper sheet structure; and the PN junction structure is arranged between the lower sheet-shaped structure and the upper sheet-shaped structure, and the PN junction structure comprises a P-type semiconductor material and an N-type semiconductor material. The PN junction structure includes: a first doped layer on the lower sheet structure and having a first type of conductivity; and a second doped layer on the first doped layer and having a second type of conductivity.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0158513, filed with the Korean Intellectual Property Office on November 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure relate to a semiconductor device. Background Technology

[0003] A semiconductor is a material that falls between a conductor and an insulator, and is defined as a material that conducts electricity under desired (and / or alternatively predetermined) conditions. Such semiconductor materials can be used to manufacture a variety of semiconductor devices, such as memory devices. Semiconductor devices can be used in a wide range of electronic devices.

[0004] As the electronics industry continues to develop, the demand for advanced features in semiconductor devices is constantly increasing. For example, there is a growing need for semiconductor devices that achieve higher reliability, higher speed, and / or multifunctionality. Consequently, the structures within semiconductor devices continue to become increasingly complex and integrated. Summary of the Invention

[0005] Some exemplary embodiments of this disclosure provide a transistor structure and a stacked structure disposed on a substrate insulating layer and / or a semiconductor substrate. Therefore, a stacked structure including diode elements, etc., can be formed together with the transistor structure without significantly increasing the number of manufacturing processes.

[0006] According to some example embodiments, a semiconductor device includes: a lower wafer structure including a plurality of alternately stacked first lower semiconductor layers and a plurality of second lower semiconductor layers; an upper wafer structure including a plurality of alternately stacked first upper semiconductor layers and a plurality of second upper semiconductor layers on the lower wafer structure; a lower semiconductor pattern on at least one side of the lower wafer structure; an upper semiconductor pattern on at least one side of the upper wafer structure; and a PN junction structure between the lower wafer structure and the upper wafer structure, the PN junction structure including a P-type semiconductor material and an N-type semiconductor material. The PN junction structure includes: a first doped layer on the lower wafer structure and having a first type of conductivity; and a second doped layer on the first doped layer and having a second type of conductivity.

[0007] According to some example embodiments, a semiconductor device includes: a lower wafer structure having a first type of conductivity and including a plurality of alternately stacked first lower semiconductor layers and a plurality of second lower semiconductor layers; an upper wafer structure having a second type of conductivity and including a plurality of alternately stacked first upper semiconductor layers and a plurality of second upper semiconductor layers on the lower wafer structure; a lower semiconductor pattern on at least one side of the lower wafer structure; and a PN junction structure between the plurality of first lower semiconductor layers and the plurality of first upper semiconductor layers, the PN junction structure including a P-type semiconductor material and an N-type semiconductor material and at least one of the plurality of second lower semiconductor layers and the plurality of second upper semiconductor layers. The PN junction structure includes: a first doped layer on the lower wafer structure and having a first type of conductivity; and a second doped layer between the first doped layer and the upper wafer structure and having a second type of conductivity.

[0008] According to some example embodiments, a semiconductor device includes: a substrate insulating layer; a lower wafer structure including a plurality of first lower semiconductor layers and a plurality of second lower semiconductor layers alternately stacked on the substrate insulating layer; an upper wafer structure including a plurality of first upper semiconductor layers and a plurality of second upper semiconductor layers alternately stacked on the lower wafer structure; a lower semiconductor pattern on at least one side of the lower wafer structure and having a first type of conductivity; an upper semiconductor pattern on at least one side of the upper wafer structure and having a second type of conductivity; a barrier structure between the lower semiconductor pattern and the upper semiconductor pattern; and a PN junction structure between the lower wafer structure and the upper wafer structure, and overlapping the barrier structure in a first direction parallel to the upper surface of the substrate insulating layer, the PN junction structure including a P-type semiconductor material and an N-type semiconductor material. The PN junction structure includes: a first doped layer on the lower wafer structure and having a first type of conductivity; and a second doped layer on the first doped layer and having a second type of conductivity, wherein the doping concentration of the first type of conductive impurity in the first doped layer is less than or equal to the doping concentration of the first type of conductive impurity in the lower semiconductor pattern.

[0009] According to some example embodiments, a method of manufacturing a semiconductor device includes: forming an active pattern on a substrate; forming a first stack on the active pattern in a first region of the substrate, the first stack including a preliminary lower wafer structure, a first preliminary intermediate insulating structure, a preliminary upper wafer structure, and a first sacrificial gate structure; forming a second stack on the active pattern in a second region of the substrate, the second stack including a lower sacrificial layer, an upper sacrificial layer, a plurality of lower channel patterns, a second preliminary intermediate insulating structure, a plurality of upper channel patterns, and a second sacrificial gate structure; forming a first sacrificial gate structure on the first stack and forming a second sacrificial gate structure on the second stack; etching the first stack using the first sacrificial gate structure as an etch mask to form a first trench; etching the second stack using the second sacrificial gate structure as an etch mask to form a second trench; forming a lower semiconductor pattern and a first barrier structure in the first trench; forming a lower source / drain pattern and a second barrier structure in the second trench; forming an upper semiconductor pattern on the first barrier structure and forming a lower source / drain pattern and a second barrier structure on the second barrier structure. Forming an upper source / drain pattern; using a thermal processing process to form a first lower wafer structure, a first upper wafer structure, a first doped layer, and a second doped layer; forming an interlayer insulating layer on the upper semiconductor pattern and the upper source / drain pattern; forming an upper gate trench in a first region and a second region by removing at least a portion of the first sacrificial gate structure and the second sacrificial gate structure; removing a second preliminary intermediate insulating layer in the second region to form a gap, and forming an intermediate insulating structure in the gap; removing the upper sacrificial layer and the lower sacrificial layer to form a lower gate trench; forming an upper gate structure and a lower gate structure in the lower gate trench; forming a dummy main gate structure in the upper gate trench in the first region, and forming a main gate structure in the upper gate trench in the second region; forming an upper contact structure through the interlayer insulating layer to contact the upper semiconductor pattern in the first region and the upper source / drain pattern in the second region; removing the substrate and the active pattern, and forming a substrate insulating layer and a protruding pattern to replace the substrate and the active pattern, respectively; and forming a lower contact structure through the substrate insulating layer and the protruding pattern.

[0010] According to some example embodiments, the method of manufacturing a semiconductor device further includes: during the formation of a first lower wafer structure, a first upper wafer structure, a first doped layer, and a second doped layer, a thermal processing process diffuses impurities from the lower semiconductor pattern and the upper semiconductor pattern into the preliminary lower wafer structure and the preliminary upper wafer structure to form the first lower wafer structure and the first upper wafer structure; and the thermal processing process further forms the first doped layer by diffusing impurities into a first portion of the first preliminary intermediate insulating structure, and forms the second doped layer by diffusing impurities into a second portion of the first preliminary intermediate insulating structure.

[0011] As described above, semiconductor devices according to some example embodiments may include stacked structures and transistor structures, the stacked structures being formed to include diode elements, etc., without significantly increasing the number of manufacturing processes. Attached Figure Description

[0012] Figure 1 This is a plan view of a semiconductor device according to some example embodiments.

[0013] Figure 2 It is along Figure 1 The cross-sectional view taken from lines A-A' and B-B'.

[0014] Figure 3 It is along Figure 1 The cross-sectional view taken from line C-C'.

[0015] Figure 4 It is along Figure 1 The cross-sectional view taken by line D-D'.

[0016] Figure 5 It shows Figure 2 The enlarged cross-sectional view of region S1 shown.

[0017] Figures 6 to 10 Is with Figure 2 The cross-sectional view corresponding to region S1 in the diagram shows a semiconductor device according to some example embodiments.

[0018] Figures 11 to 13 Is along Figure 1 The cross-sectional view corresponding to the region intercepted by line A-A' in the diagram, and the cross-sectional view illustrates a semiconductor device according to some example embodiments.

[0019] Figures 14 to 21 This is a cross-sectional view showing an intermediate stage of a method for manufacturing a semiconductor device according to some example embodiments.

[0020] Figures 22 to 24 This is a cross-sectional view showing an intermediate stage of a method for manufacturing a semiconductor device according to some example embodiments. Detailed Implementation

[0021] In the following description, various exemplary embodiments of the present disclosure are illustrated with reference to the accompanying drawings, enabling those skilled in the art to readily practice the present disclosure. The present disclosure can be modified in various different ways and is not limited to the exemplary embodiments provided in this specification.

[0022] For the sake of clarity in describing this disclosure, parts irrelevant to the description have been omitted, and throughout this specification, the same or similar components are indicated by the same reference numerals.

[0023] Furthermore, for ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated; therefore, this disclosure is not necessarily limited to the contents shown in the drawings. The thicknesses of several layers and regions have been enlarged in the drawings for clarity. Additionally, the thicknesses of some layers and regions have been enlarged in the accompanying drawings for ease of description.

[0024] Furthermore, when an element such as a layer, film, region, or plate is referred to as being "on" or "above" another element, the element may be "directly on" the other element, or it may have a third element in between. On the other hand, when an element is referred to as being "directly on" another element, there is no third element in between. Additionally, when an element is mentioned as being "on" or "above" a reference element, the element may be positioned on or below the reference element, and may not necessarily be "on" or "above" the reference element in the opposite direction of gravity.

[0025] Additionally, when any part "includes" any component, it can mean that other components are included, rather than excluded, unless there is an explicit description to the contrary.

[0026] Furthermore, throughout this specification, the phrase "on a plane" indicates the view of the target from above, and the phrase "on a cross section" indicates the view of a vertically oriented section of the target from the side of the target.

[0027] In the accompanying drawings of semiconductor devices according to some exemplary embodiments, the semiconductor devices may, for example, include all-gate (GAA), three-dimensional (3D) stacked field-effect transistor (3DSFET) structures, etc., in which the four sides of the channel are surrounded by gate electrodes. However, the exemplary embodiments are not limited thereto, and the transistors may include fin field-effect transistor (FinFET) structures, multi-bridge channel field-effect transistors (MBCFETs), etc. TM Structures such as complementary field-effect transistors (CFETs) and complementary field-effect transistors (CFETs) are also mentioned.

[0028] In the following text, see references Figures 1 to 5 To describe a semiconductor device according to some example embodiments.

[0029] Figure 1 This is a plan view of a semiconductor device according to some example embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from lines A-A' and B-B'. Figure 3 It is along Figure 1 The cross-sectional view taken from line C-C'. Figure 4 It is along Figure 1 The cross-sectional view taken by line D-D'. Figure 5 It shows Figure 2The enlarged cross-sectional view of region S1 shown.

[0030] refer to Figures 1 to 5 According to some example embodiments, a semiconductor device may include a substrate insulating layer 100, a stacked structure SS disposed on the substrate insulating layer 100, and a transistor structure TS.

[0031] The substrate insulating layer 100 may be an insulating substrate. The substrate insulating layer 100 may include oxides, nitrides, oxynitrides, or combinations thereof. However, the exemplary embodiments are not limited thereto. For example, the substrate insulating layer 100 may include silicon oxide (SiO2). The substrate insulating layer 100 is shown as a monolayer film only for ease of description, and the exemplary embodiments are not limited thereto. The substrate 101 described below (…) can be removed… Figure 14 (middle) and fill the removed portion of substrate 101 with insulating material ( Figure 14 (in the middle) to form the base insulating layer 100.

[0032] The substrate insulating layer 100 may include an upper surface and a lower surface. The upper and lower surfaces of the substrate insulating layer 100 may be formed as planes parallel to a first direction (X direction) and a second direction (Y direction), the second direction intersecting the first direction (X direction). The upper surface of the substrate insulating layer 100 may be a surface opposite to the lower surface of the substrate insulating layer 100 in a third direction (Z direction). The upper surface of the substrate insulating layer 100 may be referred to as the front side. The lower surface of the substrate insulating layer 100 may be referred to as the rear side.

[0033] The stacked structure SS and the transistor structure TS can be disposed on the substrate insulating layer 100. In some example embodiments, the stacked structure SS and the transistor structure TS are shown spaced apart from each other in a first direction (X direction), but the example embodiments are not limited thereto. For example, the stacked structure SS and the transistor structure TS can be spaced apart from each other in a second direction (Y direction). Here, the second direction (Y direction) can be a direction intersecting the first direction (X direction). In some example embodiments, the second direction (Y direction) can be a direction intersecting the first direction (X direction).

[0034] The stacked structure SS is described below.

[0035] The stacked structure SS of a semiconductor device according to some example embodiments may include a lower wafer structure 140A disposed above a substrate insulating layer 100, an upper wafer structure 140B disposed above the lower wafer structure 140A, a lower semiconductor pattern 150A disposed on at least one side of the lower wafer structure 140A, an upper semiconductor pattern 150B disposed on at least one side of the upper wafer structure 140B, and a PN junction structure 300 disposed between the lower wafer structure 140A and the upper wafer structure 140B and including P-type semiconductor material and N-type semiconductor material.

[0036] The stacked structure SS of the semiconductor device according to some example embodiments may also include a protruding pattern 110 disposed on the substrate insulating layer 100.

[0037] A protruding pattern 110 may be disposed on the substrate insulating layer 100. The protruding pattern 110 may extend in a first direction (X direction). The protruding pattern 110 may protrude from the substrate insulating layer 100 in a third direction (Z direction). The protruding pattern 110 may include various insulating materials. The protruding pattern 110 may include the same material as the substrate insulating layer 100.

[0038] The lower sheet structure 140A may be disposed above the substrate insulating layer 100. The lower sheet structure 140A may be disposed on the upper surface of the protruding pattern 110. The lower sheet structure 140A may have a first type of conductivity. The first type of conductivity may be P-type conductivity. For example, the lower sheet structure 140A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the exemplary embodiments are not limited thereto.

[0039] According to some example embodiments, the lower wafer structure 140A may include a plurality of alternately stacked first lower semiconductor layers 145A and a plurality of second lower semiconductor layers 142A. In some example embodiments, the plurality of first lower semiconductor layers 145A may have a structure, shape, and arrangement similar to that of the plurality of lower channel patterns 240A of the transistor structure TS described below, and the plurality of second lower semiconductor layers 142A may have a structure, shape, and arrangement similar to that of the lower sacrificial layer 220A of the transistor structure TS described below. Figure 14 The structure, shape, and arrangement relationships are similar to those of the structures in the middle.

[0040] Multiple first lower semiconductor layers 145A may be disposed above the protruding pattern 110. The multiple first lower semiconductor layers 145A may be spaced apart from the protruding pattern 110 in a third direction (Z direction). The multiple first lower semiconductor layers 145A may be spaced apart from each other in the third direction (Z direction). Here, the third direction (Z direction) may be a direction intersecting the first direction (X direction) and the second direction (Y direction). For example, the third direction (Z direction) may be the thickness direction of the substrate insulating layer 100. In some example embodiments, the multiple first lower semiconductor layers 145A may have substantially the same width in the first direction (X direction), but the example embodiments are not limited to this. As another example, the width of the multiple first lower semiconductor layers 145A in the first direction (X direction) may decrease as the multiple first lower semiconductor layers 145A are further away from the upper surface of the substrate insulating layer 100.

[0041] The plurality of first lower semiconductor layers 145A may include semiconductor materials. For example, the plurality of first lower semiconductor layers 145A may include elemental semiconductor materials, such as silicon (Si) or germanium (Ge). The plurality of first lower semiconductor layers 145A may be formed by etching a portion of the substrate 101. Figure 14 (middle), or may include an epitaxial layer grown from substrate 101 (middle), Figure 14 middle).

[0042] The plurality of first lower semiconductor layers 145A may include compound semiconductors, such as group IV-IV compound semiconductors or group III-V compound semiconductors. Here, group IV-IV compound semiconductors may, for example, be binary or ternary compounds comprising at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). Group III-V compound semiconductors may, for example, be binary, ternary, or quaternary compounds formed by coupling at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements. However, the exemplary embodiments are not limited thereto.

[0043] In some example embodiments, the plurality of first lower semiconductor layers 145A may include silicon (Si). As another example, the plurality of first lower semiconductor layers 145A may include silicon germanium (SiGe).

[0044] The plurality of first lower semiconductor layers 145A may have a first type of conductivity. The plurality of first lower semiconductor layers 145A may be doped with impurities of the first type of conductivity. Here, the first type of conductivity may be P-type conductivity, but the example embodiment is not limited thereto. For example, the plurality of first lower semiconductor layers 145A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiment is not limited thereto.

[0045] Multiple second lower semiconductor layers 142A may be disposed on the protruding pattern 110. The multiple second lower semiconductor layers 142A may be stacked while being spaced apart from each other in a third direction (Z direction). Multiple first lower semiconductor layers 145A may be disposed between the multiple second lower semiconductor layers 142A, while being stacked while being spaced apart from each other in a third direction (Z direction). That is, the multiple first lower semiconductor layers 145A and the multiple second lower semiconductor layers 142A may be stacked alternately in a third direction (Z direction). The bottommost second lower semiconductor layer 142A may contact the protruding pattern 110, but the example embodiment is not limited thereto. In some example embodiments, the multiple second lower semiconductor layers 142A may have substantially the same width in a first direction (X direction), but the example embodiment is not limited thereto.

[0046] The plurality of second lower semiconductor layers 142A may include semiconductor materials. The plurality of second lower semiconductor layers 142A may include semiconductor materials different from those of the plurality of first lower semiconductor layers 145A. For example, the plurality of second lower semiconductor layers 142A may include silicon germanium (SiGe), and the plurality of first lower semiconductor layers 145A may include silicon (Si). However, the example embodiment is not limited thereto, and as another example, the plurality of first lower semiconductor layers 145A and the plurality of second lower semiconductor layers 142A may include silicon germanium (SiGe). Here, the germanium (Ge) content (at%) in the plurality of first lower semiconductor layers 145A may differ from the germanium (Ge) content (at%) in the plurality of second lower semiconductor layers 142A. As an example, the germanium (Ge) content (at%) in the plurality of first lower semiconductor layers 145A may be less than the germanium (Ge) content (at%) in the plurality of second lower semiconductor layers 142A.

[0047] The plurality of second lower semiconductor layers 142A may have a first type of conductivity. The plurality of second lower semiconductor layers 142A may be doped with impurities of the first type of conductivity. Here, the first type of conductivity may be P-type conductivity, but the example embodiment is not limited thereto. For example, the plurality of second lower semiconductor layers 142A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiment is not limited thereto.

[0048] In some example embodiments, the plurality of second lower semiconductor layers 142A may have the same conductivity as the plurality of first lower semiconductor layers 145A. Here, the doping concentration of the first type of conductive impurities in the plurality of second lower semiconductor layers 142A may be greater than or substantially equal to the doping concentration of the first type of conductive impurities in the plurality of first lower semiconductor layers 145A. This is because, in the process of diffusing impurities into the lower wafer structure 140A through heat treatment, the plurality of second lower semiconductor layers 142A comprises a material in which impurities are diffused relatively better compared to the plurality of first lower semiconductor layers 145A.

[0049] Figure 2 , Figure 3 and Figure 5 The illustration shows two second lower semiconductor layers 142A and two first lower semiconductor layers 145A stacked alternately, but the example embodiment is not limited thereto. The number of multiple first lower semiconductor layers 145A and multiple second lower semiconductor layers 142A can vary.

[0050] The upper sheet structure 140B may be disposed above the lower sheet structure 140A. The upper sheet structure 140B may be disposed on the PN junction structure 300 disposed on the lower sheet structure 140A, as described below. In some example embodiments, the upper sheet structure 140B may have a width substantially the same as that of the lower sheet structure 140A in the first direction (X direction), but the example embodiments are not limited thereto. The upper sheet structure 140B may completely overlap with the lower sheet structure 140A in the third direction (Z direction), but the example embodiments are not limited thereto. The upper sheet structure 140B may have a second type of conductivity. The second type of conductivity may be N-type conductivity. For example, the upper sheet structure 140B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiments are not limited thereto.

[0051] According to some example embodiments, the top-chip structure 140B may include a plurality of alternatingly stacked first top semiconductor layers 145B and a plurality of second top semiconductor layers 142B.

[0052] In some example embodiments, a plurality of first upper semiconductor layers 145B may have a structure, shape, and arrangement similar to the structure, shape, and arrangement of a plurality of upper channel patterns 240B of the transistor structure TS described below, and a plurality of second upper semiconductor layers 142B may have an upper sacrificial layer 220B similar to the structure, shape, and arrangement of a plurality of upper channel patterns 240B of the transistor structure TS described below. Figure 14 The structure, shape, and arrangement relationships are similar to those of the structures in the middle.

[0053] Multiple first upper semiconductor layers 145B can be disposed above multiple first lower semiconductor layers 145A. Specifically, the multiple first upper semiconductor layers 145B can be disposed on the upper surface of a PN junction structure 300 disposed on the multiple first lower semiconductor layers 145A. The multiple first upper semiconductor layers 145B can be spaced apart from the multiple first lower semiconductor layers 145A in the third direction (Z direction). For example, the PN junction structure 300 can be disposed between the multiple first upper semiconductor layers 145B and the multiple first lower semiconductor layers 145A, and due to the PN junction structure 300, the multiple first upper semiconductor layers 145B can be spaced apart from the multiple first lower semiconductor layers 145A in the third direction (Z direction). The multiple first lower semiconductor layers 145A can be spaced apart from each other in the third direction (Z direction).

[0054] In some example embodiments, the plurality of first upper semiconductor layers 145B may have substantially the same width in the first direction (X direction), but the example embodiments are not limited thereto. For example, the width of the plurality of first upper semiconductor layers 145B in the first direction (X direction) may decrease as the upper semiconductor layer 145B is further away from the upper surface of the substrate insulating layer 100.

[0055] The plurality of first upper semiconductor layers 145B may include semiconductor materials. The plurality of first upper semiconductor layers 145B may include the same materials as the plurality of first lower semiconductor layers 145A. For example, the plurality of first upper semiconductor layers 145B may include elemental semiconductor materials such as silicon (Si) or germanium (Ge). However, the example embodiment is not limited thereto. The plurality of first upper semiconductor layers 145B may be formed by etching a portion of the substrate 101. Figure 14 (middle), or may include an epitaxial layer grown from substrate 101 (middle), Figure 14 (In the middle). As an example, the plurality of first upper semiconductor layers 145B may include silicon (Si).

[0056] The plurality of first upper semiconductor layers 145B may have a second type of conductivity. That is, the plurality of first upper semiconductor layers 145B may be doped with impurities of a second type of conductivity. Here, the second type of conductivity may be N-type conductivity, but the example embodiment is not limited thereto. The plurality of first upper semiconductor layers 145B may have a conductivity of a different type than that of the plurality of first lower semiconductor layers 145A. For example, the plurality of first upper semiconductor layers 145B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiment is not limited thereto.

[0057] Multiple second upper semiconductor layers 142B may be disposed above the lower wafer structure 140A. The multiple second upper semiconductor layers 142B may be stacked while being spaced apart from each other in a third direction (Z direction). Multiple first upper semiconductor layers 145B may be disposed between the multiple second upper semiconductor layers 142B, which are stacked while being spaced apart from each other in a third direction (Z direction). That is, the multiple first upper semiconductor layers 145B and the multiple second upper semiconductor layers 142B may be stacked alternately in the third direction (Z direction). In some example embodiments, the multiple second upper semiconductor layers 142B may have substantially the same width in a first direction (X direction), but the example embodiments are not limited to this.

[0058] The plurality of second upper semiconductor layers 142B may include semiconductor materials. The plurality of second upper semiconductor layers 142B may include the same materials as the plurality of second lower semiconductor layers 142A. The plurality of second upper semiconductor layers 142B may include semiconductor materials different from the plurality of first upper semiconductor layers 145B. For example, the plurality of second upper semiconductor layers 142B may include silicon germanium (SiGe), and the plurality of first upper semiconductor layers 145B may include silicon (Si). However, the example embodiment is not limited thereto, and as another example, the plurality of first upper semiconductor layers 145B and the plurality of second upper semiconductor layers 142B may include silicon germanium (SiGe). Here, the germanium (Ge) content (at%) in the plurality of first upper semiconductor layers 145B may differ from the germanium (Ge) content (at%) in the plurality of second upper semiconductor layers 142B. As an example, the germanium (Ge) content (at%) in the plurality of first upper semiconductor layers 145B may be less than the germanium (Ge) content (at%) in the plurality of second upper semiconductor layers 142B.

[0059] The plurality of second upper semiconductor layers 142B may have a second type of conductivity. The plurality of second upper semiconductor layers 142B may be doped with impurities of a second type of conductivity. Here, the second type of conductivity may be N-type conductivity, but the example embodiment is not limited thereto. For example, the plurality of second upper semiconductor layers 142B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiment is not limited thereto.

[0060] In some example embodiments, the plurality of second upper semiconductor layers 142B may have the same conductivity as the plurality of first upper semiconductor layers 145B. Here, the doping concentration of the second type of conductive impurities in the plurality of second upper semiconductor layers 142B may be greater than or substantially equal to the doping concentration of the second type of conductive impurities in the plurality of first upper semiconductor layers 145B. This is because, in the process of diffusing impurities into the upper wafer structure 140B through heat treatment, the plurality of second upper semiconductor layers 142B comprises a material in which impurities are diffused relatively better compared to the plurality of first upper semiconductor layers 145B.

[0061] The stacked structure SS of the semiconductor device according to some example embodiments may also include a field insulating layer 105 disposed on the substrate insulating layer 100.

[0062] Field insulating layer 105 may be disposed on substrate insulating layer 100. Field insulating layer 105 may cover at least a portion of the side surface of protruding pattern 110. For example, as Figure 3 As shown, the field insulating layer 105 may cover a portion of the side surface of the protruding pattern 110. That is, a portion of the side surface of the protruding pattern 110 may be covered by the field insulating layer 105, while the remaining portion may be covered by the dummy main gate structure 160M, which will be described below. The field insulating layer 105 may overlap with the protruding pattern 110 in the second direction (Y direction). Alternatively, the field insulating layer 105 may not be provided on the upper surface of the protruding pattern 110.

[0063] Figure 3 The example shows the field insulating layer 105 covering at least a portion of the side surface of the protruding pattern 110, but the example embodiment is not limited thereto. For example, the field insulating layer 105 may completely cover the side surface of the protruding pattern 110.

[0064] The field insulating layer 105 may include, for example, an oxide, nitride, oxynitride, or combination thereof film. The field insulating layer 105 is shown as a single-layer film only for ease of description, and the example embodiment is not limited thereto.

[0065] The lower semiconductor pattern 150A may be disposed on at least one side of the lower chip structure 140A. For example, the lower semiconductor pattern 150A may be disposed on each side of the lower chip structure 140A along the first direction (X direction). The lower semiconductor pattern 150A may be disposed on the protruding pattern 110. The lower semiconductor pattern 150A may contact the side surface of the lower chip structure 140A and the upper surface of the protruding pattern 110. The lower semiconductor pattern 150A may be electrically connected to the lower chip structure 140A.

[0066] In some example embodiments, at least a portion of the lower semiconductor pattern 150A may be surrounded by the protruding pattern 110. The upper surface of the lower semiconductor pattern 150A may be disposed at a height substantially the same as the height of the upper surface of the lower wafer structure 140A. The length of the lower semiconductor pattern 150A in the third direction (Z direction) may be greater than or substantially equal to the length of the lower wafer structure 140A in the third direction (Z direction). The lower surface of the lower semiconductor pattern 150A may be closer to the upper surface of the substrate insulating layer 100 than the lower surface of the lower wafer structure 140A.

[0067] The lower semiconductor pattern 150A can be achieved by using multiple first lower semiconductor layers 145A and active pattern 111 ( Figure 14The lower semiconductor pattern 150A is an epitaxial pattern formed by a selective epitaxial growth process using a seed crystal (in the middle). In some example embodiments, the lower semiconductor pattern 150A may include a semiconductor material. The lower semiconductor pattern 150A may have a first type of conductivity. The lower semiconductor pattern 150A may be doped with a first type of conductivity impurity. Here, the first type of conductivity may be P-type conductivity, but the example embodiments are not limited to this. For example, the lower semiconductor pattern 150A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiments are not limited to this.

[0068] In some example embodiments, the lower semiconductor pattern 150A may have the same conductivity as the lower sheet structure 140A. Here, the doping concentration of the first type of conductive impurity in the lower semiconductor pattern 150A may be greater than or substantially equal to the doping concentration of the first type of conductive impurity in the lower sheet structure 140A.

[0069] The lower semiconductor pattern 150A of a semiconductor device according to some example embodiments may include a first sub-lower pattern 151A and a second sub-lower pattern 152A.

[0070] The first sub-lower pattern 151A may be disposed on the side surface of the lower wafer structure 140A and the upper surface of the protruding pattern 110. The first sub-lower pattern 151A may be in contact with the lower wafer structure 140A and the protruding pattern 110. The first sub-lower pattern 151A may include a semiconductor material. For example, the first sub-lower pattern 151A may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the exemplary embodiments are not limited thereto.

[0071] The second sub-pattern 152A can be disposed on the first sub-pattern 151A. The second sub-pattern 152A can be surrounded by the first sub-pattern 151A. The upper surface of the second sub-pattern 152A can be disposed at a height substantially the same as the upper surface of the first sub-pattern 151A. That is, the upper surface of the second sub-pattern 152A can be disposed at a distance substantially the same as the distance from the upper surface of the first sub-pattern 151A to the upper surface of the substrate insulating layer 100, but the exemplary embodiment is not limited to this.

[0072] The second sub-sub-pattern 152A may include a semiconductor material. For example, the second sub-sub-pattern 152A may include the same material as the first sub-sub-pattern 151A. As an example, the first sub-sub-pattern 151A and the second sub-sub-pattern 152A may include silicon (Si) or silicon germanium (SiGe) as semiconductor materials, but the example embodiment is not limited thereto.

[0073] In some example embodiments, the first sub-sub-pattern 151A and the second sub-sub-pattern 152A may have a first type of conductivity. The first sub-sub-pattern 151A and the second sub-sub-pattern 152A may be doped with impurities of the first type of conductivity. Here, the first type of conductivity may be P-type conductivity. For example, the first sub-sub-pattern 151A and the second sub-sub-pattern 152A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiments are not limited thereto. Here, the type of impurity included in the first sub-sub-pattern 151A may be the same as or different from the type of impurity included in the second sub-sub-pattern 152A. Furthermore, the doping concentration of the impurity in the first sub-sub-pattern 151A may be different from the doping concentration of the impurity in the second sub-sub-pattern 152A. For example, the doping concentration of the first type of conductive impurity in the second sub-sub-pattern 152A may be greater than the doping concentration of the first type of conductive impurity in the first sub-sub-pattern 151A, but the example embodiments are not limited thereto. However, the example embodiment is not limited thereto, and as another example, the first sub-pattern 151A and the second sub-pattern 152A may have a second type of conductivity.

[0074] In some example embodiments, the doping concentrations of impurities in the first sub-underpattern 151A and the second sub-underpattern 152A may each be greater than or substantially equal to the doping concentrations of impurities in the lower sheet structure 140A. For example, the doping concentration of impurities in the first sub-underpattern 151A may be greater than or substantially equal to the doping concentrations of impurities in the plurality of first lower semiconductor layers 145A and the plurality of second lower semiconductor layers 142A. Additionally, the doping concentration of impurities in the second sub-underpattern 152A may be greater than or substantially equal to the doping concentrations of impurities in the plurality of first lower semiconductor layers 145A and the plurality of second lower semiconductor layers 142A. This doping concentration may be caused by process characteristics where first-type conductive impurities present in the lower semiconductor pattern 150A diffuse into the lower sheet structure 140A through a thermal processing process.

[0075] In some example embodiments, the lower semiconductor pattern 150A is described as being formed by two layers, but the example embodiments are not limited thereto. The lower semiconductor pattern 150A may be formed by a single layer comprising semiconductor material, or it may be formed by three or more layers.

[0076] The upper semiconductor pattern 150B can be disposed above the lower semiconductor pattern 150A. The upper semiconductor pattern 150B can be spaced apart from the lower semiconductor pattern 150A in the third direction (Z direction). For example, a blocking structure 170 can be disposed between the upper semiconductor pattern 150B and the lower semiconductor pattern 150A, and due to the blocking structure 170, the upper semiconductor pattern 150B and the lower semiconductor pattern 150A can be spaced apart from each other in the third direction (Z direction).

[0077] The upper semiconductor pattern 150B may be disposed on at least one side of the upper chip structure 140B. For example, the upper semiconductor pattern 150B may be disposed on each of the two sides of the upper chip structure 140B along the first direction (X direction). The upper semiconductor pattern 150B may contact the side surface of the upper chip structure 140B and the upper surface 170_U of the barrier structure 170 described below. At least a portion of the side surface of the upper semiconductor pattern 150B may contact the PN junction structure 300 described below. The upper semiconductor pattern 150B may overlap with the PN junction structure 300 described below in the first direction (X direction). The upper semiconductor pattern 150B may not contact the upper surface of the protruding pattern 110. The upper semiconductor pattern 150B may be electrically connected to the upper chip structure 140B.

[0078] The upper semiconductor pattern 150B can be an epitaxial pattern formed by a selective epitaxial growth process using multiple first upper semiconductor layers 145B as seed crystals. Here, the upper semiconductor pattern 150B can be a pattern formed using only the side surfaces of the multiple first upper semiconductor layers 145B as seed crystals. That is, it is similar to the lower semiconductor pattern 150A (which uses active pattern 111...). Figure 14 Unlike the pattern formed by using the upper surface of the middle semiconductor layer 145A and the side surfaces of the multiple first lower semiconductor layers 145A as seed crystals, the upper semiconductor pattern 150B can be a pattern formed by using only the side surfaces of the multiple first upper semiconductor layers 145B as seed crystals.

[0079] In some example embodiments, the upper surface of the upper semiconductor pattern 150B may be disposed at substantially the same height as the upper surface of the upper sheet structure 140B. That is, the distance between the upper surface of the upper semiconductor pattern 150B and the upper surface of the substrate insulating layer 100 may be substantially the same as the distance between the upper surface of the upper sheet structure 140B and the upper surface of the substrate insulating layer 100, but the example embodiments are not limited to this.

[0080] In some example embodiments, the lower surface of the upper semiconductor pattern 150B may be disposed at a lower height than the lower surface of the upper wafer structure 140B. That is, the lower surface of the upper semiconductor pattern 150B may be closer to the upper surface of the lower wafer structure 140A than the lower surface of the upper wafer structure 140B. Therefore, the lower surface of the upper semiconductor pattern 150B may be disposed at a lower height than the upper surface of the PN junction structure 300. That is, the lower surface of the upper semiconductor pattern 150B may be closer to the upper surface of the lower wafer structure 140A than the upper surface of the PN junction structure 300. Therefore, at least a portion of the upper semiconductor pattern 150B may overlap with the PN junction structure 300 disposed between the upper wafer structure 140B and the lower wafer structure 140A in a first direction (X direction). At least a portion of the upper semiconductor pattern 150B may contact the PN junction structure 300.

[0081] In some example embodiments, the upper semiconductor pattern 150B may include a semiconductor material. The upper semiconductor pattern 150B may have a second type of conductivity. The upper semiconductor pattern 150B may be doped with a second type of conductive impurity. Here, the second type of conductivity may be N-type conductivity, but the example embodiments are not limited thereto. For example, the upper semiconductor pattern 150B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiments are not limited thereto.

[0082] In some example embodiments, the upper semiconductor pattern 150B may have the same conductivity as the upper sheet structure 140B. Here, the doping concentration of the second type of conductive impurity in the upper semiconductor pattern 150B may be greater than or substantially equal to the doping concentration of the second type of conductive impurity in the upper sheet structure 140B.

[0083] The upper semiconductor pattern 150B of a semiconductor device according to some example embodiments may include a first sub-upper pattern 151B and a second sub-upper pattern 152B.

[0084] The first sub-pattern 151B may be disposed on a side surface of the upper wafer structure 140B. The first sub-pattern 151B may contact a plurality of first upper semiconductor layers 145B. In some example embodiments, the first sub-pattern 151B may not be disposed on the upper surface of the barrier structure 170, as described below. This feature may be caused by the following process feature: the first sub-pattern 151B uses a plurality of first upper semiconductor layers 145B as its seed, instead of using the barrier structure 170 as its seed. In some example embodiments, the first sub-pattern 151B may contact the upper wafer structure 140B. For example, the first sub-pattern 151B may overlap with a plurality of first upper semiconductor layers 145B and a plurality of second upper semiconductor layers 142B in a first direction (X direction).

[0085] In some example embodiments, the first sub-pattern 151B may protrude from the side surface of the upper sheet structure 140B. For example, the side surface of the first sub-pattern 151B may include a curved surface protruding from the side surface of the upper sheet structure 140B. Therefore, the width of the first sub-pattern 151B in the first direction (X direction) may increase and then decrease as the first sub-pattern 151B is further from the lower surface of the lower sheet structure 140A. The first sub-pattern 151B may include a semiconductor material. For example, the first sub-pattern 151B may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the example embodiments are not limited thereto.

[0086] The second sub-pattern 152B can be disposed on the side surface of the first sub-pattern 151B. The second sub-pattern 152B can be disposed on the barrier structure 170 described below. Therefore, the second sub-pattern 152B can be spaced apart from the lower semiconductor pattern 150A in the third direction (Z direction) due to the barrier structure 170. The second sub-pattern 152B can contact the side surface of the first sub-pattern 151B. The first sub-pattern 151B can be disposed between the second sub-pattern 152B and the upper wafer structure 140B, so the second sub-pattern 152B may not contact the upper wafer structure 140B, but the example embodiment is not limited thereto.

[0087] The second sub-pattern 152B may include a semiconductor material. For example, the second sub-pattern 152B may include the same material as the first sub-pattern 151B. As an example, the first sub-pattern 151B and the second sub-pattern 152B may include silicon (Si) or silicon germanium (SiGe) as semiconductor materials, but the example embodiment is not limited thereto.

[0088] In some example embodiments, the first sub-pattern 151B and the second sub-pattern 152B may have a second type of conductivity. The first sub-pattern 151B and the second sub-pattern 152B may be doped with impurities of the second type of conductivity. The second type of conductivity may be N-type conductivity. For example, the first sub-pattern 151B and the second sub-pattern 152B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiments are not limited thereto. Here, the type of impurity included in the first sub-pattern 151B may be the same as or different from the type of impurity included in the second sub-pattern 152B. Furthermore, the doping concentration of the impurities in the first sub-pattern 151B may be different from the doping concentration of the impurities in the second sub-pattern 152B. For example, the doping concentration of the first type of conductive impurities in the second sub-pattern 152B may be greater than the doping concentration of the first type of conductive impurities in the first sub-pattern 151B, but the example embodiments are not limited thereto. However, the example embodiment is not limited thereto, and as another example, the first sub-pattern 151B and the second sub-pattern 152B may have a first type of conductivity.

[0089] In some example embodiments, the doping concentration of impurities in the first sub-pattern 151B and the second sub-pattern 152B can each be greater than or substantially equal to the doping concentration of impurities in the upper sheet structure 140B. For example, the doping concentration of impurities in the first sub-pattern 151B can be greater than or substantially equal to the doping concentration of impurities in the plurality of first upper semiconductor layers 145B and the plurality of second upper semiconductor layers 142B. Additionally, the doping concentration of impurities in the second sub-pattern 152B can be greater than or substantially equal to the doping concentration of impurities in the plurality of first upper semiconductor layers 145B and the plurality of second upper semiconductor layers 142B.

[0090] In some example embodiments, the upper semiconductor pattern 150B is described as being formed by two layers, but the example embodiments are not limited thereto. The upper semiconductor pattern 150B may be formed by a single layer comprising semiconductor material, or it may be formed by three or more layers.

[0091] The stacked structure SS of the semiconductor device according to some example embodiments may also include a barrier structure 170 disposed between the lower semiconductor pattern 150A and the upper semiconductor pattern 150B.

[0092] The barrier structure 170 can be disposed between the lower semiconductor pattern 150A and the upper semiconductor pattern 150B. The barrier structure 170 can overlap with the lower semiconductor pattern 150A and the upper semiconductor pattern 150B in the third direction (Z direction). The barrier structure 170 can be disposed on the side surface of the PN junction structure 300 described below.

[0093] The barrier structure 170 may include a first liner 171 extending along the side surface of the PN junction structure 300 described below and the upper surface of the lower semiconductor pattern 150A, and a barrier pattern 172 disposed on the first liner 171.

[0094] The first liner 171 and the barrier pattern 172 may comprise various insulating materials. The first liner 171 and the barrier pattern 172 may comprise different materials, but the example embodiment is not limited thereto. For example, the first liner 171 may comprise silicon nitride, silicon oxynitride, or a combination thereof, and the barrier pattern 172 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the example embodiment is not limited thereto. The barrier structure 170 may allow the lower semiconductor pattern 150A and the upper semiconductor pattern 150B to be spaced apart from each other in the third direction (Z direction).

[0095] A PN junction structure 300 may be disposed on the lower wafer structure 140A. The PN junction structure 300 may be disposed between the lower wafer structure 140A and the upper wafer structure 140B. The PN junction structure 300 may be disposed between the uppermost first lower semiconductor layer 145A and the lowermost first upper semiconductor layer 145B. The PN junction structure 300 may be in contact with the uppermost first lower semiconductor layer 145A and the lowermost first upper semiconductor layer 145B. However, the exemplary embodiment is not limited thereto, and as another example, the PN junction structure 300 may be in contact with the uppermost second lower semiconductor layer 142A and the lowermost second upper semiconductor layer 142B.

[0096] The PN junction structure 300 may overlap with the barrier structure 170 in the first direction (X direction). The side surfaces of the PN junction structure 300 may contact the barrier structure 170, but the example embodiment is not limited thereto. Additionally, at least a portion of the PN junction structure 300 may overlap with the upper semiconductor pattern 150B in the first direction (X direction). The side surfaces of the PN junction structure 300 may contact the upper semiconductor pattern 150B, but the example embodiment is not limited thereto. Therefore, in the process of forming the PN junction structure 300 by heat treatment, impurities can easily diffuse into the PN junction structure 300.

[0097] In some example embodiments, the thickness of the PN junction structure 300 in the third direction (Z direction) can be greater than the thickness of the barrier structure 170 in the third direction (Z direction). In some example embodiments, the upper surface of the PN junction structure 300 can be disposed at a height higher than the lower surface of the upper semiconductor pattern 150B. That is, the upper surface of the PN junction structure 300 can be further away from the lower surface of the lower wafer structure 140A than the upper surface of the upper semiconductor pattern 150B. In other words, the upper surface of the PN junction structure 300 can be further away from the upper surface of the lower wafer structure 140A than the upper surface 170_U of the barrier structure 170.

[0098] The PN junction structure 300 may include a semiconductor material. The PN junction structure 300 may include a material different from the plurality of first lower semiconductor layers 145A and the plurality of first upper semiconductor layers 145B. For example, the PN junction structure 300 may include silicon germanium (SiGe). In some example embodiments, the PN junction structure 300, the plurality of second lower semiconductor layers 142A, and the plurality of second upper semiconductor layers 142B may include silicon germanium (SiGe), and the plurality of first lower semiconductor layers 145A and the plurality of first upper semiconductor layers 145B may include silicon (Si). However, the example embodiments are not limited thereto.

[0099] Here, the germanium (Ge) content (at%) in the PN junction structure 300 may differ from the germanium (Ge) content (at%) in the plurality of second lower semiconductor layers 142A and the plurality of second upper semiconductor layers 142B. For example, the germanium (Ge) content (at%) in the PN junction structure 300 may be greater than the germanium (Ge) content (at%) in the plurality of second lower semiconductor layers 142A and the plurality of second upper semiconductor layers 142B, but the example embodiment is not limited thereto.

[0100] In some example embodiments, after removing the initial intermediate insulation structure 220P ( Figure 14 In the process of forming the intermediate insulating structure 220 in the space where the initial intermediate insulating structure 220P has been removed, the lower sacrificial layer 220A can be formed relative to the transistor structure TS described below. Figure 14 (middle) and upper sacrificial layer 220B ( Figure 14 Selectively etch the initial intermediate insulating structure (in the middle) Figure 14 220P in the middle). For example, the initial intermediate insulation structure 220P ( Figure 14 The germanium (Ge) content (at%) in the transistor structure TS described below can be greater than that in the lower sacrificial layer 220A (in the transistor structure TS described below). Figure 14 The germanium (Ge) content (at%) in the ) and the upper sacrificial layer 220B ( Figure 14 The germanium (Ge) content (at%) in the middle.

[0101] Meanwhile, the lower sacrificial layer 220A of the transistor structure TS, which will be described below, Figure 14 (Middle) or upper sacrificial layer 220B ( Figure 14The PN junction structure 300 can be formed simultaneously using the same process as each of the plurality of second lower semiconductor layers 142A or the plurality of second upper semiconductor layers 142B, and the upper sacrificial layer 220A or 220B may comprise the same material as semiconductor layers 142A or 142B. Therefore, the germanium (Ge) content (at%) in the PN junction structure 300 may differ from the germanium (Ge) content (at%) in the plurality of second lower semiconductor layers 142A and the plurality of second upper semiconductor layers 142B. However, the example embodiment is not limited thereto, and various modifications can be made to the PN junction structure 300 within the scope of including materials different from the plurality of first lower semiconductor layers 145A and the plurality of first upper semiconductor layers 145B.

[0102] The PN junction structure 300 of the semiconductor device according to some example embodiments may include a first doped layer 320 having a first type of conductivity and disposed on a lower plate structure 140A, and a second doped layer 310 having a second type of conductivity and disposed on the first doped layer 320.

[0103] The first doped layer 320 can be disposed on the lower wafer structure 140A. For example, the first doped layer 320 can be directly disposed on the upper surface of the uppermost first lower semiconductor layer 145A, but the example embodiment is not limited thereto. As another example, the first doped layer 320 can be directly disposed on the upper surface of the uppermost second lower semiconductor layer 142A.

[0104] The first doped layer 320 may be disposed on the side surface of the barrier structure 170. The first doped layer 320 may be disposed between the barrier structures 170, which are arranged to be spaced apart from each other in a first direction (X direction). The first doped layer 320 may overlap with the barrier structure 170 in the first direction (X direction). The lower surface of the first doped layer 320 may be disposed at substantially the same height as the upper surface of the lower semiconductor pattern 150A. That is, the lower surface of the first doped layer 320 may be disposed at substantially the same distance as the distance from the upper surface of the lower semiconductor pattern 150A to the upper surface of the substrate insulating layer 100. The lower surface of the first doped layer 320 may be aligned with the lower surface of the barrier structure 170, but the example embodiments are not limited thereto. In some example embodiments, the first doped layer 320 may not overlap with the lower semiconductor pattern 150A and the upper semiconductor pattern 150B in the first direction (X direction), but the example embodiments are not limited thereto.

[0105] The upper surface of the first doped layer 320 can be disposed at a height lower than the upper surface 170_U of the barrier structure 170. That is, the height of the upper surface of the first doped layer 320 in the third direction (Z direction) can be closer to the height of the lower wafer structure 140A in the third direction (Z direction) than the height of the upper surface 170_U of the barrier structure 170 in the third direction (Z direction). In addition, the upper surface of the first doped layer 320 can be closer to the lower surface of the upper semiconductor pattern 150B than the upper surface of the lower wafer structure 140A.

[0106] The first doped layer 320 may have a first type of conductivity. The first doped layer 320 may be doped with impurities of the first type of conductivity. Here, the first type of conductivity may be p-type conductivity. For example, the first doped layer 320 may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiments are not limited thereto.

[0107] In some example embodiments, the doping concentration of the impurities in the first doped layer 320 may be less than or substantially equal to the doping concentration of the impurities in the lower sheet structure 140A. For example, the doping concentration of the impurities in the first doped layer 320 may be less than or substantially equal to the doping concentration of the impurities in the plurality of first lower semiconductor layers 145A and the doping concentration of the impurities in the plurality of second lower semiconductor layers 142A.

[0108] Furthermore, the doping concentration of impurities in the first doped layer 320 can be less than or substantially equal to the doping concentration of impurities in the lower semiconductor pattern 150A. For example, the doping concentration of impurities in the first doped layer 320 can be less than or substantially equal to the doping concentration of impurities in the first sub-lower pattern 151A and the second sub-lower pattern 152A. This doping concentration may be caused by process characteristics where impurities present in the lower semiconductor pattern 150A diffuse into the first doped layer 320 through a thermal processing process. As an example, the doping concentration of impurities in the first doped layer 320 can be 1 × 10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 However, the example embodiments are not limited thereto.

[0109] The second doped layer 310 may be disposed on the first doped layer 320. The second doped layer 310 may be disposed between the first doped layer 320 and the upper sheet structure 140B. For example, the second doped layer 310 may be disposed between the first doped layer 320 and the bottommost first upper semiconductor layer 145B. The second doped layer 310 may be in contact with the first doped layer 320 and the first upper semiconductor layer 145B, but the example embodiment is not limited thereto. As another example, the second doped layer 310 may be in contact with the second upper semiconductor layer 142B.

[0110] The second doped layer 310 can be disposed on the side surface of the upper semiconductor pattern 150B and the side surface of the barrier structure 170. The second doped layer 310 can overlap with the upper semiconductor pattern 150B and the barrier structure 170 in the first direction (X direction). The side surface of the second doped layer 310 can contact the upper semiconductor pattern 150B and the barrier structure 170. Therefore, at least a portion of the second doped layer 310 can contact the upper semiconductor pattern 150B, and thus impurities present in the upper semiconductor pattern 150B can be easily diffused into the second doped layer 310 through a thermal processing process.

[0111] The upper surface 310_U of the second doped layer 310 can be disposed at a height higher than the lower surface of the upper semiconductor pattern 150B. That is, the upper surface 310_U of the second doped layer 310 can be further away from the upper surface of the lower sheet structure 140A than the lower surface of the upper semiconductor pattern 150B. In addition, the upper surface of the second doped layer 310 can be further away from the upper surface of the lower sheet structure 140A than the upper surface 170_U of the barrier structure 170.

[0112] In some example embodiments, the second doped layer 310 may comprise the same semiconductor material as the first doped layer 320. For example, both the first doped layer 320 and the second doped layer 310 may comprise silicon germanium (SiGe), but the example embodiments are not limited thereto. Here, the germanium (Ge) content (at%) in the first doped layer 320 may be substantially the same as the germanium (Ge) content (at%) in the second doped layer 310. This content may be caused by the following process characteristics: the initial intermediate insulating structure 220P is doped with a first type of conductive impurity through a thermal processing process. Figure 14 A portion of the structure is formed by doping the remainder with a second type of conductive impurity to form a PN junction structure 300.

[0113] The second doped layer 310 may have a second type of conductivity. The second doped layer 310 may be doped with impurities of a second type of conductivity. Here, the second type of conductivity may be N-type conductivity. For example, the second doped layer 310 may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiment is not limited thereto.

[0114] In some example embodiments, the doping concentration of the impurities in the second doped layer 310 may be less than or substantially equal to the doping concentration of the impurities in the upper sheet structure 140B. For example, the doping concentration of the impurities in the second doped layer 310 may be less than or substantially equal to the doping concentration of the impurities in the plurality of first upper semiconductor layers 145B and the doping concentration of the impurities in the plurality of second upper semiconductor layers 142B.

[0115] Furthermore, the doping concentration of impurities in the second doped layer 310 can be less than or substantially equal to the doping concentration of impurities in the upper semiconductor pattern 150B. For example, the doping concentration of impurities in the second doped layer 310 can be less than or substantially equal to the doping concentration of impurities in the first sub-pattern 151B and the second sub-pattern 152B. This concentration may be caused by process characteristics where impurities present in the upper semiconductor pattern 150B diffuse into the second doped layer 310 through a thermal processing process. As an example, the doping concentration of impurities in the second doped layer 310 can be 1 × 10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 However, the example embodiments are not limited thereto.

[0116] In some exemplary embodiments, the first doped layer 320 and the second doped layer 310 may form a PN junction interface 300_J. The PN junction interface 300_J can be defined as the upper surface of the first doped layer 320 and the lower surface of the second doped layer 310 that are bonded to each other. The upper surface of the first doped layer 320 may have a shape complementary to the lower surface of the second doped layer 310. The PN junction interface 300_J may be flat in cross-section along the first-third direction (XZ direction), but the exemplary embodiments are not limited thereto. That is, the upper surface of the first doped layer 320 and the lower surface of the second doped layer 310 may be flat, but the exemplary embodiments are not limited thereto. Reference is made below. Figure 6 and Figure 7 To describe this configuration.

[0117] In summary, according to some example embodiments, the lower semiconductor pattern 150A, lower wafer structure 140A, and first doped layer 320 of the semiconductor device can have a first type of conductivity, and the upper semiconductor pattern 150B, upper wafer structure 140B, and second doped layer 310 of the semiconductor device can have a second type of conductivity. Therefore, according to some example embodiments, the lower semiconductor pattern 150A, lower wafer structure 140A, and first doped layer 320 of the semiconductor device can form a first type of conductivity doped region CS1, and the upper semiconductor pattern 150B, upper wafer structure 140B, and second doped layer 310 of the semiconductor device can form a second type of conductivity doped region CS2. The first type of conductivity doped region CS1 can have a conductivity type different from that of the second type of conductivity doped region CS2, and the first doped layer 320 and the second doped layer 310 can form a PN junction interface 300_J. Therefore, the stacked structure SS of the semiconductor device according to some example embodiments can perform diode functions.

[0118] In some example embodiments, the PN junction structure 300 is described as including a first doped layer 320 and a second doped layer 310, but the example embodiments are not limited thereto. For example, the PN junction structure 300 may include three or more layers. Here, a portion of the PN junction structure 300 may have a first type of conductivity, and the remainder may have a second type of conductivity, thereby forming a PN junction interface 300_J.

[0119] The stacked structure SS of the semiconductor device according to some example embodiments may also include a dummy main gate structure 160M disposed on the upper chip structure 140B.

[0120] The dummy main gate structure 160M may extend in a second direction (Y direction). The dummy main gate structure 160M may intersect with the protruding pattern 110. In some example embodiments, the dummy main gate structure 160M may be floating. For example, the dummy main gate structure 160M may not be electrically connected to the gate structure 260 of the transistor structure TS.

[0121] like Figure 3 As shown, the dummy main gate structure 160M can be disposed on the uppermost first upper semiconductor layer 145B. The dummy main gate structure 160M can be disposed on the side surface of the upper wafer structure 140B along the second direction (Y direction) and on the side surface of the lower wafer structure 140A along the second direction (Y direction). The dummy main gate structure 160M can be disposed on the field insulating layer 105. The dummy main gate structure 160M can be disposed on the side surface of the PN junction structure 300 along the second direction (Y direction).

[0122] The dummy gate structure 160M may include a dummy gate electrode 165M and a dummy gate insulating film 162M.

[0123] The dummy main gate electrode 165M can be set on the upper plate structure 140B. For example... Figure 3 As shown, the dummy main gate electrode 165M can be disposed on the uppermost first upper semiconductor layer 145B. The dummy main gate electrode 165M can be disposed on the side surface of the upper wafer structure 140B along the second direction (Y direction) and on the side surface of the lower wafer structure 140A along the second direction (Y direction). The dummy main gate electrode 165M can be disposed on the field insulating layer 105. The dummy main gate electrode 165M can be disposed on the side surface of the PN junction structure 300 along the second direction (Y direction).

[0124] The dummy main gate electrode 165M may include a conductive material. For example, the dummy main gate electrode 165M may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. However, the example embodiments are not limited thereto.

[0125] like Figure 2 and Figure 5 As shown, the dummy main gate insulating film 162M can extend along the side surface of the dummy main gate electrode 165M. The dummy main gate insulating film 162M can be disposed between the dummy main gate electrode 165M and the spacer 164 described below, and between the dummy main gate electrode 165M and the upper sheet structure 140B.

[0126] like Figure 3 As shown, the dummy main gate insulating film 162M can be disposed between the dummy main gate electrode 165M and the upper sheet structure 140B, between the dummy main gate electrode 165M and the PN junction structure 300, between the dummy main gate electrode 165M and the lower sheet structure 140A, and between the dummy main gate electrode 165M and the field insulating layer 105. The dummy main gate insulating film 162M can include various insulating materials.

[0127] In some example embodiments, the dummy main gate insulating film 162M is shown as a single-layer film, but the example embodiments are not limited thereto. For example, the dummy main gate insulating film 162M may be formed of a multilayer film comprising silicon oxide (SiO2) and a high-k material. Here, the high-k material may include materials with a dielectric constant higher than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO). However, the example embodiments are not limited thereto.

[0128] The semiconductor device according to some example embodiments may also include spacer 164 and capping layer 166.

[0129] Spacer 164 may be disposed on the side surface of the dummy main gate electrode 165M. Spacer 164 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, the exemplary embodiment is not limited thereto. Spacer 164 is shown as a monolayer film only for ease of description, but the exemplary embodiment is not limited thereto.

[0130] Capping layer 166 may be disposed on the dummy main gate structure 160M. Capping layer 166 may be disposed on the side surface of spacer 164. The upper surface of capping layer 166 may be coplanar (and / or substantially coplanar) with the upper surface of interlayer insulating layer 195. Unlike that shown in the figures, capping layer 166 may also be disposed on the dummy main gate structure 160M and spacer 164. For example, capping layer 166 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof. However, the exemplary embodiments are not limited thereto.

[0131] The stacked structure SS of the semiconductor device according to some example embodiments may also include an interlayer insulating layer 195.

[0132] Interlayer insulating layer 195 may be disposed on the side surface of spacer 164, the side surface of capping layer 166, and the upper surface of upper semiconductor pattern 150B. Interlayer insulating layer 195 may not cover the upper surface of capping layer 166. Interlayer insulating layer 195 may include at least one of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and low-k materials. Low-k materials may include, for example, tetraethyl fluorinated silicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl silicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl silyl ester (TMSB), diacetoxyditert-butoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), tonil silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam (PIN) (such as polypropylene oxide (PPO)), carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon (AFC), silica aerogel (SA), silica degel (SX), mesoporous silica (MS), or combinations thereof, but the exemplary embodiments are not limited thereto.

[0133] The stacked structure SS of the semiconductor device according to some example embodiments may also include a second liner 173.

[0134] The second liner 173 may be disposed between the spacer 164 and the interlayer insulating layer 195, and between the upper semiconductor pattern 150B and the interlayer insulating layer 195. The second liner 173 may comprise a material having etch selectivity relative to the interlayer insulating layer 195. The second liner 173 may, for example, comprise at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof. However, the exemplary embodiments are not limited thereto.

[0135] The transistor structure TS is described below.

[0136] The transistor structure TS of a semiconductor device according to some example embodiments may include a protruding pattern 110 disposed on a substrate insulating layer 100, a plurality of channel patterns 240 disposed on the protruding pattern 110, an intermediate insulating structure 220 disposed between a plurality of lower channel patterns 240A and a plurality of upper channel patterns 240B, a gate structure 260 disposed on the protruding pattern 110, and a source / drain pattern 250 disposed on at least one side of the gate structure 260.

[0137] A semiconductor device according to some example embodiments may include at least one transistor element. For example, a semiconductor device according to some example embodiments may include: a first transistor structure including a plurality of lower channel patterns 240A; and a second transistor structure including a plurality of upper channel patterns 240B. The first transistor structure or the second transistor structure according to some example embodiments may be formed as a gate-all-field-effect transistor (GAAFET) structure, such as a multi-bridge-channel field-effect transistor (MBCFET). TM ( ), wherein multiple lower channel patterns 240A or multiple upper channel patterns 240B are surrounded by gate structure 260.

[0138] Additionally, according to some example embodiments, the first or second transistor structure can be a three-dimensional stacked FET (3D-SFET) structure stacked along a third direction (Z direction). Here, the first transistor structure can be a first-type conductive metal-oxide-semiconductor field-effect transistor (MOSFET), and the second transistor structure can be a second-type conductive MOSFET. Here, the first type of conductivity can be P-type conductivity, and the second type of conductivity can be N-type conductivity. However, the example embodiments are not limited thereto. The first transistor structure can be a second-type conductive MOSFET, and the second transistor structure can be a first-type conductive MOSFET. Hereinafter, this specification describes a case where a plurality of lower channel patterns 240A and a plurality of upper channel patterns 240B are stacked in a third direction (Z direction) to form a 3D-SFET structure. However, the example embodiments are not limited thereto.

[0139] Multiple channel patterns 240 may be disposed on the protruding pattern 110. In some example embodiments, the multiple channel patterns 240 may include multiple lower channel patterns 240A disposed on the protruding pattern 110 and multiple upper channel patterns 240B disposed on the multiple lower channel patterns 240A.

[0140] Multiple lower channel patterns 240A may be disposed on the upper surface of the protruding pattern 110. The multiple lower channel patterns 240A may be spaced apart from the protruding pattern 110 in the third direction (Z direction). The multiple lower channel patterns 240A may be spaced apart from each other in the third direction (Z direction). In some example embodiments, the multiple lower channel patterns 240A may be multi-channel active patterns.

[0141] In some example embodiments, the plurality of lower channel patterns 240A may have a shape, structure, and arrangement similar to that of the plurality of first lower semiconductor layers 145A of the stacked structure SS. For example, the number of the plurality of lower channel patterns 240A stacked in the third direction (Z direction) may be the same as the number of the plurality of first lower semiconductor layers 145A stacked in the third direction (Z direction). Furthermore, the thickness of each of the plurality of lower channel patterns 240A in the third direction (Z direction) may be the same as the thickness of each of the plurality of first lower semiconductor layers 145A in the third direction (Z direction).

[0142] In some example embodiments, each of the plurality of lower channel patterns 240A may comprise the same semiconductor material as the plurality of first lower semiconductor layers 145A. For example, the plurality of lower channel patterns 240A may comprise the elemental semiconductor material silicon (Si) or germanium (Ge). However, the example embodiments are not limited thereto. As an example, the plurality of lower channel patterns 240A and the plurality of first lower semiconductor layers 145A may comprise silicon (Si). The plurality of lower channel patterns 240A may be formed by etching a portion of the substrate 101. Figure 14 (middle), or may include an epitaxial layer grown from substrate 101 (middle), Figure 14 middle).

[0143] In some example embodiments, the plurality of lower channel patterns 240A may be doped with impurities at a concentration lower than that of the plurality of first lower semiconductor layers 145A, or may be undoped.

[0144] Multiple upper channel patterns 240B can be disposed above multiple lower channel patterns 240A. Specifically, the multiple upper channel patterns 240B can be disposed on the upper surface of an intermediate insulating structure 220 disposed on the multiple lower channel patterns 240A. The multiple upper channel patterns 240B can be spaced apart from the multiple lower channel patterns 240A in a third direction (Z direction). For example, the intermediate insulating structure 220 can be disposed between the multiple upper channel patterns 240B and the multiple lower channel patterns 240A, and due to the intermediate insulating structure 220, the multiple upper channel patterns 240B can be spaced apart from the multiple lower channel patterns 240A in a third direction (Z direction). The multiple upper channel patterns 240B can be spaced apart from each other in a third direction (Z direction). In some example embodiments, the multiple upper channel patterns 240B can be multi-channel active patterns.

[0145] In some example embodiments, the plurality of upper channel patterns 240B may have a shape, structure, and arrangement similar to that of the plurality of first upper semiconductor layers 145B of the stacked structure SS. For example, the number of the plurality of upper channel patterns 240B stacked in the third direction (Z direction) may be the same as the number of the plurality of first upper semiconductor layers 145B stacked in the third direction (Z direction). Furthermore, the thickness of each of the plurality of upper channel patterns 240B in the third direction (Z direction) may be the same as the thickness of each of the plurality of first upper semiconductor layers 145B in the third direction (Z direction).

[0146] In some example embodiments, the plurality of upper channel patterns 240B may include the same semiconductor material as the plurality of first upper semiconductor layers 145B. For example, the plurality of upper channel patterns 240B may include silicon (Si) or germanium (Ge) as elemental semiconductor materials. However, the example embodiments are not limited thereto. As an example, the plurality of upper channel patterns 240B and the plurality of first upper semiconductor layers 145B may include silicon (Si). Additionally, the plurality of upper channel patterns 240B may include the same material as the plurality of lower channel patterns 240A, but the example embodiments are not limited thereto. The plurality of upper channel patterns 240B may be formed by etching a portion of the substrate 101. Figure 14 (middle), or may include an epitaxial layer grown from substrate 101 (middle), Figure 14 middle).

[0147] In some example embodiments, the plurality of upper channel patterns 240B may be doped with impurities at a concentration lower than that of the plurality of first upper semiconductor layers 145B, or may be undoped.

[0148] Figure 2 The illustration shows two lower channel patterns 240A and three upper channel patterns 240B stacked spaced apart from each other in the third direction (Z direction). This is for ease of description only, and the example embodiment is not limited thereto. For example, multiple lower channel patterns 240A comprising three or more patterns and / or multiple upper channel patterns 240B comprising three or more patterns may be stacked spaced apart from each other in the third direction (Z direction). Alternatively, one lower channel pattern 240A and / or one upper channel pattern 240B may be stacked spaced apart from each other in the third direction (Z direction).

[0149] The intermediate insulating structure 220 can be disposed on multiple lower channel patterns 240A. The intermediate insulating structure 220 can be disposed between the uppermost lower channel pattern 240A and the lowermost upper channel pattern 240B. In addition, the intermediate insulating structure 220 can be disposed between the uppermost lower gate structure 260A and the lowermost upper gate structure 260B.

[0150] The intermediate insulation structure 220 may include various insulating materials. For example, the intermediate insulation structure 220 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. However, the example embodiments are not limited thereto. The intermediate insulation structure 220 may allow a plurality of lower channel patterns 240A and a plurality of upper channel patterns 240B to be spaced apart from each other.

[0151] Figure 2 The intermediate insulation structure 220 is shown to be formed from a single layer. However, the intermediate insulation structure 220 is not limited to this and may be formed from multiple layers.

[0152] Gate structure 260 may be disposed on protruding pattern 110. Gate structure 260 may extend in a second direction (Y direction). Gate structure 260 may be spaced apart from dummy main gate structure 160M in a first direction (X direction). Gate structure 260 may be disposed on protruding pattern 110. Gate structure 260 may intersect with protruding pattern 110. Gate structure 260 may surround each of a plurality of channel patterns 240.

[0153] In some example embodiments, the first transistor structure and the second transistor structure may share a gate structure 260. For example, as... Figure 4 As shown, the gate structure 260 can surround multiple lower channel patterns 240A and multiple upper channel patterns 240B, so the first transistor structure and the second transistor structure can share a gate structure 260.

[0154] The gate structure 260 may include a lower gate structure 260A, an upper gate structure 260B, and a main gate structure 260M.

[0155] The lower gate structure 260A can be disposed between multiple lower channel patterns 240A adjacent to each other along the third direction (Z direction) and between the protruding pattern 110 and the lowermost lower channel pattern 240A. The upper gate structure 260B can be disposed between multiple upper channel patterns 240B adjacent to each other along the third direction (Z direction). The uppermost main gate structure 260M can be disposed on the upper channel pattern 240B.

[0156] The lower gate structure 260A may be adjacent to the lower source / drain pattern 250A, which will be described below. The upper gate structure 260B may be adjacent to the upper source / drain pattern 250B, which will be described below. The main gate structure 260M may be disposed above / on the lower gate structure 260A, the upper gate structure 260B, and a plurality of upper channel patterns 240B.

[0157] According to some example embodiments, the lower gate structure 260A and the upper gate structure 260B may each include multiple layers, and the multiple layers and multiple channel patterns 240 may be stacked alternately.

[0158] The lower gate structure 260A and the upper gate structure 260B may each include gate electrodes 265A and 265B and gate insulating films 262A and 262B.

[0159] Gate electrodes 265A and 265B may be disposed on / above the protruding pattern 110. For example, the lower gate electrode 265A may be disposed on the protruding pattern 110, and the upper gate electrode 265B may be disposed on the lower gate electrode 265A. The lower gate electrode 265A may surround a plurality of lower channel patterns 240A, and the upper gate electrode 265B may surround a plurality of upper channel patterns 240B.

[0160] Gate electrodes 265A and 265B may each comprise a conductive material. Gate electrodes 265A and 265B may each comprise at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxide nitride. Gate electrodes 265A and 265B may, for example, comprise at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbide (Ta... The materials used are: CN, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof, but the exemplary embodiments are not limited thereto. Conductive metal oxides and conductive metal nitrides may each include oxides of the above-described materials, but the exemplary embodiments are not limited thereto. Gate electrodes 265A and 265B may include the same material, but are not limited thereto, and gate electrodes 265A and 265B may include different materials.

[0161] Gate insulating films 262A and 262B may each be disposed along the periphery of the plurality of channel patterns 240. For example, the lower gate insulating film 262A may be disposed along the periphery of the plurality of lower channel patterns 240A, and the upper gate insulating film 262B may be disposed along the periphery of the plurality of upper channel patterns 240B. Additionally, the lower gate insulating film 262A may extend along the upper surface of the protruding pattern 110. Gate insulating films 262A and 262B may each comprise various insulating materials.

[0162] In some example embodiments, the gate insulating film 262A or 262B is shown as a single-layer film, but the example embodiments are not limited thereto. For example, the gate insulating film 262A or 262B may be formed of a multilayer film comprising silicon oxide (SiO2) and a high-k material. Here, the high-k material may include materials with a dielectric constant higher than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO). However, the example embodiments are not limited thereto.

[0163] The main gate structure 260M can be disposed above / on the upper gate structure 260B and multiple upper channel patterns 240B. The main gate structure 260M can be disposed on the upper surface of the multiple upper channel patterns 240B.

[0164] In some example embodiments, the main gate structure 260M may be disposed on the same layer as the dummy main gate structure 160M of the stacked structure SS. That is, the lower surface of the main gate structure 260M may be disposed at substantially the same height as the lower surface of the dummy main gate structure 160M. Furthermore, the thickness of the main gate structure 260M in the third direction (Z direction) may be substantially the same as the thickness of the dummy main gate structure 160M in the third direction (Z direction). This same thickness may be caused by the following process feature: the main gate structure 260M and the dummy main gate structure 160M are formed simultaneously in the same process.

[0165] The main gate structure 260M may include a main gate electrode 265M and a main gate insulating film 262M.

[0166] The main gate electrode 265M can be disposed above the upper gate structure 260B and the plurality of upper channel patterns 240B. The main gate electrode 265M can be disposed above the upper surface of the plurality of upper channel patterns 240B. Therefore, the four sides of the plurality of channel patterns 240B can be surrounded by gate electrodes 265A and 265B and the main gate electrode 265M. The main gate electrode 265M can include the same conductive material as the gate electrodes 265A or 265B.

[0167] The main gate insulating film 262M may extend along the side surface of the main gate electrode 265M. The main gate insulating film 262M may extend along the side surface of the spacer 164. The main gate insulating film 262M may include various insulating materials.

[0168] In some exemplary embodiments, the main gate insulating film 262M is shown as a single-layer film, but the exemplary embodiments are not limited thereto. For example, the main gate insulating film 262M may be formed of a multilayer film comprising silicon oxide (SiO2) and a high-k material. Here, the high-k material may include materials with a dielectric constant higher than that of silicon oxide (SiO2), such as hafnium oxide (HfO), aluminum oxide (AlO), or tantalum oxide (TaO). However, the exemplary embodiments are not limited thereto.

[0169] In some example embodiments, spacer 164 may also be disposed on the side surface of the main gate electrode 265M. Spacer 164 may not be disposed between the protruding pattern 110 and the plurality of channel patterns 240. Spacer 164 may not be disposed between the plurality of channel patterns 240 that are adjacent to each other along the third direction (Z direction).

[0170] In some example embodiments, the capping layer 166 may also be disposed on the main gate structure 260M and the spacer 164. The upper surface of the capping layer 166 may be coplanar (and / or substantially coplanar) with the upper surface of the interlayer insulating layer 195.

[0171] Source / drain pattern 250 may be disposed on at least one side of gate structure 260. For example, source / drain pattern 250 may be disposed on each of the two sides of gate structure 260. Source / drain pattern 250 may be disposed on protruding pattern 110. Source / drain pattern 250 may contact the side surfaces of a plurality of channel patterns 240. Source / drain pattern 250 may be connected to a plurality of channel patterns 240.

[0172] According to some example embodiments, the source / drain pattern 250 may include a lower source / drain pattern 250A and an upper source / drain pattern 250B.

[0173] The lower source / drain pattern 250A may be disposed on the protruding pattern 110. The lower source / drain pattern 250A may be disposed on at least one side of the lower gate structure 260A. For example, the lower source / drain pattern 250A may be disposed on each of the two sides of the lower gate structure 260A. The lower source / drain pattern 250A may be connected to a plurality of lower channel patterns 240A.

[0174] In some example embodiments, the lower source / drain pattern 250A may have substantially the same shape as the lower semiconductor pattern 150A of the stacked structure SS. For example, the lower source / drain pattern 250A may be disposed in a trench extending along a third direction (Z direction). At least a portion of the lower source / drain pattern 250A may be surrounded by a protruding pattern 110. The lower surface of the lower source / drain pattern 250A may be closer to the upper surface of the substrate insulating layer 100 than the lower surface of the lower channel pattern 240A. This arrangement may be caused by the simultaneous formation of the lower source / drain pattern 250A and the lower semiconductor pattern 150A.

[0175] The source / drain pattern 250A can be achieved by using the active pattern 111 ( Figure 14 The epitaxial pattern is formed by a selective epitaxial growth process using multiple lower channel patterns 240A as seed crystals. The lower source / drain pattern 250A can act as the source / drain of a transistor by using multiple lower channel patterns 240A as channel regions.

[0176] The lower source / drain pattern 250A may have a first type of conductivity. The lower semiconductor pattern 150A may be doped with a first type of conductive impurity. Here, the first type of conductivity may be P-type conductivity, but the example embodiment is not limited thereto. For example, the lower source / drain pattern 250A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiment is not limited thereto.

[0177] The lower source / drain pattern 250A of a semiconductor device according to some example embodiments may include a first lower source / drain layer 251A and a second lower source / drain layer 252A.

[0178] The first lower source / drain layer 251A may be disposed on the side surfaces of the plurality of lower channel patterns 240A and the upper surface of the protruding pattern 110. The first lower source / drain layer 251A may include a semiconductor material. The first lower source / drain layer 251A may include the same material as the first sub-lower pattern 151A. For example, the first lower source / drain layer 251A may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the example embodiment is not limited thereto.

[0179] The second lower source / drain layer 252A can be disposed on the first lower source / drain layer 251A. The second lower source / drain layer 252A can be surrounded by the first lower source / drain layer 251A. The upper surface of the second lower source / drain layer 252A can be disposed at the same height as the upper surface of the first lower source / drain layer 251A.

[0180] The second lower source / drain layer 252A may include a semiconductor material. The second lower source / drain layer 252A may include the same semiconductor material as the second sub-pattern 152A. As an example, the second lower source / drain layer 252A may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the example embodiment is not limited thereto.

[0181] In some example embodiments, the first lower source / drain layer 251A and the second lower source / drain layer 252A may each have a first type of conductivity. The first lower source / drain layer 251A and the second lower source / drain layer 252A may each be doped with a first type of conductive impurity. Here, the first type of conductivity may be P-type conductivity. Here, the doping concentration of the impurity in the first lower source / drain layer 251A may be less than or substantially equal to the doping concentration of the impurity in the first sub-lower pattern 151A of the stacked structure SS. Additionally, the doping concentration of the impurity in the second lower source / drain layer 252A may be less than or substantially equal to the doping concentration of the impurity in the second sub-lower pattern 152A of the stacked structure SS. However, the example embodiments are not limited to this, and the doping concentration of the impurity in the first lower source / drain layer 251A may be greater than the doping concentration of the impurity in the first sub-lower pattern 151A of the stacked structure SS. The doping concentration of the impurity in the second lower source / drain layer 252A may be greater than the doping concentration of the impurity in the second sub-lower pattern 152A of the stacked structure SS. As another example, the first lower source / drain layer 251A and the second lower source / drain layer 252A may each have a second type of conductivity.

[0182] In some example embodiments, the lower source / drain pattern 250A is described as being formed of multiple layers, but is not limited thereto, and may be formed of a single layer comprising semiconductor material.

[0183] According to some example embodiments, the upper source / drain pattern 250B of a semiconductor device may be disposed above the lower source / drain pattern 250A.

[0184] The upper source / drain pattern 250B can be spaced apart from the lower source / drain pattern 250A in the third direction (Z direction). For example, a blocking structure 170 can be provided between the upper source / drain pattern 250B and the lower source / drain pattern 250A, and due to the blocking structure 170, the upper source / drain pattern 250B and the lower source / drain pattern 250A can be spaced apart from each other. Therefore, the upper source / drain pattern 250B and the lower source / drain pattern 250A can be electrically insulated from each other.

[0185] The upper source / drain pattern 250B may be disposed on at least one side of the upper gate structure 260B. For example, the upper source / drain pattern 250B may be disposed on each of the two sides of the upper gate structure 260B. The upper source / drain pattern 250B may be connected to a plurality of upper channel patterns 240B.

[0186] In some example embodiments, the upper source / drain pattern 250B may have substantially the same shape as the upper semiconductor pattern 150B of the stacked structure SS. For example, the lower surface of the upper source / drain pattern 250B may be disposed at substantially the same height as the lower surface of the upper semiconductor pattern 150B. The upper surface of the upper source / drain pattern 250B may be disposed at substantially the same height as the upper surface of the upper semiconductor pattern 150B. This feature may be caused by the process feature that the upper source / drain pattern 250B and the upper semiconductor pattern 150B are formed simultaneously.

[0187] The upper source / drain pattern 250B can be an epitaxial pattern formed by a selective epitaxial growth process using multiple upper channel patterns 240B as seed crystals. Here, the upper source / drain pattern 250B can be a pattern formed using only the side surfaces of multiple upper channel patterns 240B as seed crystals. That is, compared to the lower source / drain pattern 250A (which uses the active pattern 111... Figure 14 Unlike the pattern formed by using the upper surface of the upper channel pattern 240A and the side surfaces of the multiple lower channel patterns 240A as seed crystals, the upper source / drain pattern 250B can be a pattern formed by using only the side surfaces of the multiple upper channel patterns 240B as seed crystals. The upper source / drain pattern 250B can act as the source / drain of a transistor by using the multiple upper channel patterns 240B as channel regions.

[0188] The source / drain pattern 250B of the semiconductor device according to some example embodiments may include a first source / drain layer 251B and a second source / drain layer 252B.

[0189] The first upper source / drain layer 251B may be disposed on the side surface of a plurality of upper channel patterns 240B. The first upper source / drain layer 251B may be disposed on the barrier structure 170. The first upper source / drain layer 251B may include a semiconductor material. The first upper source / drain layer 251B may include the same material as the first sub-pattern 151B. For example, the first upper source / drain layer 251B may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the example embodiment is not limited thereto.

[0190] In some example embodiments, the first upper source / drain layer 251B may have substantially the same shape as the first sub-upper pattern 151B. For example, the side surface of the first upper source / drain layer 251B may include a curved surface protruding from the side surfaces of the plurality of upper channel patterns 240B.

[0191] The second source / drain layer 252B can be disposed between the first source / drain layer 251B. The second source / drain layer 252B can be disposed on the blocking structure 170.

[0192] The second source / drain layer 252B may include a semiconductor material. The second source / drain layer 252B may include the same semiconductor material as the second sub-pattern 152B. As an example, the second source / drain layer 252B may include silicon (Si) or silicon germanium (SiGe) as the semiconductor material. However, the example embodiment is not limited thereto.

[0193] In some example embodiments, the first upper source / drain layer 251B and the second upper source / drain layer 252B may each have a second type of conductivity. The first upper source / drain layer 251B and the second upper source / drain layer 252B may each be doped with a second type of conductive impurity. Here, the second type of conductivity may be N-type conductivity. Here, the doping concentration of the impurity in the first upper source / drain layer 251B may be less than or substantially equal to the doping concentration of the impurity in the first sub-pattern 151B of the stacked structure SS. Additionally, the doping concentration of the impurity in the second upper source / drain layer 252B may be less than or substantially equal to the doping concentration of the impurity in the second sub-pattern 152B of the stacked structure SS. However, the example embodiments are not limited to this, and the doping concentration of the impurity in the first upper source / drain layer 251B may be greater than the doping concentration of the impurity in the first sub-pattern 151B of the stacked structure SS. The doping concentration of the impurity in the second upper source / drain layer 252B may be greater than the doping concentration of the impurity in the second sub-pattern 152B of the stacked structure SS. As another example, the first upper source / drain layer 251B and the second upper source / drain layer 252B may each have a first type of conductivity.

[0194] In some example embodiments, the barrier structure 170 may also be disposed between the lower source / drain pattern 250A and the upper source / drain pattern 250B. The barrier structure 170 may overlap with the lower source / drain pattern 250A and the upper source / drain pattern 250B in the third direction (Z direction). The barrier structure 170 may be disposed on the side surface of the intermediate insulating structure 220. The upper and lower surfaces of the barrier structure 170 may be flat, but the example embodiments are not limited thereto. For example, the upper and / or lower surfaces of the barrier structure 170 may convex upward or downward.

[0195] The semiconductor device according to some example embodiments may also include an upper contact structure 180 and a lower contact structure 190.

[0196] The upper contact structure 180 may be disposed on the upper semiconductor pattern 150B or the upper source / drain pattern 250B. For example, a first upper contact structure 180_1 may be electrically connected to the upper semiconductor pattern 150B through the interlayer insulating layer 195. A second upper contact structure 180_2 may be electrically connected to the upper source / drain pattern 250B through the interlayer insulating layer 195. The upper contact structure 180 may have a sloped side surface, the lower width of which is narrower than its upper width based on its aspect ratio, but the example embodiment is not limited thereto. The upper contact structure 180 may recess the upper semiconductor pattern 150B and the upper source / drain pattern 250B to a desired (and / or alternatively, predetermined) depth.

[0197] The upper contact structure 180 of a semiconductor device according to some example embodiments may include an upper contact electrode 186 and an upper silicide film 182 disposed between the upper contact electrode 186 and the upper semiconductor pattern 150B.

[0198] The upper contact electrode 186 may include, for example, at least one selected from metal, metal alloy, conductive metal nitride, conductive metal carbide, conductive metal oxide, conductive metal carbonitride, and two-dimensional (2D) material. However, the exemplary embodiments are not limited thereto. The upper silicide film 182 may surround a portion of the upper contact electrode 186 recessed into the upper semiconductor pattern 150B. The upper silicide film 182 may include a metal silicide. For example, the upper silicide film 182 may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. However, the exemplary embodiments are not limited thereto. In some exemplary embodiments, the number and arrangement of the conductive layers included in the upper contact structure 180 may be varied.

[0199] The lower contact structure 190 may be disposed on the lower semiconductor pattern 150A or the lower source / drain pattern 250A. For example, a first lower contact structure 190-1 may be electrically connected to the lower semiconductor pattern 150A through the substrate insulating layer 100. A second lower contact structure 190-2 may be electrically connected to the lower source / drain pattern 250A through the substrate insulating layer 100. The lower contact structure 190 may recess the lower semiconductor pattern 150A and the lower source / drain pattern 250A to a desired (and / or alternatively, predetermined) depth. The lower contact structure 190 of a semiconductor device according to some example embodiments may include a lower contact electrode 196 and a lower silicide film 192 disposed between the lower contact electrode 196 and the lower semiconductor pattern 150A. The description of the lower contact electrode 196 and the lower silicide film 192 is substantially the same as the description of the upper contact electrode 186 and the upper silicide film 182, and therefore their description is omitted here.

[0200] In semiconductor devices according to some example embodiments, a transistor structure TS and a stacked structure SS including diode elements, etc., can be simultaneously formed on a substrate insulating layer 100 and / or a semiconductor substrate. Therefore, the stacked structure SS including diode elements, etc., can be formed together with the transistor structure TS without significantly increasing the number of manufacturing processes, thereby improving the integration level of the semiconductor device and / or reducing manufacturing costs.

[0201] In the following text, see references Figures 6 to 10 The following describes the stacked structure of semiconductor devices according to some example embodiments.

[0202] Figures 6 to 10 Is with Figure 2 The cross-sectional view corresponding to region S1 in the diagram shows a semiconductor device according to some example embodiments.

[0203] Figures 6 to 10 The illustrated embodiments and Figures 1 to 5 The embodiments shown are essentially the same, so their descriptions are omitted and the differences are mainly described.

[0204] refer to Figure 6 and Figure 7 The PN junction interface 300_J between the first doped layer 320 and the second doped layer 310 of the semiconductor device according to some example embodiments can have various shapes.

[0205] For example, such as Figure 6 As shown, the PN junction interface 300_J between the first doped layer 320 and the second doped layer 310 can be recessed toward the upper surface of the lower sheet structure 140A. That is, the upper surface of the first doped layer 320 can be recessed toward the upper surface of the lower sheet structure 140A, and the lower surface of the second doped layer 310 can be protruding toward the upper surface of the lower sheet structure 140A. The upper surface of the first doped layer 320 can be positioned at a lower height than the upper surface of the barrier structure 170. That is, the height of the upper surface of the first doped layer 320 in the third direction (Z direction) can be closer to the height of the lower sheet structure 140A in the third direction (Z direction) than the height of the upper surface 170_U of the barrier structure 170 in the third direction (Z direction). Here, the upper surface of the first doped layer 320 can have a shape complementary to the lower surface of the second doped layer 310.

[0206] As another example, such as Figure 7As shown, the PN junction interface 300_J between the first doped layer 320 and the second doped layer 310 can protrude toward the upper surface of the upper sheet structure 140B. That is, the upper surface of the first doped layer 320 can protrude toward the upper surface of the upper sheet structure 140B, and the lower surface of the second doped layer 310 can be recessed toward the upper surface of the upper sheet structure 140B. The upper surface of the first doped layer 320 can be disposed at a height higher than the upper surface of the barrier structure 170. That is, the height of the upper surface of the first doped layer 320 in the third direction (Z direction) can be further away from the height of the upper surface of the lower sheet structure 140A in the third direction (Z direction) than the height of the upper surface of the barrier structure 170 in the third direction (Z direction). However, the example embodiment is not limited to this, and the upper surface of the first doped layer 320 can be disposed at a height lower than or substantially equal to the height of the upper surface of the barrier structure 170. In some example embodiments, the first doped layer 320 may have at least a portion that overlaps with the upper semiconductor pattern 150B in a first direction (X direction), but the example embodiments are not limited thereto.

[0207] refer to Figure 8 The stacked structure SS of the semiconductor device according to some example embodiments may include a dummy lower gate structure 160A and a dummy upper gate structure 160B. Figure 8 In some example embodiments shown, with Figures 1 to 5 The embodiments differ from those in that the lower wafer structure 140A does not include a plurality of second lower semiconductor layers 142A, and the upper wafer structure 140B does not include a plurality of second upper semiconductor layers 142B.

[0208] In some example embodiments, the dummy lower gate structure 160A can be stacked and spaced apart from each other in the third direction (Z direction). A plurality of first lower semiconductor layers 145A can be disposed between the dummy lower gate structures 160A stacked and spaced apart from each other in the third direction (Z direction). That is, the plurality of first lower semiconductor layers 145A and the dummy lower gate structure 160A can be stacked alternately in the third direction (Z direction). In some example embodiments, the dummy lower gate structure 160A can be floating. For example, the dummy lower gate structure 160A may not be electrically connected to the gate structure 260 of the transistor structure TS. In some example embodiments, the dummy lower gate structure 160A may have a shape, structure, and arrangement similar to that of the lower gate structure 260A included in the transistor structure TS.

[0209] The dummy upper gate structure 160B can be stacked and spaced apart from each other in the third direction (Z direction). A plurality of first upper semiconductor layers 145B can be disposed between the dummy upper gate structures 160B stacked and spaced apart from each other in the third direction (Z direction). That is, the plurality of first upper semiconductor layers 145B and the dummy upper gate structure 160B can be stacked alternately in the third direction (Z direction). In some example embodiments, the dummy upper gate structure 160B can be floating. For example, the dummy upper gate structure 160B may not be electrically connected to the gate structure 260 of the transistor structure TS. In some example embodiments, the dummy upper gate structure 160B may have a shape, structure, and arrangement similar to that of the upper gate structure 260B included in the transistor structure TS.

[0210] The dummy lower gate structure 160A and the dummy upper gate structure 160B may each include dummy gate electrodes 165A and 165B and dummy gate insulating films 162A and 162B. The descriptions of the dummy gate electrodes 165A and 165B and the dummy gate insulating films 162A and 162B are substantially the same as the descriptions of the gate electrodes 265A and 265B and the gate insulating films 262A and 262B included in the transistor structure TS, and therefore their descriptions are omitted.

[0211] refer to Figure 9 According to some example embodiments, the stacked structure SS of the semiconductor device may include a dummy gate pattern 350 disposed on the upper chip structure 140B, and may not include a dummy main gate structure 160M.

[0212] In some example embodiments, the dummy gate pattern 350 may extend in the second direction (Y direction). The dummy gate pattern 350 may intersect with the protruding pattern 110. The dummy gate pattern 350 may be disposed on the uppermost first upper semiconductor layer 145B. The dummy gate pattern 350 may be disposed on the side surface of the upper wafer structure 140B along the second direction (Y direction) and on the side surface of the lower wafer structure 140A along the second direction (Y direction). The dummy gate pattern 350 may be disposed on the side surface of the PN junction structure 300 along the second direction (Y direction). In some example embodiments, the dummy gate pattern 350 may be floating.

[0213] In some example embodiments, the dummy gate pattern 350 may include, for example, polysilicon, but the example embodiments are not limited thereto. The dummy gate pattern 350 may include, with respect to the sacrificial gate structure 400 ( Figure 14 The same material (in the middle). The dummy gate pattern 350 can be formed as a sacrificial gate structure 400 (in the middle). Figure 14 At least a part of (in the middle).

[0214] refer to Figure 10According to some example embodiments, the stacked structure SS of the semiconductor device may not include the blocking structure 170.

[0215] In some example embodiments, the lower semiconductor pattern 150A may be in contact with the upper semiconductor pattern 150B. The lower semiconductor pattern 150A may form an interface 150_J with the upper semiconductor pattern 150B, and the interface 150_J between the lower semiconductor pattern 150A and the upper semiconductor pattern 150B may form a PN junction interface.

[0216] The upper surface of the lower semiconductor pattern 150A may be further away from the upper surface of the substrate insulating layer 100 than the upper surface of the lower sheet structure 140A. Therefore, the side surface of the lower semiconductor pattern 150A may contact the first doped layer 320. The lower semiconductor pattern 150A may overlap with the first doped layer 320 in a first direction (X direction). In some example embodiments, the upper surface of the lower semiconductor pattern 150A may be located at a distance substantially the same as the distance from the upper surface of the first doped layer 320 to the upper surface of the lower sheet structure 140A.

[0217] Furthermore, the lower surface of the upper semiconductor pattern 150B can be closer to the upper surface of the lower wafer structure 140A than the lower surface of the upper wafer structure 140B. The lower surface of the upper semiconductor pattern 150B can be located at a distance substantially the same as the distance between the lower surface of the second doped layer 310 and the upper surface of the lower wafer structure 140A.

[0218] In the following text, see references Figures 11 to 13 To describe a semiconductor device according to some example embodiments.

[0219] Figures 11 to 13 Is along Figure 1 The cross-sectional view corresponding to the region intercepted by line A-A' in the diagram illustrates a semiconductor device according to some example embodiments. For ease of description, Figures 11 to 13 The stacked structures SS1 and SS2 are shown, and the transistor structure TS is omitted. Figure 2 (Middle). Transistor structure TS ( Figure 2 (in Chinese) can be set Figures 11 to 13 On one side of the stacked structure SS1 and SS2.

[0220] Figures 11 to 13 The illustrated embodiments and Figures 1 to 5 The embodiments shown are essentially the same, so their descriptions are omitted and the differences are mainly described.

[0221] refer to Figure 11 According to some example embodiments, the stacked structure SS of the semiconductor device may include a plurality of dummy main gate structures 160M disposed on the upper chip structure 140B.

[0222] In some example embodiments, multiple dummy main gate structures 160M may be disposed between adjacent upper semiconductor patterns 150B and spaced apart from each other in a first direction (X direction). For example, a first dummy main gate structure 160M_1 and a second dummy main gate structure 160M_2 may be disposed between adjacent upper semiconductor patterns 150B and spaced apart from each other in the first direction (X direction). An interlayer insulating layer 195 and a second liner 173 may be disposed between the first dummy main gate structure 160M_1 and the second dummy main gate structure 160M_2. Due to the interlayer insulating layer 195 and the second liner 173, the first dummy main gate structure 160M_1 and the second dummy main gate structure 160M_2 can be spaced apart from each other.

[0223] Figure 11 Two dummy main gate structures 160M_1 and 160M_2 are shown disposed between adjacent upper semiconductor patterns 150B along the first direction (X direction), and the number of dummy main gate structures 160M is not limited thereto.

[0224] refer to Figure 12 According to some example embodiments, the dummy main gate structure 160M of the semiconductor device has a first width D1 in the first direction (X direction) that is greater than or substantially equal to the second width D2 of the upper semiconductor pattern 150B in the first direction (X direction). Therefore, the width of the upper wafer structure 140B in the first direction (X direction) can be greater than or substantially equal to the second width D2 of the upper semiconductor pattern 150B in the first direction (X direction). Additionally, the width of the lower wafer structure 140A in the first direction (X direction) can be greater than or substantially equal to the second width D2 of the lower semiconductor pattern 150A in the first direction (X direction).

[0225] The semiconductor device according to some example embodiments may include a first stacked structure SS1 and a second stacked structure SS2 that are adjacent to each other in a first direction (X direction). In some example embodiments, the first stacked structure SS1 and the second stacked structure SS2 may share an upper semiconductor pattern 150B and a lower semiconductor pattern 150A, but the example embodiments are not limited thereto.

[0226] refer to Figure 13 According to some example embodiments, the semiconductor device may include a first stacked structure SS1 and a second stacked structure SS2 that are adjacent to each other in a first direction (X direction). The first stacked structure SS1 and the second stacked structure SS2 may share an upper semiconductor pattern 150B.

[0227] In some example embodiments, the stacked structures SS1 and SS2 can form a bipolar junction transistor (BJT). For example, the stacked structures SS1 and SS2 can form a PNP junction transistor, and they can also form an NPN junction transistor.

[0228] In some example embodiments, the stacked structures SS1 and SS2 may include a lower dummy pattern 410A and an upper dummy pattern 410B. For example, as Figure 13 As shown, the stacked structures SS1 and SS2 may include a lower dummy pattern 410A and two upper dummy patterns 410B. The lower dummy pattern 410A may be disposed between adjacent lower sheet structures 140A along the first direction (X direction), and the upper dummy patterns 410B may be disposed between adjacent upper sheet structures 140B along the first direction (X direction).

[0229] Both the lower dummy pattern 410A and the upper dummy pattern 410B may comprise semiconductor material. In some example embodiments, the lower dummy pattern 410A may be substantially undoped or doped with impurities at a lower concentration than that in the lower semiconductor pattern 150A. The upper dummy pattern 410B may be substantially undoped or doped with impurities at a lower concentration than that in the upper semiconductor pattern 150B. The lower dummy pattern 410A may not be electrically connected to the lower chip structure 140A. The lower dummy pattern 410A may be floating. The upper dummy pattern 410B may not be electrically connected to the upper chip structure 140B. The upper dummy pattern 410B may be floating.

[0230] Therefore, PN junction interfaces can be formed between the lower semiconductor pattern 150A, lower platen structure 140A, and first doped layer 320 of the first stacked structure SS1 with first type conductivity, and between the upper semiconductor pattern 150B, upper platen structure 140B, and second doped layer 310 of the first stacked structure SS1 with second type conductivity, and between the upper semiconductor pattern 150B, upper platen structure 140B, and second doped layer 310 of the second stacked structure SS2 with the lower semiconductor pattern 150A, lower platen structure 140A, and first doped layer 320 of the second stacked structure SS2 with first type conductivity. Therefore, the first stacked structure SS1 and the second stacked structure SS2 can form a PNP junction transistor.

[0231] However, the example embodiments are not limited thereto, and the first stacked structure SS1 and the second stacked structure SS2 can form NPN junction transistors based on the arrangement of the lower dummy pattern 410A and the upper dummy pattern 410B.

[0232] Figure 13A lower dummy pattern 410A and two upper dummy patterns 410B are shown, and the number of lower dummy patterns 410A and upper dummy patterns 410B is not limited thereto and can vary based on their design.

[0233] In the following text, see references Figures 14 to 21 This describes a method for manufacturing a semiconductor device according to some example embodiments.

[0234] Figures 14 to 21 This is a cross-sectional view showing an intermediate stage of a method for manufacturing a semiconductor device according to some example embodiments.

[0235] like Figure 14 As shown, a preliminary lower wafer structure 140AP, a preliminary intermediate insulating structure 220P, and a preliminary upper wafer structure 140BP can be formed in a first region AR1 of the substrate 101, and then a sacrificial gate structure 400 is formed thereon. Additionally, a lower sacrificial layer 220A, an upper sacrificial layer 220B, multiple lower channel patterns 240A, a preliminary intermediate insulating structure 220P, and multiple upper channel patterns 240B can be formed in a second region AR2 of the substrate 101, and then the sacrificial gate structure 400 can be formed thereafter.

[0236] The substrate 101 may be silicon-on-insulator (SOI) or bulk silicon. Alternatively, the substrate 101 may be a silicon substrate, or may include another material, such as silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the exemplary embodiments are not limited thereto.

[0237] In some example embodiments, substrate 101 may include a first region AR1 and a second region AR2. The second region AR2 may be disposed on one side of the first region AR1 along a first direction (X direction), but the example embodiments are not limited thereto. The first region AR1 may be formed as shown in the example. Figures 1 to 5 The stacked structure SS shown in the relevant example embodiment ( Figure 2 The second region AR2 can be formed as shown in the image. Figures 1 to 5 The transistor structure TS shown in the relevant example embodiment is... Figure 2 (The area in the middle).

[0238] First, the preliminary lower sheet structure 140AP, the preliminary intermediate insulating structure 220P, and the preliminary upper sheet structure 140BP can be sequentially formed in the first region AR1 of the substrate 101.

[0239] In detail, the initial under-chip structure 140AP can be formed by alternatingly forming a plurality of second initial under-semiconductor layers 142AP and a plurality of first initial under-semiconductor layers 145AP in a first region AR1 of the substrate 101. The plurality of second initial under-semiconductor layers 142AP can be formed of a semiconductor material having etch selectivity relative to the plurality of first initial under-semiconductor layers 145AP. As an example, the plurality of second initial under-semiconductor layers 142AP may include silicon germanium (SiGe), and the plurality of first initial under-semiconductor layers 145AP may include silicon (Si), but the example embodiment is not limited thereto.

[0240] A preliminary intermediate insulating structure 220P can be formed on the preliminary lower wafer structure 140AP. The preliminary intermediate insulating structure 220P can be formed from a semiconductor material that has etch selectivity relative to the preliminary lower wafer structure 140AP. As an example, the preliminary intermediate insulating structure 220P may include silicon germanium (SiGe), but the example embodiment is not limited thereto. Here, the germanium (Ge) content (at%) in the preliminary intermediate insulating structure 220P may differ from the germanium (Ge) content (at%) in the plurality of second preliminary lower semiconductor layers 142AP. Furthermore, the germanium (Ge) content (at%) in the preliminary intermediate insulating structure 220P may differ from the germanium (Ge) content (at%) in the lower sacrificial layer 220A and the upper sacrificial layer 220B.

[0241] The initial upper-layer structure 140BP can be formed by alternately forming a plurality of second initial upper-layer semiconductor layers 142BP and a plurality of first initial upper-layer semiconductor layers 145BP on the initial intermediate insulating structure 220P. The plurality of second initial upper-layer semiconductor layers 142BP can be formed of a semiconductor material that has etch selectivity relative to the plurality of first initial upper-layer semiconductor layers 145BP. As an example, the plurality of second initial upper-layer semiconductor layers 142BP may include silicon germanium (SiGe), and the plurality of first initial upper-layer semiconductor layers 145BP may include silicon (Si), but the example embodiment is not limited thereto.

[0242] Additionally, a lower sacrificial layer 220A, multiple lower channel patterns 240A, a preliminary intermediate insulating structure 220P, an upper sacrificial layer 220B, and multiple upper channel patterns 240B can be formed in the second region AR2 of the substrate 101.

[0243] The lower sacrificial layer 220A and the plurality of lower channel patterns 240A can be alternately stacked in the third direction (Z direction). In some example embodiments, the lower sacrificial layer 220A can be formed simultaneously with the plurality of second preliminary lower semiconductor layers 142AP in the same process. Therefore, the lower sacrificial layer 220A can be disposed on the same layer as the plurality of second preliminary lower semiconductor layers 142AP. The lower sacrificial layer 220A may include the same material as the plurality of second preliminary lower semiconductor layers 142AP. Additionally, the plurality of lower channel patterns 240A can be formed simultaneously with the plurality of first preliminary lower semiconductor layers 145AP in the same process. Therefore, the plurality of lower channel patterns 240A can be disposed on the same layer as the plurality of first preliminary lower semiconductor layers 145AP. The plurality of lower channel patterns 240A may include the same material as the plurality of first preliminary lower semiconductor layers 145AP.

[0244] The upper sacrificial layer 220B and the plurality of upper channel patterns 240B can be alternately stacked in the third direction (Z direction). In some example embodiments, the upper sacrificial layer 220B can be formed simultaneously with the plurality of second preliminary upper semiconductor layers 142BP in the same process. Therefore, the upper sacrificial layer 220B can be disposed on the same layer as the plurality of second preliminary upper semiconductor layers 142BP. The upper sacrificial layer 220B may include the same material as the plurality of second preliminary upper semiconductor layers 142BP. Additionally, the plurality of upper channel patterns 240B can be formed simultaneously with the plurality of first preliminary upper semiconductor layers 145BP in the same process. Therefore, the plurality of upper channel patterns 240B can be disposed on the same layer as the plurality of first preliminary upper semiconductor layers 145BP. The plurality of upper channel patterns 240B may include the same material as the plurality of first preliminary upper semiconductor layers 145BP.

[0245] The preliminary lower wafer structure 140AP, the preliminary upper wafer structure 140BP, the preliminary intermediate insulating structure 220P, the lower sacrificial layer 220A, the multiple lower channel patterns 240A, the upper sacrificial layer 220B, and the multiple upper channel patterns 240B formed in the first region AR1 of the substrate 101 can be formed by performing an epitaxial growth process using the substrate 101 as a seed crystal.

[0246] In some example embodiments, the number of multiple lower channel patterns 240A stacked alternately with the lower sacrificial layer 220A and the number of multiple upper channel patterns 240B stacked alternately with the upper sacrificial layer 220B may vary in the embodiments.

[0247] Next, an active pattern 111 can be formed by etching a preliminary lower wafer structure 140AP, a preliminary upper wafer structure 140BP, a preliminary intermediate insulating structure 220P, a lower sacrificial layer 220A, multiple lower channel patterns 240A, an upper sacrificial layer 220B, multiple upper channel patterns 240B, and a portion of the substrate 101. Then, a field insulating layer 105 can be formed. Figure 3 middle).

[0248] The active pattern 111 can be formed by removing at least a portion of the substrate 101. The active pattern 111 can extend in a first direction (X direction) and be spaced apart from each other in a second direction (Y direction).

[0249] Next, the sacrificial gate structure 400 can be formed in the first region AR1 and the second region AR2 of the substrate 101. For example, the sacrificial gate structure 400 can be formed on the initial upper chip structure 140BP and multiple upper channel patterns 240B.

[0250] The sacrificial gate structure 400 may include a first sacrificial gate electrode 402 and a second sacrificial gate electrode 405 sequentially disposed on a plurality of upper channel patterns 240B and a preliminary upper chip structure 140BP, as well as a preliminary capping layer 406. The first sacrificial gate electrode 402 may, for example, comprise silicon oxide (SiO2), but the example embodiment is not limited thereto. The second sacrificial gate electrode 405 may, for example, comprise polysilicon, but the example embodiment is not limited thereto. The preliminary capping layer 406 may, for example, comprise silicon nitride, but the example embodiment is not limited thereto. Additionally, spacers 164 may be formed on the side surfaces of the sacrificial gate structure 400.

[0251] like Figure 15 As shown, the sacrificial gate structure 400 can be used as a mask pattern in the etching process to etch the initial upper wafer structure 140BP, the initial intermediate insulating structure 220P, and the initial lower wafer structure 140AP to form the first recess 150R. Alternatively, the sacrificial gate structure 400 can be used as a mask to pattern the upper sacrificial layer 220B, multiple upper channel patterns 240B, the initial intermediate insulating structure 220P, the lower sacrificial layer 220A, and multiple lower channel patterns 240A to form the second recess 250R.

[0252] A first groove 150R may be disposed in a first region AR1 of substrate 101. The first groove 150R may extend through the preliminary upper wafer structure 140BP, the preliminary intermediate insulating structure 220P, and the preliminary lower wafer structure 140AP. In some example embodiments, the first groove 150R may have substantially the same lower and upper widths in a cross-section along a first direction-third direction (XZ direction), but the example embodiments are not limited thereto. For example, the first groove 150R may have a sloped side surface, the lower width of which is narrower than its upper width based on its aspect ratio. Here, the first groove 150R may indicate the region where the upper semiconductor pattern 150B and the lower semiconductor pattern 150A will be formed in a subsequent process.

[0253] A second groove 250R may be disposed in a second region AR2 of substrate 101. The second groove 250R may extend through the upper sacrificial layer 220B, multiple upper channel patterns 240B, preliminary intermediate insulating structure 220P, lower sacrificial layer 220A, and multiple lower channel patterns 240A. In some example embodiments, the second groove 250R may have substantially the same lower and upper widths in a cross-section along a first-third direction (XZ direction), but the example embodiments are not limited thereto. For example, the second groove 250R may have a sloped side surface, the lower width of which is narrower than its upper width based on its aspect ratio. Here, the second groove 250R may indicate the region where the upper source / drain patterns 250B and lower source / drain patterns are formed in subsequent processes.

[0254] like Figure 16 As shown, the lower semiconductor pattern 150A and the barrier structure 170 can be formed in the first groove 150R in the first region AR1 of the substrate 101. In addition, the lower source / drain pattern 250A and the barrier structure 170 can be formed in the second groove 250R in the second region AR2 of the substrate 101.

[0255] The lower semiconductor pattern 150A can be an epitaxial pattern formed by a selective epitaxial growth process using an active pattern 111 and a plurality of first preliminary lower semiconductor layers 145AP as seed crystals. Specifically, a first sub-lower pattern 151A can be formed along the inner wall and lower surface of the first groove 150R, and the lower semiconductor pattern 150A can be formed by forming a second sub-lower pattern 152A on the first sub-lower pattern 151A. The lower semiconductor pattern 150A can be in contact with the active pattern 111 and the plurality of first preliminary lower semiconductor layers 145AP. The upper surface of the lower semiconductor pattern 150A can be positioned at a distance substantially the same as the distance from the upper surface of the preliminary lower wafer structure 140AP to the upper surface of the substrate 101.

[0256] In some example embodiments, the lower semiconductor pattern 150A may have a first type of conductivity. The lower semiconductor pattern 150A may be doped with a first type of conductivity impurity. Here, the first type of conductivity may be P-type conductivity, but the example embodiments are not limited to this. For example, the lower semiconductor pattern 150A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiments are not limited to this.

[0257] The lower source / drain pattern 250A can be an epitaxial pattern formed by a selective epitaxial growth process using an active pattern 111 and multiple lower channel patterns 240A as seed crystals. Specifically, a first lower source / drain layer 251A can be formed along the inner wall and lower surface of the second groove 250R, and a second lower source / drain layer 252A can be formed to fill the second groove 250R on top of the first lower source / drain layer 251A. The lower source / drain pattern 250A can be in contact with the active pattern 111 and the multiple lower channel patterns 240A. The upper surface of the lower source / drain pattern 250A can be located at a distance substantially the same as the distance from the upper surface of the lower semiconductor pattern 150A to the upper surface of the substrate 101.

[0258] In some example embodiments, the lower source / drain pattern 250A may include the same semiconductor material as the lower semiconductor pattern 150A. As an example, the lower source / drain pattern 250A and the lower semiconductor pattern 150A may include silicon (Si) or silicon germanium (SiGe), but the example embodiments are not limited thereto.

[0259] In some example embodiments, the lower source / drain pattern 250A may have a first type of conductivity. The lower semiconductor pattern 150A may be doped with a first type of conductive impurity. Here, the first type of conductivity may be P-type conductivity, but the example embodiments are not limited thereto. For example, the lower source / drain pattern 250A may include boron (B), vanadium (V), indium (In), gallium (Ga), aluminum (Al), or combinations thereof. However, the example embodiments are not limited thereto.

[0260] A barrier structure 170 may be formed on a lower semiconductor pattern 150A and a lower source / drain pattern 250A. The barrier structure 170 may include a first liner 171 extending along a side surface of the initial intermediate insulating structure 220P and an upper surface of the lower semiconductor pattern 150A, and a barrier pattern 172 disposed on the first liner 171. The first liner 171 may be disposed on the upper surface of the lower source / drain pattern 250A. The first liner 171 and the barrier pattern 172 may include various insulating materials. The first liner 171 and the barrier pattern 172 may include different materials, but the exemplary embodiments are not limited thereto. For example, the first liner 171 may include silicon nitride, silicon oxynitride, or a combination thereof, and the barrier pattern 172 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the exemplary embodiments are not limited thereto.

[0261] like Figure 17 As shown, the upper semiconductor pattern 150B can be formed on the barrier structure 170 in the first region AR1 of the substrate 101, and the upper source / drain pattern 250B can be formed on the barrier structure 170 in the second region AR2 of the substrate.

[0262] The upper semiconductor pattern 150B can be an epitaxial pattern formed by a selective epitaxial growth process using multiple first preliminary upper semiconductor layers 145BP as seed crystals. Specifically, a first sub-upper pattern 151B can be formed on the side surfaces of the multiple first preliminary upper semiconductor layers 145BP, and the upper semiconductor pattern 150B can be formed by forming a second sub-upper pattern 152B on the first sub-upper pattern 151B. The upper surface of the upper semiconductor pattern 150B can be located at a distance substantially the same as the distance from the upper surface of the substrate 101 to the upper surface of the preliminary upper wafer structure 140BP.

[0263] In some example embodiments, the upper semiconductor pattern 150B may include a semiconductor material. The upper semiconductor pattern 150B may have a second type of conductivity. The upper semiconductor pattern 150B may be doped with a second type of conductive impurity. Here, the second type of conductivity may be N-type conductivity, but the example embodiments are not limited thereto. For example, the upper semiconductor pattern 150B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiments are not limited thereto.

[0264] The upper source / drain pattern 250B can be an epitaxial pattern formed by a selective epitaxial growth process using multiple upper channel patterns 240B as seed crystals. Specifically, a first upper source / drain layer 251B can be formed along the side surfaces of the multiple upper channel patterns 240B, and a second upper source / drain layer 252B can be formed to fill the second groove 250R on top of the first upper source / drain layer 251B. The upper source / drain pattern 250B can be in contact with the multiple upper channel patterns 240B. The upper surface of the lower source / drain pattern 250A can be located at a distance substantially the same as the distance from the upper surface of the lower semiconductor pattern 150A to the upper surface of the substrate 101.

[0265] In some example embodiments, the upper source / drain pattern 250B may include the same semiconductor material as the upper semiconductor pattern 150B. As an example, the upper source / drain pattern 250B and the upper semiconductor pattern 150B may include silicon (Si) or silicon germanium (SiGe), but the example embodiments are not limited thereto.

[0266] In some example embodiments, the source / drain pattern 250B may include a semiconductor material. The source / drain pattern 250B may have a second type of conductivity. The source / drain pattern 250B may be doped with a second type of conductive impurity. Here, the second type of conductivity may be N-type conductivity, but the example embodiments are not limited thereto. For example, the source / drain pattern 250B may include phosphorus (P), antimony (Sb), arsenic (As), or combinations thereof. However, the example embodiments are not limited thereto.

[0267] like Figure 18 As shown, in the first region AR1 of substrate 101, impurities in the lower semiconductor pattern 150A and the upper semiconductor pattern 150B can diffuse into their surrounding environment through a thermal processing process.

[0268] Specifically, the lower semiconductor pattern 150A can be formed by diffusing a first type of conductive impurity present in it into the preliminary lower semiconductor structure 140AP through a thermal processing process. For example, the first type of conductive impurity can be diffused into a plurality of first preliminary lower semiconductor layers 145AP and a plurality of second preliminary lower semiconductor layers 142AP. Here, the doping concentration of each of the impurities in the plurality of first preliminary lower semiconductor layers 145AP and the plurality of second preliminary lower semiconductor layers 142AP can be less than or substantially equal to the doping concentration of the impurities in the lower semiconductor pattern 150A.

[0269] Alternatively, a first doped layer 320 can be formed by diffusing first-type conductive impurities present in the lower semiconductor pattern 150A into a portion of the preliminary intermediate insulating structure 220P through a heat treatment process. The first doped layer 320 can be formed as a part of the preliminary intermediate insulating structure 220P. Furthermore, the doping concentration of the impurities in the first doped layer 320 can be less than or substantially equal to the doping concentration of the impurities in the lower semiconductor pattern 150A.

[0270] Alternatively, the upper semiconductor pattern 150B can be formed by diffusing second-type conductive impurities present in the upper semiconductor pattern 150B into the preliminary upper semiconductor structure 140BP through a heat treatment process. For example, the second-type conductive impurities can be diffused into multiple first preliminary upper semiconductor layers 145BP and multiple second preliminary upper semiconductor layers 142BP. Here, the doping concentration of the impurities in the multiple first preliminary upper semiconductor layers 145BP and the multiple second preliminary upper semiconductor layers 142BP can be less than or substantially equal to the doping concentration of the impurities in the upper semiconductor pattern 150B.

[0271] Alternatively, a second doped layer 310 can be formed by diffusing second-type conductive impurities present in the upper semiconductor pattern 150B into a portion of the preliminary intermediate insulating structure 220P through a heat treatment process. The second doped layer 310 can be formed as a part of the preliminary intermediate insulating structure 220P. Here, the doping concentration of the impurities in the second doped layer 310 can be less than or substantially equal to the doping concentration of the impurities in the upper semiconductor pattern 150B.

[0272] In some example embodiments, the PN junction interface 300_J can be formed by forming a first doped layer 320 and a second doped layer 310. In some example embodiments, the first doped layer 320 and the second doped layer 310 can form the PN junction interface 300_J. Figure 5 (middle). PN junction interface 300_J ( Figure 5 The PN junction interface 300 can be defined as the interface between the upper surface of the first doped layer 320 and the lower surface of the second doped layer 310. The upper surface of the first doped layer 320 may have a shape complementary to the lower surface of the second doped layer 310. Figure 5 The cross-section in the first direction – the third direction (XZ direction) can be flat, but the example embodiment is not limited to this. As another example, as with Figure 6 As shown in the relevant example embodiments, the PN junction interface 300_J ( Figure 5 (The middle) can be recessed toward the upper surface of the lower sheet structure 140A. As another example, as with Figure 7 As shown in the relevant example embodiments, the PN junction interface 300_J ( Figure 5 (The middle) can protrude toward the upper surface of the upper sheet structure 140B.

[0273] like Figure 19 As shown, an interlayer insulating layer 195 is first formed on the upper source / drain pattern 250B and the upper semiconductor pattern 150B. Next, the upper gate trench UR can be formed by removing the sacrificial gate structure 400 from the first region AR1 and the second region AR2 of the substrate 101.

[0274] Next, the preliminary intermediate insulating structure 220P can be removed from the second region AR2 of the substrate 101, and then an intermediate insulating structure 220 is formed in the removed region. The intermediate insulating structure 220 may include various insulating materials. For example, the intermediate insulating structure 220 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. However, the example embodiment is not limited thereto. The intermediate insulating structure 220 may allow a plurality of lower channel patterns 240A and a plurality of upper channel patterns 240B to be spaced apart from each other.

[0275] Next, by removing the upper sacrificial layer 220B and the lower sacrificial layer 220A, a lower gate trench LR can be formed between the plurality of channel patterns 240. In some example embodiments, the lower gate trench LR is described as being formed after the intermediate insulating structure 220 is formed, but the example embodiments are not limited thereto. As another example, the intermediate insulating structure 220 can be formed after the lower gate trench LR is formed and gate structures 260A, 260B, and 260M are formed in the lower gate trench LR. In some example embodiments, the processes of removing the sacrificial gate structure 400, the upper sacrificial layer 220B, and the lower sacrificial layer 220A can be performed simultaneously.

[0276] like Figure 20 As shown, gate insulating films 262A and 262B can be formed in the lower gate trench LR, and dummy main gate insulating films 162M and 262M can be formed in the upper gate trench UR. Then, gate electrodes 265A and 265B and dummy main gate electrodes 165M and 265M can be formed, and a capping layer 166 can be formed on the dummy main gate electrodes 165M and 265M.

[0277] like Figure 21 As shown, the upper contact structure 180 can be formed by passing through the interlayer insulating layer 195, the base insulating layer 100 can be formed by removing the substrate 101 and the active pattern 111, and then the lower contact structure 190 can be formed by passing through the base insulating layer 100.

[0278] A contact hole can first be formed through the interlayer insulating layer 195 to expose the upper source / drain pattern 250B and the upper semiconductor pattern 150B, and then an upper contact structure 180 can be formed to fill the contact hole. For example, a first upper contact structure 180_1 can be electrically connected to the upper semiconductor pattern 150B through the interlayer insulating layer 195, and a second upper contact structure 180_2 can be electrically connected to the upper source / drain pattern 250B through the interlayer insulating layer 195. The upper contact structure 180 may include an upper contact electrode 186 and an upper silicide film 182 disposed between the upper contact electrode 186 and the upper semiconductor pattern 150B.

[0279] Next, the substrate 101 and the active pattern 111 can be removed, and the substrate insulating layer 100 and the protruding pattern 110 can be formed in the removal space.

[0280] The substrate insulating layer 100 may be an insulating substrate. The substrate insulating layer 100 may include oxides, nitrides, oxynitrides, or combinations thereof. However, the exemplary embodiments are not limited thereto. For example, the substrate insulating layer 100 may include silicon oxide (SiO2). The substrate insulating layer 100 is shown as a monolayer film only for ease of description, but the exemplary embodiments are not limited thereto. The substrate insulating layer 100 may be formed by removing the substrate 101 and filling the removed portion of the substrate 101 with an insulating material. The protruding pattern 110 may be formed by removing the active pattern 111 and filling the removed portion of the active pattern 111 with an insulating material.

[0281] Finally, the lower contact structure 190 can be formed by passing through the substrate insulating layer 100 and the protruding pattern 110.

[0282] Contact holes can be formed through the substrate insulating layer 100 and the protruding pattern 110 to expose the lower source / drain pattern 250A and the lower semiconductor pattern 150A, and then a lower contact structure 190 can be formed to fill the contact holes. For example, a first lower contact structure 190-1 can be electrically connected to the lower semiconductor pattern 150A through the substrate insulating layer 100 and the protruding pattern 110, and a second lower contact structure 190-2 can be electrically connected to the lower source / drain pattern 250A through the substrate insulating layer 100 and the protruding pattern 110. The lower contact structure 190 may include a lower contact electrode 196 and a lower silicide film 192 disposed between the lower contact electrode 196 and the lower semiconductor pattern 150A.

[0283] Therefore, a stacked structure SS and a transistor structure TS of semiconductor devices can be formed according to some example embodiments.

[0284] In the following text, see references Figures 22 to 24 This describes a method for manufacturing a semiconductor device according to some example embodiments.

[0285] Figures 22 to 24 This is a cross-sectional view showing an intermediate stage of a method for manufacturing a semiconductor device according to some example embodiments.

[0286] like Figure 22 As shown, the initial lower sheet structure 140AP and the initial intermediate insulating structure 220P can be formed in the first region AR1 of the substrate 101. In addition, the lower sacrificial layer 220A, the plurality of lower channel patterns 240A and the initial intermediate insulating structure 220P can be formed in the second region AR2 of the substrate 101.

[0287] In some example embodiments, substrate 101 may include a first region AR1 and a second region AR2. The second region AR2 may be disposed on one side of the first region AR1 along a first direction (X direction), but the example embodiments are not limited thereto. The first region AR1 may be formed as shown in the example. Figures 1 to 5 The stacked structure SS shown in the relevant example embodiment ( Figure 2 The second region AR2 can be formed as shown in the image. Figures 1 to 5 The transistor structure TS shown in the relevant example embodiment is... Figure 2 (The area in the middle).

[0288] The process of forming a preliminary lower wafer structure 140AP and a preliminary intermediate insulating structure 220P in the first region AR1 of substrate 101, and the process of forming a lower sacrificial layer 220A, multiple lower channel patterns 240A, and a preliminary intermediate insulating structure 220P in the second region AR2 of substrate 101 are as follows: Figures 14 to 21 The processes described in the illustrated embodiments are essentially the same, so their description is omitted.

[0289] In some example embodiments, the preliminary intermediate insulating structure 220P may include a semiconductor material. As an example, the preliminary intermediate insulating structure 220P may include silicon germanium (SiGe). Here, the germanium (Ge) content (at%) in the preliminary intermediate insulating structure 220P may differ from the germanium (Ge) content (at%) in the plurality of second preliminary lower semiconductor layers 142AP, but the example embodiments are not limited thereto.

[0290] like Figure 23As shown, in some example embodiments, semiconductor material can be implanted into a portion of the preliminary intermediate insulating structure 220P disposed in a first region AR1 of the substrate 101. An ion implantation process can be used to perform the process of implanting semiconductor material into the portion of the preliminary intermediate insulating structure 220P disposed in the first region AR1 of the substrate 101. For example, germanium (Ge) can be implanted into the portion of the preliminary intermediate insulating structure 220P disposed in the first region AR1 of the substrate 101. Therefore, the germanium (Ge) content (at%) in the first preliminary intermediate insulating structure 220P_2 disposed in the first region AR1 of the substrate 101 can be greater than the germanium (Ge) content (at%) in the second preliminary intermediate insulating structure 220P_1 disposed in the second region AR2 of the substrate 101.

[0291] In subsequent processes, the PN junction structure 300 can be formed by injecting impurities into the first preliminary intermediate insulation structure 220P. In some example embodiments, the process of injecting impurities into the first preliminary intermediate insulation structure 220P can be performed separately, thereby easily forming a PN junction structure 300 with a germanium (Ge) content (at%) different from that in the second preliminary intermediate insulation structure 220P.

[0292] like Figure 24 As shown, a preliminary upper sheet structure 140BP can be formed on the first preliminary intermediate insulation structure 220P, and an upper sacrificial layer 220B and a plurality of upper channel patterns 240B can be formed on the second preliminary intermediate insulation structure 220P. Next, [the process] can be performed with... Figures 15 to 21 The processes shown in the related example embodiments are the same as those used to form semiconductor devices according to some example embodiments.

[0293] Although exemplary embodiments of this disclosure have been described in detail above, the scope of this disclosure is not limited thereto. That is, various modifications and alterations made by those skilled in the art using the basic concept of this disclosure as defined in the appended claims also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: The lower-layer structure includes multiple alternating stacked first lower semiconductor layers and multiple second lower semiconductor layers; The upper sheet structure includes a plurality of first upper semiconductor layers and a plurality of second upper semiconductor layers alternately stacked on the lower sheet structure; A lower semiconductor pattern is present on at least one side of the lower wafer structure; A semiconductor pattern is present on at least one side of the upper sheet structure; as well as A PN junction structure is located between the lower wafer structure and the upper wafer structure, and the PN junction structure comprises P-type semiconductor material and N-type semiconductor material. The PN junction structure includes: A first doped layer is disposed on the lower sheet structure and has a first type of conductivity; and A second doped layer is placed on the first doped layer and has a second type of conductivity.

2. The semiconductor device according to claim 1, wherein, The lower semiconductor pattern and the lower sheet structure have the same conductivity, and The upper semiconductor pattern and the upper sheet structure have the same conductivity.

3. The semiconductor device according to claim 2, wherein, The lower sheet-like structure has the first type of conductivity, and The upper sheet-like structure has the second type of conductivity.

4. The semiconductor device according to claim 3, wherein, The doping concentration of the first type of conductive impurity in the first doped layer is less than or equal to the doping concentration of the first type of conductive impurity in the lower semiconductor pattern.

5. The semiconductor device according to claim 3, wherein, The doping concentration of the first type of conductive impurity in the first doped layer is less than or equal to the doping concentration of the first type of conductive impurity in the lower sheet structure.

6. The semiconductor device according to claim 3, wherein, The plurality of first lower semiconductor layers and the plurality of second lower semiconductor layers each have the first type of conductivity, and The doping concentration of the first type of conductive impurity in the plurality of first lower semiconductor layers is less than or equal to the doping concentration of the first type of conductive impurity in the plurality of second lower semiconductor layers.

7. The semiconductor device according to claim 1, wherein, The first type of conductive impurity in the first doped layer has 10 17 cm -3 Up to 10 19 cm -3 The doping concentration.

8. The semiconductor device according to claim 1, wherein, Each of the plurality of first lower semiconductor layers and the plurality of first upper semiconductor layers comprises silicon, and Each of the plurality of second lower semiconductor layers and the plurality of second upper semiconductor layers comprises silicon germanium.

9. The semiconductor device according to claim 8, wherein, The PN junction structure includes silicon and germanium, and The germanium content (at%) in the PN junction structure is different from the germanium content (at%) in the plurality of second upper semiconductor layers.

10. The semiconductor device according to claim 1, wherein, At least a portion of the second doped layer overlaps with the upper semiconductor pattern in a first direction parallel to the upper surface of the lower sheet structure.

11. The semiconductor device according to claim 1, wherein, The upper surface of the first doped layer is closer to the upper surface of the lower sheet structure than the lower surface of the upper sheet structure.

12. The semiconductor device according to claim 1, further comprising: The dummy main gate structure on the upper plate structure, The dummy main gate structure covers the side surface of the upper sheet structure, the side surface of the lower sheet structure, and the side surface of the PN junction structure.

13. The semiconductor device according to claim 1, further comprising: A barrier structure is located between the lower semiconductor pattern and the upper semiconductor pattern. Wherein, at least a portion of the blocking structure overlaps with the PN junction structure in a first direction parallel to the upper surface of the lower sheet structure.

14. The semiconductor device according to claim 13, wherein, The height of the upper surface of the first doped layer in the vertical direction is closer to the height of the upper surface of the lower sheet structure in the vertical direction than the height of the upper surface of the barrier structure in the vertical direction. The vertical direction is perpendicular to the upper surface of the lower sheet-like structure.

15. The semiconductor device according to claim 13, wherein, The thickness of the PN junction structure is greater than the thickness of the barrier structure.

16. A semiconductor device, comprising: The lower sheet structure has a first type of conductivity and includes a plurality of alternatingly stacked first lower semiconductor layers and a plurality of second lower semiconductor layers; The upper sheet structure has a second type of conductivity and includes a plurality of first upper semiconductor layers and a plurality of second upper semiconductor layers alternately stacked on the lower sheet structure; A lower semiconductor pattern is present on at least one side of the lower wafer structure; as well as A PN junction structure is provided between the plurality of first lower semiconductor layers and the plurality of first upper semiconductor layers. The PN junction structure includes a P-type semiconductor material, an N-type semiconductor material, and a material identical to at least one of the plurality of second lower semiconductor layers and the plurality of second upper semiconductor layers. The PN junction structure includes: A first doped layer is disposed on the lower sheet structure and has the first type of conductivity; and A second doped layer is located between the first doped layer and the upper sheet structure and has the second type of conductivity.

17. The semiconductor device according to claim 16, wherein, The doping concentration of the first type of conductive impurity in the first doped layer is less than or equal to the doping concentration of the first type of conductive impurity in the lower sheet structure, and The doping concentration of the second type of conductive impurity in the second doped layer is less than or equal to the doping concentration of the second type of conductive impurity in the upper sheet structure.

18. The semiconductor device according to claim 17, wherein, The doping concentration of the first type of conductive impurity in the plurality of first lower semiconductor layers is less than or equal to the doping concentration of the first type of conductive impurity in the plurality of second lower semiconductor layers, and The doping concentration of the second type of conductive impurity in the plurality of first upper semiconductor layers is less than or equal to the doping concentration of the second type of conductive impurity in the plurality of second upper semiconductor layers.

19. The semiconductor device according to claim 17, wherein, The doping concentration of the first type of conductive impurity in the lower sheet structure is less than or equal to the doping concentration of the first type of conductive impurity in the lower semiconductor pattern.

20. A semiconductor device, comprising: Substrate insulation layer; The lower-layer structure includes a plurality of first lower semiconductor layers and a plurality of second lower semiconductor layers alternately stacked on the substrate insulating layer; The upper sheet structure includes a plurality of first upper semiconductor layers and a plurality of second upper semiconductor layers alternately stacked on the lower sheet structure; A lower semiconductor pattern is located on at least one side of the lower sheet structure and has a first type of conductivity; The semiconductor pattern is on at least one side of the upper sheet structure and has a second type of conductivity; A blocking structure is located between the lower semiconductor pattern and the upper semiconductor pattern; as well as A PN junction structure is provided between the lower and upper wafer structures and overlaps with the barrier structure in a first direction parallel to the upper surface of the substrate insulating layer. The PN junction structure comprises P-type and N-type semiconductor materials. The PN junction structure includes: A first doped layer is disposed on the lower sheet structure and has the first type of conductivity; and A second doped layer, on top of the first doped layer, having the second type of conductivity, and The doping concentration of the first type of conductive impurity in the first doped layer is less than or equal to the doping concentration of the first type of conductive impurity in the lower semiconductor pattern.

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