Semiconductor device structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device structure and a forming method thereof. In one embodiment, a structure includes a source / drain region, a contact etch stop layer disposed over the source / drain region, a first interlayer dielectric (ILD) layer disposed over the contact etch stop layer, an etch stop layer disposed over the contact etch stop layer and the first ILD layer, a second ILD layer disposed over the etch stop layer, a substrate portion disposed under the source / drain region; and an isolation region disposed adjacent to the substrate portion. The isolation region includes: a first dielectric layer including a first dielectric material; and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer includes a second dielectric material different from the first dielectric material. The isolation region further includes a hard mask structure disposed on the first dielectric layer and the second dielectric layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor device structure, including: a source / drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; a contact etch stop layer disposed above the source / drain region; a first interlayer dielectric layer disposed above the contact etch stop layer; and an etch stop layer disposed above the contact etch stop layer. The first interlayer dielectric layer is located above the top surface and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a substrate portion is disposed below the source / drain region; and an isolation region is disposed adjacent to the substrate portion, wherein the isolation region includes: a first dielectric layer comprising a first dielectric material; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material different from the first dielectric material; and a hard mask structure disposed on the first dielectric layer and the second dielectric layer.

[0005] Some other embodiments of this application provide a semiconductor device structure, including: a first source / drain region, comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region, disposed adjacent to the first source / drain region; a gate electrode layer, disposed adjacent to the first source / drain region and the second source / drain region; a contact etch stop layer, disposed above the first source / drain region and the second source / drain region; a first interlayer dielectric (ILD) layer, disposed above the contact etch stop layer; and an etch stop layer. An etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a first substrate portion is disposed below the first source / drain region; a second substrate portion is disposed below the second source / drain region; and an isolation region is disposed between the first substrate portion and the second substrate portion, wherein the isolation region includes a first dielectric layer and a hard mask structure disposed above the first dielectric layer, the hard mask structure including a first portion and a second portion, wherein the contact etch stop layer extends through the first portion of the hard mask structure, and the gate electrode layer is disposed above the second portion of the hard mask structure.

[0006] Further embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a fin structure over a substrate, wherein the fin structure includes a substrate portion and a first protective layer located over the substrate portion; forming an isolation region adjacent to the substrate portion, comprising: depositing a first dielectric layer around the fin structure; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; recessing the first dielectric layer to expose the sidewalls of the first protective layer; removing the first protective layer; recessing the first dielectric layer and the third dielectric layer; and recessing the first dielectric layer and the second dielectric layer; and forming a source / drain region over the substrate portion, wherein the source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 and Figure 2 These are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0010] Figure 12 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0011] Figure 13 , Figure 14 and Figure 15 It is according to some embodiments the various stages of manufacturing semiconductor device structures along Figure 12 The side view of the section cut by line AA.

[0012] Figure 16 and Figure 17 It is according to some embodiments the various stages of manufacturing semiconductor device structures along Figure 12 The side view of the cross section cut by line BB.

[0013] Figure 18 and Figure 19 It is according to some embodiments the various stages of manufacturing semiconductor device structures along Figure 12 The side view of the cross section cut by line CC.

[0014] Figure 20 This is one of the various stages in the manufacturing of a semiconductor device structure according to some embodiments. Figure 12 The side view of the section cut by line AA.

[0015] Figure 21A and Figure 21B These are, respectively, one of the various stages in the manufacturing of a semiconductor device structure according to an optional embodiment. Figure 12 The side view of the cross section cut by lines BB and CC.

[0016] Figure 22Aand Figure 22B These are, respectively, one of the various stages in the manufacturing of a semiconductor device structure according to an optional embodiment. Figure 12 The side view of the cross section cut by lines BB and CC.

[0017] Figure 23A and Figure 23B These are, respectively, one of the various stages in the manufacturing of a semiconductor device structure according to an optional embodiment. Figure 12 The side view of the cross section cut by lines BB and CC. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “on,” “top,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] While embodiments of this disclosure are discussed with respect to nanostructured channel FETs, such as gate-all-around (GAA) FETs, such as horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs, implementations of some aspects of the embodiments of this disclosure can be used in other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications are contemplated within the scope of the embodiments of this disclosure. In the case of a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0021] Figures 1 to 20 An exemplary process for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure is shown. It should be understood that... Figures 1 to 20 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and may be interchanged.

[0022] Figure 1 and Figure 2 These are perspective views of various stages in the fabrication of a semiconductor device structure 100 according to some embodiments. For example... Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony phosphide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0023] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field-effect transistors (NFETs) and boron for p-type field-effect transistors (PFETs).

[0024] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Optionally, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0025] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be carried out by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0026] The first semiconductor layer 106, or portions thereof, may form nanostructured channels of the semiconductor device structure 100 in a later manufacturing stage. The term nanostructure is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructured channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0027] Each first semiconductor layer 106 may have a thickness in the range of about 3 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range of about 2 nm to about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged as follows... Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the scope beyond what is specifically enumerated in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels for the semiconductor device structure 100. Figure 1 As shown, a nitride layer 110 is formed on the topmost first semiconductor layer 106, and an oxide layer 111 is formed on the nitride layer 110. The nitride layer 110 may be silicon nitride and may have different etch selectivity compared to the oxide layer 111. The oxide layer 111 may include any suitable nitride material, such as silicon oxide. In some embodiments, the nitride layer 110 and the oxide layer 111 may be a mask structure. The nitride layer 110 may be a protective layer to protect the semiconductor layer stack 104 located beneath it.

[0028] exist Figure 2 In this embodiment, fin structures 112 are formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (such as a nitride layer 110 and an oxide layer 111) formed on the semiconductor layer stack 104 using multiple patterning operations including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include: forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element can be implemented using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in unprotected areas that penetrate the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving multiple extending fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0029] Figure 3 , Figure 4 , Figure 5, Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional side view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 3 yes Figure 2 A cross-sectional side view of the semiconductor device structure 100 shown. Next, as... Figure 4 As shown, oxide layer 111 is removed, and an optional pad 113 is formed on fin structure 112 and substrate 101. Oxide layer 111 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. The etching process for removing oxide layer 111 can be a selective etching process that substantially does not affect nitride layer 110 and semiconductor layer stack 104. Pad 113 can comprise a semiconductor material, such as silicon, for example, amorphous silicon. Pad 113 can be used to protect semiconductor layer stack 104 from oxidation. In some embodiments, pad 113 is a conformal layer and is formed by a conformal process, such as atomic layer deposition (ALD). In some embodiments, pad 113 is optional and absent.

[0030] exist Figure 5 In this embodiment, a first dielectric layer 115 is deposited on a pad 113, a second dielectric layer 117 is deposited on the first dielectric layer 115, and a third dielectric layer 118 is deposited on the second dielectric layer 117. In embodiments where the pad 113 is absent, the first dielectric layer 115 is deposited around the fin structure 112. In some embodiments, the first dielectric layer 115 is an oxide layer, the second dielectric layer 117 is a nitrogen-containing or carbon-containing layer, and the third dielectric layer 118 is an oxide layer. In some embodiments, the first dielectric layer 115 comprises SiO2. x The first dielectric layer 115 has a thickness ranging from about 0.5 nm to about 5 nm. The first dielectric layer 115 can be deposited by any suitable process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or ALD. In some embodiments, the first dielectric layer 115 is a conformal layer formed by ALD.

[0031] The second dielectric layer 117 comprises SiN, SiCN, SiOC, SiOCN, SiC, or other suitable nitrogen- or carbon-containing materials. In some embodiments, the material of the second dielectric layer 117 differs from that of the first dielectric layer 115. For example, the k-value of the second dielectric layer 117 may be greater than the k-value of the first dielectric layer 115. The second dielectric layer 117 may serve as a protective layer during subsequent processes. In some embodiments, the second dielectric layer 117 ensures that the sides of the substrate portion 116 are not exposed by protecting the first dielectric layer 115 during subsequent processes. However, if the second dielectric layer 117 is deposited directly on a semiconductor material (such as the substrate portion 116 or pad 113), fixed charges may be generated at the interface between the substrate portion 116 or pad 113 and the second dielectric layer 117. Fixed charges formed at the interface between the substrate portion 116 or pad 113 and the second dielectric layer 117 may cause current leakage. Therefore, in some embodiments, a first dielectric layer 115 is deposited between a substrate portion 116 and a second dielectric layer 117 to prevent the generation of fixed charges, such as Figure 5 As shown in the diagram. In some embodiments, if the thickness of the first dielectric layer 115 is less than about 0.5 nm, the fixed charge may still form between the second dielectric layer 117 and the substrate portion 116. On the other hand, if the thickness of the first dielectric layer 115 is greater than about 5 nm, the first dielectric layer 115 can be etched to expose the sides of the substrate portion 116 during subsequent processes. In some embodiments, the thickness of the second dielectric layer 117 is in the range of about 0.5 nm to about 10 nm. If the thickness of the second dielectric layer 117 is less than about 0.5 nm, the second dielectric layer 117 is not thick enough to protect the first dielectric layer 115. On the other hand, if the thickness of the second dielectric layer 117 is greater than about 10 nm, the capacitance will increase due to the high k value of the second dielectric layer 117. The second dielectric layer 117 can be formed by any suitable process, such as CVD, PECVD, or ALD. In some embodiments, the second dielectric layer 117 is a conformal layer formed by ALD, such as... Figure 5 As shown in the image.

[0032] like Figure 5As shown, a third dielectric layer 118 is deposited on the second dielectric layer 117 and fills the trench 114 between adjacent fin structures 112. The third dielectric layer 118 can be made of silicon oxide, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. In some embodiments, the third dielectric layer 118 comprises the same material as the first dielectric layer 115. The third dielectric layer 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), PECVD, or flowable CVD (FCVD). The third dielectric layer 118 has a lower k-value compared to the second dielectric layer 117. Therefore, if the third dielectric layer 118 is made of the same material as the second dielectric layer 117, the capacitance will be too high.

[0033] like Figure 6 As shown, planarization operations, such as chemical mechanical polishing (CMP) and / or etching-back methods, are performed to expose the top of the fin structure 112. In some embodiments, the planarization process removes portions of the third dielectric layer 118, the second dielectric layer 117, the first dielectric layer 115, and the pad 113 above the nitride layer 110. In some embodiments, the nitride layer 110 serves as a CMP stop layer during the CMP process. The nitride layer 110 protects the topmost first semiconductor layer 106 during the planarization process.

[0034] like Figure 7 As shown, the first dielectric layer 115 and the third dielectric layer 118 are recessed, and the sides of the nitride layer 110 are exposed. In some embodiments, the recessing of the first dielectric layer 115 and the third dielectric layer 118 is performed by a selective etching process, such as a selective dry etching process. The selective dry etching process recesses the first dielectric layer 115 and the third dielectric layer 118 until the sides of the nitride layer 110 are exposed. Due to the selective dry etching process, portions of the second dielectric layer 117 may also be exposed. The selective etching process substantially does not affect the nitride layer 110 and the second dielectric layer 117. The next step, as... Figure 8 As shown, exposed portions of the second dielectric layer 117 and the nitride layer 110 are removed. In some embodiments, a wet etching process is performed to remove the exposed portions of the second dielectric layer 117 and the nitride layer 110. For example, an H3PO4 solution is used in the wet etching process to remove the exposed portions of the second dielectric layer 117 and the nitride layer 110. The wet etching process can be a selective process that substantially does not affect the materials of the first dielectric layer 115, the third dielectric layer 118, and the first semiconductor layer 106.

[0035] like Figure 9As shown, the first dielectric layer 115 and the third dielectric layer 118 are further recessed. In some embodiments, a selective dry etching process may be performed to recess the first dielectric layer 115 and the third dielectric layer 118. The selective dry etching process may be... Figure 7 The same selective dry etching process described in [the document], except that... Figure 7 Compared to the selective dry etching process described herein, the selective dry etching process has a longer execution time. In some embodiments, the heights of the first dielectric layer 115 and the third dielectric layer 118 differ due to loading effects. The height of the first dielectric layer 115 may be substantially greater than the height of the third dielectric layer 118, such as... Figure 9 As shown in the image. The next step, as... Figure 10 As shown, portions of the first dielectric layer 115 and the second dielectric layer 117 disposed along the sidewalls of the fin structure 112 are removed. In some embodiments, a first wet etching process may be performed to remove portions of the second dielectric layer 117, and the wet etching process may utilize an H3PO4 solution to remove portions of the second dielectric layer 117. Then, a selective dry etching process is performed to remove portions of the first dielectric layer 115. The selective dry etching process may also cause the third dielectric layer 118 to be recessed, such as... Figure 10 As shown in the diagram. In some embodiments, the resulting first dielectric layer 115, second dielectric layer 117, and third dielectric layer 118 have substantially coplanar top surfaces. In some embodiments, a vertical distance D1 is located between the coplanar top surfaces of the first dielectric layer 115, second dielectric layer 117, and third dielectric layer 118 and the bottom surface of the bottommost second semiconductor layer 108, as shown in the diagram. Figure 10 As shown in the figure. The distance D1 can range from about 8 nm to about 20 nm.

[0036] In some embodiments, such as Figure 10 As shown, the top surfaces of the first dielectric layer 115, the second dielectric layer 117, and the third dielectric layer 118 are substantially flat. In some embodiments, the top surfaces of the first dielectric layer 115, the second dielectric layer 117, and the third dielectric layer 118 are curved. Figure 23B This is because Figure 9 and Figure 10 The document describes several etching processes.

[0037] like Figure 11As shown, a hard mask structure 124 is formed on a first dielectric layer 115, a second dielectric layer 117, and a third dielectric layer 118. In some embodiments, the hard mask structure 124 has the same height as the distance D1. The hard mask structure 124 may include an oxide layer 123 and a protective layer 125. In some embodiments, the oxide layer 123 comprises the same material as the first dielectric layer 115, and the protective layer 125 comprises the same material as the second dielectric layer 117. Similar to the first dielectric layer 115 and the second dielectric layer 117, the oxide layer 123 is disposed between the protective layer 125 and the substrate portion 116 or pad 113 to prevent the generation of fixed charges. In some embodiments, the oxide layer 123 has a thickness ranging from about 0.5 nm to about 3 nm. In some embodiments, if the thickness of the oxide layer 123 is less than about 0.5 nm, fixed charges may still form at the interface between the protective layer 125 and the oxide layer 123. On the other hand, if the thickness of oxide layer 123 is greater than about 3 nm, oxide layer 123 can be etched to expose the sides of substrate portion 116 during subsequent processes. In some embodiments, the thickness of protective layer 125 is in the range of about 0.5 nm to about 20 nm. If the thickness of protective layer 125 is less than about 0.5 nm, protective layer 125 is not thick enough to protect oxide layer 123. On the other hand, if the thickness of protective layer 125 is greater than about 20 nm, capacitance will increase due to the high k value of protective layer 125.

[0038] In some embodiments, a first dielectric layer 115, a second dielectric layer 117, and a third dielectric layer 118 disposed between adjacent fin structures 112, and a hard mask structure 124 form an isolation region 120. The isolation region 120 may be shallow trench isolation (STI). In some embodiments, such as... Figure 11 As shown, the top surface of the isolation region 120 (i.e., the top surface of the oxide layer 123 and the protective layer 125) can be located at or below the bottom surface of the bottom second semiconductor layer 108.

[0039] Figure 12 This is a perspective view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments. (e.g.) Figure 12As shown, one or more sacrificial gate structures 130 are formed over a semiconductor device structure 100. The sacrificial gate structures 130 are formed over a first portion of a fin structure 112 and a first portion of an isolation region 120, while a second portion of the fin structure 112 and a second portion of the isolation region 120 are exposed. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. In some embodiments, the mask layer 136 is a multilayer structure. For example, the mask layer 136 includes an oxide layer 135 and a nitride layer 137 formed on the oxide layer 135. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 and then patterning those layers into the sacrificial gate structure 130. The sacrificial gate dielectric layer 132 may include one or more layers of a dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100. In some embodiments, the pad 113 located on the second portion of the fin structure 112 may be removed during the patterning process. For clarity, the pad 113 formed on the first portion of the fin structure 112 and adjacent to the isolation region 120 is omitted.

[0040] Figure 13 , Figure 14 and Figure 15 It is according to some embodiments the various stages of manufacturing the semiconductor device structure 100 along Figure 12 The side view of the cross section intercepted by line AA. (See example...) Figure 13 As shown, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. Spacers 138 can be formed by depositing a dielectric layer on the exposed surface of the semiconductor device structure 100, followed by an anisotropic etching process to remove horizontal portions of the dielectric layer. Spacers 138 can be made of dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiCON, and / or combinations thereof. In some embodiments, spacers 138 comprise a multilayer structure. Spacers 138 can be formed on the sidewalls of the sacrificial gate structure 130 and on the sidewalls of the exposed portions of the fin structure 112. Figure 12 ).

[0041] Next step, such as Figure 13As shown, one or more etching processes are performed to recess the portion of fin structure 112 not covered by sacrificial gate structure 130 and spacer 138. In some embodiments, the portion of fin structure 112 not covered by sacrificial gate structure 130 and spacer 138 is recessed to a level above, below, or above the top surface of isolation region 120. Recessing the portion of fin structure 112 can be accomplished by an etching process, either isotropic or anisotropic. The etching process can be dry etching (such as RIE, NBE, etc.) or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). After the portion of fin structure 112 is recessed, substrate portion 116 can be exposed on the opposite side of sacrificial gate structure 130, such as... Figure 13 As shown in the image.

[0042] like Figure 14 As shown, the second semiconductor layer 108 is removed. In some embodiments, the second semiconductor layer 108 comprises Ge, and the subsequently formed source / drain (S / D) region comprises phosphorus-doped silicon for an n-type FET. The Ge in the second semiconductor layer 108 and the phosphorus in the S / D region can diffuse into each other, which can cause a high interface state density (Dit) on the first semiconductor layer 106. Therefore, the mobility of the n-type device may be reduced. Therefore, in some embodiments, the second semiconductor layer 108 is removed before the S / D region is formed. In some embodiments, the second semiconductor layer 108 is completely removed, and an opening 141 is formed between vertically adjacent first semiconductor layers 106, as shown. Figure 14 As shown in the diagram. The second semiconductor layer 108 can be removed by a selective etching process, such as selective dry etching, selective wet etching, or a combination thereof. The selective etching process substantially does not affect the spacer 138 and the first semiconductor layer 106.

[0043] like Figure 15As shown, a dielectric layer 145 is formed in the opening 141, and the dielectric layer 145 is covered by a dielectric spacer 144 along the X direction. The dielectric layer 145 can be formed by first depositing a dielectric layer in the opening 141 and on the semiconductor device structure 100. The dielectric layer can be formed by any suitable process, such as CVD, PECVD, FCVD, or ALD. The dielectric layer can include any suitable dielectric material. In some embodiments, the dielectric layer includes an oxide, such as silicon oxide. In some embodiments, the dielectric layer 145 includes the same material as the third dielectric layer 118. Next, an anisotropic etching process is performed to remove portions of the dielectric layer other than the portion formed in the opening 141. Next, the edge portions of the dielectric layer are horizontally removed along the X direction to form the dielectric layer 145. The removal of the edge portions of the dielectric layer forms a cavity. In some embodiments, the edge portions of the dielectric layer are removed by a selective wet etching process. After forming the dielectric layer 145, a dielectric layer is deposited in the cavity to form the dielectric spacer 144, as shown. Figure 15 As shown in the diagram. The dielectric spacer 144 can be made of a dielectric material such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD), followed by an anisotropic etching to remove portions of the conformal dielectric layer other than the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by a first semiconductor layer 106. In some embodiments, the dielectric spacer 144 and the dielectric layer 145 comprise different materials with different etch selectivity.

[0044] Figure 16 and Figure 17 It is according to some embodiments the various stages of manufacturing the semiconductor device structure 100 along Figure 12 The side view of the cross section intercepted by line BB. (See example...) Figure 16 As shown, the process of partially recessing the fin structure 112 and forming the dielectric layer 145 and dielectric spacer 144 also recesses the isolation region 120. For example, making Figure 13 One or more etching processes described herein that recess the portion of fin structure 112 not covered by sacrificial gate structure 130 and spacer 138 can also recess the spacer 138 formed on the sidewall of the exposed portion of fin structure 112 and hard mask structure 124. The recessed spacer 138 can be disposed on hard mask structure 124, such as... Figure 16As shown in the diagram. In some embodiments, the etching process forming dielectric layer 145 may further recess portions of hard mask structure 124 and third dielectric layer 118 located below hard mask structure 124. In some embodiments, without second dielectric layer 117, third dielectric layer 118 and first dielectric layer 115 may be recessed to expose substrate portion 116 or pad 113. Therefore, subsequently formed S / D regions 146n, 146p may merge. In the presence of second dielectric layer 117, which is made of a different material than the first dielectric layer 115 and third dielectric layer 118, the various processes described above substantially do not affect second dielectric layer 117. Therefore, merging of adjacent S / D regions 146n, 146p is avoided. In some embodiments, the presence of hard mask structure 124 also protects second dielectric layer 117. Without hard mask structure 124, etching may be performed through second dielectric layer 117.

[0045] In some embodiments, such as Figure 16 As shown, the exposed surfaces of the protective layer 125, oxide layer 123, third dielectric layer 118, and second dielectric layer 117 can together form a curved surface, such as a concave surface.

[0046] like Figure 17 As shown, an interposer layer is formed between a substrate portion 116 and source / drain regions 146n, 146p. In some embodiments, the interposer layer is a semiconductor layer 150 formed on an exposed portion of the substrate portion 116, and the S / D regions 146n, 146p are formed over the semiconductor layer 150. In some embodiments, the semiconductor layer 150 may include undoped silicon or undoped SiGe. The term undoped may include unintentionally doped materials. For example, the interposer layer 150 may be undoped at deposition but may contain dopants diffused from other regions during subsequent processes. The S / D region 146n may be an S / D epitaxial component formed in an n-type device region, and the S / D region 146p may be an S / D epitaxial component formed in a p-type device region. The S / D regions 146n, 146p may be formed at different times using a mask. For example, a mask is formed on the substrate portion 116 in the p-type device region, and the S / D region 146n is formed over the substrate portion 116 in the n-type device region. Then, the mask in the p-type device region is removed, and another mask is formed on the S / D region 146n. Then, the S / D region 146p is formed over the substrate portion 116 in the p-type region.

[0047] In some embodiments, the interposer may be a dielectric layer 152 formed between the substrate portion 116 and the S / D region 146n, such as Figure 17As shown in the diagram. Dielectric layer 152 may comprise any suitable dielectric material, such as SiN. In some embodiments, the interposer comprises semiconductor layer 150, dielectric layer 152, or a combination thereof. The interposer prevents current leakage. In some embodiments, dielectric layer 152 is also formed between semiconductor layer 150 and S / D region 146p. In some embodiments, dielectric layer 152 is formed in one of an n-type device region and a p-type device region. In some embodiments, dielectric layer 152 is formed in both an n-type device region and a p-type device region.

[0048] In some embodiments, S / D regions 146n and 146p can be grown vertically and horizontally to form facets, which may correspond to crystal planes of the materials used for the first semiconductor layer 106 and semiconductor layer 150. In embodiments of this disclosure, source and drain regions are used interchangeably and their structures are substantially the same. Furthermore, source / drain regions may refer to either a source or a drain, individually or collectively, depending on the context. In some embodiments, S / D region 146n is an n-type S / D epitaxial component and may be made of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. In some embodiments, S / D region 146p is a p-type epitaxial component and may be made of one or more layers of Si, SiGe, and Ge for a p-channel FET. For p-channel FETs, p-type dopants such as boron (B) may also be included in S / D region 146p. S / D regions 146n and 146p can be formed using epitaxial growth methods such as CVD, ALD, or MBE. In some embodiments, the thickness of the S / D region 146n or 146p along the Z direction is different from the width of the S / D region 146n or 146p along the Y direction. In some embodiments, the S / D region 146n or 146p comprises two or more epitaxial layers with different dopant concentrations.

[0049] like Figure 17 As shown, after forming the S / D regions 146n and 146p, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the spacer 138 and is disposed on the S / D regions 146n and 146p. In some embodiments, the CESL 162 is in contact with or connected to the spacer 138, the protective layer 125, the oxide layer 123, the third dielectric layer 118, and the second dielectric layer 117, such as... Figure 17As shown in the diagram. CESL 162 may include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 163 is formed on CESL 162. The material used for ILD layer 163 may include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers may also be used for ILD layer 163. ILD layer 163 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of ILD layer 163, the semiconductor device structure 100 may undergo a thermal process to anneal ILD layer 163.

[0050] Figure 18 and Figure 19 It is according to some embodiments the various stages of manufacturing the semiconductor device structure 100 along Figure 12 A cross-sectional side view taken from line CC. After forming the ILD layer 163, a planarization process is performed to expose the sacrificial gate electrode layer 134, and the sacrificial gate structure 130 and dielectric layer 145 are removed, as shown. Figure 18 As shown in the diagram. The planarization process can be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layer 163 and CESL 162 disposed on the sacrificial gate structure 130. The planarization process may also remove the mask layer 136. The sacrificial gate electrode layer 134 can be removed first by any suitable process, such as a dry etching process, a wet etching process, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can be implemented by any suitable process, such as a dry etching process, a wet etching process, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134, but without removing the spacer 138, ILD layer 163, and CESL 162. The dielectric layer 145 can be removed by any suitable process. In some embodiments, the dielectric layer 145 is removed by a selective etching process. Selective etching removes the dielectric layer 145 between the first semiconductor layers 106, but does not remove the protective layer 125 of the first semiconductor layer 106, ILD layer 163, CESL 162, spacer 138, and hard mask structure 124. Figure 18 As shown in the diagram, the protective layer 125 of the hard mask structure 124 protects the third dielectric layer 118 from being recessed by the selective etching process. After the dielectric layer 145 is removed, the portions of each first semiconductor layer 106 not covered by the dielectric spacer 144 can be exposed. Each first semiconductor layer 106 can be a nanostructured channel.

[0051] After forming the nanostructured channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170, as follows. Figure 19 As shown in the diagram. The gate dielectric layer 170 and the gate electrode layer 172 can be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) 168 is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. The IL 168 may include an oxide, such as silicon oxide. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate dielectric layer 170 and the gate electrode layer 172 may also be deposited over the ILD layer 163. The gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 163 are then removed by, for example, CMP until the top surface of the ILD layer 163 is exposed.

[0052] Figure 20 It is one of the various stages in the manufacturing of the semiconductor device structure 100 according to some embodiments. Figure 12 The side view of the cross section intercepted by line AA. (See example...) Figure 20 As shown, in some embodiments, the S / D region 146 (146n or 146p) includes two or more epitaxial layers, such as a first epitaxial layer 153 and a second epitaxial layer 154. The first epitaxial layer 153 and the second epitaxial layer 154 may comprise the same semiconductor material but have different dopant concentrations. In some embodiments, the first epitaxial layer 153 and the second epitaxial layer 154 have different compositions.

[0053] like Figure 20As shown, after the CMP process exposing the ILD layer 163, an etch stop layer 222 and another ILD layer 206 are formed on the ILD layer 163 and the gate structure 174. In some embodiments, the etch stop layer 222 comprises the same material as CESL 162. The ILD layer 206 may comprise the same material as the ILD layer 163. In some embodiments, the thickness of the ILD layer 163 is greater than the thickness of the ILD layer 206. Next, a conductive contact 180 is formed in the ILD layer 206 and the etch stop layer 222, and a silicide layer 182 is formed between the conductive contact 180 and the S / D region 146n. Next, another etch stop layer 224 and another ILD layer 226 are formed on the conductive contact 180 and the ILD layer 206, as shown. Figure 20 As shown in the diagram. In some embodiments, etch stop layer 224 comprises the same material as etch stop layer 222. Next, as... Figure 20 As shown, conductive components 228 are formed in ILD layer 226, etch stop layer 224, ILD layer 206, and etch stop layer 222. Conductive components 228 are electrically connected to gate electrode layer 172 and conductive contact 180.

[0054] Figure 21A and Figure 21B These are, respectively, one of the various stages in the manufacturing of the semiconductor device structure 100 according to the optional embodiment. Figure 12 The cross-sectional side view taken from lines BB and CC. In some embodiments, the pad 113 is absent, and the first dielectric layer 115 is deposited on and in contact with the substrate portion 116, as shown below. Figure 21A and Figure 21B As shown in the image.

[0055] Figure 22A and Figure 22B These are, respectively, one of the various stages in the manufacturing of the semiconductor device structure 100 according to the optional embodiment. Figure 12 The cross-sectional side view taken by lines BB and CC. In some embodiments, the first dielectric layer 115 is absent, and the second dielectric layer 117 is deposited on and in contact with the substrate portion 116 or the pad 113, as shown. Figure 22A and Figure 22B As shown in the image.

[0056] Figure 23A and Figure 23B These are, respectively, one of the various stages in the manufacturing of the semiconductor device structure 100 according to the optional embodiment. Figure 12 The side view of the cross section taken by lines BB and CC. In some embodiments, the top surfaces of the first dielectric layer 115, the second dielectric layer 117, and the third dielectric layer 118 together form a curved surface, which is due to Figure 9 and Figure 10 The document describes several etching processes. In some embodiments, the bottom surface of the hard mask structure 124 is also curved. For example, the top surfaces of the first dielectric layer 115, the second dielectric layer 117, and the third dielectric layer 118 may together form a concave surface, and the bottom surface of the hard mask structure 124 may form a convex surface. In some embodiments, the oxide layer 123 and the protective layer 125 are both conformal layers, and the top surface of the hard mask structure 124 may be curved, such as concave.

[0057] In some embodiments, Figure 23A The curvature of the concave surface shown, formed by the combined surface of protective layer 125, oxide layer 123, third dielectric layer 118, and second dielectric layer 117, is similar to... Figure 23B The concave surface shown, formed by the combination of the first dielectric layer 115, the second dielectric layer 117, and the third dielectric layer 118, has different curvatures.

[0058] Embodiments of this disclosure provide a semiconductor device structure 100 including an isolation region 120, the isolation region 120 including at least dielectric layers 117 and 118 and a hard mask structure 124 disposed on the dielectric layers 117 and 118. Some embodiments may achieve advantages. For example, the protective layer 125 of the dielectric layer 117 and the hard mask structure 124 prevents the substrate portion 116 from being exposed. Therefore, the merging of the S / D regions 146n and 146p can be avoided.

[0059] The embodiment is a semiconductor device structure. The structure includes source / drain regions, each comprising a first epitaxial layer and a second epitaxial layer, both doped with dopants. The dopant concentration in the first epitaxial layer differs from that in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain regions differs from their width. The structure also includes a contact etch stop layer disposed above the source / drain regions, a first interlayer dielectric (ILD) layer disposed above the contact etch stop layer, an etch stop layer disposed above the top surface of the contact etch stop layer and the top surface of the first ILD layer, and a second ILD layer disposed above the etch stop layer. The thickness of the first ILD layer is greater than the thickness of the second ILD layer. The structure also includes a substrate portion disposed below the source / drain regions and an isolation region disposed adjacent to the substrate portion. The isolation region includes: a first dielectric layer comprising a first dielectric material; and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer comprises a second dielectric material different from the first dielectric material. The isolation region also includes a hard mask structure disposed on the first dielectric layer and the second dielectric layer.

[0060] Another embodiment is a semiconductor device structure. The structure includes a first source / drain region comprising a first epitaxial layer and a second epitaxial layer, both doped with dopants. The dopant concentration in the first epitaxial layer differs from that in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region differs from its width. The structure also includes a second source / drain region adjacent to the first source / drain region, a gate electrode layer adjacent to the first and second source / drain regions, a contact etch stop layer disposed above the first and second source / drain regions, a first interlayer dielectric (ILD) layer disposed above the contact etch stop layer, an etch stop layer disposed above the top surface of the contact etch stop layer and the top surface of the first ILD layer, and a second ILD layer disposed above the etch stop layer. The thickness of the first ILD layer is greater than the thickness of the second ILD layer. The structure also includes a first substrate portion disposed below the first source / drain region, a second substrate portion disposed below the second source / drain region, and an isolation region disposed between the first substrate portion and the second substrate portion. The isolation region includes a first dielectric layer and a hard mask structure disposed above the first dielectric layer, the hard mask structure including a first portion and a second portion. A contact etch stop layer extends through the first portion of the hard mask structure, and a gate electrode layer is disposed above the second portion of the hard mask structure.

[0061] A further embodiment is a method. The method includes forming a fin structure over a substrate, and the fin structure includes a substrate portion and a first protective layer located over the substrate portion. The method also includes forming an isolation region adjacent to the substrate portion. The method for forming the isolation region includes: depositing a first dielectric layer around the fin structure; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; recessing the first dielectric layer to expose the sides of the first protective layer; removing the first protective layer; recessing the first and third dielectric layers; and recessing the first and second dielectric layers. The method also includes forming a source / drain region over the substrate portion. The source / drain region includes a first epitaxial layer and a second epitaxial layer, the first and second epitaxial layers being doped with dopants, the concentration of the dopants in the first epitaxial layer being different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region being different from the width of the source / drain region.

[0062] Some embodiments of this application provide a semiconductor device structure, including: a source / drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region; a contact etch stop layer disposed above the source / drain region; a first interlayer dielectric layer disposed above the contact etch stop layer; and an etch stop layer disposed above the contact etch stop layer. The first interlayer dielectric layer is located above the top surface and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a substrate portion is disposed below the source / drain region; and an isolation region is disposed adjacent to the substrate portion, wherein the isolation region includes: a first dielectric layer comprising a first dielectric material; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material different from the first dielectric material; and a hard mask structure disposed on the first dielectric layer and the second dielectric layer.

[0063] In some embodiments, the hard mask structure includes an oxide layer and a protective layer disposed on the oxide layer. In some embodiments, the protective layer includes a second dielectric material. In some embodiments, the first dielectric material includes silicon oxide, and the second dielectric material includes SiN, SiCN, SiOC, SiOCN, or SiC. In some embodiments, the semiconductor device structure further includes spacers disposed on the hard mask structure, wherein the spacers are adjacent to the source / drain regions. In some embodiments, the contact etch stop layer is connected to the spacers, the hard mask structure, the first dielectric layer, and the second dielectric layer. In some embodiments, the semiconductor device structure further includes a semiconductor layer disposed between the substrate portion and the source / drain regions, wherein the semiconductor layer is adjacent to the hard mask structure. In some embodiments, the semiconductor device structure further includes a third dielectric layer disposed between the semiconductor layer and the source / drain regions.

[0064] Some other embodiments of this application provide a semiconductor device structure, including: a first source / drain region, comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region; a second source / drain region, disposed adjacent to the first source / drain region; a gate electrode layer, disposed adjacent to the first source / drain region and the second source / drain region; a contact etch stop layer, disposed above the first source / drain region and the second source / drain region; a first interlayer dielectric (ILD) layer, disposed above the contact etch stop layer; and an etch stop layer. An etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; a second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; a first substrate portion is disposed below the first source / drain region; a second substrate portion is disposed below the second source / drain region; and an isolation region is disposed between the first substrate portion and the second substrate portion, wherein the isolation region includes a first dielectric layer and a hard mask structure disposed above the first dielectric layer, the hard mask structure including a first portion and a second portion, wherein the contact etch stop layer extends through the first portion of the hard mask structure, and the gate electrode layer is disposed above the second portion of the hard mask structure.

[0065] In some embodiments, the second portion of the hard mask structure has a flat top surface. In some embodiments, the second portion of the hard mask structure has a curved top surface. In some embodiments, the hard mask structure includes an oxide layer and a protective layer disposed on the oxide layer. In some embodiments, the first dielectric layer and the protective layer comprise the same material. In some embodiments, the isolation region further includes a second dielectric layer disposed on the first dielectric layer, wherein the hard mask layer is disposed on the second dielectric layer. In some embodiments, the top surface of the second dielectric layer is curved. In some embodiments, the contact etch stop layer is in contact with the top surface of the second dielectric layer.

[0066] Further embodiments of this application provide a method for forming a semiconductor device structure, comprising: forming a fin structure over a substrate, wherein the fin structure includes a substrate portion and a first protective layer located over the substrate portion; forming an isolation region adjacent to the substrate portion, comprising: depositing a first dielectric layer around the fin structure; depositing a second dielectric layer on the first dielectric layer; depositing a third dielectric layer on the second dielectric layer; recessing the first dielectric layer to expose the sidewalls of the first protective layer; removing the first protective layer; recessing the first dielectric layer and the third dielectric layer; and recessing the first dielectric layer and the second dielectric layer; and forming a source / drain region over the substrate portion, wherein the source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region.

[0067] In some embodiments, after the first and second dielectric layers are recessed, the top surfaces of the first, second, and third dielectric layers are substantially coplanar. In some embodiments, after the first and second dielectric layers are recessed, the top surfaces of the first, second, and third dielectric layers together form a concave surface. In some embodiments, forming the isolation region further includes forming a hard mask structure on the first, second, and third dielectric layers, wherein the hard mask structure includes an oxide layer and a second protective layer.

[0068] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device structure, comprising: The source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region. A contact etch stop layer is disposed above the source / drain region; The first interlayer dielectric layer is disposed above the contact etch stop layer; An etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; A second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; The substrate portion is disposed below the source / drain regions; and An isolation region is disposed adjacent to the substrate portion, wherein the isolation region includes: The first dielectric layer includes a first dielectric material; A second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer includes a second dielectric material different from the first dielectric material; and A hard mask structure is disposed on the first dielectric layer and the second dielectric layer.

2. The semiconductor device structure according to claim 1, wherein, The hard mask structure includes an oxide layer and a protective layer disposed on the oxide layer.

3. The semiconductor device structure according to claim 2, wherein, The protective layer includes the second dielectric material.

4. The semiconductor device structure according to claim 3, wherein, The first dielectric material includes silicon oxide, and the second dielectric material includes SiN, SiCN, SiOC, SiOCN, or SiC.

5. The semiconductor device structure according to claim 1, further comprising spacers disposed on the hard mask structure, wherein, The spacer is adjacent to the source / drain region.

6. The semiconductor device structure according to claim 5, wherein, The contact etch stop layer is connected to the spacer, the hard mask structure, the first dielectric layer, and the second dielectric layer.

7. The semiconductor device structure according to claim 1, further comprising a semiconductor layer disposed between the substrate portion and the source / drain region, wherein, The semiconductor layer is adjacent to the hard mask structure.

8. The semiconductor device structure according to claim 7 further includes a third dielectric layer disposed between the semiconductor layer and the source / drain region.

9. A semiconductor device structure, comprising: The first source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the first source / drain region is different from the width of the first source / drain region. The second source / drain region is located adjacent to the first source / drain region; A gate electrode layer is disposed adjacent to the first source / drain region and the second source / drain region; A contact etch stop layer is disposed above the first source / drain region and the second source / drain region; The first interlayer dielectric layer is disposed above the contact etch stop layer; An etch stop layer is disposed above the top surface of the contact etch stop layer and the top surface of the first interlayer dielectric layer; A second interlayer dielectric layer is disposed above the etch stop layer, wherein the thickness of the first interlayer dielectric layer is greater than the thickness of the second interlayer dielectric layer; The first substrate portion is disposed below the first source / drain region; The second substrate portion is disposed below the second source / drain region; and An isolation region is disposed between a first substrate portion and a second substrate portion, wherein the isolation region includes a first dielectric layer and a hard mask structure disposed above the first dielectric layer, the hard mask structure including a first portion and a second portion, wherein the contact etch stop layer extends through the first portion of the hard mask structure, and the gate electrode layer is disposed above the second portion of the hard mask structure.

10. A method for forming a semiconductor device structure, comprising: A fin structure is formed above a substrate, wherein the fin structure includes a substrate portion and a first protective layer located above the substrate portion; An isolation region is formed adjacent to the substrate portion, including: A first dielectric layer is deposited around the fin structure; Deposit a second dielectric layer on the first dielectric layer; Deposit a third dielectric layer on the second dielectric layer; The first dielectric layer is recessed to expose the side surface of the first protective layer; Remove the first protective layer; The first dielectric layer and the third dielectric layer are recessed; and The first dielectric layer and the second dielectric layer are recessed; and A source / drain region is formed above the substrate portion, wherein the source / drain region includes a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with dopants, the concentration of the dopants in the first epitaxial layer is different from the concentration of the dopants in the second epitaxial layer, and in a cross-sectional view, the thickness of the source / drain region is different from the width of the source / drain region.

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