Semiconductor device structure and preparation method thereof

Abstract

The invention discloses a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductor devices.The semiconductor device structure comprises a substrate, a first transistor, a second transistor and two common side walls, the first transistor is arranged on the substrate, the second transistor is arranged on the first transistor, and the two common side walls are arranged on the substrate; an isolation layer is arranged between the first transistor and the second transistor, the first transistor comprises a first grid electrode and a first channel region, the first grid electrode is arranged in the first channel region, the second transistor comprises a second grid electrode and a second channel region, and the second grid electrode is arranged in the second channel region; the two common side walls are oppositely arranged on the substrate, and the first channel region and the second channel region are oppositely arranged in the direction perpendicular to the substrate and located between the two common side walls; according to the invention, the alignment precision of the first transistor and the second transistor in the direction perpendicular to the substrate can be improved, so that the preparation difficulty of the stacked semiconductor device structure is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a semiconductor device structure and its fabrication method. Background Technology

[0002] To further improve the integration density of integrated circuits, a semiconductor device structure that stacks and integrates N-type and P-type field-effect transistors has emerged. This design can overcome the area limitations of traditional planar complementary metal-oxide-semiconductor (CMOS) technology, significantly increasing the integration density of integrated circuits, which is of great significance for continuing Moore's Law and reducing chip power consumption.

[0003] In existing processes, the upper-layer transistor is typically fabricated by bonding a wafer on top of a pre-fabricated lower-layer transistor, vertically stacking two transistors. However, this method requires extremely high alignment precision, making the fabrication process quite challenging. Summary of the Invention

[0004] The main objective of this invention is to propose a semiconductor device structure and its fabrication method, aiming to solve the problem of the difficulty in fabricating field-effect transistors in the prior art.

[0005] To achieve the above objectives, the present invention proposes a semiconductor device structure, the semiconductor device structure comprising:

[0006] Substrate; A first transistor and a second transistor, the first transistor being disposed on the substrate, the second transistor being disposed on the first transistor, an isolation layer being disposed between the first transistor and the second transistor, the first transistor including a first gate and a first channel region, the first gate being disposed in the first channel region, and the second transistor including a second gate and a second channel region, the second gate being disposed in the second channel region; and Two common sidewalls are disposed opposite to each other on the substrate. The first channel region and the second channel region are aligned in a direction perpendicular to the substrate and are located between the two common sidewalls.

[0007] In one embodiment, the first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain; The first source electrode and the second source electrode are aligned in a direction perpendicular to the substrate, and the first drain electrode and the second drain electrode are aligned in a direction perpendicular to the substrate. A portion of the isolation layer is disposed between the first source electrode and the second source electrode and between the first drain electrode and the second drain electrode, and another portion of the isolation layer is disposed between the first channel region and the second channel region; or The first source and the second drain are aligned in a direction perpendicular to the substrate, and the first drain and the second source are aligned in a direction perpendicular to the substrate. A portion of the isolation layer is disposed between the first source and the second drain and between the first drain and the second source, and another portion of the isolation layer is disposed between the first channel region and the second channel region.

[0008] In one embodiment, the first channel region includes multiple first channel layers, the first channel layer closest to the isolation layer being a first top channel layer, the first top channel layer being disposed between the first gate and the isolation layer; and / or The second channel region includes multiple second channel layers, with the second channel layer closest to the isolation layer being the first bottom channel layer, which is disposed between the second gate and the isolation layer.

[0009] In one embodiment, the semiconductor device structure further includes a plurality of inner sidewalls disposed between the first gate and the first source and the first drain of the first transistor, and between the second gate and the second source and the second drain of the second transistor.

[0010] In one embodiment, the semiconductor device structure further includes a first dielectric layer disposed between the first transistor and the substrate. The first dielectric layer contains a plurality of first contact metal layers, and the first source, the first drain, and the first gate are electrically connected to at least one of the first contact metal layers. The second transistor further includes a second dielectric layer disposed on the side of the second transistor away from the first transistor. The second dielectric layer contains a plurality of second contact metal layers, and the second source, the second drain, and the second gate are electrically connected to at least one of the second contact metal layers.

[0011] The present invention also provides a method for fabricating a semiconductor device structure, which includes the following steps: A sacrificial substrate is provided, and a stacked structure and a virtual gate structure are formed on the sacrificial substrate, the stacked structure including a first sub-stacked structure, an isolation sacrificial layer and a second sub-stacked structure; A mask structure is formed, and the mask structure and the second sub-stack structure are etched to form a common sidewall and a first groove that exposes the isolation sacrificial layer; The isolation sacrificial layer is removed and an isolation layer is formed, and a first transistor is formed on the isolation layer; After bonding the substrate to the first transistor, the sacrificial substrate is removed, exposing the first sub-stack structure; A second transistor is formed.

[0012] In one embodiment, the step of forming a mask structure and etching the mask structure and the second sub-stack structure to form a common sidewall and a first groove exposing the isolation sacrificial layer includes: A dielectric overlay layer is formed on the stacked structure and the virtual gate structure; A first mask layer is formed on the dielectric cover layer, and the first mask layer and the dielectric cover layer form the mask structure; The mask structure and the second sub-stack structure are etched to form the first grooves that expose the isolation sacrificial layer on both sides of the virtual gate structure, and at the same time, the common sidewalls located on the sidewalls of the virtual gate structure are formed.

[0013] In one embodiment, the step of removing the isolation sacrificial layer and forming an isolation layer, and forming a first transistor on the isolation layer, includes: Remove the isolation sacrificial layer and form the isolation layer; The end of the second sub-stack structure exposed from the sidewall of the first groove is etched to cause a portion of the second sub-stack structure to be recessed inward to form a back-etching area; An inner wall is formed within the engraved area; A first source and a first drain of a first transistor are formed on the isolation layer; A portion of the virtual gate structure and a portion of the second sub-stack structure are removed to form the first gate of the first transistor.

[0014] In one embodiment, the step of removing the isolation sacrificial layer and forming an isolation layer, and forming a first transistor on the isolation layer, includes: The end of the second sub-stack structure exposed from the sidewall of the first groove is etched to cause a portion of the second sub-stack structure to be recessed inward to form a back-etching area; An inner wall is formed within the engraved area; Remove the isolation sacrificial layer and form the isolation layer; A first source and a first drain of a first transistor are formed on the isolation layer; A portion of the virtual gate structure and a portion of the second sub-stack structure are removed to form the first gate of the first transistor.

[0015] In one embodiment, the step of removing the isolation sacrificial layer and forming the isolation layer includes: Forming an etching barrier layer; Etch the etch barrier layer to expose the isolation sacrificial layer; Etching removes the isolation sacrificial layer; The isolation layer is formed.

[0016] In one embodiment, after the step of removing the isolation sacrificial layer and forming the isolation layer, and before the step of forming the first source and first drain of the first transistor on the isolation layer, the method includes: Remove the first mask layer.

[0017] In one embodiment, the step of removing the sacrificial substrate after bonding the substrate to the first transistor and exposing the first sub-stack structure includes: A substrate is bonded to the side of the first transistor away from the sacrificial substrate to form an intermediate semiconductor structure; The intermediate semiconductor structure is flipped, and the sacrificial substrate is removed to expose the first sub-stack structure.

[0018] In one embodiment, the step of removing the sacrificial substrate to expose the first sub-stack structure includes: Thinning of the sacrificial substrate; The thinned sacrificial substrate is etched until the first sub-stack structure is exposed.

[0019] In one embodiment, the step of forming the second transistor includes: The first sub-stack structure is etched to form a second groove on both sides of the virtual gate structure to expose the isolation layer; The second source and the second drain of the second transistor are formed in the second groove; A portion of the virtual gate structure and a portion of the first sub-stack structure are removed to form the second gate of the second transistor.

[0020] In one embodiment, after the step of forming the first transistor on the isolation layer and before the step of bonding the substrate to the first transistor, the method includes: Forming a first dielectric layer and a first contact metal layer located in the first dielectric layer; and / or Following the step of forming the second transistor, the following is included: A second dielectric layer and a second contact metal layer located in the second dielectric layer are formed.

[0021] In the technical solution of this application, the first transistor and the second transistor are separated by an isolation layer, thereby blocking the electrical coupling between the first transistor and the second transistor; the first channel region of the first transistor and the second channel region of the second transistor are both located between two oppositely arranged common sidewalls. The common sidewalls serve as alignment references between the first transistor and the second transistor, ensuring accurate alignment between the first channel region and the second channel region in the direction perpendicular to the substrate; thereby improving the alignment accuracy of the first transistor and the second transistor in the direction perpendicular to the substrate, thus reducing the fabrication difficulty of the stacked semiconductor device structure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the semiconductor device structure provided by the present invention; Figure 2 A schematic flowchart illustrating the method for fabricating the semiconductor device structure provided by the present invention; Figure 3 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 1 ; Figure 4 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 ; Figure 5 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 3 ; Figure 6 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 4 ; Figure 7 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 5 ; Figure 8 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 6 ; Figure 9 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 7 ; Figure 10 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 8 ; Figure 11 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 9 ; Figure 12 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 ; Figure 13 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 one; Figure 14 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 two; Figure 15 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 three; Figure 16 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 Four; Figure 17 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 five; Figure 18 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 six; Figure 19 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 seven; Figure 20 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 eight; Figure 21 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 10 Nine; Figure 22 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 ten; Figure 23 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 eleven; Figure 24 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 twelve; Figure 25 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2Thirteen; Figure 26 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 fourteen; Figure 27 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 fifteen; Figure 28 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 sixteen; Figure 29 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 Seventeen; Figure 30 Schematic diagram of the semiconductor device structure provided by the present invention during the fabrication process Figure 2 eighteen.

[0024] Icon labels: 1. Substrate; 2. First transistor; 21. First gate; 22. First source; 23. First drain; 24. First channel region; 241. First channel layer; 2411. First top channel layer; 25. First dielectric layer; 26. First contact metal layer; 3. Second transistor; 31. Second gate; 32. Second source; 33. Second drain; 34. Second channel region; 341. Second channel layer; 3411. First bottom channel layer; 35. Second dielectric layer; 36. Second contact metal layer; 4. Mask structure; 41. Dielectric capping layer; 411. Common sidewall; 42. First mask layer; 5. Isolation layer; 6. Inner sidewall; 7. Sacrificial substrate; 8. Stacked structure; 81. First sub-stacked structure; 811. First sacrificial layer; 812. First semiconductor layer; 82. Isolation layer; 83. Sacrificial layer; 84. Second sub-stack structure; 85. Second semiconductor layer; 86. Second sacrificial layer; 97. Virtual gate structure; 98. First virtual gate segment; 99. Second virtual gate segment; 90. Third virtual gate segment; 10. Stacked structure; 101. First sub-stacked structure; 1011. First epitaxial layer; 1012. Second epitaxial layer; 102. Third epitaxial layer; 103. Second sub-stacked structure; 1031. Fourth epitaxial layer; 1032. Fifth epitaxial layer; 11. First trench; 12. Intermediate semiconductor structure; 13. Second trench; 14. Gate oxide layer; 15. Etch stop layer; 16. First etch stop layer; 17. First interlayer dielectric layer; 18. Second mask layer; 19. Second etch stop layer; 20. Second interlayer dielectric layer; 27. Isolation structure.

[0025] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially. Furthermore, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, or solution B, or a solution where both A and B are satisfied simultaneously. In addition, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To further improve the integration density of integrated circuits, a semiconductor device structure that stacks and integrates N-type and P-type field-effect transistors has emerged. This design can overcome the area limitations of traditional planar complementary metal-oxide-semiconductor (CMOS) technology, significantly increasing the integration density of integrated circuits, which is of great significance for continuing Moore's Law and reducing chip power consumption.

[0028] In existing processes, the upper-layer transistor is typically fabricated by bonding a wafer on top of a pre-fabricated lower-layer transistor, vertically stacking two transistors. However, this approach requires extremely high alignment precision, making the fabrication process quite challenging.

[0029] In view of this, firstly, this application proposes a semiconductor device structure, Figure 1 These are some embodiments of this application.

[0030] Please see Figure 1In some embodiments of this application, the semiconductor device structure includes a substrate 1, a first transistor 2, a second transistor 3, and two common sidewalls 411. The first transistor 2 is disposed on the substrate 1, and the second transistor 3 is disposed on the first transistor 2. An isolation layer 5 is disposed between the first transistor 2 and the second transistor 3. The first transistor 2 includes a first gate 21 and a first channel region 24, with the first gate 21 disposed in the first channel region 24. The second transistor 3 includes a second gate 31 and a second channel region 34, with the second gate 31 disposed in the second channel region 34. The two common sidewalls 411 are disposed opposite to each other on the substrate 1. The first channel region 24 and the second channel region 34 are aligned in a direction perpendicular to the substrate 1 and located between the two common sidewalls 411.

[0031] In the technical solution of this application, the first transistor 2 and the second transistor 3 are separated by an isolation layer 5, thereby blocking the electrical coupling between the first transistor 2 and the second transistor 3; the first channel region 24 of the first transistor 2 and the second channel region 34 of the second transistor 3 are both located between two oppositely arranged common sidewalls 411. The common sidewalls 411 serve as alignment references between the first transistor 2 and the second transistor 3, ensuring accurate alignment between the first channel region 24 and the second channel region 34 in the direction perpendicular to the substrate 1; thereby improving the alignment accuracy of the first transistor 2 and the second transistor 3 in the direction perpendicular to the substrate 1, thus reducing the fabrication difficulty of the stacked semiconductor device structure.

[0032] The direction perpendicular to substrate 1 is defined as the up-down direction. Substrate 1 has mutually perpendicular length and width directions. Exemplarily, the first transistor 2, the second transistor 3, and two common sidewalls 411 are all located above substrate 1. The first transistor 2 further includes a first source 22 and a first drain 23, which are arranged sequentially along the length of substrate 1. The second transistor 3 further includes a second source 32 and a second drain 33, which are also arranged sequentially along the length of substrate 1. The two common sidewalls 411 are disposed opposite to each other on both sides of the first transistor 2, the second transistor 3, and the isolation layer 5 in the width direction of substrate 1.

[0033] The common sidewall 411 is made of a low dielectric material, that is, the common sidewall 411 is a low dielectric constant dielectric sidewall, which can effectively reduce the parasitic capacitance between the gate and the source and drain electrodes, that is, reduce the parasitic capacitance between the first gate 21 and the first source 22 and the second drain 33, and between the second gate 31 and the second source 32 and the second drain 33.

[0034] In some embodiments of this application, the material of the isolation layer 5 is silicon nitride.

[0035] Specifically, a portion of the isolation layer 5 is disposed between the first source 22 and the second source 32, and between the first drain 23 and the second drain 33. This portion of the isolation layer 5 can effectively block the electrical coupling between the first source 22 and the second source 32, and between the first drain 23 and the second drain 33, thereby significantly suppressing electrical crosstalk, leakage current, and the formation of parasitic PN junctions. Another portion of the isolation layer 5 is disposed between the first channel region 24 and the second channel region 34. This portion of the isolation layer 5 separates the first channel region 24 and the second channel region 34, and also separates the first gate 21 and the second gate 31, thereby ensuring that the first transistor 2 and the second transistor 3 have independent and precise gate control capabilities.

[0036] In some embodiments of this application, the first channel region 24 includes multiple first channel layers 241 disposed above the substrate 1. The first gate 21 is disposed in the first channel region 24 and on the outer periphery of the first channel layers 241. The first channel layer 241 closest to the isolation layer 5 is a first top channel layer 2411, which is disposed between the first gate 21 and the isolation layer 5. The second channel region 34 includes multiple second channel layers 341 disposed above the substrate 1. The second gate 31 is disposed in the second channel region 34 and on the outer periphery of the second channel layers 341. The second channel layer 341 closest to the isolation layer 5 is a first bottom channel layer 3411, which is disposed between the second gate 31 and the isolation layer 5.

[0037] Based on the above structure, in the direction perpendicular to the substrate 1, a first top channel layer 2411, an isolation layer 5, and a first bottom channel layer 3411 are sequentially disposed between the first gate 21 and the second gate 31. The first top channel layer 2411 and the first bottom channel layer 3411 are made of semiconductor materials, such as silicon or silicon-germanium. Since the isolation layer 5 has the function of blocking the electrical coupling between the first transistor 2 and the second transistor 3, it can effectively isolate the first gate 21 and the second gate 31 in the direction perpendicular to the substrate 1, thereby suppressing the electric field coupling and signal crosstalk that may occur between the first gate 21 and the second gate 31, and ensuring the independent and precise gate control capability of the first transistor 2 and the second transistor 3.

[0038] In some embodiments of this application, the semiconductor device structure further includes a plurality of inner sidewalls 6, which are disposed between the first gate 21 and the first source 22 and the first drain 23 of the first transistor 2 and between the second gate 31 and the second source 32 and the second drain 33 of the second transistor 3, so as to increase the spacing between the first gate 21 and the first source 22 and the first drain 23 and between the second gate 31 and the second source 32 and the second drain 33, thereby significantly reducing parasitic capacitance.

[0039] In some embodiments of this application, the first transistor 2 and the second transistor 3 are precisely aligned in the direction perpendicular to the substrate 1 by aligning the first source 22 and the second drain 33 with the first drain 23 and the second source 32 using the common sidewall 411 as the alignment reference, or by aligning the first source 22 and the second source 32 with the first drain 23 and the second drain 33 using the common sidewall 411 as the alignment reference.

[0040] It should be further explained that when the first source 22 and the second source 32 are aligned in a direction perpendicular to the substrate 1, and the first drain 23 and the second drain 33 are aligned in a direction perpendicular to the substrate 1, a portion of the isolation layer 5 is disposed between the first source 22 and the second source 32 and between the first drain 23 and the second drain 33, and another portion of the isolation layer 5 is disposed between the first channel region 24 and the second channel region 34; when the first source 22 and the second drain 33, and the second source 32 and the first drain 23 are aligned in a direction perpendicular to the substrate 1, a portion of the isolation layer 5 is disposed between the first source 22 and the second drain 33 and between the second source 32 and the first drain 23, and another portion of the isolation layer 5 is disposed between the first channel region 24 and the second channel region 34.

[0041] In some embodiments of this application, the semiconductor device structure further includes a first dielectric layer 25, which is disposed on the side of the first transistor 2 away from the second transistor 3 and located between the first transistor 2 and the substrate 1. The first dielectric layer 25 has a plurality of first contact metal layers 26, and the first source 22, the first drain 23 and the first gate 21 are electrically connected to at least one of the first contact metal layers 26 respectively. The first contact metal layers 26 realize the connection between the first gate 21, the first source 22 and the first drain 23 of the first transistor 2 and the external circuit.

[0042] In some embodiments of this application, the semiconductor device structure further includes a second dielectric layer 35, which is disposed on the side of the second transistor 3 away from the first transistor 2; the second dielectric layer 35 is provided with a plurality of second contact metal layers 36, and the second source 32, the second drain 33 and the second gate 31 are electrically connected to at least one of the second contact metal layers 36; the second contact metal layers 36 realize the connection between the second gate 31, the second source 32 and the second drain 33 of the second transistor 3 and the external circuit.

[0043] Secondly, in order to prepare the semiconductor device structure as described in the above embodiments, this application provides a corresponding method for preparing the semiconductor device structure.

[0044] Please see Figure 2 In some embodiments of this application, the preparation method includes the following steps: S1: Provide a sacrificial substrate 7, and form a stacked structure 8 and a virtual gate structure 9 on the sacrificial substrate 7. The stacked structure 8 includes a first sub-stacked structure 81, an isolation sacrificial layer 82 and a second sub-stacked structure 83.

[0045] The sacrificial substrate 7 can be made of various materials, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the sacrificial substrate 7 is made of single-crystal silicon.

[0046] The stacked structure 8 includes a first sub-stacked structure 81, an isolation sacrificial layer 82, and a second sub-stacked structure 83, which are sequentially stacked upward from the sacrificial substrate 7. The first sub-stacked structure 81 includes a plurality of first sacrificial layers 811 and a plurality of first semiconductor layers 812 that are sequentially and alternately stacked upward from the sacrificial substrate 7 in the thickness direction. The second sub-stacked structure 83 includes a plurality of second semiconductor layers 831 and a plurality of second sacrificial layers 832 that are sequentially and alternately stacked upward from the isolation sacrificial layer 82 in the thickness direction of the sacrificial substrate 7.

[0047] Specifically, the steps of providing a sacrificial substrate 7 and forming a stacked structure 8 and a dummy gate structure 9 on the sacrificial substrate 7 include: S11: A stacked structure 10 is formed on the sacrificial substrate 7.

[0048] Specifically, in this step, a first epitaxial layer 1011 is first formed on the upper surface of the sacrificial substrate 7, then a second epitaxial layer 1012 is formed on the first epitaxial layer 1011, and then a first epitaxial layer 1011 is formed on the second epitaxial layer 1012, thereby forming a predetermined number of second epitaxial layers 1012. The multiple first epitaxial layers 1011 and the multiple second epitaxial layers 1012 are combined to form a first sub-stack structure 101.

[0049] For example, such as Figure 3 As shown, a total of four second epitaxial layers 1012 are formed. Of course, the number of second epitaxial layers 1012 can be one, two, three, or four or more.

[0050] Next, after the deposition of the first sub-stack structure 101 is completed, a third epitaxial layer 102 is formed on the upper surface of the first sub-stack structure 101 by a process such as chemical vapor deposition or atomic layer deposition. The thickness of the third epitaxial layer 102 is greater than the thickness of the first epitaxial layer 1011 and the second epitaxial layer 1012.

[0051] Finally, a fourth epitaxial layer 1031 is formed on the upper surface of the third epitaxial layer 102, a fifth epitaxial layer 1032 is formed on the fourth epitaxial layer 1031, and then a fourth epitaxial layer 1031 is formed on the fifth epitaxial layer 1032. A predetermined number of fourth epitaxial layers 1031 are formed in sequence. The multiple fourth epitaxial layers 1031 and the multiple fifth epitaxial layers 1032 are combined to form the second sub-stack structure 103.

[0052] For example, such as Figure 3 As shown, a total of four fourth epitaxial layers 1031 are formed. Of course, the number of fourth epitaxial layers 1031 can be one, two, three, or more than four.

[0053] In the specific steps described above, the first sub-stack structure 101, the third epitaxial layer 102, and the second sub-stack structure 103 are combined to form the stack structure 10.

[0054] It should be further noted that the constituent materials of the first epitaxial layer 1011 and the second epitaxial layer 1012 are different. The constituent material of the second epitaxial layer 1012 is a semiconductor material, and the constituent material of the first epitaxial layer 1011 may include any semiconductor material different from the constituent material of the second epitaxial layer 1012. For example, in one embodiment, the constituent material of the second epitaxial layer 1012 is silicon, and the constituent material of the first epitaxial layer 1011 is germanium-silicon or germanium.

[0055] The constituent materials of the fourth epitaxial layer 1031 and the fifth epitaxial layer 1032 are different. The constituent material of the fourth epitaxial layer 1031 is a semiconductor material, while the constituent material of the fifth epitaxial layer 1032 may include any semiconductor material different from the constituent material of the fourth epitaxial layer 1031. For example, in one embodiment, the constituent material of the fourth epitaxial layer 1031 is silicon, and the constituent material of the fifth epitaxial layer 1032 is germanium-silicon or germanium.

[0056] Furthermore, the constituent materials of the third epitaxial layer 102 include, but are not limited to, silicon and germanium, and the constituent materials of the third epitaxial layer 102 are different from the constituent materials of the adjacent second epitaxial layer 1012 and the fourth epitaxial layer 1031.

[0057] S12: Etch the stacked structure 10 to form a plurality of the stacked structures 8.

[0058] Specifically, a layer of photoresist is coated on the stacked structure 10, and the photoresist is patterned using a photolithography process. Then, the stacked structure 10 is etched using the patterned photoresist as a mask. After etching, the stacked structure 10 is separated, thereby forming multiple stacked structures 8 on the sacrificial substrate 7.

[0059] Specifically, please refer to Figures 3 to 4 This embodiment uses a stacked structure 8 as an example for illustration. After etching, the first sub-stacked structure 101 forms the first sub-stacked structure 81, the first epitaxial layer 1011 forms the first sacrificial layer 811, the second epitaxial layer 1012 forms the first semiconductor layer 812; the third epitaxial layer 102 forms the isolation sacrificial layer 82; the second sub-stacked structure 103 forms the second sub-stacked structure 83, the fourth epitaxial layer 1031 forms the second semiconductor layer 831, and the fifth epitaxial layer 1032 forms the second sacrificial layer 832.

[0060] For ease of explanation, the sacrificial substrate 7 is defined to have mutually perpendicular length and width directions.

[0061] S13: Form the virtual gate structure 9.

[0062] Specifically, a virtual gate material is formed. Subsequently, a gate pattern is defined on the virtual gate material using photolithography, and a virtual gate structure 9 is patterned by photolithography and etching to span and cover part of the top and sidewalls of the stacked structure 8 along the width direction of the sacrificial substrate 7.

[0063] For example, such as Figure 5 As shown, three virtual gate structures 9 are formed on a stacked structure 8, and the three virtual gate structures 9 are spaced apart in the length direction of the sacrificial substrate 7.

[0064] The virtual gate structure 9 includes a first virtual gate segment 91 and a second virtual gate segment 92 arranged sequentially along a direction perpendicular to the sacrificial substrate 7; the first virtual gate segment 91 partially covers two opposite side surfaces of the first sub-stacked structure 81, and the second virtual gate segment 92 partially covers two opposite side surfaces and the top surface of the second sub-stacked structure 83.

[0065] S2: Form mask structure 4 and etch mask structure 4 and second sub-stack structure 83 to form common sidewall 411 and first groove 11 exposing the isolation sacrificial layer 82.

[0066] Please see Figures 6 to 8 In this step, the mask structure 4 covers the outer surface of the virtual gate structure 9 and the outer surface of the stacked structure 8 that is not covered by the virtual gate structure 9.

[0067] Further, the mask structure 4 covering the upper surface of the virtual gate structure 9 and the first sub-stack structure 81 is etched and removed, thereby exposing the upper surface of the virtual gate structure 9 and the second sub-stack structure 83. Then, using the virtual gate structure 9 as a mask, the second sub-stack structures 83 exposed on both sides of the virtual gate structure 9 are etched and removed, thereby forming the first grooves 11 on both sides of the virtual gate structure 9 to expose the isolation sacrificial layer 82.

[0068] Specifically, the upper surface of the isolation sacrificial layer 82 forms the bottom of the first groove 11.

[0069] In the steps of etching and removing the mask structure 4 covering the upper surface of the virtual gate structure 9 and the first sub-stack structure 81, the mask structure 4 located on the sidewall of the virtual gate structure 9 is not removed, and a portion of the mask structure 4 located on the sidewall of the virtual gate structure 9 is etched to form a common sidewall 411.

[0070] S3: Remove the isolation sacrificial layer 82 and form an isolation layer 5, and form a first transistor 2 on the isolation layer 5.

[0071] In this step, the isolation sacrificial layer 82 is first etched through the first groove 11 to completely remove the isolation sacrificial layer 82, thereby forming a cavity between the first sub-stack structure 81 and the second sub-stack structure 83. Subsequently, a dielectric material, such as silicon nitride, is filled into the cavity by processes such as atomic layer deposition or chemical vapor deposition to form the isolation layer 5.

[0072] Please see Figure 20The first transistor 2 formed in this step includes a first source 22, a first gate 21 and a first drain 23 arranged sequentially along the length direction of the sacrificial substrate 7; wherein, the first channel region 24 of the first transistor 2 is located between two common sidewalls 411, and the first gate 21 is disposed in the first channel region 24.

[0073] Specifically, after the isolation layer 5 is formed, the first source 22 and the first drain 23 of the first transistor 2 are formed in the first groove 11 by selective epitaxial growth process. Then, the second virtual gate segment 92 and the second sacrificial layer 832 are removed, and the gate dielectric layer and gate electrode material are deposited in the released space to finally form the first gate 21 located outside the second semiconductor layer 831.

[0074] After this step is completed, the resulting structure, from bottom to top in a direction perpendicular to the sacrificial substrate 7, includes the sacrificial substrate 7, the first sub-stack structure 81, the isolation layer 5, and the first transistor 2.

[0075] S4: After bonding the substrate 1 to the first transistor 2, remove the sacrificial substrate 7 and expose the first sub-stack structure 81.

[0076] In this step, the substrate 1 is first bonded to the side of the first transistor 2 facing away from the sacrificial substrate 7. At this time, the first transistor 2, the isolation layer 5 and the first sub-stack structure 81 are sandwiched between the substrate 1 and the sacrificial substrate 7. Then the sacrificial substrate 7 is removed to expose the first sub-stack structure 81.

[0077] S5: Forms the second transistor 3.

[0078] Please see Figure 1 , Figures 26 to 30 In this step, the first sub-stack structure 81 is etched and the second transistor 3 is formed.

[0079] Please see Figure 1 The second transistor 3 formed in this step includes a second source 32, a second gate 31 and a second drain 33 arranged sequentially along the length of the substrate 1; wherein, the second channel region 34 of the second transistor 3 is located between two common sidewalls 411, and the second gate 31 is disposed in the second channel region 34.

[0080] After this step is completed, the resulting structure, from bottom to top in a direction perpendicular to the substrate 1, includes the substrate 1, the first transistor 2, the isolation layer 5, and the second transistor 3.

[0081] It should be noted that the length and width directions of the sacrificial substrate 7 are the same as those of the substrate 1.

[0082] The method of forming the second transistor 3 can be the same as or different from the method of forming the first transistor 2, and this application does not impose any restrictions on this. Regardless of the fabrication method used, the second transistor 3 uses the common sidewall 411 as the alignment reference to ensure that its second gate 31, second source 32 and second drain 33 are precisely aligned with the first gate 21, first source 22 and first drain 23 of the first transistor 2 in a direction perpendicular to the substrate 1.

[0083] In the fabrication method of this application, a mask structure 4 including a common sidewall 411 and a virtual gate structure 9 are first constructed as a mask, and the first transistor 2 and the second transistor 3 are formed by layering from top to bottom based on this. This ensures that the first gate 21 and the second gate 31, the first source 22 and the first drain 23, and the second source 32 and the second drain 33 of the first transistor 2 and the second transistor 3 are all restricted by the common sidewall 411 during the manufacturing process, achieving precise alignment and significantly reducing the fabrication difficulty.

[0084] Please see Figure 5 In some embodiments of this application, the step of forming the virtual gate structure 9 includes: S131: A gate oxide layer 14 is formed on the stacked structure 8.

[0085] In this step, a gate oxide layer 14 is formed on the surface of the stacked structure 8 by processes such as thermal oxidation or atomic layer deposition. This layer serves as a temporary gate dielectric layer to protect the stacked structure 8.

[0086] The gate oxide layer 14 is composed of materials including, but not limited to, silicon dioxide.

[0087] S132: A virtual gate layer is formed on the gate oxide layer 14.

[0088] In this step, a dummy gate material is deposited on the surface of the stacked structure 8 using processes such as chemical vapor deposition, physical vapor deposition, and epitaxial growth to form a dummy gate layer. The material of the dummy gate layer includes, but is not limited to, polysilicon.

[0089] S133: Pattern the virtual gate layer to form the virtual gate structure 9.

[0090] In this step, the virtual gate layer is etched to form a virtual gate structure 9 through photolithography and etching processes.

[0091] It should be noted that, in some embodiments, while patterning the virtual gate layer, the gate oxide layer 14 below the virtual gate layer is also etched into a pattern aligned with the virtual gate structure 9.

[0092] In other embodiments, the gate oxide layer 14 may not be patterned when patterning the dummy gate layer; for example... Figure 5 As shown, in this case, the gate oxide layer 14 is a continuous thin film layer, located both between the stacked structure 8 covered by the virtual gate structure 9 and the surface of the stacked structure 8 not covered by the virtual gate structure 9.

[0093] In some embodiments of this application, the step of forming the mask structure 4 and etching the mask structure 4 and the second sub-stack structure 83 to form the common sidewall 411 and the first groove 11 exposing the isolation sacrificial layer 82 includes: S21: A dielectric cover layer 41 is formed on the stacked structure 8 and the virtual gate structure 9.

[0094] In this step, a dielectric material, such as silicon oxide or silicon carbide, is formed on the surface of the exposed stacked structure 8 and the virtual gate structure 9 by deposition processes such as chemical vapor deposition or atomic layer deposition to form a dielectric capping layer 41.

[0095] S22: A first mask layer 42 is formed on the medium covering layer 41.

[0096] In this step, a hard mask material, such as silicon nitride, is formed on the surface of the dielectric capping layer 41 by chemical vapor deposition to form the first mask layer 42.

[0097] The first mask layer 42 and the dielectric covering layer 41 form a mask structure 4.

[0098] For example, please refer to Figure 6 The area of ​​the stacked structure 8 not covered by the virtual gate structure 9 still retains the gate oxide layer 14. Therefore, in step S21, the dielectric capping layer 41 is deposited on the surface of the gate oxide layer 14, that is, the dielectric capping layer 41 covers the surface of the virtual gate structure 9 and the surface of the gate oxide layer 14.

[0099] S23: Etch mask structure 4 and second sub-stack structure 83 to form the first groove 11 exposing the isolation sacrificial layer 82 on both sides of the virtual gate structure 9, and simultaneously form the common sidewall 411 located on the sidewall of the virtual gate structure 9.

[0100] like Figure 6Since the first mask layer 42 covers the sidewalls and top surface of the virtual gate structure 9, and also covers the surface of the second sub-stacked structure 83 not covered by the virtual gate structure 9, in this step, the mask structure 4 is first etched to expose the upper surface covering the second sub-stacked structure 83, and simultaneously expose the top surface of the virtual gate structure 9, while the mask structure 4 covering the sidewalls of the virtual gate structure 9 is retained, thereby etching the dielectric overlay layer 41 located on the sidewalls of the virtual gate structure 9 to form a common sidewall 411; then, the second sub-stacked structure 83 is etched with the virtual gate structure 9 as a shielding structure until the upper surface of the isolation sacrificial layer 82 is exposed, thereby forming a first groove 11 between the two virtual gate structures 9, ultimately forming as shown in the image. Figure 8 The structure shown.

[0101] In some embodiments of this application, after the step of forming the first mask layer 42 on the dielectric overlay layer 41, and before the step of forming the first groove 11 exposing the isolation sacrificial layer 82 on both sides of the virtual gate structure 9 and simultaneously forming the common sidewall 411 located on the sidewall of the virtual gate structure 9, the method further includes: S22A: Forming an isolation structure 27.

[0102] Please see Figure 7 In this step, insulating materials, such as silicon dioxide or silicon nitride, are filled between adjacent stacked structures 8 using processes such as atomic layer deposition or chemical vapor deposition to form an isolation structure 27.

[0103] The isolation structure 27 fills the space between adjacent stacked structures 8, achieving electrical isolation between different stacked structures 8.

[0104] In some embodiments of this application, the step of removing the isolation sacrificial layer 82 and forming the isolation layer 5, and forming the first transistor 2 on the isolation layer 5, includes: S3A: Remove the isolation sacrificial layer 82 and form the isolation layer 5.

[0105] In this step, a wet etching or dry etching process is used to remove the isolation sacrificial layer 82 via the first groove 11. After this step, the area originally occupied by the isolation sacrificial layer 82 is transformed into a cavity extending along the length of the sacrificial substrate 7. This cavity connects to the first groove 11 located on both sides of the virtual gate structure 9, thereby exposing the top surface of the first sub-stack structure 81.

[0106] Subsequently, a dielectric material, such as silicon nitride, is filled into the cavity using processes such as atomic layer deposition or chemical vapor deposition. During the deposition process, the dielectric material fills the cavity released from the original isolation sacrificial layer 82, thereby forming the isolation layer 5.

[0107] The isolation layer 5 is formed on the first sub-stack structure 81, replacing the original isolation sacrificial layer 82. It precisely separates the first transistor 2 and the second transistor 3 to be formed in the direction perpendicular to the sacrificial substrate 7, and becomes an electrical isolation barrier between the first transistor 2 and the second transistor 3.

[0108] S3B: Etch the end of the second sub-stack structure 83 exposed from the sidewall of the first groove 11, so that a portion of the second sub-stack structure 83 is recessed inward to form a back-etching area.

[0109] The second sub-layer structure 83 includes a second semiconductor layer 831 and a second sacrificial layer 832. In this step, a dry etching process is used, utilizing the high etching selectivity between the second semiconductor layer 831 and the second sacrificial layer 832 to perform a lateral etching back on the end of the second sacrificial layer 832 exposed from the sidewall of the first groove 11; the end of the second sacrificial layer 832 is selectively etched inward, while the end of the second semiconductor layer 831 remains unchanged, thereby forming an inwardly recessed etching back region at the end of the second sacrificial layer 832.

[0110] The lateral etching of the end of the second sacrificial layer 832 exposed from the sidewall of the first groove 11 refers to etching the end of the second sacrificial layer 832 in the length direction of the sacrificial substrate 7.

[0111] S3C: An inner sidewall 6 is formed within the engraved area.

[0112] In this step, dielectric material, such as silicon nitride, silicon dioxide, or nitrogen-doped silicon carbide, is fully covered on the sidewalls of the first groove 11, the upper surface of the isolation layer 5, and the etch-back area by deposition processes such as atomic layer deposition or chemical vapor deposition. Subsequently, the dielectric material outside the etch-back area is removed by dry etching, leaving only the dielectric material in the etch-back area, thereby forming the inner sidewall 6.

[0113] S3D: The first source 22 and the first drain 23 of the first transistor 2 are formed on the isolation layer 5.

[0114] In this step, a highly doped semiconductor material is grown on the isolation layer 5 by selective epitaxy to fill the first groove 11, thereby forming the first source 22 and the first drain 23 of the first transistor 2.

[0115] S3E: Remove a portion of the virtual gate structure 9 and a portion of the second sub-stack structure 83 to form the first gate 21 of the first transistor 2.

[0116] Specifically, in this step, the second virtual gate segment 92 of the virtual gate structure 9 is removed to form a gate cavity, which exposes the second semiconductor layer 831 and the second sacrificial layer 832 in the second sub-stack structure 83. Then, the second sacrificial layer 832 is removed. Finally, a gate dielectric layer and a gate electrode material are sequentially deposited on the surface of the second semiconductor layer 831 to form the first gate 21.

[0117] It should be noted that the second semiconductor layer 831 forms the first channel layer 241 of the first transistor 2.

[0118] In other embodiments of this application, the step of removing the isolation sacrificial layer 82 and forming the isolation layer 5, and forming the first transistor 2 on the isolation layer 5, may further include: S31: Etch the end of the second sub-stack structure 83 exposed from the sidewall of the first groove 11, so that a portion of the second sub-stack structure 83 is recessed inward to form a back-etching area.

[0119] The second sub-layer structure 83 includes a second semiconductor layer 831 and a second sacrificial layer 832. In this step, a dry etching process is used, utilizing the high etching selectivity between the second semiconductor layer 831 and the second sacrificial layer 832 to perform a lateral etching back on the end of the second sacrificial layer 832 exposed from the sidewall of the first groove 11; the end of the second sacrificial layer 832 is selectively etched inward, while the end of the second semiconductor layer 831 remains unchanged, thereby forming an inwardly recessed etching back region at the end of the second sacrificial layer 832.

[0120] The lateral etching of the end of the second sacrificial layer 832 exposed from the sidewall of the first groove 11 refers to etching the end of the second sacrificial layer 832 in the length direction of the sacrificial substrate 7.

[0121] S32: An inner wall 6 is formed within the engraved area.

[0122] Please see Figure 9 In this step, dielectric material, such as silicon nitride, silicon dioxide, or nitrogen-doped silicon carbide, is fully covered on the sidewalls of the first groove 11, the upper surface of the isolation sacrificial layer 82, and the etch-back area by deposition processes such as atomic layer deposition or chemical vapor deposition. Subsequently, the dielectric material outside the etch-back area is removed by dry etching, leaving only the dielectric material in the etch-back area, thereby forming the inner sidewall 6.

[0123] S33: Remove the isolation sacrificial layer 82 and form the isolation layer 5.

[0124] In this step, a wet etching or dry etching process is used to remove the isolation sacrificial layer 82 via the first groove 11. After this step, the area occupied by the original isolation sacrificial layer 82 is transformed into a cavity extending along the length of the sacrificial substrate 7. This cavity connects to the first groove 11 located on both sides of the virtual gate structure 9 in a direction perpendicular to the sacrificial substrate 7, thereby exposing the top surface of the first sub-stacked structure 81.

[0125] Subsequently, a dielectric material, such as silicon nitride, is filled into the cavity using processes such as atomic layer deposition or chemical vapor deposition. During the deposition process, the dielectric material fills the cavity released from the original isolation sacrificial layer 82, thereby forming the isolation layer 5.

[0126] The isolation layer 5 is formed on the first sub-stack structure 81, replacing the original isolation sacrificial layer 82. It precisely separates the first transistor 2 and the second transistor 3 to be formed in the direction perpendicular to the sacrificial substrate 7, and becomes an electrical isolation barrier between the first transistor 2 and the second transistor 3.

[0127] S34: The first source 22 and the first drain 23 of the first transistor 2 are formed on the isolation layer 5.

[0128] Please see Figure 15 In this step, a highly doped semiconductor material is grown on the isolation layer 5 by selective epitaxy to fill the first groove 11, thereby forming the first source 22 and the first drain 23 of the first transistor 2.

[0129] S35: Remove a portion of the virtual gate structure 9 and a portion of the second sub-stack structure 83 to form the first gate 21 of the first transistor 2.

[0130] Please see Figures 19 to 20 In this step, the second virtual gate segment 92 of the virtual gate structure 9 is removed to form a gate cavity, which exposes the second semiconductor layer 831 and the second sacrificial layer 832 in the second sub-stack structure 83. Then the second sacrificial layer 832 is removed. Finally, a gate dielectric layer and a gate electrode material are sequentially deposited on the surface of the second semiconductor layer 831 to form the first gate 21.

[0131] It should be noted that the second semiconductor layer 831 forms the first channel layer 241 of the first transistor 2.

[0132] The above-described steps S3A to S3E and steps S31 to S35 represent two different implementations of step S3, differing only in the order in which the inner wall 6 and the isolation layer 5 are formed. Specifically, steps S3A to S3E involve forming the isolation layer 5 first, followed by the inner wall 6, while steps S31 to S35 involve forming the inner wall 6 first, followed by the isolation layer 5. This application does not restrict the order in which the inner wall 6 and the isolation layer 5 are formed.

[0133] Please refer to it again. Figure 5 When the virtual gate structure 9 covers the stacked structure 8, a portion of the virtual gate structure 9 will cover the sidewall of the isolation sacrificial layer 82. The portion of the virtual gate structure 9 covering the sidewall of the isolation sacrificial layer 82 is defined as the third virtual gate segment 93. That is, the third virtual gate segment 93 is disposed between the first virtual gate segment 91 and the second virtual gate segment 92. During the removal of the second virtual gate segment 92 in step S3E or step S35, at least a portion of the third virtual gate segment 93 may be removed simultaneously or the third virtual gate segment 93 may not be removed.

[0134] For example, such as Figure 18 As shown, in step S3E or step S35, during the process of removing the second virtual gate segment 92, a portion of the third virtual gate segment 93 is removed simultaneously.

[0135] In some embodiments of this application, after the step of removing the isolation sacrificial layer 82 and forming the isolation layer 5, and before the step of forming the first source 22 and the first drain 23 of the first transistor 2 on the isolation layer 5, the method includes: S3A: Remove the first mask layer 42.

[0136] Please see Figure 14 The first mask layer 42 in the mask structure 4 covering the sidewall of the virtual gate structure 9 is selectively removed by wet etching or dry etching process. After etching, the first mask layer 42 located on the sidewall of the first groove 11 is removed, thereby exposing the common sidewall 411 located in the fabrication area of ​​the first transistor 2, so that the first source 22 and the first drain 23 can be selectively epitaxially grown with the common sidewall 411 as the boundary.

[0137] It should be noted that in this step, since only the first transistor 2 is being fabricated, the first mask layer 42 located in the subsequent fabrication area of ​​the second transistor 3 is not removed. Specifically, the portion of the first mask layer 42 covering the surface of the first sub-stack structure 81 and located below the isolation layer 5 is completely retained.

[0138] In some embodiments of this application, the step of removing the isolation sacrificial layer 82 and forming the isolation layer 5 includes: S331: Form an etch barrier layer 15.

[0139] Please see Figure 10 In this step, an etch barrier layer 15 is applied to the entire surface of the structure after the inner sidewall 6 has been formed. Specifically, the etch barrier layer 15 covers the top of the virtual gate structure 9, the outer surface of the mask structure 4, the surface of the inner sidewall 6, the sidewall of the first groove 11, and the upper surface of the isolation sacrificial layer 82.

[0140] S332: Etch the etch barrier layer 15 to expose the isolation sacrificial layer 82.

[0141] Please see Figure 11 In this step, the etching process removes the etching barrier layer 15 located on the upper surface of the isolation sacrificial layer 82, thereby exposing the isolation sacrificial layer 82. At the same time, the etching barrier layer 15 located on the top of the virtual gate structure 9 is also removed simultaneously, while the etching barrier layer 15 located on the sidewall of the first groove 11 is retained, that is, the inner sidewall 6 and the surface of the mask structure 4 are covered with the etching barrier layer 15.

[0142] S333: Etch away the isolation sacrificial layer 82.

[0143] Please see Figure 12 In this step, a wet etching or dry etching process is used to etch the isolation sacrificial layer 82 to remove the isolation sacrificial layer 82 exposed from the first groove 11 and the isolation sacrificial layer 82 covered by the virtual gate structure 9, so that the area occupied by the isolation sacrificial layer 82 forms a cavity. The cavity connects to the first groove 11 located on both sides of the virtual gate structure 9 and exposes the top surface of the first sub-stack structure 81.

[0144] S334: Form the isolation layer 5.

[0145] Please see Figure 13 In this step, a dielectric material is filled into the cavity formed after removing the isolation sacrificial layer 82 using a deposition process to form the isolation layer 5. The isolation layer 5 completely fills the cavity between the first sub-stack structure 81 and the second sub-stack structure 83, with its top surface flush with the bottom of the first groove 11 and its bottom surface in direct contact with the top surface of the first sub-stack structure 81. Furthermore, the side and top surfaces of the isolation layer 5 also contact the inner surface of the common sidewall 411.

[0146] Through the above-described structural arrangement of the isolation layer 5, the isolation layer 5 serves as an electrical isolation barrier between the subsequently formed first transistor 2 and second transistor 3 in a direction perpendicular to the sacrificial substrate 7. The isolation layer 5 is an integral structure and contacts the common sidewall 411, enabling it to more comprehensively block potential leakage current paths and signal crosstalk between the first transistor 2 and the second transistor 3.

[0147] In some embodiments of this application, after the step of forming the first source 22 and the first drain 23 of the first transistor 2 on the isolation layer 5, and before the step of removing a portion of the virtual gate structure 9 and a portion of the second sub-stack structure 83 and forming the first gate 21 of the first transistor 2, the method includes: S341: Form the first etch stop material layer and the first interlayer dielectric layer 17.

[0148] Please see Figure 16 In this step, a dielectric material is deposited on the surface of the first source 22, the first drain 23 and the virtual gate structure 9 by a process such as chemical vapor deposition or atomic layer deposition to form a first etch stop material layer.

[0149] Furthermore, an interlayer dielectric material layer is deposited on the first etch stop material layer using processes such as chemical vapor deposition. This interlayer dielectric material layer fills the gaps formed by the first source 22, the first drain 23, and the dummy gate structure 9. Then, the first etch stop material layer and the interlayer dielectric material layer are planarized until the first etch stop material layer on top of the dummy gate structure 9 is exposed, thereby forming the first interlayer dielectric layer 17 located above the first source 22 and the first drain 23.

[0150] S342: Etch the first etch stop material layer to expose the virtual gate structure 9.

[0151] Please see Figure 17 In this step, the first etch stop material layer is etched using a dry etching process to remove the first etch stop material layer located on top of the virtual gate structure 9, thereby exposing the top of the virtual gate structure 9 and forming the first etch stop layer 16. The first etch stop layer 16 is located between the first source 22, the first drain 23 and the first interlayer dielectric layer 17.

[0152] In some embodiments of this application, the step of forming the first transistor 2 on the isolation layer 5, after which and before the step of bonding the substrate 1 to the first transistor 2, includes: S36: Forming a first dielectric layer 25 and a first contact metal layer 26 located in the first dielectric layer 25.

[0153] Please see Figure 21In this step, a first dielectric layer 25 is formed on the surface of the completed first gate 21 structure by a deposition process. Subsequently, contact holes are formed in the first dielectric layer 25 to expose the first source 22, the first drain 23 and the first gate 21 respectively by photolithography and etching processes, and metal material is filled in the contact holes to form a first contact metal layer 26. The first source 22, the first drain 23 and the first gate 21 are electrically connected to at least one of the first contact metal layers 26 to realize the electrical connection between the first transistor 2 and the external circuit.

[0154] In some embodiments of this application, the step of removing the sacrificial substrate 7 after bonding the substrate 1 over the first transistor 2 and exposing the first sub-stack structure 81 includes: S41: The substrate 1 is bonded to the side of the first transistor 2 away from the sacrificial substrate 7 to form an intermediate semiconductor structure 12.

[0155] Please see Figure 22 In this step, after the first transistor 2 is formed, the substrate 1 is bonded to the surface of the first transistor 2 away from the sacrificial substrate 7 by wafer bonding technology to form an intermediate semiconductor structure 12. The intermediate semiconductor structure 12 includes the substrate 1, the sacrificial substrate 7, and the first transistor 2, the isolation layer 5, and the first sub-stack structure 81 sandwiched between the substrate 1 and the sacrificial substrate 7.

[0156] S42: Flip the intermediate semiconductor structure 12 and remove the sacrificial substrate 7 to expose the first sub-stack structure 81.

[0157] Please see Figures 23 to 25 In this step, the entire intermediate semiconductor structure 12 is flipped, that is, flipped 180 degrees, so that the sacrificial substrate 7, which was originally located at the bottom, becomes the processing surface. Then the sacrificial substrate 7 is removed, thereby exposing the surface of the first sub-stack structure 81 away from the substrate 1.

[0158] In some embodiments of this application, the step of removing the sacrificial substrate 7 to expose the first sub-stacked structure 81 in the stacked structure 8 includes: S421: Thin the sacrificial substrate 7.

[0159] Please see Figure 24 In this step, a chemical mechanical polishing process is used to thin the sacrificial substrate 7 from the side away from the first sub-layer structure 81 to reduce the thickness of the sacrificial substrate 7.

[0160] For example, after chemical mechanical polishing, the thickness of the sacrificial substrate 7 is 100~200nm.

[0161] S422: Etch the thinned sacrificial substrate 7 until the first sub-stack structure 81 is exposed.

[0162] Please see Figure 25 In this step, the sacrificial substrate 7 is removed using a wet etching or dry etching process. The etching process terminates on the surface of the first sub-stacked structure 81, thereby exposing the first sub-stacked structure 81.

[0163] In some embodiments of this application, the step of forming the second transistor 3 includes: S51: Etch the first sub-stack structure 81 to form a second groove 13 on both sides of the virtual gate structure 9 to expose the isolation layer 5.

[0164] Please see Figure 28 In this step, the first sub-stack structure 81 is etched with the virtual gate structure 9 as a shielding structure until the surface of the isolation layer 5 is exposed, thereby forming a second groove 13 between the two virtual gate structures 9.

[0165] S52: The second source 32 and the second drain 33 of the second transistor 3 are formed in the second groove 13.

[0166] Please see Figure 29 In this step, highly doped semiconductor material is selectively epitaxially grown on the isolation layer 5 to fill the second groove 13, thereby forming the second source 32 and the second drain 33 of the second transistor 3.

[0167] S53: Remove a portion of the virtual gate structure 9 and a portion of the first sub-stack structure 81, and form the second gate 31 of the second transistor 3.

[0168] Please see Figure 1 and Figure 30 In this step, the first virtual gate segment 91 in the virtual gate structure 9 is removed to form a gate cavity, which exposes the first semiconductor layer 812 and the first sacrificial layer 811 in the first sub-stack structure 81. Then the first sacrificial layer 811 is removed. Finally, a gate dielectric layer and a gate electrode material are sequentially deposited on the surface of the first semiconductor layer 812 to form the second gate 31.

[0169] It should be noted that the first semiconductor layer 812 forms the second channel layer 341 of the second transistor 3.

[0170] Furthermore, if step S35 or step S3E has completely removed the third virtual gate segment 93, then this step only needs to remove the first virtual gate segment 91; if step S35 or step S3E has not removed the third virtual gate segment 93, then this step removes the first virtual gate segment 91 and the third virtual gate segment 93 simultaneously; if step S35 or step S3E has only removed a part of the third virtual gate segment 93, then this step removes the remaining part of the third virtual gate segment 93.

[0171] For example, in step S3E or step S35, a portion of the third virtual gate segment 93 is removed simultaneously during the removal of the second virtual gate segment 92, so in step S53, another portion of the third virtual gate segment 93 is removed simultaneously when the first virtual gate segment 91 is removed.

[0172] In some embodiments of this application, prior to the step of etching the first sub-stack structure 81 to form a second groove 13 exposing the isolation layer 5 on both sides of the virtual gate structure 9, the method further includes: S501: Etch the virtual gate structure 9.

[0173] Please see Figure 26 In this step, the upper portion of the exposed second virtual gate segment 92 is etched by wet etching or dry etching process to reduce the size of the second virtual gate segment 92 in the direction perpendicular to the substrate 1.

[0174] For example, the top surface of the second virtual gate segment 92 is etched to be substantially flush with the top surface of the first sub-stack structure 81.

[0175] S502: Form the second mask layer 18.

[0176] Please see Figure 27 In this step, a second mask layer 18 is deposited on the top surface of the second virtual gate segment 92 and the top surface of the first sub-stacked structure 81 within the coverage area of ​​the virtual gate structure 9 by a deposition process. The second mask layer 18 will serve as an etching mask during the subsequent etching of the first sub-stacked structure 81, protecting the first sub-stacked structure 81 within the coverage area of ​​the virtual gate structure 9 from damage.

[0177] In some embodiments of this application, the step of forming the second source 32 and the second drain 33 of the second transistor 3 within the second groove 13 includes: S521: Etch the end of the first sub-stack structure 81 exposed from the sidewall of the second groove 13 so that a portion of the first sub-stack structure 81 is recessed inward to form a back-etching area.

[0178] The first sub-layer structure 81 includes a first sacrificial layer 811 and a first semiconductor layer 812. In this step, a dry etching process is used, utilizing the high etching selectivity between the first semiconductor layer 812 and the first sacrificial layer 811 to perform a lateral etching back on the end of the first sacrificial layer 811 exposed from the sidewall of the second groove 13; the end of the first sacrificial layer 811 is selectively etched inward, while the end of the first semiconductor layer 812 remains unchanged, thereby forming an inwardly recessed etching back region at the end of the first sacrificial layer 811.

[0179] S522: An inner wall 6 is formed within the engraved area.

[0180] In this step, dielectric material, such as silicon nitride, silicon dioxide, or nitrogen-doped silicon carbide, is fully covered on the sidewalls of the second groove 13, the upper surface of the isolation layer 5, and the etch-back area by deposition processes such as atomic layer deposition or chemical vapor deposition. Subsequently, the dielectric material outside the etch-back area is removed by dry etching, leaving only the dielectric material in the etch-back area, thereby forming the inner sidewall 6.

[0181] S523: Remove the first mask layer 42 in the mask structure 4.

[0182] In this step, the first mask layer 42 covering the surface of the first sub-stack structure 81 is removed by wet etching or dry etching process. After etching is completed, the first mask layer 42 is completely removed, thereby exposing the common sidewall 411 located in the fabrication area of ​​the second transistor 3, so that selective epitaxial growth can be performed with the common sidewall 411 as the boundary when the second source 32 and the second drain 33 are subsequently formed.

[0183] S524: Forming the second source 32 and the second drain 33 of the second transistor 3.

[0184] In this step, a highly doped semiconductor material is grown on the isolation layer 5 by selective epitaxy to fill the second groove 13, forming the second source 32 and the second drain 33 of the second transistor 3.

[0185] In some embodiments of this application, after the step of forming the second source 32 and the second drain 33 of the second transistor 3 in the second recess 13, and before the step of removing a portion of the dummy gate structure 9 and a portion of the first sub-stack structure 81 and forming the second gate 31 of the second transistor 3, the method includes: S52A: Forming a second etch stop material layer and a second interlayer dielectric layer 20.

[0186] Please see Figure 29In this step, a dielectric material is deposited on the surface of the first source 22, the first drain 23 and the virtual gate structure 9 by a process such as chemical vapor deposition or atomic layer deposition to form a second etch stop material layer.

[0187] Furthermore, an interlayer dielectric material layer is deposited on the second etch stop material layer using processes such as chemical vapor deposition. This interlayer dielectric material layer fills the gaps formed by the second source 32, the second drain 33, and the dummy gate structure 9. Then, the second etch stop material layer and the interlayer dielectric material layer are planarized until the second etch stop material layer on top of the dummy gate structure 9 is exposed, thereby forming the second interlayer dielectric layer 20 located above the second source 32 and the second drain 33.

[0188] S52B: Etch the second etch stop material layer to expose the virtual gate structure 9.

[0189] In this step, the second etch stop material layer is etched using a dry etching process to remove the second etch stop material layer located on top of the virtual gate structure 9, thereby exposing the top of the virtual gate structure 9 and forming the second etch stop layer 19. The second etch stop layer 19 is located between the second source 32, the second drain 33, and the second interlayer dielectric layer 20.

[0190] In some embodiments of this application, after the step of forming the second transistor 3, the following is included: S6: Form a second dielectric layer 35 and a second contact metal layer 36 located in the second dielectric layer 35.

[0191] Please see Figure 1 In this step, a second dielectric layer 35 is formed on the surface of the completed second gate 31 structure by a deposition process. Subsequently, contact holes are formed in the second dielectric layer 35 to expose the second source 32, the second drain 33 and the second gate 31 respectively by photolithography and etching processes, and metal material is filled in the contact holes to form a second contact metal layer 36. The second source 32, the second drain 33 and the second gate 31 are electrically connected to at least one of the second contact metal layers 36 to realize the electrical connection between the second transistor 3 and the external circuit.

[0192] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the patent protection scope of the present invention.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate; A first transistor and a second transistor, wherein the first transistor is disposed on the substrate, the second transistor is disposed on the first transistor, and an isolation layer is disposed between the first transistor and the second transistor. The first transistor includes a first gate and a first channel region, wherein the first gate is disposed in the first channel region. The second transistor includes a second gate and a second channel region, wherein the second gate is disposed in the second channel region. and Two common sidewalls are disposed opposite to each other on the substrate. The first channel region and the second channel region are aligned in a direction perpendicular to the substrate and are located between the two common sidewalls.

2. The semiconductor device structure as described in claim 1, characterized in that, The first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain; The first source electrode and the second source electrode are aligned in a direction perpendicular to the substrate, and the first drain electrode and the second drain electrode are aligned in a direction perpendicular to the substrate. A portion of the isolation layer is disposed between the first source electrode and the second source electrode and between the first drain electrode and the second drain electrode, and another portion of the isolation layer is disposed between the first channel region and the second channel region; or The first source and the second drain are aligned in a direction perpendicular to the substrate, and the first drain and the second source are aligned in a direction perpendicular to the substrate. A portion of the isolation layer is disposed between the first source and the second drain and between the first drain and the second source, and another portion of the isolation layer is disposed between the first channel region and the second channel region.

3. The semiconductor device structure as described in claim 2, characterized in that, The first channel region includes multiple first channel layers, the first channel layer closest to the isolation layer being the first top channel layer, which is disposed between the first gate and the isolation layer; and / or The second channel region includes multiple second channel layers, with the second channel layer closest to the isolation layer being the first bottom channel layer, which is disposed between the second gate and the isolation layer.

4. The semiconductor device structure as described in claim 2, characterized in that, The semiconductor device structure further includes a plurality of inner sidewalls, which are disposed between the first gate, the first source, and the first drain of the first transistor and between the second gate, the second source, and the second drain of the second transistor.

5. The semiconductor device structure as described in claim 2, characterized in that, The semiconductor device structure further includes a first dielectric layer, which is disposed between the first transistor and the substrate. The first dielectric layer contains a plurality of first contact metal layers, and the first source, the first drain and the first gate are electrically connected to at least one of the first contact metal layers. The second transistor further includes a second dielectric layer disposed on the side of the second transistor away from the first transistor. The second dielectric layer contains a plurality of second contact metal layers, and the second source, the second drain, and the second gate are electrically connected to at least one of the second contact metal layers.

6. A method for fabricating a semiconductor device structure, used to fabricate the semiconductor device structure as described in any one of claims 1 to 5, characterized in that, Includes the following steps: A sacrificial substrate is provided, and a stacked structure and a virtual gate structure are formed on the sacrificial substrate, the stacked structure including a first sub-stacked structure, an isolation sacrificial layer and a second sub-stacked structure; A mask structure is formed, and the mask structure and the second sub-stack structure are etched to form a common sidewall and a first groove that exposes the isolation sacrificial layer; The isolation sacrificial layer is removed and an isolation layer is formed, and a first transistor is formed on the isolation layer; After bonding the substrate to the first transistor, the sacrificial substrate is removed, exposing the first sub-stack structure; A second transistor is formed.

7. The preparation method according to claim 6, characterized in that, The step of forming a mask structure and etching the mask structure and the second sub-stacked structure to form a common sidewall and expose a first groove of the isolation sacrificial layer includes: A dielectric overlay layer is formed on the stacked structure and the virtual gate structure; A first mask layer is formed on the dielectric cover layer, and the first mask layer and the dielectric cover layer form the mask structure; The mask structure and the second sub-stack structure are etched to form the first grooves that expose the isolation sacrificial layer on both sides of the virtual gate structure, and at the same time, the common sidewalls located on the sidewalls of the virtual gate structure are formed.

8. The preparation method according to claim 7, characterized in that, The step of removing the isolation sacrificial layer and forming an isolation layer, and forming a first transistor on the isolation layer, includes: Remove the isolation sacrificial layer and form the isolation layer; The end of the second sub-stack structure exposed from the sidewall of the first groove is etched to cause a portion of the second sub-stack structure to be recessed inward to form a back-etching area; An inner wall is formed within the engraved area; A first source and a first drain of a first transistor are formed on the isolation layer; A portion of the virtual gate structure and a portion of the second sub-stack structure are removed to form the first gate of the first transistor.

9. The preparation method according to claim 7, characterized in that, The step of removing the isolation sacrificial layer and forming an isolation layer, and forming a first transistor on the isolation layer, includes: The end of the second sub-stack structure exposed from the sidewall of the first groove is etched to cause a portion of the second sub-stack structure to be recessed inward to form a back-etching area; An inner wall is formed within the engraved area; Remove the isolation sacrificial layer and form the isolation layer; A first source and a first drain of a first transistor are formed on the isolation layer; A portion of the virtual gate structure and a portion of the second sub-stack structure are removed to form the first gate of the first transistor.

10. The preparation method according to claim 9, characterized in that, The step of removing the isolation sacrificial layer and forming the isolation layer includes: Forming an etching barrier layer; Etch the etch barrier layer to expose the isolation sacrificial layer; Etching removes the isolation sacrificial layer; The isolation layer is formed.

11. The preparation method according to claim 8 or 9, characterized in that, After the step of removing the isolation sacrificial layer and forming the isolation layer, and before the step of forming the first source and first drain of the first transistor on the isolation layer, the method includes: Remove the first mask layer.

12. The preparation method according to claim 6, characterized in that, The step of removing the sacrificial substrate after bonding the substrate to the first transistor and exposing the first sub-stack structure includes: A substrate is bonded to the side of the first transistor away from the sacrificial substrate to form an intermediate semiconductor structure; The intermediate semiconductor structure is flipped, and the sacrificial substrate is removed to expose the first sub-stack structure.

13. The preparation method according to claim 12, characterized in that, The step of removing the sacrificial substrate to expose the first sub-stack structure includes: Thinning of the sacrificial substrate; The thinned sacrificial substrate is etched until the first sub-stack structure is exposed.

14. The preparation method according to claim 12, characterized in that, The step of forming the second transistor includes: The first sub-stack structure is etched to form a second groove on both sides of the virtual gate structure to expose the isolation layer; The second source and the second drain of the second transistor are formed in the second groove; A portion of the virtual gate structure and a portion of the first sub-stack structure are removed to form the second gate of the second transistor.

15. The preparation method according to claim 6, characterized in that, After the step of forming the first transistor on the isolation layer and before the step of bonding the substrate to the first transistor, the method includes: Forming a first dielectric layer and a first contact metal layer located in the first dielectric layer; and / or Following the step of forming the second transistor, the following is included: A second dielectric layer and a second contact metal layer located in the second dielectric layer are formed.

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