Electrostatic discharge device and method of operating same

Abstract

According to some embodiments, a device includes a reference power pad, a negative power pad, a resistor connected to the negative power pad, and a first transistor connected to the reference power pad and the negative power pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power pad in response to an electrostatic voltage being applied to one of the reference power pad or the negative power pad.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically, to electrostatic discharge (ESD) protection circuits for negative power pads. Background Technology

[0002] Integrated circuit (IC) devices may include ESD protection circuitry designed to protect the IC from transient events such as ESD events and surges. ESD protection circuitry is typically designed to conduct during an ESD event and form a current discharge path to shunt large ESD currents and clamp the voltages of input / output (I / O) pads and power pads to sufficiently low levels to prevent IC damage. ESD protection circuitry typically promotes low-resistance paths to suppress voltage buildup to levels that could cause damage. Summary of the Invention

[0003] The present invention is provided in a simplified form to introduce the concepts, which will be further described in the following detailed description. The present invention is not intended to identify key elements or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0004] According to some embodiments, a device includes a reference power pad, a negative power pad, a resistor connected to the negative power pad, and a first transistor connected to the reference power pad and the negative power pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power pad in response to an electrostatic voltage applied to one of the reference power pad or the negative power pad.

[0005] According to some embodiments, a device includes: a substrate; a metallization structure on the substrate, the metallization structure including a reference power pad and a negative power pad; a first well having a first conductivity type in the substrate; a second well having a second conductivity type in the first well; a first contact having a first conductivity type in the second well and connected to the reference power pad; a second contact having a first conductivity type in the second well and connected to the negative power pad; a first gate electrode between the first contact and the second contact; and a resistor connected between the first gate electrode and the negative power pad.

[0006] According to some embodiments, a method includes: connecting a resistor to a negative power pad; connecting a first transistor between a reference power pad and the negative power pad; connecting a resistor to a first gate electrode of the first transistor; and shunting current to the negative power pad via the first transistor in response to an electrostatic voltage applied to the reference power pad.

[0007] According to some embodiments, a system includes: a unit for connecting a resistor to a negative power pad; a unit for connecting a first transistor between a reference power pad and a negative power pad; a unit for connecting a resistor to a first gate electrode of the first transistor; and a unit for shunting current to the negative power pad via the first transistor in response to an electrostatic voltage applied to the reference power pad.

[0008] To achieve the foregoing and related objectives, the following description and accompanying drawings illustrate certain illustrative aspects and embodiments. These are merely examples of a variety of ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of this disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1A This is a schematic diagram of an integrated circuit device having an electrostatic discharge protection circuit connected to a negative power supply pad, according to some embodiments.

[0010] Figure 1B and 1C This is a diagram illustrating the operation of an electrostatic discharge protection circuit according to some embodiments.

[0011] Figure 2 This is a cross-sectional view of an electrostatic discharge protection circuit according to some embodiments.

[0012] Figure 3 This is a layout diagram of an electrostatic discharge protection circuit according to some embodiments.

[0013] Figure 4 This is a flowchart of a method for providing electrostatic discharge protection according to some embodiments. Detailed Implementation

[0014] The claimed subject matter will now be described with reference to the accompanying drawings, wherein similar reference numerals are used throughout to denote similar elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent, however, that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0015] Equivalent or similar elements, or elements with equivalent or similar functions, are indicated by equivalent or similar reference numerals in the following description. Because identical or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of elements with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals are interchangeable.

[0016] In this regard, directional terms such as "top," "bottom," "below," "above," "front," "back," "rear," "front," and "rear" may be used with reference to the orientation of the described figures. Because components of the embodiments can be positioned in multiple different orientations, these directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be considered limiting.

[0017] It should be understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", etc.).

[0018] In the embodiments described herein or illustrated in the accompanying drawings, any direct electrical connection or coupling (i.e., any connection or coupling without additional intermediate elements) may also be achieved by an indirect connection or coupling (i.e., a connection or coupling with one or more additional intermediate elements), or vice versa, as long as the overall purpose of the connection or coupling (e.g., for transmitting a signal or transmitting information) is essentially preserved. Features from different embodiments may be combined to form other embodiments. For example, unless otherwise stated, variations or modifications described with respect to one embodiment may also apply to other embodiments.

[0019] The term “substantially” can be used herein to describe small manufacturing tolerances (e.g., within 5%) that are considered acceptable in the industry without departing from the embodiments described herein.

[0020] In integrated circuit (IC) devices, an external power supply is connected to the pads of the IC device to provide one or more supply voltages or reference voltages (e.g., ground). The supply voltage can be positive or negative relative to the reference voltage. One challenge in providing ESD protection for negative power supply pads is avoiding forward biasing the protection device (e.g., a diode) during normal operation so that the IC device component being supplied with a negative power supply voltage can operate correctly.

[0021] Figure 1AThis is a schematic diagram of an integrated circuit device 100 including an electrostatic discharge (ESD) protection circuit 102 connected to a negative power supply pad 104, according to some embodiments. In some embodiments, the IC device 100 includes a positive power supply pad 106 and a reference power supply pad 108. The reference power supply voltage (V) is relative to the provided reference power supply voltage. REF For example, grounding, positive power supply voltage (V) POS A positive power supply voltage (V) is applied to the positive power pad 106, and a negative power supply voltage (V) is applied to the negative power pad 106. NEG In normal operating mode, a negative power supply pad 104 is applied. ESD protection circuitry 102 shunts current from ESD events to prevent damage to protected circuitry 109A, 109B, and / or 109C connected to one or more of pads 104, 106, and / or 108. Example protected circuitry 109A, 109B, and / or 109C includes memory device circuitry, logic device circuitry, switching circuitry, power regulator circuitry, amplifier circuitry, sensor circuitry, or other circuitry with components sensitive to ESD events.

[0022] In some embodiments, the ESD protection circuit 102 includes cascaded transistors 110, 112 connected between a negative power pad 104 and a reference power pad 108 to shunt current generated by an ESD event. In some embodiments, the gate terminal of transistor 112 is connected to the negative power pad 104 via a resistor 114 to keep transistor 112 in a cutoff state during normal operation. The gate terminal of transistor 110 may be connected to resistor 114. In an alternative embodiment, the gate terminal of transistor 110 may be floating and may be connected to the reference power pad 108 via a resistor (not shown), or may be connected to the drain of transistor 112 via a resistor (not shown). Although transistors 110, 112 remain in a cutoff state during normal operation, the body diodes 110B, 112B of transistors 110 and 112 conduct current in response to an ESD event. In some embodiments, the number of transistors 110 and 112 (e.g., from 1 to N) depends on the voltage protection requirements of the IC device 100. At least the last transistor 112 has a gate terminal connected to the negative power supply pad 104 via a resistor 114.

[0023] In some embodiments, additional ESD protection is provided by a diode 116 connected between the negative power pad 104 and the reference power pad 108, a diode 118 connected between the reference power pad 108 and the positive power pad 106, or a power clamping circuit 120 connected between the positive power pad 106 and the reference power pad 108. In some embodiments, the anode of diode 116 is connected to the negative power pad 104, and the anode of diode 118 is connected to the reference power pad 108. In some embodiments, the power clamping circuit 120 is an ESD protection structure that is off during normal operation and on during an ESD event to conduct current to maintain the voltage at a safe level to protect the power pads 106, 108 from overvoltage damage.

[0024] ESD protection circuit 102 provides an ESD discharge path 122 from negative power pad 104 to reference power pad 108 or an ESD discharge path 124 from reference power pad 108 to negative power pad 104. In some embodiments, diode 116 is biased to provide an ESD discharge path 126 from negative power pad 104 to reference power pad 108, diode 118 is biased to provide an ESD discharge path 128 from reference power pad 108 to positive power pad 106, and power clamping circuit 120 is biased to provide an ESD discharge path 130 from reference power pad 108 to positive power pad 106 or an ESD discharge path 132 from positive power pad 106 to reference power pad 108. ESD events can have positive or negative polarity, so the ESD discharge paths 122, 124, 126, 128, 130, and 132 activated for a given ESD event depend on the polarity of the ESD event and the pads 104, 106, and 108 where the ESD event occurred.

[0025] Figure 1B and 1C This is a diagram illustrating the operation of an electrostatic discharge protection circuit 102 according to some embodiments. Figure 1B The current-voltage (IV) curve 140 is shown, which illustrates the operation of cascaded transistors 110, 112 in reverse bias mode activating ESD discharge path 124 to discharge current through negative power pad 104 in response to a positive ESD voltage applied to reference power pad 108.

[0026] Figure 1BIV curve 142 is also shown, illustrating the operation of the power clamping circuit 120 activating the ESD discharge path 132 and the operation of the cascaded transistors 110, 112 in reverse bias mode activating the ESD discharge path 124 to discharge current through the negative power pad 104 in response to a positive ESD voltage applied to the positive power pad 106. IV curves 140 and 142 show the voltage increase across the cascaded transistors 110, 112 until the breakdown voltage of the body diodes 110B, 112B is reached and a snapback occurs.

[0027] Figure 1C IV curve 150 is shown, illustrating the operation of cascaded transistors 110, 112 in forward bias mode, activating ESD discharge path 122 to discharge current through reference power pad 108 in response to a positive ESD voltage applied to negative power pad 104. Diode 116 is also activated in response to the positive ESD voltage applied to negative pad 104 to enable ESD discharge path 126.

[0028] Figure 1C IV curve 152 is also shown, illustrating the operation of the power clamping circuit 120 activating the ESD discharge path 130 and the operation of cascaded transistors 110, 112 in forward bias mode activating the ESD discharge path 122 to discharge current through the positive power pad 106 in response to a positive ESD voltage applied to the negative power pad 104. IV curves 150 and 152 show the voltage increase across cascaded transistors 110, 112 until the threshold voltage of body diodes 110B, 112B is reached and conduction occurs. In response to a positive ESD voltage applied to the negative power pad 104, diodes 116, 118 are also activated to enable ESD discharge paths 126, 128, respectively.

[0029] Figure 2This is a cross-sectional view of an electrostatic discharge protection circuit 102 according to some embodiments. In some embodiments, the electrostatic discharge protection circuit 102 is a semiconductor device 200 formed in and above a substrate 202. A deep n-well 204 is formed in the substrate 202, and a p-well 206 is formed in the deep n-well. In some embodiments, the deep n-well 204 is doped with impurities having n-type conductivity, such as phosphorus, arsenic, antimony, tellurium, sulfur, or some other n-type impurities, and the p-well 206 is doped with impurities having p-type conductivity, such as boron, gallium, zinc, aluminum, or some other p-type impurities. N-type contact regions 208, 210, 212 and p-type contact region 214 are formed in the p-well 206. An n-type contact region 215 is formed in the deep n-well 204. Contact regions 208, 210, 212, and 214 can be active regions, such as source / drain regions, and can be formed by implantation, diffusion, epitaxial growth, or some other process to introduce dopants or impurities of a specified conductivity type. The conductivity type indicates the net conductivity type. For example, since contact regions 208, 210, and 212 are formed in p-well 206, p-type impurities are present, but a higher concentration of n-type impurities is present to define the net conductivity type. Gate structures 216 and 218 are formed on substrate 202. In some embodiments, gate structures 216 and 218 each include a gate insulating layer 220 (e.g., a dielectric), a gate electrode 222 (e.g., polysilicon, metal), and sidewall spacers 224 adjacent to the gate insulating layer 220 and the gate electrode 222. p-well 206, N-type contact regions 208 and 210, and gate structure 216 define transistor 110, and p-well 206, N-type contact regions 210 and 212, and gate structure 216 define transistor 112. n-type contact regions 208 and 210, and p-well 206 define body diodes 110B and 112B.

[0030] In some embodiments, an n-well 226 is formed in the substrate 202, and a p-type contact region 228 connected to the reference power pad 108 and an n-type contact region 230 connected to the negative power pad 104 are formed in the n-well to define a diode 116. An n-well 232 is formed in the substrate 202, and an n-type contact region 234 connected to the positive power pad 106 and a p-type contact region 236 connected to the reference power pad 108 are formed in the n-well 202 to define a diode 118.

[0031] In some embodiments, a silicide barrier layer 238 is formed on the substrate 202 to enhance the ESD characteristics of the semiconductor device 200. In some embodiments, the silicide barrier layer 238 covers at least some of the contact regions 208, 210, 212, gate electrodes 216, 218, and sidewall spacers 224 to prevent the formation of silicide layers present in other portions of the integrated circuit device 100, wherein the silicide layer typically reduces resistance where the silicide layer is present.

[0032] In some embodiments, a metallization structure 240 is formed on a substrate to provide connections between transistors 110, 112, resistors 114, and diodes 116, 118 and negative power pads 104, positive power pads 106, or reference power pads 108, as described above. n-type contact regions 208 and 215 are connected to the reference power pad 108. n-type contact regions 212 and p-type contact regions 214 are connected to the negative power pad 104. The metallization structure 240 may include one or more dielectric layers 242 and interconnect structures 244. For ease of illustration, the interconnect structure 244 is shown in a simplified form. In a real device, the interconnect structure 244 may be formed using a network of conductive lines and conductive vias in a stacked arrangement to provide the illustrated connections. In some embodiments, resistors 114 are formed using polysilicon lines in the same layer as the gate electrode 222. Alternatively, resistors 114 may be formed using resistive structures in the layers of the metallization structure 240.

[0033] ESD protection circuit 102 includes gate-grounded transistors 110, 112 in isolated p-well 206, without any forward-biased diodes from p-well 206 to n-type contact regions 208, 210, 212. p-well 206 and n-type contact region 212 are connected to negative power pad 104 (<0V). The voltage across any of n-type contact regions 208, 210, 212 will not be lower than the voltage of p-well 206, therefore no forward-biased diodes are present during normal operation. In some embodiments, deep n-well 204 is connected to either reference power pad 108 or positive power pad 106, provided the voltage between the negatively connected p-well 206 and the reference or positively connected deep n-well 204 does not exceed the junction breakdown voltage.

[0034] Figure 3 This is a layout diagram of an electrostatic discharge protection circuit 102 according to some embodiments. In some embodiments, a silicide barrier layer 238 covers the substrate 202 above the deep n-well 204 and p-well 206. Gate structures 216, 218 are formed on the substrate 202. Openings may be formed in the silicide barrier layer 238 to expose n-type contact regions 208, 212 to allow connection to transistors 110, 112. Figure 3 Adjacent electrostatic discharge protection circuits 102' are shown, wherein n-type contact areas 212 can be shared between adjacent circuits.

[0035] Figure 4This is a flowchart of a method 400 for providing electrostatic discharge protection according to some embodiments. At 402, resistor 114 is connected to negative power pad 104. At 404, first transistor 110 is connected to reference power pad 108 and negative power pad 104. At 406, resistor 114 is connected to the first gate electrode of first transistor 110. At 408, in response to an electrostatic voltage applied to reference power pad 108, current is shunted to negative power pad 104 through first transistor 110.

[0036] According to some embodiments, a device includes a reference power pad, a negative power pad, a resistor connected to the negative power pad, and a first transistor connected to the reference power pad and the negative power pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power pad in response to an electrostatic voltage applied to one of the reference power pad or the negative power pad.

[0037] According to some embodiments, the device includes a second transistor connected to at least one of a reference power pad or a negative power pad connected in series with the first transistor, and has a second gate electrode connected to a resistor.

[0038] According to some embodiments, the first transistor includes an n-type transistor.

[0039] According to some embodiments, the device includes a diode connected between a reference power pad and a negative power pad, wherein the anode of the diode is connected to the negative power pad.

[0040] According to some embodiments, the device includes a positive power pad and a power clamping circuit connected between the positive power pad and a reference power pad.

[0041] According to some embodiments, the device includes a first diode connected between a reference power pad and a negative power pad, and a second diode connected between a reference power pad and a positive power pad.

[0042] According to some embodiments, a device includes: a substrate; a metallization structure on the substrate, the metallization structure including a reference power pad and a negative power pad; a first well having a first conductivity type in the substrate; a second well having a second conductivity type in the first well; a first contact having a first conductivity type in the second well and connected to the reference power pad; a second contact having a first conductivity type in the second well and connected to the negative power pad; a first gate electrode between the first contact and the second contact; and a resistor connected between the first gate electrode and the negative power pad.

[0043] According to some embodiments, the device includes a third contact having a first conductivity type in a second well, and a second gate electrode between the second contact and the third contact, wherein a resistor is connected between the second gate electrode and the negative power supply pad.

[0044] According to some embodiments, the device includes a third contact portion having a second conductivity type in a second well and connected to a negative power supply pad.

[0045] According to some embodiments, the device includes a third contact having a first conductivity type in a first well and connected to a reference power pad.

[0046] According to some embodiments, the device includes a silicide barrier layer over portions of the first contact, the second contact, and the first gate electrode.

[0047] According to some embodiments, the first conductivity type includes n-type conductivity, and the second conductivity type includes p-type conductivity.

[0048] According to some embodiments, the device includes a third well having a first conductivity type in a substrate, a third contact having a first conductivity type in the third well and connected to a reference power pad, and a fourth contact having a second conductivity type in the third well and connected to a negative power pad.

[0049] According to some embodiments, the metallized structure includes a positive power pad, and the device further includes a third well having a first conductivity type in the substrate, a third contact having a first conductivity type in the third well and connected to a reference power pad, and a fourth contact having a second conductivity type in the third well and connected to the positive power pad.

[0050] According to some embodiments, a method includes: connecting a resistor to a negative power pad; connecting a first transistor between a reference power pad and the negative power pad; connecting a resistor to a first gate electrode of the first transistor; and shunting current to the negative power pad via the first transistor in response to an electrostatic voltage applied to the reference power pad.

[0051] According to some embodiments, the method includes: connecting a second transistor between a reference power pad and a negative power pad connected in series with a first transistor; connecting a resistor to a second gate electrode of the second transistor; and shunting current to the negative power pad through the first transistor and the second transistor in response to an electrostatic voltage applied to the reference power pad.

[0052] According to some embodiments, the method includes: connecting a diode between a reference power pad and a negative power pad, wherein the anode of the diode is connected to the negative power pad; and, in response to a second electrostatic voltage applied to the negative power pad, shunting a second current to the reference power pad via a first transistor and shunting a third current to the reference power pad via the diode.

[0053] According to some embodiments, the method includes: connecting a power clamping circuit between a positive power pad and a reference power pad; and shunting a second current to a negative power pad via the power clamping circuit and a first transistor in response to a second electrostatic voltage applied to the positive power pad.

[0054] According to some embodiments, the method includes: connecting a first diode between a reference power pad and a negative power pad, wherein the anode of the first diode is connected to the negative power pad; connecting a second diode between a reference power pad and a positive power pad, wherein the anode of the second diode is connected to the reference power pad; and, in response to a third electrostatic voltage applied to the negative power pad, shunting a third current to the positive power pad via a first transistor and a power clamping circuit, and shunting a fourth current to the positive power pad via the first and second diodes.

[0055] According to some embodiments, connecting the first transistor to the reference power pad and the negative power pad includes connecting an n-type transistor to the reference power pad and the negative power pad.

[0056] Although the subject matter has been described using language specific to structural features or methodological actions, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing at least some of the claims.

[0057] This document provides various operations of the embodiments. The order in which some or all operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings that have the benefits of this specification will be appreciated. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Additionally, it should be understood that not all operations are necessary in some embodiments.

[0058] Furthermore, the terms "exemplary" and / or similar terms are used herein to indicate that something is used as an example, instance, illustration, etc., and are not necessarily advantageous. Rather, the use of the terms "exemplary" and / or similar terms is intended to illustrate a possible aspect and / or implementation of the technology presented herein. Such examples are not necessary for such technology or are intended to be limiting. Various embodiments of such technology may include such examples, alone or in combination with other features, and / or the examples shown may be modified and / or omitted.

[0059] As used herein, “or” is intended to mean an inclusive “or” rather than an exclusive “or.” Furthermore, “a” and “an” as used herein and in the appended claims are generally interpreted as meaning “one or more” unless otherwise stated or clearly indicated from the context as singular. Additionally, “at least one of A and B” and / or similar terms generally mean A or B or A and B. Furthermore, in the extent to which “comprising,” “owning,” “having,” “with,” or variations thereof are used, these terms are intended to be inclusive in a manner similar to the term “comprising.” Furthermore, unless otherwise stated, “first,” “second,” etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, these terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or identical elements.

[0060] Furthermore, although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, regarding the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe these components is intended to correspond to any component that performs a particular function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure. Additionally, while specific features of this disclosure may have been disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application. Furthermore, the use of the terms “comprising,” “having,” “having,” “with,” or variations thereof in the embodied descriptions or claims is intended to be inclusive in a manner similar to the term “including.”

Claims

1. A device comprising: Reference power pads; Negative power pad; A resistor connected to the negative power supply pad; as well as A first transistor is connected to the reference power pad and the negative power pad and has a first gate electrode connected to the resistor, wherein, in response to an electrostatic voltage applied to one of the reference power pad or the negative power pad, the first transistor is operable to shunt current to the negative power pad.

2. The device according to claim 1, comprising: The second transistor is connected to at least one of the reference power pad or the negative power pad connected in series with the first transistor, and has a second gate electrode connected to the resistor.

3. The device according to claim 1, wherein: The first transistor includes an n-type transistor.

4. The device according to claim 1, comprising: A diode connected between the reference power pad and the negative power pad, wherein the anode of the diode is connected to the negative power pad.

5. The device according to claim 1, comprising: Positive power pad; as well as A power clamping circuit is connected between the positive power pad and the reference power pad.

6. The device according to claim 5, comprising: A first diode is connected between the reference power pad and the negative power pad; as well as A second diode is connected between the reference power pad and the positive power pad.

7. A device comprising: Substrate; A metallization structure, located on the substrate, comprising: Reference power pads; and Negative power pad; A first well having a first conductivity type, the first well being located in the substrate; A second well having a second conductivity type is located within the first well; A first contact portion having the first conductivity type is located in the second well and connected to the reference power pad; A second contact portion having the first conductivity type is located in the second well and connected to the negative power pad; A first gate electrode, the first gate electrode being located between the first contact portion and the second contact portion; and A resistor is connected between the first gate electrode and the negative power supply pad.

8. The device according to claim 7, comprising: The third contact portion has the first conductivity type in the second well; as well as The second gate electrode is located between the second contact portion and the third contact portion, wherein: The resistor is connected between the second gate electrode and the negative power supply pad.

9. The device according to claim 7, comprising: The third contact portion has the second conductivity type in the second well and is connected to the negative power pad.

10. The device according to claim 7, comprising: A third contact portion having the first conductivity type in the first well and connected to the reference power pad.

11. The device according to claim 7, comprising: A silicide barrier layer is located on the first contact portion, the second contact portion, and a portion of the first gate electrode.

12. The device according to claim 7, wherein: The first conductivity type includes n-type conductivity; and The second conductivity type includes p-type conductivity.

13. The device according to claim 7, comprising: A third well, wherein the third well has the first conductivity type in the substrate; A third contact portion, wherein the third contact portion has the first conductivity type in the third well and is connected to the reference power pad; as well as A fourth contact portion, which has the second conductivity type in the third well and is connected to the negative power pad.

14. The device according to claim 7, wherein: The metallization structure includes a positive power pad; and The device also includes: A third well, wherein the third well has the first conductivity type in the substrate; A third contact portion, the third contact portion having the first conductivity type in the third well and connected to the reference power pad; and A fourth contact portion, which has the second conductivity type in the third well and is connected to the positive power pad.

15. A method comprising: Connect the resistor to the negative power supply pad; Connect the first transistor between the reference power pad and the negative power pad; Connect the resistor to the first gate electrode of the first transistor; as well as In response to an electrostatic voltage applied to the reference power pad, current is shunted to the negative power pad via the first transistor.

16. The method of claim 15, comprising: The second transistor is connected between the reference power pad and the negative power pad, which are connected in series with the first transistor. Connect the resistor to the second gate electrode of the second transistor; as well as In response to the electrostatic voltage applied to the reference power pad, the current is shunt to the negative power pad via the first transistor and the second transistor.

17. The method of claim 15, comprising: A diode is connected between the reference power pad and the negative power pad, wherein the anode of the diode is connected to the negative power pad; and In response to the application of a second electrostatic voltage to the negative power pad: The second current is shunted to the reference power pad via the first transistor; and The third current is shunted to the reference power pad via the diode.

18. The method of claim 15, comprising: Connect the power clamping circuit between the positive power pad and the reference power pad; as well as In response to the application of a second electrostatic voltage to the positive power pad, a second current is shunted to the negative power pad via the power clamping circuit and the first transistor.

19. The method of claim 18, comprising: A first diode is connected between the reference power pad and the negative power pad, wherein the anode of the first diode is connected to the negative power pad; A second diode is connected between the reference power pad and the positive power pad, wherein the anode of the second diode is connected to the reference power pad; and In response to a third electrostatic voltage applied to the negative power pad: The third current is shunted to the positive power pad via the first transistor and the power clamping circuit; and The fourth current is shunted to the positive power pad through the first diode and the second diode.

20. The method of claim 15, wherein: Connecting the first transistor to the reference power pad and the negative power pad includes: Connect the n-type transistor to the reference power pad and the negative power pad.

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