Image sensor and preparation method thereof
By forming trenches and performing inverse doping in the image sensor, the manufacturing challenges caused by pixel size reduction are solved, enabling the manufacturing of smaller pixels and improving photosensitive performance, thus simplifying the process of back-illuminated image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-01-07
- Publication Date
- 2026-05-08
AI Technical Summary
In the process of shrinking the pixel size of image sensors, the aspect ratio of photoresist and the ion implantation depth are limited by existing technologies, which increases the manufacturing difficulty, especially in high-end CIS products where there are process challenges.
By forming trenches in the interlayer dielectric layer, filling them with N-type doped epitaxial layers, and performing inversion doping at the top of the interlayer dielectric layer through ion implantation to form a P-type ion implantation region, thus forming an isolation structure, the P-type ion implantation depth can be adjusted by combining selective epitaxy and thermal oxidation processes, thus omitting the back-side deep trench etching process.
It breaks through the limitations of traditional processes on ion implantation depth, enabling the manufacture of smaller pixel units, reducing the manufacturing difficulty of image sensors, improving photosensitivity, and simplifying the process flow of back-illuminated image sensors.
Smart Images
Figure CN122002928A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to an image sensor and its fabrication method. Background Technology
[0002] The photosensitivity of an image sensor (CIS) is strongly correlated with the size of its pixel area, and the photodiode (PD) is the most basic unit of the pixel structure, consisting of N-type and P-type regions. Traditional photodiodes are formed vertically using photolithography and ion implantation processes. However, as CIS increasingly pursues higher pixel counts, the size of each pixel (the total lateral width of the N-type and P-type regions) will continuously shrink. For example, when the size of each pixel is 1μm / 0.7μm / 0.64μm, or even 0.56μm and below, the aspect ratio of the photoresist used to fabricate the photodiode, as well as the ion implantation depth and concentration, will be severely limited, seriously hindering the development of high-end CIS products. Summary of the Invention
[0003] This application provides an image sensor and its fabrication method, which can solve the problem of the difficulty in manufacturing image sensors caused by the continuous reduction in pixel size requirements at present.
[0004] On one hand, embodiments of this application provide a method for fabricating an image sensor, including: A substrate is provided on which a pad oxide layer, an interlayer dielectric layer and a hard mask layer are sequentially formed; The hard mask layer, the interlayer dielectric layer, and the pad oxide layer are etched to the substrate surface to form multiple trenches arranged in an array; A repair oxide layer is formed, which covers the bottom wall of the trench; Remove the repair oxide layer and the hard mask layer; An N-type doped epitaxial layer is formed, which fills the trench and covers the interlayer dielectric layer; A sacrificial oxide layer is formed, which covers the epitaxial layer; A patterned photoresist layer is formed on the sacrificial oxide layer, wherein a pattern for defining a P-type ion implantation region for a photodiode is formed in the patterned photoresist layer, and the pattern for defining the P-type ion implantation region for a photodiode opens the epitaxial layer at the top of the remaining interlayer dielectric layer. Using the patterned photoresist layer and the sacrificial oxide layer as masks, the epitaxial layer at the top of the remaining interlayer dielectric layer is inverted and doped to obtain a P-type ion implantation region, wherein the P-type ion implantation region and the interlayer dielectric layer at the bottom of the P-type ion implantation region together constitute an isolation structure. Remove the patterned photoresist layer and the sacrificial oxide layer; A capping layer is formed, which covers the P-type ion implantation region and the N-type doped epitaxial layer.
[0005] Optionally, in the fabrication method of the image sensor, using the patterned photoresist layer and the sacrificial oxide layer as masks, inversion doping is performed on the epitaxial layer at the top of the remaining interlayer dielectric layer to obtain the P-type ion implantation region. During this process, the ion implantation energy is 480 keV to 1250 keV, and the ion implantation dose is 1E17 atoms / cm². 3 ~5E17atoms / cm 3 .
[0006] Optionally, in the fabrication method of the image sensor, an N-type doped epitaxial layer is formed using a selective epitaxial process.
[0007] Optionally, in the method for fabricating the image sensor, during the process of forming an N-type doped epitaxial layer using a selective epitaxial process, the gases involved in the selective epitaxial process include at least: silicon source gas, HCl gas, and H2; the flow rate of the silicon source gas is 1000 sccm to 1600 sccm; the flow rate of the HCl gas is 50 sccm to 100 sccm; the flow rate of the H2 gas is 20 sccm to 40 sccm; the process temperature is 800℃ to 900℃; and the pressure in the process chamber is 50 Torr to 100 Torr.
[0008] Optionally, in the method for fabricating the image sensor, the ratio of the thickness of the epitaxial layer at the top of the remaining interlayer dielectric layer to the thickness of the interlayer dielectric layer is (4:3) to (2:1).
[0009] Optionally, in the method for fabricating the image sensor, after forming the array of trenches, the width of the remaining interlayer dielectric layer between two adjacent trenches is less than 0.24 μm.
[0010] Optionally, in the method for fabricating the image sensor, after forming the array of trenches, the sum of the lateral opening size of each trench and the width of the remaining interlayer dielectric layer between two adjacent trenches is less than 1 μm.
[0011] Optionally, in the method for fabricating the image sensor, a thermal oxidation process is used to form the repair oxide layer.
[0012] Optionally, in the method for fabricating the image sensor, after forming the N-type doped epitaxial layer and before forming the sacrificial oxide layer, the method further includes: The epitaxial layer of a certain thickness is removed by chemical mechanical polishing.
[0013] On the other hand, embodiments of this application also provide an image sensor, including: A substrate on which a pad oxide layer and an interlayer dielectric layer are sequentially formed; Multiple trenches arranged in an array, the trenches being located in the interlayer dielectric layer and the pad oxide layer; An N-type doped epitaxial layer, wherein the epitaxial layer fills the trench and extends beyond the top of the trench to a certain height; The P-type ion implantation region is located on the interlayer dielectric layer between the trenches, wherein the upper surface of the P-type ion implantation region is flush with the upper surface of the epitaxial layer, and the P-type ion implantation region and the interlayer dielectric layer at the bottom of the P-type ion implantation region together constitute an isolation structure. A capping layer that covers the P-type ion implantation region and the N-type doped epitaxial layer.
[0014] The technical solution of this application has at least the following advantages: This application provides an image sensor and its fabrication method. In the fabrication method, trenches are first formed in an interlayer dielectric layer. Then, an N-type doped epitaxial layer is formed to fill the trenches and cover the interlayer dielectric layer. Next, the epitaxial layer at the top of the interlayer dielectric layer is inverted and doped using an ion implantation process to obtain a P-type ion implantation region. The isolation structure and the N-type doped epitaxial layer constitute a photodiode region. The P-type ion implantation region and the interlayer dielectric layer constitute a stacked isolation structure (photodiode isolation region). The N-type doped epitaxial layer in the trench and at the top of the trench constitutes the N-type region of the photodiode. The depth of the P-type ion implantation region in the isolation structure can be adjusted as needed, and the vertical depth of the N-type region can be adjusted by the height of the interlayer dielectric layer. This not only overcomes the limitations of traditional isolation structures on extremely high ion implantation depths but also overcomes the limitations of photolithography and ion implantation processes for smaller pixel units. Furthermore, it eliminates the need for deep trench etching (BDTI) on the back side when developing backside illumination (BSI) image sensors, significantly reducing the manufacturing difficulty of the image sensor. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a flowchart of the method for fabricating an image sensor according to an embodiment of the present invention; Figures 2-11 This is a schematic diagram of the semiconductor structure in each process step of manufacturing the image sensor according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Substrate, 20-Pad oxide layer, 30-Interlayer dielectric layer, 31-Remaining interlayer dielectric layer, 40-Hard mask layer, 51-Trench, 52-Repair oxide layer, 53-Sacrificial oxide layer, 54-Photoresist layer, 55-Patterned photoresist layer, 60-Epiaxial layer, 70-P-type ion implantation region, 80-Capping layer. Detailed Implementation
[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0021] This application provides a method for fabricating an image sensor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating an image sensor according to an embodiment of the present invention. The method for fabricating the image sensor includes: First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the formation of the hard mask layer according to an embodiment of this application. A substrate 10 is provided, on which a pad oxide layer 20, an interlayer dielectric layer 30 and a hard mask layer 40 are sequentially formed.
[0022] Preferably, the thickness of the interlayer dielectric layer 30 is 0.5μm to 1.5μm.
[0023] In this embodiment, the interlayer dielectric layer 30 is made of silicon dioxide.
[0024] Preferably, the hard mask layer 40 is made of silicon nitride.
[0025] In this embodiment, the substrate 10 is p-type doped.
[0026] Then, proceed to step S2: (Refer to...) Figure 3 and Figure 4 , Figure 3 This is a cross-sectional view of the semiconductor structure after trench formation according to an embodiment of this application. Figure 4This is a top view of the semiconductor structure after trench formation according to an embodiment of this application. First, a photoresist layer (not shown) is formed on the hard mask layer 40. Then, the N-type region and P-type isolation region (not shown) of the photodiode are defined on the photoresist layer using a photolithography process. Next, using the photoresist layer as a mask, the hard mask layer 40, the interlayer dielectric layer 30, and the pad oxide layer 20 are etched to the surface of the substrate 10 to form a plurality of trenches 51 arranged in an array. The trenches 51 are located at the N-type region of the photodiode, and the remaining interlayer dielectric layer 30 is located at the P-type isolation region of the photodiode.
[0027] In this embodiment, as Figure 4 As shown, the hard mask layer 40, the interlayer dielectric layer 30 and the pad oxide layer 20 are etched to the surface of the substrate 10 to form a 3-row, 4-column trench 51 array.
[0028] Preferably, after the trenches 51 are arranged in an array, the widths b and b' of the remaining interlayer dielectric layers between two adjacent trenches 51 are both less than 0.24 μm.
[0029] Furthermore, after forming the array of trenches 51, the sum of the lateral opening size a along the X direction of each trench 51 and the width b of the remaining interlayer dielectric layer 31 between two adjacent trenches 51 is less than 1 μm; similarly, the sum of the lateral opening size a' along the Y direction of each trench 51 and the width b' of the remaining interlayer dielectric layer 31 between two adjacent trenches 51 is less than 1 μm.
[0030] Next, proceed to step S3: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the repair oxide layer according to an embodiment of this application. The repair oxide layer 52 is formed and covers the bottom wall of the trench 51.
[0031] Preferably, the repair oxide layer 52 is formed by a thermal oxidation process, wherein the surface damage on the substrate 10 surface of the bottom wall of the trench 51 caused by the etching in step S2 can be repaired by the thermal oxidation process.
[0032] In this embodiment, the thickness of the repair oxide layer 52 is 10 angstroms to 30 angstroms.
[0033] Further, proceed to step S4: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after removing the repair oxide layer and the hard mask layer according to an embodiment of this application, with the repair oxide layer 52 and the hard mask layer 40 removed.
[0034] In this embodiment, the repair oxide layer 52 and the hard mask layer 40 are removed by wet etching.
[0035] Next, proceed to step S5: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of an N-type doped epitaxial layer according to an embodiment of this application. An N-type doped epitaxial layer 60 is formed, which fills the trench 51 and covers the remaining interlayer dielectric layer 31.
[0036] Preferably, an N-type doped epitaxial layer 60 is formed using a selective epitaxial process.
[0037] In the process of forming the N-type doped epitaxial layer 60 using selective epitaxy, the gases involved in the selective epitaxy process include at least: silicon source gas, HCl gas, and H2; the flow rate of the silicon source gas is 1000 sccm to 1600 sccm; the flow rate of the HCl gas is 50 sccm to 100 sccm; the flow rate of the H2 gas is 20 sccm to 40 sccm; the process temperature is 800℃ to 900℃; and the pressure in the process chamber is 50 Torr to 100 Torr.
[0038] In this embodiment, the silicon source gas is DCS (dichlorosilane).
[0039] Preferably, the doping concentration of the epitaxial layer 60 is 5E16 / cm². 2 ~1.5E17 / cm 2 .
[0040] In this embodiment, the thickness of the epitaxial layer 60 is 2 μm to 3 μm higher than the upper surface of the remaining dielectric layer 31.
[0041] Furthermore, after forming the N-type doped epitaxial layer 60 (step S5) and before forming the sacrificial oxide layer (step S6), the method for fabricating the image sensor may further include: using a chemical mechanical polishing (CMP) process to grind and remove the epitaxial layer 60 of a certain thickness.
[0042] After the surface of the epitaxial layer 60 is planarized, the final thickness of the epitaxial layer 60 is 1 μm to 2 μm higher than the upper surface of the remaining dielectric layer 31.
[0043] Preferably, the ratio of the thickness of the epitaxial layer 60 located at the top of the remaining interlayer dielectric layer 31 to the thickness of the interlayer dielectric layer 31 is (4:3) to (2:1).
[0044] Further, proceed to step S6: Refer to Figure 8 , Figure 8This is a schematic diagram of the semiconductor structure after the formation of the photoresist layer in an embodiment of this application, wherein a sacrificial oxide layer 53 is formed, and the sacrificial oxide layer 53 covers the epitaxial layer 60.
[0045] Preferably, the sacrificial oxide layer 53 is formed using a thermal oxidation process. This thermal oxidation process, which forms the sacrificial oxide layer 53 on the epitaxial layer 60, can repair surface scratches on the epitaxial layer caused by the CMP process in step S5. Furthermore, the sacrificial oxide layer 53 formed by this thermal oxidation process can serve as a spacer between the photoresist layer 54 and the epitaxial layer 60 in the next step.
[0046] Next, proceed to step S7: (Refer to...) Figure 8 and reference Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the P-type ion implantation region according to an embodiment of this application. First, a photoresist layer 54 is coated on the surface of the epitaxial layer 60, and then a patterned photoresist layer 55 is formed by photolithography. The patterned photoresist layer 55 is located on the sacrificial oxide layer 53. The patterned photoresist layer 55 has a pattern for defining the P-type ion implantation region of the photodiode. The pattern for defining the P-type ion implantation region of the photodiode opens the epitaxial layer 60 at the top of the remaining interlayer dielectric layer 31.
[0047] Further, proceed to step S8: Continue to refer to Figure 9 Using the patterned photoresist layer 55 and the sacrificial oxide layer 53 as masks, the epitaxial layer at the top of the remaining interlayer dielectric layer 31 is inverted and doped to obtain a P-type ion implantation region 70, wherein the P-type ion implantation region 70 and the interlayer dielectric layer 31 at the bottom of the P-type ion implantation region 70 together constitute an isolation structure.
[0048] Specifically, using the patterned photoresist layer 55 and the sacrificial oxide layer 53 as masks, the epitaxial layer 60 at the top of the remaining interlayer dielectric layer 31 is inverted and doped to obtain a P-type ion implantation region. During this process, the ion implantation energy is 480 keV to 1250 keV, and the ion implantation dose is 1E17 atoms / cm². 3 ~5E17atoms / cm 3 .
[0049] In this embodiment, the injected P-type ions can be boron ions.
[0050] It is worth noting that the P-type ion implantation region 70 is spatially projected perpendicularly onto the upper surface of the remaining interlayer dielectric layer 31.
[0051] Next, proceed to step S9: (Refer to...) Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after removing the patterned photoresist layer and the sacrificial oxide layer according to an embodiment of this application, showing the removal of the patterned photoresist layer 55 and the sacrificial oxide layer 53.
[0052] Preferably, the patterned photoresist layer 55 can be removed by an ashing process, and the sacrificial oxide layer 53 can be removed by a wet etching process or a dry etching process.
[0053] Finally, proceed to step S10: (Refer to...) Figure 11 , Figure 11 This is a schematic diagram of the semiconductor structure after the formation of the capping layer in an embodiment of this application. The capping layer 80 is formed, which covers the P-type ion implantation region 70 and the N-type doped epitaxial layer 60.
[0054] In this embodiment, the thickness of the cap layer 80 is 0.3μm~0.5μm.
[0055] The P-type ion implantation region 70 and the interlayer dielectric layer 31 at the bottom of the P-type ion implantation region 70 together constitute the isolation structure of the photodiode; the N-type doped epitaxial layer 60 in the trench constitutes the N-type region of the photodiode.
[0056] In this application, when developing image sensors with smaller pixel sizes, the depth of the P-type ion implantation region in the isolation structure can be adjusted as needed, and the depth of the P-type ion implantation region in the isolation structure can be reduced as needed, thus breaking through the limitation of P-type isolation implantation depth. Furthermore, in this application, the epitaxial layer (i.e., the N-type region of the photodiode) is formed by selective epitaxial doping. The vertical depth of the N-type region can be adjusted by the height of the interlayer dielectric layer, and the doping concentration is more uniform, resulting in more photoelectron absorption and improved photosensitivity of the image sensor. Furthermore, in this application, when developing a back-illuminated image sensor, the interlayer dielectric layer can be used as the filling dielectric layer for the back-side deep trench. This eliminates the need for traditional back-illuminated image sensor back-side deep trench photolithography, etching, and dielectric filling steps, making the process simple and easy to implement.
[0057] Based on the same inventive concept, this application also provides an image sensor, see reference. Figure 11 The image sensor includes: Substrate 10, on which a pad oxide layer 20 and an interlayer dielectric layer 31 are sequentially formed; Multiple trenches 51 arranged in an array, the trenches 51 being located in the interlayer dielectric layer 31 and the pad oxide layer 20; An N-type doped epitaxial layer 60 fills the trench 51 and extends beyond the top of the trench 51 to a certain height. P-type ion implantation region 70, the P-type ion implantation region 70 is located on the interlayer dielectric layer 31 between the trenches 51, wherein the upper surface of the P-type ion implantation region 70 is flush with the upper surface of the epitaxial layer 60, and the P-type ion implantation region 70 and the interlayer dielectric layer 31 at the bottom of the P-type ion implantation region 70 together form an isolation structure. A capping layer 80 covers the P-type ion implantation region 70 and the N-type doped epitaxial layer 60.
[0058] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating an image sensor, characterized in that, include: A substrate is provided on which a pad oxide layer, an interlayer dielectric layer and a hard mask layer are sequentially formed; The hard mask layer, the interlayer dielectric layer, and the pad oxide layer are etched to the substrate surface to form multiple trenches arranged in an array; A repair oxide layer is formed, which covers the bottom wall of the trench; Remove the repair oxide layer and the hard mask layer; An N-type doped epitaxial layer is formed, which fills the trench and covers the interlayer dielectric layer; A sacrificial oxide layer is formed, which covers the epitaxial layer; A patterned photoresist layer is formed on the sacrificial oxide layer, wherein a pattern for defining a P-type ion implantation region for a photodiode is formed in the patterned photoresist layer, and the pattern for defining the P-type ion implantation region for a photodiode opens the epitaxial layer at the top of the remaining interlayer dielectric layer. Using the patterned photoresist layer and the sacrificial oxide layer as masks, the epitaxial layer at the top of the remaining interlayer dielectric layer is inverted and doped to obtain a P-type ion implantation region, wherein the P-type ion implantation region and the interlayer dielectric layer at the bottom of the P-type ion implantation region together constitute an isolation structure. Remove the patterned photoresist layer and the sacrificial oxide layer; A capping layer is formed, which covers the P-type ion implantation region and the N-type doped epitaxial layer.
2. The method for fabricating an image sensor according to claim 1, characterized in that, Using the patterned photoresist layer and the sacrificial oxide layer as masks, inversion doping is performed on the epitaxial layer at the top of the remaining interlayer dielectric layer to obtain the P-type ion implantation region. During this process, the ion implantation energy is 480 keV to 1250 keV, and the ion implantation dose is 1E17 atoms / cm². 3 ~5E17atoms / cm 3 .
3. The method for fabricating an image sensor according to claim 1, characterized in that, An N-type doped epitaxial layer is formed using a selective epitaxial process.
4. The method for fabricating an image sensor according to claim 1, characterized in that, In the process of forming an N-type doped epitaxial layer using selective epitaxy, the gases involved in the selective epitaxy process include at least: silicon source gas, HCl gas, and H2; the flow rate of silicon source gas is 1000 sccm to 1600 sccm; the flow rate of HCl gas is 50 sccm to 100 sccm; the flow rate of H2 is 20 sccm to 40 sccm; the process temperature is 800℃ to 900℃; and the pressure in the process chamber is 50 Torr to 100 Torr.
5. The method for fabricating an image sensor according to claim 1, characterized in that, The ratio of the thickness of the epitaxial layer at the top of the remaining interlayer dielectric layer to the thickness of the interlayer dielectric layer is (4:3) to (2:1).
6. The method for fabricating an image sensor according to claim 1, characterized in that, After the trenches are formed in an array, the width of the remaining interlayer dielectric layer between two adjacent trenches is less than 0.24 μm.
7. The method for fabricating an image sensor according to claim 6, characterized in that, After the trenches are formed in an array, the sum of the lateral opening size of each trench and the width of the remaining interlayer dielectric layer between two adjacent trenches is less than 1 μm.
8. The method for fabricating an image sensor according to claim 1, characterized in that, The repair oxide layer is formed using a thermal oxidation process.
9. The method for fabricating an image sensor according to claim 1, characterized in that, The method for fabricating the image sensor, after forming the N-type doped epitaxial layer and before forming the sacrificial oxide layer, further includes: The epitaxial layer of a certain thickness is removed by chemical mechanical polishing.
10. An image sensor, characterized in that, include: A substrate on which a pad oxide layer and an interlayer dielectric layer are sequentially formed; Multiple trenches arranged in an array, the trenches being located in the interlayer dielectric layer and the pad oxide layer; An N-type doped epitaxial layer, wherein the epitaxial layer fills the trench and extends beyond the top of the trench to a certain height; The P-type ion implantation region is located on the interlayer dielectric layer between the trenches, wherein the upper surface of the P-type ion implantation region is flush with the upper surface of the epitaxial layer, and the P-type ion implantation region and the interlayer dielectric layer at the bottom of the P-type ion implantation region together constitute an isolation structure. A capping layer that covers the P-type ion implantation region and the N-type doped epitaxial layer.