Image sensor structure and forming method thereof

Abstract

The invention provides an image sensor structure and a forming method thereof, the image sensor structure comprises a semiconductor substrate, the semiconductor substrate comprises a first surface and a second surface opposite to each other, the first surface comprises a plurality of pixel areas distributed in an array, and at least one photodiode is formed in each pixel area; the buried metal structures are located in the semiconductor substrate between the adjacent pixel regions; a first metal interconnection structure electrically connected with the at least one photodiode and the buried metal structure is formed on the first surface of the semiconductor substrate; and a plurality of transistor structures and a second metal interconnection structure which is electrically connected with the plurality of transistor structures and the buried metal structure are formed on the second surface of the semiconductor substrate. The invention provides an image sensor structure and a forming method thereof. The image quality and low-light performance of an image sensor can be improved at the same time, and the number of pixel units and the light sensing area can be increased.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and in particular to an image sensor structure and a method for forming the same. Background Technology

[0002] A front-illuminated image sensor (FS CIS) is a structure that allows light to enter the pixel unit from the front of the sensor. Its structure, from top to bottom, consists of: microlenses, filters, a circuit layer, and photodiodes. Due to the presence of the circuit layer, some light may be blocked or scattered, which can degrade image quality and low-light (illuminance) performance. Furthermore, the presence of side-mounted signal processing logic circuitry limits the photosensitive area of ​​a front-illuminated CIS.

[0003] To improve the image quality and low-light performance of front-illuminated CIS (CMOS Image Sensor), back-illuminated image sensors (BSI CIS) were proposed. In BSI CIS, light can directly enter the photodiode from the back, eliminating the need for a metal wiring layer, thus reducing light loss and improving image quality and low-light performance. However, the signal processing logic circuitry located on the side of the BSI CIS still occupies a certain chip area, limiting further increases in pixel count and photosensitive area.

[0004] Therefore, it is necessary to provide a more efficient and reliable technical solution that can simultaneously improve the image quality and low-light performance of image sensors, as well as increase the number of pixel units and photosensitive area. Summary of the Invention

[0005] This application provides an image sensor structure and a method for forming the same, which can simultaneously improve the image quality and low-light performance of the image sensor, as well as increase the number of pixel units and the photosensitive area.

[0006] One aspect of this application provides a method for forming an image sensor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a first side and a second side opposite to each other, the first side including a plurality of pixel regions arranged in an array; forming a buried metal structure in the semiconductor substrate between adjacent pixel regions; forming at least one photodiode in the pixel regions; forming a first metal interconnect structure on the first side of the semiconductor substrate electrically connecting the at least one photodiode and the buried metal structure; and forming a plurality of transistor structures and a second metal interconnect structure electrically connecting the plurality of transistor structures and the buried metal structure on the second side of the semiconductor substrate.

[0007] In some embodiments of this application, the buried metal structure is located in a semiconductor substrate at the center of every four adjacent pixel regions arranged in an array.

[0008] In some embodiments of this application, the first metal interconnect structure includes: a plurality of first contact structures that are electrically connected to the at least one photodiode and the buried metal structure respectively; and a first inner interconnect layer that is electrically connected to the plurality of first contact structures.

[0009] In some embodiments of this application, the plurality of transistor structures include: a gate structure located on a second side of the semiconductor substrate and a source and a drain located on both sides of the gate structure in the semiconductor substrate.

[0010] In some embodiments of this application, the second metal interconnect structure includes: a plurality of second contact structures that are electrically connected to the gate, source, and drain of the plurality of transistor structures and the buried metal structure respectively; a second inner interconnect layer that is electrically connected to the plurality of second contact structures; and a metal pad structure that is electrically connected to the second inner interconnect layer.

[0011] In some embodiments of this application, the method for forming the image sensor structure further includes: forming a plurality of filters with positions corresponding to the plurality of pixel regions above the first metal interconnect structure and a plurality of microlenses located above the plurality of filters.

[0012] Another aspect of this application provides an image sensor structure, comprising: a semiconductor substrate including a first side and a second side opposite to each other, the first side including a plurality of pixel regions arranged in an array, wherein at least one photodiode is formed in the pixel regions; a buried metal structure located in the semiconductor substrate between adjacent pixel regions; a first metal interconnect structure electrically connecting the at least one photodiode and the buried metal structure is formed on the first side of the semiconductor substrate; and a plurality of transistor structures and a second metal interconnect structure electrically connecting the plurality of transistor structures and the buried metal structure are formed on the second side of the semiconductor substrate.

[0013] In some embodiments of this application, the buried metal structure is located in a semiconductor substrate at the center of every four adjacent pixel regions arranged in an array.

[0014] In some embodiments of this application, the first metal interconnect structure includes: a plurality of first contact structures that are electrically connected to the at least one photodiode and the buried metal structure respectively; and a first inner interconnect layer that is electrically connected to the plurality of first contact structures.

[0015] In some embodiments of this application, the plurality of transistor structures include: a gate structure located on a second side of the semiconductor substrate and a source and a drain located on both sides of the gate structure in the semiconductor substrate.

[0016] In some embodiments of this application, the second metal interconnect structure includes: a plurality of second contact structures that are electrically connected to the gate, source, and drain of the plurality of transistor structures and the buried metal structure respectively; a second inner interconnect layer that is electrically connected to the plurality of second contact structures; and a metal pad structure that is electrically connected to the second inner interconnect layer.

[0017] In some embodiments of this application, the image sensor structure further includes: a plurality of filters located above the first metal interconnect structure and corresponding to the plurality of pixel regions, and a plurality of microlenses located above the plurality of filters.

[0018] This application provides an image sensor structure and a method for forming the same, which can simultaneously improve the image quality and low-light performance of the image sensor, as well as increase the number of pixel units and the photosensitive area. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0020] in:

[0021] Figures 1 to 10 This is a schematic diagram of each step in the method for forming the image sensor structure described in the embodiments of this application. Detailed Implementation

[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0024] Figures 1 to 10 This is a schematic diagram of each step in the method for forming an image sensor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 1 and Figure 2 As shown, where, Figure 1 This is a top view. Figure 2 For along Figure 1 A longitudinal cross-sectional view at the dashed line AA. A semiconductor substrate 100 is provided, the semiconductor substrate 100 including a first surface 101 and a second surface 102 opposite to each other, the first surface 101 including a plurality of pixel regions 110 arranged in an array.

[0026] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.

[0027] In some embodiments of this application, the number of pixel regions 110 is multiple. For the sake of brevity, this application only shows four pixel regions 110 arranged in an array as an example.

[0028] refer to Figure 3 and Figure 4 As shown, where, Figure 3 This is a top view. Figure 4 For along Figure 3 A longitudinal cross-sectional view at the dashed line BB. A buried metal structure 120 is formed in the semiconductor substrate 100 between adjacent pixel regions 110. The material of the buried metal structure 120 is, for example, copper or tungsten.

[0029] Specifically, refer to Figure 3 As shown, in some embodiments of this application, the buried metal structure 120 is located in the semiconductor substrate 100 at the center of every four adjacent pixel regions 110 arranged in an array. This region ensures that each buried metal structure 120 is surrounded by four pixel regions simultaneously, reducing the density and number of buried metal structures 120, saving costs while reducing circuit crosstalk in the metal interconnects. Furthermore, the distance from this location to the four adjacent pixel regions is equidistant, avoiding signal transmission delay errors.

[0030] In some embodiments of this application, the buried metal structure 120 is completely buried within the semiconductor substrate 100. The top surface of the buried metal structure 120 may be higher or lower than the bottom surface of the pixel region 110, and the bottom surface of the buried metal structure 120 is lower than the bottom surface of the pixel region 110.

[0031] In some embodiments of this application, the method of forming the buried metal structure 120 includes: etching a first surface 101 of the semiconductor substrate 100 to form a trench in the semiconductor substrate 100 between adjacent pixel regions 110; filling the trench with a metal material to form the buried metal structure 120 filling the trench; and using a semiconductor epitaxial growth process to grow a semiconductor material (e.g., the same material as the semiconductor substrate 110) on the semiconductor substrate 110 of the trench sidewalls until the trench is filled, such that the buried metal structure 120 is buried and extends to cover the surface of the semiconductor substrate.

[0032] refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5 A longitudinal cross-sectional view at the dashed line BB. At least one photodiode 111 is formed in each pixel region 110. The number of photodiodes 111 can be arbitrary; this application only uses three photodiodes as an example. Photodiodes are a fundamental structure of image sensors, and their formation methods are well known to those skilled in the art.

[0033] refer to Figure 7 and Figure 8 As shown, where, Figure 7 This is a top view. Figure 8 For along Figure 7 Longitudinal cross-sectional view at the dashed line BB. A first metal interconnect structure 130 is formed on the first surface 101 of the semiconductor substrate 100, electrically connecting the at least one photodiode 111 and the buried metal structure 120.

[0034] refer to Figure 7 and Figure 8 As shown, in some embodiments of this application, the first metal interconnect structure 130 includes: a plurality of first contact structures 131 electrically connected to the at least one photodiode 111 and the buried metal structure 120 respectively; and a first inner interconnect layer 132 electrically connected to the plurality of first contact structures 131. The first inner interconnect layer 132 is a single metal layer. The metal interconnect process in the back-end process is also a conventional basic process in the field of semiconductor technology, therefore, the detailed structure and formation steps of the first metal interconnect structure 130 are not described in detail here.

[0035] refer to Figure 7 As shown, in order to minimize the shading area of ​​the first metal interconnect structure 130 on the photodiode 111, the first in-layer interconnect layer 132 extends from the length direction of each photodiode 111 (i.e., the lateral direction in the figure) to a portion above each photodiode 111.

[0036] refer to Figure 8 As shown, in some embodiments of this application, the first surface 101 of the semiconductor substrate 100 is further formed with a first interlayer dielectric layer 140 covering the semiconductor substrate 100 and the first metal interconnect structure 130. Figure 7 (omitted). The material of the first interlayer dielectric layer 140 includes insulating dielectric materials such as silicon oxide or silicon nitride.

[0037] refer to Figure 7 As shown, in the technical solution of this application, the first inner interconnect layer 132 is a single metal layer, which covers a smaller area of ​​the photodiode and blocks less light, thereby increasing the amount of light entering the photodiode.

[0038] In some embodiments of this application, after the first metal interconnect structure 130 is formed, the second surface 102 of the semiconductor substrate 100 is thinned.

[0039] In some embodiments of this application, the method for thinning the second surface 102 of the semiconductor substrate 100 is, for example, to: flip the semiconductor substrate 100 and use a carrier wafer as a carrier to support the first surface 101 of the semiconductor substrate 100; and to grind and thin the second surface 102 of the semiconductor substrate 100 using a chemical mechanical polishing process.

[0040] refer to Figure 9 As shown, a plurality of transistor structures 150 and a second metal interconnect structure 160 electrically connecting the plurality of transistor structures 150 are formed on the second surface 102 of the semiconductor substrate 100. The transistor structures 150 serve as logic devices in the image sensor structure of this application, and the second metal interconnect structure 160 serves as the circuit interconnect layer of the logic devices.

[0041] refer to Figure 9 As shown, in some embodiments of this application, the plurality of transistor structures 150 include: a gate structure 151 located on the second surface 102 of the semiconductor substrate 100, and a source 152 and a drain 153 located on both sides of the gate structure 151 in the semiconductor substrate 100. The number of the plurality of transistor structures 150 can be arbitrary; only two are shown here as an example. Transistor structures are common basic structures in the semiconductor field, therefore, the detailed structure and formation process of the transistor structure 150 are not described here, but those skilled in the art can understand the fabrication steps of the transistor structure 150 based on common knowledge.

[0042] refer to Figure 9As shown, in some embodiments of this application, the number and position of the plurality of pixel regions 110 correspond to the number and position of the plurality of transistor structures 150. The correspondence between the number and position of the plurality of pixel regions 110 and the plurality of transistor structures 150 means that, according to the dimensions in the actual design, the positions of the plurality of pixel regions 110 and the plurality of transistor structures 150 approximately coincide in the vertical direction. Those skilled in the art should understand that the number and position of the plurality of pixel regions 110 and the plurality of transistor structures 150 may also be different.

[0043] refer to Figure 9 As shown, in some embodiments of this application, the second metal interconnect structure 160 includes: a plurality of second contact structures 161 that are respectively electrically connected to the gate structure 151, source 152, and drain 153 of the plurality of transistor structures 150 and the buried metal structure 120; a second inner interconnect layer 162 that is electrically connected to the plurality of second contact structures 161; and a metal pad structure 163 that is electrically connected to the second inner interconnect layer 162. The metal interconnect process in the back-end process is also a conventional basic process in the semiconductor technology field; therefore, the detailed structure and formation steps of the first metal interconnect structure 160 are not described in detail here.

[0044] refer to Figure 9 As shown, in some embodiments of this application, the second surface 102 of the semiconductor substrate 100 is further formed with a second interlayer dielectric layer 170 covering the semiconductor substrate 100 and the transistor structure 150 and filling the gaps of the second metal interconnect structure 160. The material of the second interlayer dielectric layer 170 includes insulating dielectric materials such as silicon oxide or silicon nitride.

[0045] In conventional image sensor structures, logic devices and circuits, along with pixel devices and circuits, are formed on the front side of a semiconductor substrate. Light is easily blocked by these circuits, affecting image quality and low-light performance, and also limiting the number of pixel units and the photosensitive area. However, in this application's solution, pixel devices and circuits are formed on the first surface 101 of the semiconductor substrate, while logic devices and circuits are formed on the second surface 102. A buried metal structure 120 is used as the connection point for the pixel circuits and logic circuits, reducing the number of interconnect layers in the pixel circuits (only one interconnect layer 132 is needed on the first surface 101 to connect to the buried metal structure; light loss can be almost completely avoided through this design). This reduces the light blocking caused by the circuit interconnect layers and frees up space for the pixel units. This application's solution can simultaneously improve the image quality and low-light performance of the image sensor, as well as increase the number of pixel units and the photosensitive area, resulting in an overall performance improvement.

[0046] Compared to stacked image sensors, this application eliminates the need to stack two wafers. With further reduction in logic wafer nodes and a further increase in the number of transistors, it is more conducive to heat dissipation during CIS chip operation.

[0047] refer to Figure 10 As shown, in some embodiments of this application, the method for forming the image sensor structure further includes: forming a plurality of filters 180 on the surface of the first interlayer dielectric layer 140 (above the first metal interconnect structure 130) corresponding to the plurality of pixel regions 110, and a plurality of microlenses 190 located above the plurality of filters 180. Filters and microlenses are also basic structures in image sensors, therefore their detailed structures and fabrication processes will not be described in detail here.

[0048] In some embodiments of this application, the microlens 180 is located directly above the pixel region 110 and the projected area of ​​the microlens 180 in the vertical direction is larger than the area of ​​the pixel region 110, so that light can fully enter the pixel unit.

[0049] This application provides a method for forming an image sensor structure that can simultaneously improve the image quality and low-light performance of the image sensor, as well as increase the number of pixel units and the photosensitive area.

[0050] Embodiments of this application also provide an image sensor structure, see reference. Figure 10 As shown, the semiconductor substrate 100 includes a first surface 101 and a second surface 102 facing each other. The first surface 101 includes a plurality of pixel regions 110 arranged in an array, and at least one photodiode 111 is formed in each pixel region 110. A buried metal structure 120 is located in the semiconductor substrate 100 between adjacent pixel regions 110. The first surface 101 of the semiconductor substrate 100 has a first metal interconnect structure 130 that electrically connects the at least one photodiode 111 and the buried metal structure 120. The second surface 102 of the semiconductor substrate 100 has a plurality of transistor structures 150 and a second metal interconnect structure 160 that electrically connects the plurality of transistor structures 150 and the buried metal structure 120.

[0051] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.

[0052] In some embodiments of this application, the number of pixel regions 110 is multiple. For the sake of brevity, this application only shows four pixel regions 110 arranged in an array as an example.

[0053] refer to Figure 3 As shown, in some embodiments of this application, the buried metal structure 120 is located in the semiconductor substrate 100 at the center of every four adjacent pixel regions 110 arranged in an array. This region ensures that each buried metal structure 120 is surrounded by four pixel regions simultaneously, reducing the density and number of buried metal structures 120, saving costs while reducing circuit crosstalk in the metal interconnects. Furthermore, the distance from this location to the four adjacent pixel regions is equidistant, avoiding signal transmission delay errors.

[0054] In some embodiments of this application, the buried metal structure 120 is completely buried within the semiconductor substrate 100. The top surface of the buried metal structure 120 may be higher or lower than the bottom surface of the pixel region 110, and the bottom surface of the buried metal structure 120 is lower than the bottom surface of the pixel region 110.

[0055] In some embodiments of this application, the number of photodiodes 111 can be arbitrary; this application only uses three photodiodes as an example. Photodiodes are a basic structure of image sensors, and their formation methods are well known to those skilled in the art.

[0056] In some embodiments of this application, the first metal interconnect structure 130 includes: a plurality of first contact structures 131 electrically connecting the at least one photodiode 111 and the buried metal structure 120 respectively; and a first internal interconnect layer 132 electrically connecting the plurality of first contact structures 131. The first internal interconnect layer 132 is a single metal layer. The metal interconnect process in the later stages is also a conventional basic process in the field of semiconductor technology, therefore, the detailed structure and formation steps of the first metal interconnect structure 130 are not described in detail here.

[0057] refer to Figure 7 As shown, in order to minimize the shading area of ​​the first metal interconnect structure 130 on the photodiode 111, the first in-layer interconnect layer 132 extends from the length direction of each photodiode 111 (i.e., the lateral direction in the figure) to a portion above each photodiode 111.

[0058] In some embodiments of this application, the first surface 101 of the semiconductor substrate 100 is further formed with a first interlayer dielectric layer 140 covering the semiconductor substrate 100 and the first metal interconnect structure 130. The material of the first interlayer dielectric layer 140 includes insulating dielectric materials such as silicon oxide or silicon nitride.

[0059] In the technical solution of this application, the first inner interconnect layer 132 is a single metal layer, which covers a smaller area of ​​the photodiode and blocks the photodiode less, thereby increasing the amount of light entering.

[0060] In some embodiments of this application, the transistor structure 150 serves as a logic device in the image sensor structure of this application, and the second metal interconnect structure 160 serves as the circuit connection layer of the logic device.

[0061] In some embodiments of this application, the plurality of transistor structures 150 includes: a gate structure 151 located on the second surface 102 of the semiconductor substrate 100, and a source 152 and a drain 153 located on both sides of the gate structure 151 in the semiconductor substrate 100. The number of the plurality of transistor structures 150 can be arbitrary; only two are shown here as an example. Transistor structures are common basic structures in the semiconductor field, therefore, the detailed structure and formation process of the transistor structure 150 are not described in detail here, but those skilled in the art can understand the fabrication steps of the transistor structure 150 based on common general knowledge.

[0062] In some embodiments of this application, the number and position of the plurality of pixel regions 110 correspond to the number and position of the plurality of transistor structures 150. The correspondence between the number and position of the plurality of pixel regions 110 and the plurality of transistor structures 150 means that, according to the dimensions in the actual design, the positions of the plurality of pixel regions 110 and the plurality of transistor structures 150 approximately coincide in the vertical direction. Those skilled in the art will understand that the number and position of the plurality of pixel regions 110 and the plurality of transistor structures 150 may also be different.

[0063] In some embodiments of this application, the second metal interconnect structure 160 includes: a plurality of second contact structures 161 electrically connecting the gate structure 151, source 152, and drain 153 of the plurality of transistor structures 150 and the buried metal structure 120; a second inner interconnect layer 162 electrically connecting the plurality of second contact structures 161; and a metal pad structure 163 electrically connecting the second inner interconnect layer 162. The metal interconnect process in the later stages is also a conventional basic process in the semiconductor technology field; therefore, the detailed structure and formation steps of the first metal interconnect structure 160 are not described in detail here.

[0064] In some embodiments of this application, the second surface 102 of the semiconductor substrate 100 is further formed with a second interlayer dielectric layer 170 covering the semiconductor substrate 100 and the transistor structure 150 and filling the gaps of the second metal interconnect structure 160. The material of the second interlayer dielectric layer 170 includes insulating dielectric materials such as silicon oxide or silicon nitride.

[0065] In conventional image sensor structures, logic devices and circuits, along with pixel devices and circuits, are formed on the front side of a semiconductor substrate. Light is easily blocked by these circuits, affecting image quality and low-light performance, and also limiting the number of pixel units and the photosensitive area. In contrast, the present application's solution forms pixel devices and circuits on the first surface 101 of the semiconductor substrate, while logic devices and circuits are formed on the second surface 102. A buried metal structure 120 serves as the connection point between the pixel circuits and the logic circuits, reducing the number of interconnect layers in the pixel circuits. This reduces the light blocking caused by the interconnect layers and frees up space for the pixel units. The present application's solution simultaneously improves image quality and low-light performance while increasing the number of pixel units and the photosensitive area, resulting in a comprehensive performance improvement.

[0066] Compared to stacked image sensors, this application eliminates the need to stack two wafers. With further reduction in logic wafer nodes and a further increase in the number of transistors, it is more conducive to heat dissipation during CIS chip operation.

[0067] In some embodiments of this application, the image sensor structure further includes: a plurality of filters 180 located on the surface of the first interlayer dielectric layer 140 (above the first metal interconnect structure 130) corresponding to the plurality of pixel regions 110, and a plurality of microlenses 190 located above the plurality of filters 180. Filters and microlenses are also basic structures in image sensors, therefore their detailed structures and fabrication processes will not be described in detail here.

[0068] In some embodiments of this application, the microlens 180 is located directly above the pixel region 110 and the projected area of ​​the microlens 180 in the vertical direction is larger than the area of ​​the pixel region 110, so that light can fully enter the pixel unit.

[0069] This application provides a method for forming an image sensor structure that can simultaneously improve the image quality and low-light performance of the image sensor, as well as increase the number of pixel units and the photosensitive area.

[0070] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0071] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0072] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0073] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0074] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming an image sensor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface opposite to each other, the first surface including a plurality of pixel regions arranged in an array; A buried metal structure is formed in a semiconductor substrate between adjacent pixel regions; At least one photodiode is formed in the pixel region; A first metal interconnect structure is formed on the first surface of the semiconductor substrate to electrically connect the at least one photodiode and the buried metal structure; A plurality of transistor structures and a second metal interconnect structure electrically connecting the plurality of transistor structures and the buried metal structure are formed on the second surface of the semiconductor substrate.

2. The method for forming the image sensor structure as described in claim 1, characterized in that, The buried metal structure is located in a semiconductor substrate at the center of every four adjacent pixel regions arranged in an array.

3. The method for forming the image sensor structure as described in claim 1, characterized in that, The first metal interconnect structure includes: a plurality of first contact structures that are electrically connected to the at least one photodiode and the buried metal structure respectively; and a first inner interconnect layer that is electrically connected to the plurality of first contact structures.

4. The method for forming the image sensor structure as described in claim 1, characterized in that, The plurality of transistor structures include: a gate structure located on the second side of the semiconductor substrate, and a source and a drain located on both sides of the gate structure in the semiconductor substrate.

5. The method for forming the image sensor structure as described in claim 4, characterized in that, The second metal interconnect structure includes: a plurality of second contact structures that are electrically connected to the gate, source, and drain of the plurality of transistor structures and the buried metal structure respectively; a second inner interconnect layer that is electrically connected to the plurality of second contact structures; and a metal pad structure that is electrically connected to the second inner interconnect layer.

6. The method for forming the image sensor structure as described in claim 1, characterized in that, Also includes: A plurality of filters corresponding to the plurality of pixel regions are formed above the first metal interconnect structure, and a plurality of microlenses are formed above the plurality of filters.

7. An image sensor structure, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to each other, the first surface including a plurality of pixel regions arranged in an array, wherein at least one photodiode is formed in the pixel regions; Buried metal structures are located in semiconductor substrates between adjacent pixel regions; A first metal interconnect structure is formed on the first surface of the semiconductor substrate, which electrically connects the at least one photodiode and the buried metal structure. The second surface of the semiconductor substrate has a plurality of transistor structures and a second metal interconnect structure electrically connecting the plurality of transistor structures and the buried metal structure.

8. The image sensor structure as described in claim 7, characterized in that, The buried metal structure is located in a semiconductor substrate at the center of every four adjacent pixel regions arranged in an array.

9. The image sensor structure as described in claim 7, characterized in that, The first metal interconnect structure includes: a plurality of first contact structures that are electrically connected to the at least one photodiode and the buried metal structure respectively; and a first inner interconnect layer that is electrically connected to the plurality of first contact structures.

10. The image sensor structure as described in claim 7, characterized in that, The plurality of transistor structures include: a gate structure located on the second side of the semiconductor substrate, and a source and a drain located on both sides of the gate structure in the semiconductor substrate.

11. The image sensor structure as described in claim 10, characterized in that, The second metal interconnect structure includes: a plurality of second contact structures that are electrically connected to the gate, source, and drain of the plurality of transistor structures and the buried metal structure respectively; a second inner interconnect layer that is electrically connected to the plurality of second contact structures; and a metal pad structure that is electrically connected to the second inner interconnect layer.

12. The image sensor structure as described in claim 7, characterized in that, Also includes: A plurality of filters located above the first metal interconnect structure and corresponding to the plurality of pixel regions, and a plurality of microlenses located above the plurality of filters.

Images