Light emitting diode chip and manufacturing method thereof

Abstract

The invention provides a light emitting diode chip and a manufacturing method thereof, and belongs to the technical field of semiconductors. The light emitting diode chip comprises an epitaxial layer, a transparent conductive layer, a first electrode and a second electrode. The epitaxial layer comprises a first semiconductor layer, a second semiconductor layer and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; the transparent conducting layer is positioned on the second semiconductor layer and is in direct contact with the second semiconductor layer; the first electrode is connected with the first semiconductor layer, and the second electrode is connected with the transparent conductive layer; the transparent conductive layer is provided with a plurality of first through holes which are arranged at intervals, and the orthographic projection of the plurality of first through holes on one surface of the second semiconductor layer is not overlapped with the orthographic projection of the second electrode on the surface of the second semiconductor layer. The light emitting efficiency of the light emitting diode chip can be improved.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a light-emitting diode chip and its manufacturing method. Background Technology

[0002] With the widespread use of light-emitting diode (LED) chips, the market demand for products with high brightness, low voltage, and high luminous efficiency is increasing. Transparent conductive layers, such as indium tin oxide (ITO) films, are widely used in LED chips due to their combination of high conductivity and high light transmittance.

[0003] In related technologies, a light-emitting diode (LED) chip includes a substrate and an epitaxial layer, a transparent conductive layer, a first electrode, and a second electrode sequentially stacked on the substrate. The first electrode is in ohmic contact with the n-type layer of the epitaxial layer, and the second electrode is in ohmic contact with the p-type layer of the epitaxial layer through the transparent conductive layer.

[0004] However, the conductivity of the transparent conductive layer depends on its internal doping. For example, the conductivity of indium tin oxide (ITO) films is positively correlated with Sn doping. Increasing the doping concentration of the dopant enhances the absorption and scattering of visible light by the transparent conductive layer, leading to a decrease in transmittance and ultimately affecting the brightness of the LED chip. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) chip and its fabrication method, which can improve the brightness of the LED chip while ensuring the conductivity of the transparent conductive layer. The technical solution is as follows: This disclosure provides a light-emitting diode (LED) chip, which includes an epitaxial layer, a transparent conductive layer, a first electrode, and a second electrode. The epitaxial layer includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer. The transparent conductive layer is located on the second semiconductor layer and is in direct contact with it. The first electrode is connected to the first semiconductor layer, and the second electrode is connected to the transparent conductive layer. The transparent conductive layer has a plurality of spaced-apart first vias, and the orthographic projection of the plurality of first vias onto a surface of the second semiconductor layer does not overlap with the orthographic projection of the second electrode onto the surface of the second semiconductor layer.

[0006] In another implementation of this disclosure, the cross-sectional area of ​​the first via increases monotonically along the normal direction of the surface of the second semiconductor layer and toward the surface, and the cross-section of the first via is a plane parallel to the surface of the second semiconductor layer.

[0007] In another implementation of this disclosure, the angle between the wall of the first via and the surface of the second semiconductor layer is 30-70°.

[0008] In another implementation of this disclosure, the orthographic projection of the cross-section of the first via onto the surface of the second semiconductor layer is a regular polygon, and the number of sides of the regular polygon is 3-10.

[0009] In another implementation of this disclosure, the vertices of the regular polygon are all rounded.

[0010] In another implementation of this disclosure, the diameter of the largest circumscribed circle of the first through hole is 2-10 μm.

[0011] In another implementation of this disclosure, the plurality of first through holes are evenly arranged, and the arrangement density is 50-200 holes / mm. 2 .

[0012] In another implementation of this disclosure, the light-emitting diode chip further includes a passivation layer, which is located on the side of the transparent conductive layer away from the second semiconductor layer; The passivation layer has second through holes that correspond one-to-one with a plurality of first through holes, and each second through hole is connected to the corresponding first through hole.

[0013] In another implementation of this disclosure, the orthographic projection of the second via on the surface of the second semiconductor layer is located inside the orthographic projection of the corresponding first via on the surface of the second semiconductor layer.

[0014] On the other hand, this disclosure also provides a method for fabricating a light-emitting diode chip, the method comprising: sequentially forming an epitaxial layer and a transparent conductive layer, and fabricating a first electrode and a second electrode; the epitaxial layer comprising a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; the transparent conductive layer being located above the second semiconductor layer and in direct contact with the second semiconductor layer; the first electrode being connected to the first semiconductor layer, and the second electrode being connected to the transparent conductive layer; the transparent conductive layer having a plurality of spaced-apart first vias, the orthographic projection of the plurality of first vias onto a surface of the second semiconductor layer not overlapping the orthographic projection of the second electrode onto the surface of the second semiconductor layer.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: When using the light-emitting diode chip provided in this embodiment, since a first through-hole is provided in the transparent conductive layer of the light-emitting diode chip, and the first through-hole penetrates the transparent conductive layer, opening multiple first through-holes is equivalent to directly removing part of the transparent conductive layer that absorbs light. When light shines on the chip, it can pass directly through the first through-hole without passing through the transparent conductive layer, reducing the light absorption loss of the transparent conductive layer and thus improving the overall light transmittance.

[0016] Furthermore, the first via acts as a light-transmitting channel, allowing light emitted from the epitaxial layer to escape directly while reducing multiple reflections and folding losses at the interfaces between the transparent conductive layer and air, substrate, etc. Simultaneously, the sidewalls of the first via can form microstructures, altering the direction of light propagation and allowing light that was originally blocked or absorbed by the transparent conductive layer to escape more easily, indirectly improving light extraction efficiency.

[0017] In other words, the presence of the first through hole makes the transparent conductive layer present a "hollowed-out" structure, and the effective area of ​​the transparent conductive layer that actually participates in blocking and absorbing light will also be reduced in effect. At the same time, it also reduces light reflection, ultimately improving light transmittance and reducing light loss. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip provided in an embodiment of this disclosure; Figure 2 yes Figure 1 Cross-sectional view along the AA direction; Figure 3 This is a flowchart illustrating a method for manufacturing a light-emitting diode chip according to an embodiment of this disclosure; Figure 4 This is a flowchart of another method for manufacturing a light-emitting diode chip provided in this embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure after the epitaxial layer is etched to expose the first semiconductor layer. Figure 6 This is a schematic diagram of the current blocking layer structure; Figure 7 This is a schematic diagram showing the arrangement of the first through-hole on the transparent conductive layer; Figure 8 This is a schematic diagram showing the arrangement of the third through hole; Figure 9 This is a schematic diagram showing the arrangement of the first and second electrodes; Figure 10 This is a schematic diagram of the structure of a light-emitting diode chip provided in related technologies.

[0020] The symbols in the diagram represent the following meanings: 1. Substrate; 2. Epitaxial layer; 21. First semiconductor layer; 22. Second semiconductor layer; 23. Light-emitting layer; 4. Transparent conductive layer; 401. First through-hole; 402. Third through-hole; 51. First electrode; 52. Second electrode; 6. Passivation layer; 601. Second through-hole; 7. Current blocking layer; 100. U-shaped structure. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] This disclosure provides a light-emitting diode chip, such as... Figure 1 and Figure 2 As shown, the light-emitting diode chip includes an epitaxial layer 2, a transparent conductive layer 4, a first electrode 51, and a second electrode 52.

[0023] The epitaxial layer 2 includes a first semiconductor layer 21, a second semiconductor layer 22, and a light-emitting layer 23 located between the first semiconductor layer 21 and the second semiconductor layer 22; The transparent conductive layer 4 is located on top of and in direct contact with the second semiconductor layer 22. The first electrode 51 is connected to the first semiconductor layer 21, and the second electrode 52 is connected to the transparent conductive layer 4.

[0024] The transparent conductive layer 4 has a plurality of first through holes 401 arranged at intervals. The orthographic projection of the plurality of first through holes 401 on one surface of the second semiconductor layer 22 does not overlap with the orthographic projection of the second electrode 52 on the surface of the second semiconductor layer 22.

[0025] When using the light-emitting diode chip provided in this embodiment, since a first through-hole 401 is provided in the transparent conductive layer 4 of the light-emitting diode chip, and the first through-hole 401 penetrates the transparent conductive layer 4, opening multiple first through-holes 401 is equivalent to directly removing part of the transparent conductive layer 4 that absorbs light. When light shines on the chip, it can pass directly through the first through-hole 401 without passing through the transparent conductive layer 4, reducing the absorption loss of light by the transparent conductive layer 4, thereby improving the overall light transmittance.

[0026] Furthermore, the first via 401 acts as a light-transmitting channel, allowing light emitted from the epitaxial layer 2 to exit directly while reducing multiple reflections and folding losses at the interfaces between the transparent conductive layer 4 and air, substrate, etc. Simultaneously, during the formation of the first via 401, a microstructure with nano- or micron-scale rough textures is formed on its sidewall surface. These microstructures alter the direction of light propagation, making it easier for light that was originally blocked or absorbed by the transparent conductive layer 4 to escape, indirectly improving light extraction efficiency.

[0027] In other words, the presence of the first through hole 401 makes the transparent conductive layer 4 present a "hollowed-out" structure, and the effective area of ​​the transparent conductive layer 4 that actually participates in blocking and absorbing light will also be reduced in a disguised way. At the same time, it also reduces light reflection, ultimately improving light transmittance and reducing light loss.

[0028] In this embodiment, both the first semiconductor layer 21 and the second semiconductor layer 22 can be gallium nitride layers.

[0029] The light-emitting diode provided in this embodiment is a front-mounted structure. The surface of the epitaxial layer 2 away from the substrate 1 is etched to expose the U-shaped structure 100 (see [reference]). Figure 5 The first semiconductor layer 21 is exposed. The first electrode 51 is in ohmic contact with the exposed first semiconductor layer 21. The second electrode 52 is in direct ohmic contact with the transparent conductive layer 4.

[0030] In this embodiment, the transparent conductive layer 4 is an indium tin oxide thin film layer. In other examples, it can be aluminum-doped zinc oxide, fluorine-doped tin oxide, or indium-doped zinc oxide, etc.

[0031] Optionally, along the normal direction of the surface of the second semiconductor layer 22 and toward the surface, the area of ​​the cross-section of the first via 401 increases monotonically, and the cross-section of the first via 401 is a plane parallel to the surface of the second semiconductor layer 22.

[0032] In the above implementation, this design means that the first through hole 401 is a funnel shape with a smaller top and a larger bottom, which is a frustum structure.

[0033] Since the refractive index of the epitaxial layer is generally higher than that of air and the transparent conductive layer 4, light rays are prone to total internal reflection when they travel from the epitaxial layer to the transparent conductive layer 4 and cannot escape. The inclined sidewall of the frustum-shaped first through-hole 401 can adjust the propagation angle of the light, so that the light rays that originally met the conditions for total internal reflection can meet the emission requirements after being refracted by the sidewall and can be emitted more smoothly from the first through-hole 401, reducing the total internal reflection loss of the light rays.

[0034] See Figure 2Because the refractive index of epitaxial layer 2 (e.g., GaN, approximately 2.4) is significantly higher than that of the transparent conductive layer 4 above it (e.g., indium tin oxide film, 1.9-2.0), when light travels from epitaxial layer 2 to transparent conductive layer 4, if the incident angle α is too large, total internal reflection will occur at the interface between epitaxial layer 2 and transparent conductive layer 4, confining the light within epitaxial layer 2 and ultimately leading to absorption. However, in the above structure, the sloping sidewall of the frustum-shaped first through-hole 401 physically alters the light propagation path. The sloping sidewall allows light to reach the interface at a smaller incident angle β, thus avoiding total internal reflection at the interface and allowing the light to escape.

[0035] Moreover, the frustum-shaped first via 401 facilitates etching during the fabrication process (such as dry etching), avoids bottom residue or sidewall damage, and ensures the contact quality between the bottom of the first via 401 and the epitaxial layer 2; at the same time, the inclined sidewall stress distribution of the first via 401 is more uniform, reducing the risk of film cracking and detachment, and improving the stability of the chip structure.

[0036] Optionally, the cross-section of the first via 401, when projected onto the surface of the second semiconductor layer 22, is a regular polygon. The number of sides of the regular polygon is 3-10.

[0037] In the above implementation, the first through hole 401 of the regular polygon not only allows light to pass through smoothly, but is also easy to manufacture.

[0038] In this embodiment, the cross-section of the first via 401 projected onto the substrate 1 is a regular hexagon. A regular hexagon is the closest polygon to a circle, enabling a close, gapless arrangement. Within the same chip area, the total area of ​​the regular hexagonal first via 401 is larger than that of the square or circular second vias, allowing for the removal of more light-absorbing areas from the transparent conductive layer 4, thus improving light transmission efficiency. Furthermore, a regular hexagon can be easily achieved through photolithography, and the tilt of the sidewalls (such as the frustum mentioned earlier) is easier to control during etching. Compared to the higher requirements for photolithographic alignment in circular vias and the greater risk of etching residue in square vias, the regular hexagon offers stronger process compatibility and higher yield.

[0039] Optionally, multiple vertices of the regular polygon are rounded.

[0040] Furthermore, the multiple parallel sidewalls and vertices of the regular polygon are rounded, allowing for a more uniform adjustment of the light propagation angle. Compared to sharp corners (which easily lead to light reflection and refraction) and the single curvature of a circle (which has a limited range of angle adjustment), this design allows more totally internally reflected light to escape through refraction at the sidewalls, reducing light loss. Simultaneously, the rounded transitions also result in a more uniform stress distribution on the regular polygon, with the stress concentration on the sidewalls of the first through-hole 401 being significantly lower than that of the square first through-hole 401 (where stress tends to accumulate at right angles). This structure prevents the transparent conductive layer 4 from cracking or detaching due to excessive perforation, while ensuring the flatness of the epitaxial layer 2 surface and not affecting the overall reliability of the chip structure.

[0041] Optionally, the first through holes 401 are evenly distributed, with a density of 50-200 holes / mm. 2 .

[0042] The uniform arrangement of the first vias 401 mentioned above refers to the fact that the orthographic projection of the first vias 401 on the substrate 1 is arranged in a regular array. That is, the spacing between two adjacent orthographic projections in each column or each row is equal.

[0043] In the above implementation, the first through hole 401 is configured with 50-200 holes / mm. 2 The optimal density range allows for the removal of a sufficient amount of light-absorbing area from the transparent conductive layer through multiple uniformly distributed first vias 401, significantly improving light transmittance. Furthermore, it avoids disrupting the continuous structure of the transparent conductive layer due to excessive perforation, ensuring that the remaining transparent conductive layer still meets the chip's lateral conductivity requirements and preventing insufficient conductivity. Moreover, it ensures a uniform distribution of the light-transmitting area on the chip surface, preventing localized light concentration or severe light blocking and reducing uneven light emission. Simultaneously, the close-packed hexagonal structure combined with this density maximizes the light-transmitting area, allowing light emitted from the epitaxial layer 2 to escape smoothly from all areas, reducing light loss. Furthermore, the uniform arrangement of the first vias 401 ensures a uniform stress distribution in the transparent conductive layer, preventing stress concentration caused by excessive localized perforation and reducing the risk of film cracking and detachment.

[0044] Optionally, the diameter of the largest circumscribed circle of the first through hole 401 is 2-10 μm.

[0045] In the above implementation, the maximum outer circle diameter of the first through hole 401 is 2-10μm, which makes the light-transmitting area of ​​each first through hole 401 large enough, effectively reducing the light-absorbing area of ​​the transparent conductive layer; at the same time, it will not cause the remaining skeleton of the transparent conductive layer to be too narrow due to the excessive aperture, avoiding stress concentration or breakage of the conductive path, and ensuring the stability of the thin film structure and its lateral conductivity.

[0046] Optionally, the radius of the arc at the angle between adjacent sidewalls of the first through hole 401 is 0.5-2μm.

[0047] In the above implementation, if the walls of the first via 401 are sharp angles, these angles become stress concentration points. Thermal cycling and external forces during the fabrication or use of the LED chip can easily cause these points to crack and detach. A 0.5-2μm arc can disperse stress, making the stress on the transparent conductive layer and epitaxial layer 2 around the first via 401 more uniform, preventing structural damage and extending chip lifespan. Furthermore, sharp angles can cause chaotic light scattering at the hole walls, with some light being reflected back by the transparent conductive layer or the chip's interior, increasing absorption loss. A rounded transition allows light to refract more regularly at the hole walls, guiding light out smoothly, while reducing light obstruction and scattering at the hole edges, indirectly improving light transmission efficiency.

[0048] Optionally, the planar roughness Ra of the transparent conductive layer 4 is 5-20 nm.

[0049] It should be noted that the planar roughness Ra of the transparent conductive layer 4 refers to the roughness of the surface of the unetched transparent conductive layer 4.

[0050] The calculation method is to take the arithmetic mean of the vertical distances from each point on the surface profile of the transparent conductive layer 4 to the reference plane within a sampling length L (the area under test). The reference plane is an imaginary plane that minimizes the sum of the squares of the distances from all points on the surface under test to this plane.

[0051] In the above implementation, the planar roughness Ra of the transparent conductive layer 4 is 5-20 nm, which allows the surface of the transparent conductive layer 4 to form micro-nano textures, thereby breaking the specular reflection of light and increasing the diffuse reflection ratio. This makes it more difficult for the light emitted by the epitaxial layer 2 to undergo total internal reflection at the interface between the transparent conductive layer 4 and the air / current blocking layer 7, making it easier for the light to escape from the chip and indirectly improving the light transmission and luminous efficiency.

[0052] Optionally, the angle α between the wall of the first via 401 and the surface of the second semiconductor layer 22 is 30-70°.

[0053] In the above implementation, the design means that the tilt angle of the first via 401 is 30-70°. This allows the tilted sidewall of the first via 401 to effectively adjust the light propagation angle, breaking the total internal reflection limitation caused by the difference in refractive index between the epitaxial layer 2 and air. Light that was originally trapped inside the chip by total internal reflection can meet the emission conditions after being refracted by the tilted sidewall, greatly reducing light loss and directly improving light transmission efficiency.

[0054] If the tilt is too small (<30°), approaching a vertical aperture, the light refraction effect is limited; if it is too large (>70°), the top opening of the through-hole will be too large and the bottom too narrow, which will reduce the effective light transmission area and may also make the remaining skeleton of the transparent conductive layer too thin, affecting the structural stability. The 30-70° range can ensure that the transparent conductive layer 4 has a large light transmission area while also having strong structural load-bearing capacity.

[0055] In this embodiment, the inclination angle of the first through-hole 401 is 60°. This allows the transparent conductive layer 4 to not only have a large light-transmitting area but also a strong structural load-bearing capacity.

[0056] Optionally, the thickness of the transparent conductive layer 4 is 200 Å - 300 Å.

[0057] In the above implementation, the absorption of visible light by the transparent conductive layer 4 increases with thickness. Setting the thickness of the transparent conductive layer 4 to 200-300 Å makes it ultra-thin, significantly reducing its own light absorption and scattering. Combined with the first via 401 structure, light emitted from the epitaxial layer can pass through almost unobstructed, directly improving the chip's brightness. Simultaneously, although the transparent conductive layer 4 is thin, the 200-300 Å thickness ensures the continuity of the Sn-doped carrier channels. With a reasonable Sn doping concentration, the lateral conductivity requirements of the chip can be met. Low resistance can be achieved without relying on excessively high doping concentrations, avoiding the contradiction of "high doping reduces light transmittance" and meeting the low-voltage design goal. Furthermore, the ultra-thin transparent conductive layer has lower internal stress and a tighter interface with the underlying current blocking layer 7 and epitaxial layer 2, reducing the likelihood of cracking or detachment. It also adapts to thermal cycling and etching processes during chip fabrication, reducing the risk of structural damage.

[0058] Furthermore, a thickness of 200 Å to 300 Å allows the refractive index of the transparent conductive layer to achieve good optical matching with air and the epitaxial layer, reducing interface reflection loss. This thickness is also within the controllable range of conventional fabrication processes such as magnetron sputtering, enabling precise control of film uniformity and improving production yield.

[0059] Optionally, the light-emitting diode chip further includes a passivation layer 6, which is located on the side of the transparent conductive layer 4 away from the second semiconductor layer 22. The passivation layer 6 has a plurality of second vias 601 corresponding one-to-one with the first vias 401. Each second via 601 is connected to the corresponding first via 401.

[0060] In the above implementation, the passivation layer 6 is used to cover the surface of the epitaxial layer 2 and the surface of the transparent conductive layer 4. That is, the passivation layer 6 is deposited not only on the surface of the transparent conductive layer 4, but also on the exposed surface of the epitaxial layer 2, and the passivation layer 6 enters the first via 401 (not shown in the figure).

[0061] The passivation layer 6 is used to isolate the transparent conductive layer from air, moisture, and acidic / alkaline environments, preventing oxidation and corrosion of the transparent conductive layer. It also prevents external impurities from intruding into the epitaxial layer 2, ensuring the long-term stability and lifespan of the chip. Furthermore, the passivation layer 6 covers the surface of the transparent conductive layer 4, filling surface defects and micropores, reducing leakage current at the chip surface, and preventing a decrease in luminous efficiency or an increase in power consumption due to leakage. It also buffers mechanical damage to the transparent conductive layer 4 from subsequent processes.

[0062] The second through-hole 601 is connected to the first through-hole 401 one by one, forming a complete light-transmitting channel from epitaxial layer 2 to first through-hole 401 to second through-hole 601 to air. This will not block the light-transmitting function of the first through-hole 401, ensuring that the previously designed light-transmitting gain is not canceled out by the passivation layer.

[0063] Optionally, the orthographic projection of the second via 601 on the surface of the second semiconductor layer 22 is located inside the orthographic projection of the first via 401 on the surface of the second semiconductor layer 22. The orthographic projection of the second via 601 on the surface of the second semiconductor layer 22 is also a regular hexagon, and the six vertices of the regular hexagon are all rounded.

[0064] The above settings allow the second via 601 to be adapted to the tilt and size of the first via 401, while guiding light to exit the chip more smoothly and reducing scattering loss at the interface of the two vias.

[0065] Optionally, the passivation layer 6 is SiO2 or SiN. x Layers or SiO2, SiN x A structure formed by alternating layers.

[0066] This design not only makes the passivation layer 6 insulating, but also isolates it from air, moisture, and acidic / alkaline environments, preventing the transparent conductive layer from being oxidized and corroded. It also prevents external impurities from intruding into the epitaxial layer 2, ensuring the long-term stability and lifespan of the chip. Furthermore, these features allow the refractive index of the passivation layer 6 to fall between that of the transparent conductive layer 4 and air, reducing light reflection loss at the interface between the transparent conductive layer 4 and air, indirectly improving the overall light extraction efficiency.

[0067] In this embodiment, the passivation layer 6 is SiO2. This facilitates the fabrication of the passivation layer 6.

[0068] The shape and size of the cross-section of the second through hole 601 are fixed, meaning the cross-section is the same at any position. The diameter of the circumscribed circle of the second through hole 601 is 1-2 μm.

[0069] In the above implementation, the diameter of the outer circle of the second through hole 601 is 1-2μm, which allows the second through hole 601 to be located inside the top opening of the first through hole 401, forming a stepped light transmission channel that is wider at the bottom and narrower at the top. This not only does not block the light transmission path of the first through hole 401, but also reduces the intrusion of external impurities through the smaller top opening, thus balancing light transmission and protection.

[0070] Optionally, the thickness of the passivation layer 6 is 2500 Å-2600 Å, which is 250 nm-260 nm.

[0071] In the above implementation, a thickness of 250nm-260nm can form a dense and uniform protective layer, effectively isolating water vapor, oxygen and external pollutants, completely avoiding oxidation and corrosion of the transparent conductive layer and the intrusion of impurities in the epitaxial layer, and greatly improving the long-term working stability of the chip.

[0072] Moreover, this thickness is combined with the passivation layer material (such as SiO2, SiN). x The refractive index of the passivation layer 6 is such that it can form an optical interference layer that meets the requirements, reducing the reflection loss of light at the interface between the transparent conductive layer 4 and the passivation layer 6, as well as between the passivation layer 6 and the air, thereby further improving the light extraction efficiency. At the same time, the passivation layer 6 of this thickness can sufficiently support the hole wall structure of the second via 601, preventing the passivation layer 6 from collapsing after the hole is opened.

[0073] See also Figure 1 and Figure 2 Optionally, the light-emitting diode further includes a current blocking layer 7, which is located between the transparent conductive layer 4 and the epitaxial layer 2, and the orthographic projection of the second electrode 52 on the surface of the second semiconductor layer 22 is located within the orthographic projection of the second semiconductor layer 22 on the surface of the current blocking layer 7.

[0074] In the above design, after the current enters from the second electrode 52, it is blocked by the current blocking layer 7, which forces the current to diffuse laterally in the transparent conductive layer 4, thus optimizing the current distribution and light output.

[0075] For example, the current blocking layer 7 is a SiO2 layer. The SiO2 layer is an excellent insulator with extremely high resistivity. This ensures that it can effectively block the vertical current path directly below the second electrode 52, forcing the current to diffuse laterally.

[0076] In this embodiment, the current blocking layer 7 includes three strip structures. The shape of the second electrode 52 is identical to that of the current blocking layer 7. The first electrode 51 has a U-shaped structure and is located on both sides of one of the strip structures of the second electrode 52. The other two strip structures of the second electrode 52 are located on opposite sides of the first electrode 51.

[0077] For example, both the second electrode and the first electrode are made of a multilayer metal composite structure, with the metal layers stacked in the following order: Cr, Al, Li, Pt, Li, Pt, Au. Each metal layer is deposited using thin film deposition processes such as sputtering and evaporation to form a continuous and tightly bonded electrode film.

[0078] In other embodiments, the second electrode and the first electrode may also adopt other structures, as long as they can achieve the conductivity function, and the embodiments disclosed herein do not impose any restrictions on this.

[0079] Optionally, the transparent conductive layer 4 and the passivation layer 6 are also provided with a plurality of spaced-apart third vias 402, which simultaneously penetrate the transparent conductive layer 4 and the passivation layer 6. The orthographic projection of the third via 402 on the surface of the second semiconductor layer 22 lies within the orthographic projection of the current blocking layer 7 on the surface of the second semiconductor layer 22, or within the orthographic projection of the region in the epitaxial layer 2 used for ohmic contact with the first electrode on the surface of the second semiconductor layer 22. The arrangement of the third vias 402 facilitates the first electrode 51 to achieve ohmic contact with the n-region in the epitaxial layer 2 after passing through the transparent conductive layer 4 and the passivation layer 6. Simultaneously, it also facilitates the second electrode 52 to achieve ohmic contact with the transparent conductive layer 4 after passing through the passivation layer 6.

[0080] Optionally, the light-emitting diode chip also includes a substrate 1, which is a sapphire (Al2O3) substrate. The substrate 1 is connected to the side of the epitaxial layer 2 away from the transparent conductive layer 4.

[0081] In the above implementation, sapphire has a high melting point and strong chemical inertness. Therefore, using sapphire as a substrate can enable it to withstand the high-temperature epitaxy and etching processes in the fabrication of light-emitting diode chips. Moreover, it is not easy for it to have an interface reaction with the epitaxial layer 2 during long-term operation, thus ensuring the reliability of the chip.

[0082] In other examples, substrate 1 may also be a silicon substrate.

[0083] This disclosure also provides a method for manufacturing a light-emitting diode chip, such as... Figure 3 As shown, the manufacturing method includes: S301: The epitaxial layer and the transparent conductive layer are formed sequentially, and the first electrode and the second electrode are fabricated.

[0084] The epitaxial layer includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer.

[0085] The transparent conductive layer is located above the second semiconductor layer and is in direct contact with the second semiconductor layer.

[0086] The first electrode is connected to the first semiconductor layer, and the second electrode is connected to the transparent conductive layer.

[0087] The transparent conductive layer has multiple first vias arranged at intervals, and the orthographic projection of the multiple first vias on one surface of the second semiconductor layer does not overlap with the orthographic projection of the second electrode on the surface of the second semiconductor layer.

[0088] The above-mentioned chips have the same beneficial effects as the aforementioned LED chips, and will not be repeated here.

[0089] This disclosure also provides another method for manufacturing a light-emitting diode chip, such as... Figure 4 As shown, the manufacturing method includes: S401: An epitaxial layer is formed on the substrate.

[0090] The substrate is a sapphire substrate. The epitaxial layer 2 includes a first semiconductor layer 21, a second semiconductor layer 22, and a light-emitting layer 23 located between the first semiconductor layer 21 and the second semiconductor layer 22. The first semiconductor layer 21 is connected to the substrate 1.

[0091] In this embodiment, both the first semiconductor layer 21 and the second semiconductor layer 22 are gallium nitride layers.

[0092] S402: Etch the epitaxial layer to expose the first semiconductor layer.

[0093] The above steps facilitate the subsequent fabrication of the first electrode. Since the epitaxial layers, from bottom to top, consist of a first semiconductor layer 21, a light-emitting layer 23, and a second semiconductor layer 22, with the second semiconductor layer 22 located on the top layer, the second electrode can be directly fabricated on top of it. However, the first semiconductor layer 21 is buried at the bottom. To provide a connection point for the first electrode, etching is necessary to remove the topmost second semiconductor layer 22 and the middle light-emitting layer 23 in a specific area, exposing the lower first semiconductor layer 21. This exposed area is the connection area for the first electrode.

[0094] Figure 5 This is a schematic diagram of the structure after the epitaxial layer is etched to expose the first semiconductor layer. (See attached diagram) Figure 5 The epitaxial layer is etched to expose the first semiconductor layer, which is a U-shaped structure 100, and is also the shape of the subsequent first electrode.

[0095] S403: A SiO2 thin film is deposited on the second semiconductor layer, and photolithography and cleaning are performed to form a current blocking layer.

[0096] Figure 6 See the schematic diagram of the current blocking layer. Figure 6 The deposition of a SiO2 thin film covers the entire surface of the second semiconductor layer, as well as the exposed first semiconductor layer. Then, through photolithography and cleaning, the entire surface-covered SiO2 thin film can be formed into a... Figure 6The diagram shows a current blocking layer comprising three strip-shaped structures. Because the current blocking layer is misaligned with the previously exposed first semiconductor layer, the previously exposed first semiconductor layer will still be exposed, only... Figure 6 Not shown in the image.

[0097] S404: A transparent conductive layer is formed on the surface of the current blocking layer and the epitaxial layer.

[0098] The thickness of the transparent conductive layer is 200-300 Å.

[0099] In this embodiment, an indium tin oxide thin film is deposited over the epitaxial layer and the current blocking layer to form a transparent conductive layer. The transparent conductive layer covers the current blocking layer, the surface of the p-type semiconductor layer of the epitaxial layer, and the previously exposed first semiconductor layer.

[0100] S405: Multiple first through holes are fabricated on the transparent conductive layer.

[0101] Figure 7 See the schematic diagram of the arrangement of the first via on the transparent conductive layer. Figure 7 In this embodiment, several hexagonal first vias with a tilt angle of 60° are etched into the transparent conductive layer using photolithography. Simultaneously, after photolithography of the transparent conductive layer, the previously exposed first semiconductor layer remains exposed through the first vias.

[0102] S406: Create a passivation layer.

[0103] In this embodiment, a SiO2 thin film with a thickness of 2500 Å-2600 Å is deposited on the surface of the epitaxial layer and the surface of its transparent conductive layer to form a passivation layer.

[0104] S407: Multiple second vias are formed on the passivation layer.

[0105] In this process, multiple second vias, corresponding one-to-one with the first vias, are formed on the passivation layer using photolithography. Each second via is also a regular hexagon, and the diameter of the circumscribed circle of the second via is 1-2 μm.

[0106] S408: Multiple third vias are formed simultaneously in the passivation layer and the transparent conductive layer.

[0107] Figure 8 See the schematic diagram for the arrangement of the third through hole. Figure 8 In this embodiment, a portion of the third vias is projected onto the substrate 1 within the projection of the previously exposed U-shaped structure 100 of the first semiconductor layer onto the substrate, and another portion of the third vias 402 is projected onto the substrate 1 within the projection of the current blocking layer 7 onto the substrate.

[0108] The third via facilitates ohmic contact between the subsequently fabricated first electrode and the previously exposed first semiconductor layer. The shape of the first electrode is consistent with the U-shaped structure 100 of the previously exposed first semiconductor layer. The shape of the second electrode is consistent with the shape of the current blocking layer, comprising three strip structures.

[0109] That is, after the first electrode passes through the passivation layer and the transparent conductive layer, it will make ohmic contact with the exposed first semiconductor layer. At the same time, the setting of the third via also facilitates the subsequent formation of the second electrode to make ohmic contact with the transparent conductive layer, that is, after the second electrode passes through the passivation layer, it will make ohmic contact with the transparent conductive layer.

[0110] S409: The first electrode and the second electrode are fabricated in the third through hole respectively.

[0111] Figure 9 See the schematic diagram showing the arrangement of the first and second electrodes. Figure 9 In the third through-hole, a first electrode and a second electrode are formed by vapor deposition, making the first electrode ohmic in contact with the previously exposed first semiconductor layer, and the second electrode ohmic in contact with the transparent conductive layer. Corresponding electrode pads are also formed. At this point, the core structure of the light-emitting diode is complete.

[0112] In this embodiment, the first via can be patterned by wet etching (for example, by using a buffer oxide etching solution, wherein the buffer oxide etching solution is a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F) in a certain proportion). The second via on the passivation layer can also be patterned by the buffer oxide etching method or other etching methods.

[0113] The light-emitting diode chip (new light-emitting diode, i.e., the one prepared by the above method) is used to prepare the light-emitting diode chip. Figure 1 and Figure 2 The illustrated LED chip) and related technologies (old LEDs, i.e. Figure 10 The light-emitting diode chips in the process were tested before packaging, as shown in Table 1. The LEDs were all packaged in the corresponding LED beads. The photoelectric parameters of the LED beads were tested using a remote integrating sphere test system at a test current of 60mA at room temperature, and the results are shown in Table 2.

[0114] The transmittance and total reflectance in Table 1 refer to the unpackaged LED chip. Transmittance was measured using a microspectrophotometer. A light source illuminates the substrate of the LED, and the light distribution on one side of the light-emitting surface is detected. By comparing the intensity of the emitted light spectrum with that of the incident reference light spectrum, the transmittance of the LED within the target wavelength range can be obtained. Total reflectance was measured using a high-precision angle-resolved measurement system. A light source illuminates the LED chip from the side, and a detector in the angle-resolved measurement system collects and scans the light at the light-emitting surface, plotting a three-dimensional light intensity distribution map. The total reflectance loss is then analyzed to obtain the total reflectance value.

[0115] The integrating sphere spectral testing system comprises an integrating sphere, a spectrometer, a constant current source, and a standard probe. The integrating sphere is a hollow sphere with its inner wall coated with a highly diffuse reflective material (such as barium sulfate), which uniformly mixes the stray light emitted by the light-emitting diode (LED) to ensure measurement accuracy. The spectrometer, connected to the integrating sphere, is used to analyze the optical power distribution of the mixed light, i.e., the intensity of the light at various wavelengths. The constant current source provides a 60mA drive current. The standard probe is used to measure luminous flux, optical power, etc.

[0116] Optical power is obtained through a spectrometer. Working distance is the specified distance from the probe to the light-emitting surface of the LED when measuring brightness. Brightness is measured by placing the LED in a specific position and using a brightness probe on an integrating sphere or a luminance meter. Luminous flux is calculated by the spectrometer based on the optical power distribution. Forward voltage is measured by directly measuring the voltage drop across the LED using a voltmeter or data acquisition card while applying a constant current of 60mA to drive the LED; the remote integrating sphere spectral testing system simultaneously acquires this data. The color rendering index (CRI) is calculated by the spectrometer based on the spectral power distribution, calculating the color rendering of the LED illuminated by 15 standard color plates, and taking the average of the first eight. Thermal conductivity refers to the LED's thermal resistance value measured using a specialized transient thermal resistance tester.

[0117] Compared to the new LED, the old LED does not have a first through hole 401 and a second through hole 601.

[0118] Table 1

[0119] Table 2

[0120] It should be noted that the blue light packaging in Table 2 refers to the direct packaging, protection, electrical connection, and optical design of the light-emitting diode chip prepared by the above method, without adding any wavelength conversion materials.

[0121] White light packaging refers to the process of coating or filling one or more layers of phosphor along the optical path of a light-emitting diode (LED) chip prepared by the above method. The blue light emitted by the LED originally excites the phosphor to produce yellow light (or red or green light). The remaining unabsorbed blue light mixes with the light emitted by the phosphor to ultimately form white light with a color temperature controlled at around 6000K.

[0122] Therefore, it can be seen that the light-emitting diode chip provided in this embodiment can significantly improve light transmittance and effectively improve the performance of the device.

[0123] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0124] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode chip, characterized in that, The light-emitting diode chip includes an epitaxial layer (2), a transparent conductive layer (4), a first electrode (51), and a second electrode (52); The epitaxial layer (2) includes a first semiconductor layer (21), a second semiconductor layer (22), and a light-emitting layer (23) located between the first semiconductor layer (21) and the second semiconductor layer (22). The transparent conductive layer (4) is located above the second semiconductor layer (22) and is in direct contact with the second semiconductor layer (22). The first electrode (51) is connected to the first semiconductor layer (21), and the second electrode (52) is connected to the transparent conductive layer (4); The transparent conductive layer (4) has a plurality of spaced first vias (401), and the orthographic projection of the plurality of first vias (401) on one surface of the second semiconductor layer (22) does not overlap with the orthographic projection of the second electrode (52) on the surface of the second semiconductor layer (22).

2. The light-emitting diode chip according to claim 1, characterized in that, Along the normal direction of the surface of the second semiconductor layer (22) and toward the surface, the area of ​​the cross section of the first via (401) increases monotonically, and the cross section of the first via (401) is a plane parallel to the surface of the second semiconductor layer (22).

3. The light-emitting diode chip according to claim 2, characterized in that, The angle between the hole wall of the first through hole (401) and the surface of the second semiconductor layer (22) is 30-70°.

4. The light-emitting diode chip according to claim 2, characterized in that, The cross-section of the first via (401) is projected onto the surface of the second semiconductor layer (22) as a regular polygon.

5. The light-emitting diode chip according to claim 4, characterized in that, The vertices of the regular polygon are all rounded.

6. The light-emitting diode chip according to claim 4, characterized in that, The diameter of the largest circumscribed circle of the first through hole (401) is 2-10 μm.

7. The light-emitting diode chip according to any one of claims 1-6, characterized in that, The plurality of first through holes (401) are evenly arranged, and the arrangement density is 50-200 holes / mm. 2 .

8. The light-emitting diode chip according to any one of claims 1-6, characterized in that, The light-emitting diode chip also includes a passivation layer (6), which is located on the side of the transparent conductive layer (4) away from the second semiconductor layer (22); The passivation layer (6) has a second through hole (601) corresponding to a plurality of first through holes (401) one by one, and each second through hole (601) is connected to the corresponding first through hole (401).

9. The light-emitting diode chip according to claim 8, characterized in that, The orthographic projection of the second via (601) on the surface of the second semiconductor layer (22) lies inside the orthographic projection of the corresponding first via (401) on the surface of the second semiconductor layer (22).

10. A method for manufacturing a light-emitting diode chip, characterized in that, The manufacturing method includes: An epitaxial layer and a transparent conductive layer are formed sequentially, and a first electrode and a second electrode are fabricated. The epitaxial layer includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; The transparent conductive layer is located on top of the second semiconductor layer and is in direct contact with the second semiconductor layer; The first electrode is connected to the first semiconductor layer, and the second electrode is connected to the transparent conductive layer; The transparent conductive layer has a plurality of spaced first vias, and the orthographic projection of the plurality of first vias onto one surface of the second semiconductor layer does not overlap with the orthographic projection of the second electrode onto the surface of the second semiconductor layer.

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