Display panel and electronic device including the same

Abstract

The invention relates to a display panel and an electronic device including the same. The electronic device includes: a pixel defining layer through which a first opening that at least partially overlaps the light emitting region and a second opening that overlaps the contact region are defined; a light emitting element including a first electrode, a second electrode, and a common layer, at least a portion of which is exposed through the first opening; and a boundary barrier overlapping the contact region and disposed on the pixel defining layer. At least a portion of the first electrode overlapping the non-display area is exposed through the second opening, and the second electrode at least partially covers the boundary barrier in the non-display area and is connected to the first electrode exposed through the second opening.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0153651 filed on November 1, 2024 and Korean Patent Application No. 10-2025-0021380 filed on February 19, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to display panels and electronic devices including display panels. More specifically, this disclosure relates to display panels having improved display quality and electronic devices including display panels. Background Technology

[0003] Multimedia electronic devices that generate images, such as smartphones, digital cameras, laptops, navigation units, and smart TVs, include electronic devices for displaying images via a screen.

[0004] The electronic device includes multiple pixels for generating images and multiple lines connected to the pixels. Pixels receive drive signals through the lines to be driven by the drive signals.

[0005] In medium to large electronic devices with large display areas, such as tablet computers or smart TVs, the driving voltage applied to each pixel varies, and therefore, designs that compensate for these differences are required.

[0006] The information disclosed in this Background section was already known to or derived by the inventors before or during the process of implementing the embodiments of this application, or is technical information obtained during the implementation of the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0007] This disclosure provides an electronic device including a display panel capable of applying a constant driving voltage to pixels.

[0008] Embodiments of this disclosure provide an electronic device that may include: a processor configured to provide image data; a display panel connected to the processor; and a driver configured to receive the image data and drive the display panel based on the image data. The display panel may include: a substrate including a display area and a non-display area, the display area including a light-emitting area and a non-display area adjacent to the display area and including a contact area; a pixel defining layer defining a first opening in a third direction perpendicular to a top surface of the substrate and overlapping the light-emitting area, and a second opening at least partially overlapping the contact area, the pixel defining layer being on the substrate; a light-emitting element including a first electrode at least a portion of which is exposed through the first opening, a second electrode on the first electrode, and a common layer between the first and second electrodes; and a boundary barrier on the pixel defining layer, the boundary barrier overlapping the contact area in a third direction, wherein at least a portion of the first electrode overlapping the non-display area is exposed through the second opening, and the second electrode covers the boundary barrier in the non-display area and is connected to the first electrode exposed through the second opening.

[0009] The boundary barrier may include: a first pattern on the pixel-defining layer; a second pattern on the first pattern; a first barrier pattern on the second pattern; and a second barrier pattern on the first barrier pattern.

[0010] The first barrier pattern may include aluminum, and the second barrier pattern may include titanium.

[0011] The first barrier pattern may have a width smaller than that of the second barrier pattern, and the first barrier pattern may have a thickness greater than that of the second barrier pattern.

[0012] The second pattern can have a width greater than that of the second barrier pattern.

[0013] The second pattern can have a width greater than that of the first pattern.

[0014] The electronic device may include: a dummy pattern on the second barrier pattern and at least partially covered by the second electrode, and the dummy pattern may be made of the same material as the common layer.

[0015] The electronic device may include a protective layer disposed between the dummy pattern and the second barrier pattern, and may include inorganic material.

[0016] The second barrier pattern, which protrudes from the first barrier pattern, can define the downwardly protruding tip portion.

[0017] The electronic device may further include: a normal barrier overlapping the non-light-emitting area and disposed on the pixel defining layer, and the normal barrier may be covered by a second electrode.

[0018] Normal barriers can have the same shape as boundary barriers.

[0019] Normal barriers can be provided as a pattern integrated with boundary barriers.

[0020] The second electrode can have a greater thickness than the first pattern.

[0021] The second opening may be arranged in the contact area in the first direction and in the second direction intersecting the first direction, and the boundary barrier may not overlap with the second opening in the contact area.

[0022] The boundary barrier may include: a first portion extending in a first direction and spaced apart from each other in a second direction; and a second portion disposed between adjacent first portions.

[0023] Each of the second parts can have a stepped shape.

[0024] Each of the second parts can extend in the second direction.

[0025] The electronic device may further include: a thin-film encapsulation layer, comprising a first inorganic layer covering the light-emitting element, a second inorganic layer on the first inorganic layer, and an organic layer between the first inorganic layer and the second inorganic layer.

[0026] The display panel may further include a dam portion disposed in the non-display area and surrounding at least a portion of the contact area, and the dam portion includes sequentially stacked organic patterns.

[0027] In the non-display area, the boundary of the organic layer is defined by the dam section.

[0028] Embodiments of this disclosure provide a display panel that may include: a substrate including a display area and a non-display area, the display area including a light-emitting area and a non-display area adjacent to the display area and including a contact area; a pixel defining layer defining a first opening that overlaps with the light-emitting area in a third direction perpendicular to a first direction and a second direction parallel to the top surface of the substrate and a second opening that at least partially overlaps with the contact area, the pixel defining layer being on the substrate; a light-emitting element including a first electrode at least a portion of which is exposed through the first opening, a second electrode on the first electrode, and a common layer between the first electrode and the second electrode; and a boundary barrier on the pixel defining layer, the boundary barrier overlapping the contact area in a third direction, wherein at least a portion of the first electrode overlapping the non-display area is exposed through the second opening, and the second electrode covers the boundary barrier in the non-display area and is connected to the first electrode exposed through the second opening.

[0029] The boundary barrier may include: a first pattern on the pixel-defining layer; a second pattern on the first pattern; a first barrier pattern on the second pattern; and a second barrier pattern on the first barrier pattern.

[0030] The first barrier pattern may include aluminum, and the second barrier pattern may include titanium.

[0031] The first barrier pattern may have a width smaller than that of the second barrier pattern, and the first barrier pattern may have a thickness greater than that of the second barrier pattern.

[0032] The second pattern can have a width greater than that of the second barrier pattern.

[0033] The second pattern can have a width greater than that of the first pattern.

[0034] The display panel may include a dummy pattern disposed on the second barrier pattern and covered by the second electrode, and the dummy pattern may be made of the same material as the common layer.

[0035] The display panel may include a protective layer disposed between the dummy pattern and the second barrier pattern, and may include an inorganic material.

[0036] The second barrier pattern, which protrudes from the first barrier pattern, can define the downwardly protruding tip portion.

[0037] The display panel may include: a normal barrier that overlaps with the non-light-emitting area and is disposed on the pixel-defining layer, and the normal barrier may be covered by a second electrode.

[0038] According to this disclosure, electrodes can be connected to each other in non-display areas via barriers, thereby simplifying the manufacturing process and reducing manufacturing costs. Furthermore, electrodes covered by barriers comprising different metal layers can have reduced resistance, thus improving the reliability of the display panel. Attached Figure Description

[0039] Figure 1A It is a block diagram of an electronic device according to one or more embodiments.

[0040] Figure 1B This is a schematic diagram of an electronic device according to one or more embodiments.

[0041] Figure 1C It is a perspective view of an electronic device according to one or more embodiments.

[0042] Figure 2 It is a cross-sectional view of an electronic device according to one or more embodiments.

[0043] Figure 3It is a cross-sectional view of a display panel according to one or more embodiments.

[0044] Figure 4A It is a block diagram of a display module according to one or more embodiments.

[0045] Figure 4B yes Figure 4A The equivalent circuit diagram of one pixel in the pixel diagram is shown.

[0046] Figure 5A It is a plan view of pixel units according to one or more embodiments.

[0047] Figure 5B It is a plan view of pixel units according to one or more embodiments.

[0048] Figure 6 It is along Figure 5A The cross-sectional view taken from line I-I'.

[0049] Figure 7 It is along Figure 5A The cross-sectional view taken from line II-II'.

[0050] Figure 8 It is a cross-sectional view of a display panel according to one or more embodiments.

[0051] Figure 9A It is a plan view of the contact area of ​​a display panel according to one or more embodiments.

[0052] Figure 9B It is a plan view of the contact area of ​​a display panel according to one or more other embodiments.

[0053] Figure 10 It is along Figure 9A The cross-sectional view taken from line III-III'.

[0054] Figure 11 It is a cross-sectional view of the contact area of ​​a display panel according to one or more embodiments.

[0055] Figure 12 It is a cross-sectional view of the contact area of ​​a display panel according to one or more other embodiments.

[0056] Figure 13 It is a cross-sectional view of the contact area of ​​a display panel according to one or more other embodiments. Detailed Implementation

[0057] In this disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being "on" another element or layer, "connected to" or "linked to" another element or layer, it may be directly on, directly connected to or directly linked to that other element or layer, or there may be an intermediary element or layer.

[0058] The same reference numerals refer to the same elements throughout. In the drawings, the thickness, proportions, and dimensions of parts are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" can include any and all combinations of one or more of the relevant listed items.

[0059] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to also include the plural forms.

[0060] For ease of description, spatial relative terms such as “below,” “under,” “above,” and “above” may be used in this document to describe the relationship between one element or feature and another element or feature as shown in the figure.

[0061] It will be further understood that, when used in this specification, the terms “comprising” and / or “including” indicate the presence of the stated features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0062] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0063] In the following description, non-limiting exemplary embodiments of this disclosure will be described with reference to the accompanying drawings.

[0064] Figure 1A This is a block diagram of an electronic device according to one or more embodiments. Reference Figure 1A The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0065] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), etc., but is not limited thereto.

[0066] The memory 13 can store data information required for the operation of at least one of the processor 12 and the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals to output image information through the display screen.

[0067] The power module 14 may include a power source such as a power adapter or battery device, and a power converter that converts the power supplied by the power source to generate the power required for the operation of the electronic device 10.

[0068] At least one of the components of electronic device 10 may be included in the display device. Some of the components may be included in the display device, while others may be provided separately from the display device. As an example, the display device may include display module 11, while processor 12, memory 13, and power module 14 may be provided as separate devices within electronic device 10 and may not be included in the display device.

[0069] Figure 1B This is a schematic diagram of an electronic device according to one or more embodiments.

[0070] Figure 1B The illustrations apply various electronic devices to the embodiments described herein. These electronic devices may be or may include electronic devices for displaying images, such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions 10_1d, desktop monitors 10_1e, etc.; wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.; or in-vehicle electronic devices 10_3 including display modules, such as central information displays (CID) mounted on dashboards, center consoles, or dashboards, interior mirror displays, etc.

[0071] These electronic devices may further include modules or devices that have more functions than just display functions.

[0072] Figure 1C This is a perspective view of an electronic device according to one or more embodiments. Reference Figure 1B The described electronic device may be applied to or include references. Figure 1C The described electronic device DD. As an example, refer to... Figure 1B The described tablet PC 10_1b can be used with Figure 1C The electronic device DD corresponds to this.

[0073] refer to Figure 1C The electronic device DD may include a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. The corner where the long side of the electronic device DD connects to the short side may have a curved shape. The curved corner of the electronic device DD may be defined as a rounded corner. The shape of the electronic device DD may be defined as a rectangle with rounded corners. However, this is merely an example of an electronic device DD, and the shape of the electronic device DD should not be limited to a rectangle with rounded corners.

[0074] In the following text, a direction perpendicular to or substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 may be referred to as the third direction DR3. For example, the plane defined by the first direction DR1 and the second direction DR2 may be... Figure 3 The top or bottom surface of the substrate SUB shown is parallel. In this disclosure, the expressions "when viewed in a plane" and "in a plan view" refer to the state viewed on a third-party DR3.

[0075] The front surface of the electronic device DD can be defined as the display surface DS, and may include a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the electronic device DD can be provided through the display surface DS.

[0076] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA displays an image IM, and the non-display area NDA does not display an image like the image IM. The non-display area NDA may surround the display area DA and may define an edge of the electronic device DD printed in a selected color.

[0077] Depending on the shape of the electronic device DD, the display area DA can have a rectangular shape with rounded corners. As an example, the display area DA may include multiple sides of a rectangular shape extending in a first direction DR1 and a second direction DR2, and rounded corners connecting the multiple sides. Among the four sides, the side extending in the first direction DR1 can be defined as the long side, and the side extending in the second direction DR2 can be defined as the short side.

[0078] The electronic device DD can sense inputs applied to it from outside. For example, the electronic device DD can sense a first input generated by a stylus PEN and a second input generated by a touch TC. The stylus PEN can be defined as an input device.

[0079] The stylus (PEN) can be an active pen that outputs signals. The second input generated by the touch TC can include, but is not limited to, various types of external inputs such as a part of the user's body, light, heat, or pressure.

[0080] The electronic device DD and the stylus PEN can communicate in both directions. The electronic device DD can provide uplink signals to the stylus PEN. For example, the uplink signals may include panel information and information about the protocol version, but are not limited to this.

[0081] The stylus pen (PEN) can provide downlink signals to the electronic device (DD). The downlink signals may include synchronization signals or information about the state of the stylus pen (PEN). For example, the downlink signals may include, but are not limited to, the coordinates of the stylus pen (PEN), battery information, tilt information, and / or various information stored in the stylus pen (PEN).

[0082] The electronic device DD can be applied to large electronic devices such as televisions, monitors, or outdoor billboards. Additionally, the electronic device DD can be applied to small to medium-sized electronic devices such as personal computers (e.g., laptops or tablets), personal digital assistants, car navigation units, gaming units, smartphones, or cameras. However, these are merely examples, and the electronic device DD can be applied to other electronic devices as long as they do not depart from this disclosure.

[0083] Figure 2 It is a cross-sectional view of an electronic device according to one or more embodiments. Figure 3 It is a cross-sectional view of a display panel according to one or more embodiments.

[0084] Figure 2 When viewed on the second direction DR2 Figure 1C A cross-sectional view of the electronic device DD. Figure 2 References have been omitted. Figure 1C Some components of the described electronic device DD.

[0085] refer to Figure 2 The electronic device DD may include a display panel DP, an input sensor ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2.

[0086] Display panel DP can be a light-emitting display panel. As an example, display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots and quantum rods. In the following description, an organic light-emitting display panel will be used as a representative example of a display panel DP.

[0087] An input sensor ISP can be disposed on the display panel DP. The input sensor ISP may include multiple sensors (not shown) for sensing external input via capacitive methods. The input sensor ISP can be directly fabricated on the display panel DP during the manufacture of the electronic device DD. Therefore, the input sensor ISP can be directly disposed on the display panel DP. However, this disclosure should not be limited thereto or thereby restricted, and according to one or more other embodiments, the input sensor ISP can be attached to the display panel DP via an adhesive layer after being manufactured separately from the display panel DP.

[0088] An anti-reflective layer RPL can be disposed on the input sensor ISP. The anti-reflective layer RPL can be formed directly on the input sensor ISP during the manufacture of the electronic device DD. However, this disclosure should not be limited thereto or thereby restricted, and according to one or more other embodiments, the anti-reflective layer RPL can be attached to the input sensor ISP via an adhesive layer after it has been manufactured as a separate panel.

[0089] An anti-reflective layer (RPL) can be defined as an external light anti-reflective film. The RPL reduces the reflectivity of external light incident on the display panel (DP) from above the electronic device (DD). Because of the RPL, external light is not perceived by the user.

[0090] When external light propagating towards the display panel DP is reflected by the display panel DP and delivered to the user, the user can perceive the external light, much like a mirror. The anti-reflective layer RPL may include multiple color filters (not shown) to prevent the aforementioned phenomenon from displaying the same color as the pixels of the display panel DP.

[0091] A color filter can filter external light to have the same color as the pixel. In this case, the external light may not be perceived by the user. However, this disclosure should not be limited to or restricted by this, and according to one or more other embodiments, the anti-reflective layer RPL may include a retarder and / or a polarizer for reducing the reflectivity of external light.

[0092] The WIN window can be set on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external scratches and impacts.

[0093] A panel protective film (PPF) can be applied beneath the display panel (DP). The PPF protects the lower portion of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0094] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF. The display panel DP and the panel protective film PPF can be connected to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be connected to each other through the second adhesive layer AL2.

[0095] Figure 3 yes Figure 2 The image shows a cross-sectional view of the display panel. As an example, Figure 3 This is a cross-sectional view of the display panel DP when viewed in the second direction DR2.

[0096] refer to Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0097] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include a glass material or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed in the display area DA.

[0098] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element OLED disposed in the display element layer DP-OLED and connected to the transistor (see reference). Figure 4B ).

[0099] A thin-film encapsulation layer (TFE) can be deposited on the DP-CL circuit element layer to cover the DP-OLED display element layer. The TFE can protect the pixels from moisture, oxygen, and foreign matter.

[0100] A thin-film encapsulation layer (TFE) can be disposed on the OLED light-emitting element to at least partially cover the OLED. For example... Figure 6 As shown, the thin-film encapsulation layer TFE may include a layer disposed at pixel PXij (reference). Figure 4B The first inorganic layer LIL on the first inorganic layer LIL, the second inorganic layer UIL disposed on the first inorganic layer LIL, and the organic layer OL disposed between the first inorganic layer LIL and the second inorganic layer UIL.

[0101] The first inorganic layer LIL and the second inorganic layer UIL can include inorganic materials and can protect the pixel from moisture and oxygen. The organic layer OL can include organic materials and can protect the pixel PXij (reference). Figure 4B It is protected from foreign matter such as dust particles. The organic layer OL can be formed by solution processes such as spin coating, slot coating, inkjet printing, etc.

[0102] Figure 4A It is a block diagram of a display module according to one or more embodiments.

[0103] refer to Figure 4A The display module DM may include a display panel DP, a timing controller TC, a scan driver SDV, a data driver DDV, a light-emitting driver EDV, and a voltage generator VG. The display module DM can be... Figure 1A The display module 11 shown in the figure or with Figure 1A Corresponding to the display module 11 shown, and the display panel DP can be Figure 2 and Figure 3 The display panel DP shown in the image or with Figure 2 and Figure 3 The DP is shown in the image.

[0104] The display panel DP may include multiple scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, multiple emission lines EML1 to EMLm, multiple data lines DL1 to DLn, and multiple pixels PX. Each of “m” and “n” is a natural number greater than 0.

[0105] Pixel PX can be electrically connected to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, emission lines EML1 to EMLm and data lines DL1 to DLn. Each pixel PX can be electrically connected to four corresponding scan lines, one corresponding data line and one corresponding emission line.

[0106] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include multiple initialization scan lines GIL1 to GILm, multiple compensation scan lines GCL1 to GCLm, multiple write scan lines GWL1 to GWLm, and multiple bias scan lines GBL1 to GBLm.

[0107] Each pixel PX can be connected to the corresponding initialization scan line among initialization scan lines GIL1 to GILm, the corresponding compensation scan line among compensation scan lines GCL1 to GCLm, the corresponding write scan line among write scan lines GWL1 to GWLm, and the corresponding bias scan line among bias scan lines GBL1 to GBLm.

[0108] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm can be connected to the scan driver SDV, can extend in the first direction DR1, and can be arranged in the second direction DR2. Emit lines EML1 to EMLm can be connected to the light-emitting driver EDV, can extend in the first direction DR1, and can be arranged in the second direction DR2. Data lines DL1 to DLn can be connected to the data driver DDV, can extend in the second direction DR2, and can be arranged in the first direction DR1.

[0109] The scan driver (SDV), the light emission driver (EDV), and the data driver (DDV) can be included in the display panel (DP), and this configuration will be discussed below. Figure 8 As shown in the image.

[0110] The timing controller TC can receive image signals (RGB) and control signals (CTRL). The timing controller TC can convert the RGB data format into a format suitable for the interface between the data driver DDV and the timing controller TC to generate the image data signal DAS. The timing controller TC can generate scan control signals (SCS), data control signals (DCS), and illumination control signals (ECS) in response to the control signal CTRL.

[0111] The voltage generator VG generates the voltages required to operate the display panel DP. The voltage generator VG generates a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. These voltages can be applied to pixels PX.

[0112] The scan driver SDV can receive scan control signals SCS from the timing controller TC. In response to the scan control signals SCS, the scan driver SDV can output scan signals to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals can be applied to pixels PX via scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0113] The data driver DDV receives data control signals (DCS) and image data signals (DAS) from the timing controller TC. The data driver DDV converts the image data signals (DAS) into data signals and can output these data signals. The data signals can be analog voltages corresponding to the gray levels of the image data signals (DAS). The data signals can be applied to pixels (PX) via data lines DL1 to DLn.

[0114] The EDV (Emitting Driver) can receive the ECS (Emitting Control Signal) from the timing controller TC. In response to the ECS, the EDV can output an emission signal to the emission lines EML1 to EMLm. The emission signal can be applied to the pixel PX via the emission lines EML1 to EMLm.

[0115] Pixel PX can receive a data voltage corresponding to a data signal from data driver DDV in response to a scan signal from scan driver SDV. Pixel PX can also emit light with a brightness corresponding to the data voltage in response to a transmit signal to display an image.

[0116] Figure 4B yes Figure 4A The equivalent circuit diagram of one pixel in the pixel diagram is shown.

[0117] As an example, Figure 4B The pixel PXij is shown as connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi. Each of “i” and “j” is a natural number greater than 0.

[0118] refer to Figure 4B A pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The light-emitting element OLED may be driven by the pixel circuit PC.

[0119] The pixel circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST can control the amount of current Id flowing through the light-emitting element OLED. The light-emitting element OLED can emit light with a selected brightness corresponding to the amount of current Id supplied to it.

[0120] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCI. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th transmit line EMLi can receive the i-th transmit signal EMi.

[0121] Pixel PXij can be connected to the j-th data line DLj, the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th emit line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0122] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS. The first power line PL1 can receive the first drive voltage ELVDD, and the second power line PL2 can receive the second drive voltage ELVSS.

[0123] Each of transistors T1 through T8 may include a source electrode, a drain electrode, and a gate electrode. In the following text, in Figure 4B In this context, for illustrative purposes, one of the source electrode and the drain electrode may be referred to as the first electrode, and the other may be referred to as the second electrode. Additionally, the gate electrode may be referred to as the control electrode.

[0124] Transistors T1 to T8 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The first transistor T1, the second transistor T2, and the fifth transistors T5 through T8 may be PMOS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0125] The first transistor T1 can be defined as a driving transistor, and the second transistor T2 can be defined as a switching transistor. The third transistor T3 can be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors. The eighth transistor T8 can be defined as a bias transistor.

[0126] The light-emitting element (OLED) can be defined as an organic light-emitting element. The OLED may include a first electrode AE ​​and a second electrode CE. The first electrode AE, which can be the anode, can receive a first driving voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first driving voltage ELVDD can be applied to the pixel circuit PC via a first power line PL1.

[0127] The second electrode CE, which can be the cathode, can receive a second driving voltage ELVSS that has a lower level than the first driving voltage ELVDD. The second driving voltage ELVSS can be applied to the pixel circuit PC via the second power line PL2.

[0128] The first transistor T1 can be positioned between the fifth transistor T5 and the sixth transistor T6, and can be connected to both the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can be connected to the first power line PL1 via the fifth transistor T5, and can be connected to the first electrode AE ​​via the sixth transistor T6.

[0129] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the first electrode AE ​​via a sixth transistor T6, and a control electrode connected to the first node N1.

[0130] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current Id flowing through the light-emitting element OLED based on the voltage applied to the control electrode of the first transistor T1, the first node N1.

[0131] The second transistor T2 can be disposed between the first transistor T1 and the j-th data line DLj, and can be connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWLi.

[0132] The second transistor T2 can be turned on in response to the i-th write scan signal GWi applied through the i-th write scan line GWLi, so as to electrically connect the j-th data line DLj and the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage VD corresponding to the above-mentioned data signal and provided through the j-th data line DLj to the first electrode of the first transistor T1.

[0133] The third transistor T3 can be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0134] The third transistor T3 can be turned on in response to the i-th compensation scan signal GCI applied to the third transistor T3 through the i-th compensation scan line GCLi, so as to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 can be connected by a diode.

[0135] A fourth transistor T4 may be connected to a first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to a first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 may be turned on in response to an i-th initialization scan signal GIi applied to the fourth transistor T4 via the i-th initialization scan line GILi, so as to provide a first initialization voltage VINT received via the first initialization line VIL1 to the first node N1.

[0136] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th emitter line EMLi.

[0137] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode AE, and a control electrode connected to the i-th emitter line EMLi.

[0138] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the i-th emission signal EMi applied through the i-th emission line EMi. Due to the conduction of the fifth transistor T5 and the sixth transistor T6, the first driving voltage ELVDD can be provided to the light-emitting element OLED, and therefore, the driving current Id can flow through the light-emitting element OLED. Accordingly, the light-emitting element OLED can emit light.

[0139] The seventh transistor T7 may include a first electrode connected to the first electrode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on in response to the i-th bias scan signal GBi applied through the i-th bias scan line GBLi, so as to provide the second initialization voltage VAINT received through the second initialization line VIL2 to the first electrode AE ​​of the light-emitting element OLED.

[0140] The second initialization voltage VAINT may have a different level than the first initialization voltage VINT; however, it should not be limited to or restricted by this. According to one or more other embodiments, the second initialization voltage VAINT may have the same or substantially the same level as the first initialization voltage VINT.

[0141] The seventh transistor T7 can improve the ability of the display pixel PXij to display true black. When the seventh transistor T7 is turned on, the parasitic capacitance (not shown) of the light-emitting element OLED can be discharged. Accordingly, when achieving black brightness, the light-emitting element OLED does not emit light due to leakage current from the first transistor T1, and thus the ability to display true black can be improved.

[0142] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage charged into the capacitor CST.

[0143] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0144] The eighth transistor T8 can be turned on in response to the i-th bias scan signal GBi to apply the bias voltage VBIAS applied through the bias line VBL to the first electrode of the first transistor T1. However, the transistors included in the pixel PXij should not be limited to this or thereby restricted.

[0145] Figure 5A It is a plan view of pixel units according to one or more embodiments. Figure 5B It is a plan view of pixel units according to one or more embodiments.

[0146] refer to Figure 5A A pixel unit (PXU) may include a reference. Figure 4A and Figure 4B Described as multiple pixels. Pixel units PXU can be provided as multiple, and multiple pixel units PXU can be referenced. Figure 1C The described display area DA is arranged in the first oblique direction CDR1 and the second oblique direction CDR2.

[0147] Pixel unit PXU may include a first pixel PX-G1, a second pixel PX-G2, a second pixel PX-R, and a third pixel PX-B. The first pixel PX-G1 can generate green light. The light generated in the first pixel PX-G1 can be provided to the display area DA (see reference) through the first emitting region PXA-G1. Figure 1C The first luminescent region PXA-G1 can have a rhomboid shape.

[0148] The first-second pixel PX-G2 can produce green light just like the first-first pixel PX-G1. The light produced in the first-second pixel PX-G2 can be provided to the display area DA (reference) through the first-second emitting area PXA-G2. Figure 1C The first-second luminescent region PXA-G2 can be spaced apart from the first-first luminescent region PXA-G1 in the first direction DR1. The first-second luminescent region PXA-G2 can have a rhomboid shape.

[0149] The second pixel, PX-R, can generate red light. The light generated in the second pixel, PX-R, can be provided to the display area, DA, through the second emitting area, PXA-R (see reference). Figure 1C The second luminescent region PXA-R can be spaced apart from the third luminescent region PXA-B in the second direction DR2. The second luminescent region PXA-R can be spaced apart from the first-first luminescent region PXA-G1 in the first diagonal direction CDR1, and can be spaced apart from the first-second luminescent region PXA-G2 in the second diagonal direction CDR2. The second luminescent region PXA-R can have a rhomboid shape.

[0150] The third pixel PX-B can produce blue light. The light generated in the third pixel PX-B can be supplied to the display area DA through the third emitting area PXA-B (see reference). Figure 1C The third luminescent region PXA-B may be spaced apart from the first-second luminescent region PXA-G2 along the first oblique direction CDR1, and may be spaced apart from the first-first luminescent region PXA-G1 along the second oblique direction CDR2. The third luminescent region PXA-B may have a rhomboid shape.

[0151] The second luminescent region PXA-R can have a size larger than each of the first-first luminescent regions PXA-G1 and the first-second luminescent regions PXA-G2, and smaller than the size of the third luminescent region PXA-B.

[0152] The region between the luminescent regions PXA-G1, PXA-G2, PXA-R, and PXA-B can be defined as the non-luminescent region NPXA.

[0153] According to the present disclosure, the display panel DP of the electronic device DD (reference) Figure 3 This can include a barrier WL. A portion of the barrier WL (i.e., the normal barrier WA-N) can be set in the display area DA (see reference). Figure 3 The non-light-emitting region NPXA is located within the non-display region NDA. Another portion of the barrier WL (i.e., the boundary barrier WA-C) can be located within the non-display region NDA (see reference). Figure 3 The setting in the non-display area NDA (see reference) will be described later. Figure 3) in the barrier WL.

[0154] The barrier WL disposed in the non-luminous region NPXA may surround at least a portion of the luminous regions PXA-G1, PXA-G2, PXA-R, and PXA-B. That is, the barrier WL disposed in the non-luminous region NPXA may completely surround the luminous regions PXA-G1, PXA-G2, PXA-R, and PXA-B, or may have a partially open shape; however, this disclosure should not be limited thereto or thereby restricted.

[0155] refer to Figure 5B A pixel unit PXU-a may include a reference Figure 4A and Figure 4B The described pixel. Pixel unit PXU-a can be provided in multiple forms, and multiple pixel units PXU-a can be referenced. Figure 1C The described display area DA is arranged in the first direction DR1 and the second direction DR2.

[0156] Pixel unit PXU-a may include a first pixel PX-R, a second pixel PX-B, and a third pixel PX-G. The first pixel PX-R can generate red light. The light generated in the first pixel PX-R can be provided to the display area DA (reference) through the first emitting region PXA-R. Figure 1C The first luminescent region PXA-R can have a rectangular shape with rounded corners.

[0157] The second pixel PX-B can produce blue light. The light produced in the second pixel PX-B can be provided to the display area DA through the second light-emitting area PXA-B (see reference). Figure 1C The second luminescent region PXA-B may be spaced apart from the first luminescent region PXA-R in the first direction DR1. When viewed in the first direction DR1, the second luminescent region PXA-B may at least partially overlap with the first luminescent region PXA-R and the third luminescent region PXA-G. The second luminescent region PXA-B may extend in the second direction DR2 and may have a rectangular shape with rounded corners.

[0158] The third pixel, PX-G, can produce green light. The light generated in the third pixel, PX-G, can be supplied to the display area, DA, through the third emitting region, PXA-G (see reference). Figure 1C The third luminescent region PXA-G can be spaced apart from the first luminescent region PXA-R in the second direction DR2. The third luminescent region PXA-G can have a rectangular shape with rounded corners.

[0159] The first luminescent region PXA-R can have a larger size than the third luminescent region PXA-G, and can have a smaller size than the second luminescent region PXA-B.

[0160] The region between the luminescent regions PXA-R, PXA-G, and PXA-B can be defined as the non-luminescent region NPXA.

[0161] According to the present disclosure, the display panel DP of the electronic device DD (reference) Figure 3 This may include a barrier (WL). A portion of the barrier (WL) may be set in the display area (DA) (see reference). Figure 3 The non-light-emitting area NPXA of the barrier WL can be located in the non-display area NDA (see reference). Figure 3 The setting in the non-display area NDA (see reference) will be described later. Figure 3 ) in the barrier WL.

[0162] Figure 6 It is along Figure 5A The cross-sectional view taken from line I-I'. Figure 7 It is along Figure 5A The cross-sectional view taken from line II-II'.

[0163] Figure 6 It shows Figure 5A The cross-section of the second pixel PX-R. Reference Figure 6 Together Figure 3 , Figure 4A and Figure 4B An OLED light-emitting element may include a first electrode AE, a second electrode CE, and a common layer CL. The common layer CL may include a hole control layer, an electron control layer, and a light-emitting layer.

[0164] The second electrode CE can be disposed on the first electrode AE, and the common layer CL can be disposed between the first electrode AE ​​and the second electrode CE. The light-emitting element OLED can further include a protective layer disposed on the second electrode CE. The protective layer can include an organic material and can prevent components disposed under the protective layer from being damaged in subsequent processes. The protective layer can be omitted.

[0165] The first transistor T1, the fourth transistor T4, and the sixth transistor T6, along with the light-emitting element OLED, can be disposed on the substrate SUB. The display area DA may include pixels PXij (see reference). Figure 4B The corresponding second luminescent region PXA-R and the non-luminescent region NPXA adjacent to the second luminescent region PXA-R.

[0166] The substrate SUB can include a glass material or a flexible plastic material such as polyimide (PI). The circuit element layer DP-CL, the display element layer DP-OLED, and the thin-film encapsulation layer TFE can be disposed on the substrate SUB. The circuit element layer DP-CL can be disposed on the substrate SUB. The circuit element layer DP-CL can include an insulating layer and conductive patterns. The display element layer DP-OLED can include a light-emitting element OLED and a pixel defining layer PDL.

[0167] A barrier layer (BRL) can be disposed on a substrate (SUB). The barrier layer (BRL) can improve the adhesion between the semiconductor pattern included in the transistor and the substrate (SUB). The barrier layer (BRL) can include inorganic materials.

[0168] A metal layer BML can be disposed on a barrier layer BRL. The metal layer BML can at least partially overlap with the first transistor T1 on a third-direction DR3. The metal layer BML can receive a constant voltage. When a constant voltage is applied to the metal layer BML, the threshold voltage (Vth) of the first transistor T1 disposed on the metal layer BML can be maintained without being changed.

[0169] The metal layer BML can block light incident on the first transistor T1 from underneath the metal layer BML. The metal layer BML may include a reflective metallic material. According to one or more other embodiments, the metal layer BML may be omitted.

[0170] The buffer layer BFL can be disposed on the barrier layer BRL and can at least partially cover the metal layer BML. The buffer layer BFL may include inorganic materials.

[0171] The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 may comprise polycrystalline silicon. However, this disclosure should not be limited thereto or thereby restricted, and the semiconductor layers S1, A1, D1, S6, A6, and D6 may comprise amorphous silicon.

[0172] Semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with N-type or P-type dopants. Semiconductor layers S1, A1, D1, S6, A6, and D6 may include highly doped and lightly doped regions. The highly doped regions may have a higher conductivity than the lightly doped regions and may substantially serve as the source and drain electrodes of the first transistor T1 and the sixth transistor T6. The lightly doped regions may substantially correspond to the active regions (or channels) of the first transistor T1 and the sixth transistor T6.

[0173] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 can be formed by semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 can be formed by semiconductor layers S6, A6, and D6. The first channel region A1 can be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 can be disposed between the sixth source region S6 and the sixth drain region D6.

[0174] A first insulating layer INS1 may be disposed on a buffer layer BFL to at least partially cover semiconductor layers S1, A1, D1, S6, A6, and D6. A first gate electrode G1 (or control electrode) of the first transistor T1 and a sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. When viewed in a plane, the first gate electrode G1 may at least partially overlap with the first channel region A1, and the sixth gate electrode G6 may at least partially overlap with the sixth channel region A6.

[0175] The source region, channel region, drain region, and gate electrode of each of the second transistor T2, the fifth transistor T5, and the seventh transistor T7 may have the same or substantially the same structure as the source region, channel region, drain region, and gate electrode of the first transistor T1 and the sixth transistor T6.

[0176] A second insulating layer INS2 may be disposed on the first insulating layer INS1 to at least partially cover the first gate electrode G1 and the sixth gate electrode G6. A dummy electrode DME may be disposed on the second insulating layer INS2. The dummy electrode DME may be disposed on the first gate electrode G1 and, when viewed in a plane, may at least partially overlap with the first gate electrode G1. The dummy electrode DME may form a capacitor together with the first gate electrode G1.

[0177] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to at least partially cover the dummy electrode DME. The semiconductor layers S4, A4, and D4 of the fourth transistor T4 may be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and D4 may include oxide semiconductors comprising metal oxides. The oxide semiconductor may include crystalline or amorphous oxide semiconductors.

[0178] Depending on whether the metal oxide is reduced, semiconductor layers S4, A4, and D4 may include multiple regions distinct from each other. Regions where the metal oxide is reduced (hereinafter referred to as "reduced regions") may have a higher conductivity than regions where the metal oxide is not reduced (hereinafter referred to as "non-reduced regions"). The reduced regions may substantially function as the source and drain electrodes of the fourth transistor T4. The non-reduced regions may substantially correspond to the active region (or channel) of the fourth transistor T4.

[0179] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 can be formed by semiconductor layers S4, A4, and D4. The fourth channel region A4 can be disposed between the fourth source region S4 and the fourth drain region D4.

[0180] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to at least partially cover semiconductor layers S4, A4, and D4. The fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4. When viewed in a plane, the fourth gate electrode G4 may at least partially overlap with the fourth channel region A4.

[0181] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 to at least partially cover the fourth gate electrode G4. The source region, channel region, drain region and gate electrode of the third transistor T3 can have substantially the same structure as the source region, channel region, drain region and gate electrode of the fourth transistor T4.

[0182] The barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise inorganic materials. As an example, the barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise one of silicon oxide and silicon nitride, or an insulating layer may have a multilayer structure with multiple inorganic layers; however, this disclosure should not be particularly limited. The multiple inorganic layers may have a structure in which layers including silicon nitride and layers including silicon oxide are stacked alternately one after another.

[0183] The connecting electrode CNE can be disposed between the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE can electrically connect the sixth transistor T6 and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0184] The first connecting electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 via a first contact hole CE-1 defined through the first insulating layer INS1 to the fifth insulating layer INS5. The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to at least partially cover the first connecting electrode CNE1.

[0185] The second connecting electrode CNE2 can be disposed on the sixth insulating layer INS6. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 via a second contact hole CE-2 defined through the sixth insulating layer INS6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 via a third contact hole CE-3 defined through the seventh insulating layer INS7.

[0186] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to at least partially cover the second connecting electrode CNE2. The sixth insulating layer INS6 and the seventh insulating layer INS7 may comprise organic materials.

[0187] A pixel defining layer (PDL) may be disposed on a seventh insulating layer (INS7). A first opening (PDL-OP1) may be defined through the pixel defining layer (PDL) to expose at least a portion of the first electrode (AE). The pixel defining layer (PDL) may comprise an organic material. Additionally, the pixel defining layer (PDL) may have a selected color; however, this disclosure should not be considered particularly limiting.

[0188] The common layer CL and the second electrode CE included in the light-emitting element OLED can be disposed on the pixel-defining layer PDL.

[0189] The thin-film encapsulation layer TFE can be disposed on the light-emitting element OLED and can at least partially cover the light-emitting element OLED. The thin-film encapsulation layer TFE can be disposed over the entire display area DA. The thin-film encapsulation layer TFE may include multiple inorganic layers and an organic layer disposed between the multiple inorganic layers; however, this disclosure should not be limited thereto or thereby restricted.

[0190] Figure 7 A cross-section of a normal barrier WA-N disposed in the non-luminescent region NPXA is shown. (Reference) Figure 5A The described barrier WL can include normal barriers WA-N and boundary barriers WA-C (see reference). Figure 8 The normal barrier WA-N can be set in the non-emitting area NPXA of the display area DA, and the boundary barrier WA-C (see reference). Figure 8 It can be set in the non-display area NDA (see reference). Figure 8 The contact area CA (reference) Figure 8 )middle.

[0191] refer to Figure 7 The normal barrier WA-N can be set in the non-light-emitting area NPXA of the display area DA. The normal barrier WA-N can include a first pattern IN1, a second pattern IN2, a first barrier pattern W1, and a second barrier pattern W2.

[0192] A first pattern IN1 can be disposed on a pixel-defined layer (PDL). The first pattern IN1 may include an inorganic material. A second pattern IN2 can be disposed on the first pattern IN1. The second pattern IN2 may include an inorganic material different from the inorganic material of the first pattern IN1.

[0193] As an example, the first pattern IN1 may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second pattern IN2 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0194] The first pattern IN1 can be used to disconnect or isolate the P-type hole injection layer included in the common layers CL-G1. Accordingly, the first pattern IN1 can have a thickness greater than the thickness of the P-type hole injection layer included in the common layers CL-G1.

[0195] When viewed in cross-section, the width of the second pattern IN2 can be greater than the width of the first pattern IN1. This difference in width can be caused by the difference in etching rates between the first pattern IN1 and the second pattern IN2 relative to the etching solution.

[0196] The step difference can be formed between the portion of the second pattern IN2 that at least partially overlaps with the first barrier pattern W1 on the third direction DR3 and the portion of the second pattern IN2 that does not overlap with the first barrier pattern W1. Therefore, the portion of the second pattern IN2 that at least partially overlaps with the first barrier pattern W1 can have a greater thickness than the portion of the second pattern IN2 that does not overlap with the first barrier pattern W1.

[0197] The common layers CL-G1 and CL-B, included in different pixels PX-G1 and PX-B, can be disconnected from each other via a first pattern IN1 and a second pattern IN2, and a barrier WL can be disposed between the common layers CL-G1 and CL-B. The disconnected common layers CL-G1 and CL-B can contact the side surfaces of the first pattern IN1 and the second pattern IN2. However, this disclosure should not be limited to or restricted by this, and the disconnected common layers CL-G1 and CL-B can also contact the side surfaces N1-S of the first barrier pattern W1.

[0198] A first barrier pattern W1 may be disposed on a second pattern IN2. The first barrier pattern W1 may include a metallic material. As an example, the first barrier pattern W1 may include aluminum. When the first barrier pattern W1 includes aluminum, the side surfaces N1-S of the first barrier pattern W1 may be oxidized and may lose their conductivity. Accordingly, the side surfaces N1-S of the first barrier pattern W1 may include non-conductive regions N1-O.

[0199] A second barrier pattern W2 may be disposed on the first barrier pattern W1. The second barrier pattern W2 may include a metal different from the metal of the first barrier pattern W1. As an example, the second barrier pattern W2 may include titanium.

[0200] The first barrier pattern W1 may have a greater thickness than the second barrier pattern W2, and the first barrier pattern W1 may have a smaller width than the second barrier pattern W2. A portion of the second barrier pattern W2 may protrude from the first barrier pattern W1 and may be exposed without being covered by the first barrier pattern W1.

[0201] Therefore, the lower surface N2-B of the second barrier pattern W2 can be exposed without being covered by the first barrier pattern W1. This structure can be formed due to the difference in etching rates between the first barrier pattern W1 and the second barrier pattern W2 relative to the etching solution. The first barrier pattern W1 and the second barrier pattern W2 can be defined as having a pointed structure.

[0202] The width of the second pattern IN2 may be greater than or equal to the width of the second barrier pattern W2; however, this disclosure should not be subject to any particular limitation.

[0203] The second electrode CE can be obtained from Figure 6 The second luminescent region PXA-R shown extends into the non-luminescent region NPXA and may at least partially cover (or surround) the normal barrier WA-N. For example, the second electrode CE may completely cover (or surround) the normal barrier WA-N. The second electrode CE, which overlaps with the normal barrier WA-N, may contact the side surface N1-S of the first barrier pattern W1, the exposed lower surface N2-B of the second barrier pattern W2 that is not covered by the first barrier pattern W1, and the side surface N2-S of the second barrier pattern W2.

[0204] The second electrode CE may include indium zinc oxide. The second electrode CE can be formed by a sputtering process.

[0205] As described above, when the side surface N1-S of the first barrier pattern W1 includes a non-conductive region N1-O that is oxidized and loses its conductivity, the portion of the second electrode CE that at least partially covers the normal barrier WA-N can be connected to another portion of the second electrode CE via the exposed lower surface N2-B of the second barrier pattern W2 that is not covered by the first barrier pattern W1 and the internal portion of the first barrier pattern W1. These descriptions also apply to the boundary barrier WA-C.

[0206] The first thickness TH1 of the second electrode CE disposed on the common layers CL-G1 and CL-B can be greater than the second thickness TH2 of the second electrode CE surrounding the normal barrier WA-N. The second thickness TH2 can be approximately 20% to approximately 25% of the first thickness TH1.

[0207] A dummy pattern CL-P can be disposed on the second barrier pattern W2. The dummy pattern CL-P can be at least partially covered by the second electrode CE. For example, the dummy pattern CL-P can be completely covered by the second electrode CE. The dummy pattern CL-P can be formed using the same process as the common layers CL-G1 and CL-B, and can comprise the same material as the common layers CL-G1 and CL-B. The common layers CL-G1 and CL-B can be disconnected from each other on the second barrier pattern W2 through the tip structure of the barrier WL, and the disconnected portion of the common layers CL-G1 and CL-B can be defined as the dummy pattern CL-P.

[0208] Since the second electrode CE and the normal barrier WA-N, which includes different metal layers, are in contact with each other in the display area DA, the resistance of the second electrode CE can be reduced.

[0209] Figure 8 It is a cross-sectional view of a display panel according to one or more embodiments. Figure 8 yes Figures 2 to 3 A cross-sectional view of the portion of the display panel DP that overlaps with the non-display area NDA on the third-direction DR3. Figure 6 Among the components described herein, the component from the barrier layer BRL disposed on the substrate SUB to the fifth insulating layer INS5 is simply illustrated as the insulating layer INS. At least one of the components from the barrier layer BRL to the fifth insulating layer INS5 may be omitted, and they shall not be particularly limited thereto.

[0210] The display panel DP may include a first dam portion DMP-1 and a second dam portion DMP-2 disposed at the outer edge of the non-display area NDA. The first dam portion DMP-1 may be closer to the display area DA than the second dam portion DMP-2 (see reference). Figure 6 Arrangement. The first dam section DMP-1 and the second dam section DMP-2 can be arranged in the non-display area NDA and can surround at least a portion of the contact area CA.

[0211] Each of the first dam section DMP-1 and the second dam section DMP-2 may include a dam pattern in which organic layers are stacked. Each of the dam patterns may be consistent with a reference. Figure 6 The insulating layer described includes layers containing organic materials, which are made of the same material.

[0212] The first dam portion DMP-1 may include a first dam pattern D-1, a second dam pattern D-2, and a third dam pattern D-3 sequentially stacked on the insulating layer INS. The second dam portion DMP-2 may include a first dam pattern D-1, a second dam pattern D-2, a third dam pattern D-3, and a fourth dam pattern D-4 sequentially stacked on the insulating layer INS. The first dam pattern D-1, the second dam pattern D-2, and the third dam pattern D-3 may each contain the same material as the sixth insulating layer INS6, the seventh insulating layer INS7, and the pixel defining layer PDL, respectively. The fourth dam pattern D-4 may contain a material corresponding to a spacer disposed on the pixel defining layer PDL and acting as a support in the deposition process.

[0213] At least one of the first dam section DMP-1 and the second dam section DMP-2 can define the organic layer OL in the non-display region NDA. Figure 6 and Figure 8 (shown in the image) boundary. In processes where the organic layer OL is formed using solution processes such as spin coating, slot coating, or inkjet printing, the height of the first dam portion DMP-1 can prevent solution overflow.

[0214] The non-display area NDA of the display panel DP may include the contact area CA. The contact area CA can be defined as the area in which the second electrode CE, which is commonly arranged in the light-emitting element OLED, contacts the first electrode AE.

[0215] A barrier WL can be disposed in the contact region CA. More specifically, a boundary barrier WA-C can be disposed within the barrier WL. The barrier WL can be disposed on the pixel defining layer PDL. In the contact region CA, a second opening PDL-OP2 can be defined through the pixel defining layer PDL to expose at least a portion of the first electrode AE. That is, a first opening PDL-OP1 (refer to) at least partially overlaps with the first electrode AE ​​included in each light-emitting element OLED on the third-direction DR3. Figure 6 The second opening PDL-OP2, which can be defined through the pixel-defining layer PDL and exposes a portion of the first electrode AE ​​arranged as a single pattern in the non-display area NDA, can be defined through the pixel-defining layer PDL.

[0216] Figure 9A It is a plan view of the contact area of ​​a display panel according to one or more embodiments. Figure 9B It is a plan view of the contact area of ​​a display panel according to one or more other embodiments. Figure 9A and Figure 9B The shapes of the boundary barriers WA-C and WA-Ca as viewed in a plane are shown.

[0217] refer to Figure 9A Together Figure 8 The boundary barrier WA-C may include a first portion WU and a second portion WS. The first portion WU and the second portion WS may be disposed on the pixel-defining layer PDL and may be spaced apart from the second opening PDL-OP2. The first portion WU and the second portion WS essentially form a single pattern, but they are distinguished for ease of illustration.

[0218] Each of the first WU portions can extend along the second direction DR2, and the first WU portions can be spaced apart from each other along the first direction DR1. The second WS portions can be positioned between the first WU portions. Within the first WU portions, the portion closest to the display area DA (see reference) Figure 6 The first part of WU can be connected from the display area DA (reference). Figure 6 ) extended normal barrier WA-N (reference Figure 7 ). Correspondingly, the normal barrier WA-N (reference Figure 7 It can be provided as a pattern integrated with the boundary barrier WA-C.

[0219] Each of the second parts WS can have a stepped shape. The second parts WS can be spaced apart from each other in the second direction DR2 between two first parts WS that are adjacent to each other along the first direction DR1.

[0220] refer to Figure 9B Together Figure 8 The boundary barrier WA-Ca may include a first portion WU and a second portion WH. The first portion WU and the second portion WH may be disposed on the pixel-defining layer PDL and may be spaced apart from the second opening PDL-OP2. The first portion WU and the second portion WH essentially form a single pattern, but they are distinguished for ease of illustration.

[0221] Each of the first parts WU can extend in the second direction DR2, and the first parts WU can be spaced apart from each other in the first direction DR1. The second parts WH can be set between the first parts WU.

[0222] Each of the second parts WH can extend in the first direction DR1, and the second parts WH can be spaced apart from each other in the second direction DR2 between two first parts WU that are adjacent to each other along the first direction DR1.

[0223] Figure 10 It is along Figure 9A The cross-sectional view taken from line III-III'.

[0224] refer to Figure 10The boundary barrier WA-C can be set in the contact region CA and on the pixel-limiting layer PDL. The boundary barrier WA-C can be connected to the reference. Figure 7 The described normal barriers WA-N have the same layer structure. The boundary barrier WA-C may include a first pattern IN1, a second pattern IN2, a first barrier pattern W1, and a second barrier pattern W2.

[0225] A first pattern IN1 can be disposed on a pixel-defined layer (PDL). The first pattern IN1 may include an inorganic material. A second pattern IN2 can be disposed on the first pattern IN1. The second pattern IN2 may include an inorganic material different from the inorganic material of the first pattern IN1.

[0226] As an example, the first pattern IN1 may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second pattern IN2 may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0227] The first pattern IN1 can be used to disconnect the P-type hole injection layer included in the common layers CL-G1. Accordingly, the first pattern IN1 can have a thickness greater than the thickness of the P-type hole injection layer included in the common layers CL-G1.

[0228] When viewed in cross-section, the width of the second pattern IN2 can be greater than the width of the first pattern IN1. This difference in width can be caused by the difference in etching rates between the first pattern IN1 and the second pattern IN2 relative to the etching solution.

[0229] The thickness of the second electrode CE can be greater than the thickness of the first pattern IN1. Accordingly, even if the second electrode CE at least partially covers the boundary barrier WA-C, the second electrode CE may not be disconnected by the first pattern IN1.

[0230] The step difference can be formed between the portion of the second pattern IN2 that overlaps with the first barrier pattern W1 and the portion of the second pattern IN2 that does not overlap with the first barrier pattern W1.

[0231] A first barrier pattern W1 may be disposed on a second pattern IN2. The first barrier pattern W1 may include a metallic material. As an example, the first barrier pattern W1 may include aluminum. When the first barrier pattern W1 includes aluminum, the side surfaces C1-S of the first barrier pattern W1 may be oxidized and may lose their conductivity. Accordingly, the side surfaces C1-S of the first barrier pattern W1 may include non-conductive regions C1-I.

[0232] A second barrier pattern W2 may be disposed on the first barrier pattern W1. The second barrier pattern W2 may include a metal different from the metal of the first barrier pattern W1. As an example, the second barrier pattern W2 may include titanium.

[0233] The first barrier pattern W1 may have a greater thickness than the second barrier pattern W2, and the first barrier pattern W1 may have a smaller width than the second barrier pattern W2. A portion of the second barrier pattern W2 may protrude from the first barrier pattern W1 and may be exposed without being covered by the first barrier pattern W1.

[0234] Therefore, the lower surface of the second barrier pattern W2 can be exposed without being covered by the first barrier pattern W1. This structure can be formed due to the difference in etching rates between the first barrier pattern W1 and the second barrier pattern W2 relative to the etching solution. The first barrier pattern W1 and the second barrier pattern W2 can be defined as having a pointed structure.

[0235] The width of the second pattern IN2 may be greater than or equal to the width of the second barrier pattern W2; however, this disclosure should not be subject to any particular limitation.

[0236] A dummy pattern CL-P can be disposed on the second barrier pattern W2. The dummy pattern CL-P can be at least partially covered by the second electrode CE. For example, the dummy pattern CL-P can be completely covered by the second electrode CE. The dummy pattern CL-P can be combined with common layers CL-G1 and CL-B (see reference). Figure 7 It is formed using the same process and can be combined with common layers CL-G1 and CL-B (see reference). Figure 7 (Includes the same materials.)

[0237] The patterns and barrier patterns included in the normal barrier WA-N can use the same materials as the patterns and barrier patterns included in the boundary barrier WA-C, and can be patterned using the same process as the patterns and barrier patterns included in the boundary barrier WA-C.

[0238] The second electrode CE can be connected to the first electrode AE ​​in the contact area CA of the non-display area NDA. The second electrode CE can be commonly located in the reference area. Figure 6 The light-emitting element described in the OLED can extend from the display area DA to the non-display area NDA.

[0239] The second opening PDL-OP2 can be defined by passing through the pixel-defining layer PDL that at least partially overlaps with the contact area CA on the third-direction DR3 to expose a portion of the first electrode AE. A second electrode CE extending to the non-display area NDA can at least partially cover the pixel-defining layer PDL and can be connected to the first electrode AE. A portion of the second electrode CE can at least partially cover the boundary barrier WA-C disposed on the pixel-defining layer PDL.

[0240] The second electrode CE may include a first portion on a first side of the boundary barrier WA-C and a second portion on a second side of the boundary barrier WA-C opposite to the first side, and the first portion and the second portion may be connected across the boundary barrier WA-C. Since the second electrode CE at least partially covers the boundary barrier WA-C, which includes different metal layers, in the contact region CA, the resistance of the second electrode CE can be reduced.

[0241] The resistance of the second electrode CE can be reduced by the boundary barrier WA-C in the non-display area NDA, and the second electrode CE can contact the first electrode AE. Therefore, it is unnecessary to omit the connection of the second electrode CE and the second electric field line PL2 (see reference) through the normal barrier WA-N in the display area DA. Figure 4B The separate mask process for connecting the components can simplify the manufacturing process of electronic device DDs and reduce their manufacturing cost.

[0242] Figure 11 It is a cross-sectional view of the contact area of ​​a display panel according to one or more embodiments. Figure 12 It is a cross-sectional view of the contact area of ​​a display panel according to one or more other embodiments. Figure 13 This is a cross-sectional view of the contact area of ​​a display panel according to one or more other embodiments. Figures 11 to 13 In the figures, the same / similar reference numerals indicate... Figure 10 The same / similar elements in the text will be omitted, and therefore, detailed descriptions of the same elements will be omitted.

[0243] refer to Figure 11 The display panel DP-1 may include a boundary barrier WA-C1 disposed in the contact area CA of the non-display area NDA. The boundary barrier WA-C1 may be disposed on the pixel limiting layer PDL. The boundary barrier WA-C1 may include a first pattern IN1 disposed on the pixel limiting layer PDL, a second pattern IN2 disposed on the first pattern IN1, a first barrier pattern W1 disposed on the second pattern IN2, and a second barrier pattern W2 disposed on the first barrier pattern W1.

[0244] The second pattern IN2 may have a first width WD1 that is larger than the second width WD2 of the second barrier pattern W2. Accordingly, the side surface I2-S of the second pattern IN2 may protrude outward toward the outer side of the boundary barrier WA-C1 than the side surface C2-S of the second barrier pattern W2. Normal barrier WA-N (reference) Figure 7 It can have the same shape as the boundary barrier WA-C1. Accordingly, when forming common layers CL-G1 and CL-B (refer to...) Figure 7 When this is done, it can be ensured that it is included in the common layers CL-G1 and CL-B (see reference). Figure 7The thickness of the light-emitting layer in the ) can be easily broken, and the layers CL-G1 and CL-B included in the common layers (reference) can be easily disconnected. Figure 7 The P-type hole injection layer in ).

[0245] refer to Figure 12 The display panel DP-2 may include a boundary barrier WA-C2 disposed in the contact area CA of the non-display area NDA. The boundary barrier WA-C2 may be disposed on the pixel limiting layer PDL. The boundary barrier WA-C2 may include a first pattern IN1 disposed on the pixel limiting layer PDL, a second pattern IN2 disposed on the first pattern IN1, a first barrier pattern W1 disposed on the second pattern IN2, and a second barrier pattern W2 disposed on the first barrier pattern W1.

[0246] The boundary barrier WA-C2 may further include a protective layer PL. The protective layer PL may be disposed on the second barrier pattern W2 and may be at least partially covered by the dummy pattern CL-P. The protective layer PL may be disposed on the upper surface of the second barrier pattern W2. The protective layer PL may be disposed on the second barrier pattern W2 and may prevent the second barrier pattern W2 from being damaged in subsequent processes.

[0247] The protective layer PL may comprise an inorganic material. As an example, the protective layer PL may comprise at least one of silicon nitride and silicon oxide.

[0248] With the protective layer PL positioned on the second barrier pattern W2, the boundary barrier WA-C2 can have a robust tip structure. (Reference) Figure 7 The normal barrier WA-N described may further include a protective layer PL in the same manner as the boundary barrier WA-C2.

[0249] refer to Figure 13 The display panel DP-3 may include a boundary barrier WA-C3 disposed in the contact area CA of the non-display area NDA. The boundary barrier WA-C3 may be disposed on the pixel limiting layer PDL. The boundary barrier WA-C3 may include a first pattern IN1 disposed on the pixel limiting layer PDL, a second pattern IN2 disposed on the first pattern IN1, a first barrier pattern W1 disposed on the second pattern IN2, and a second barrier pattern W2 disposed on the first barrier pattern W1.

[0250] The exposed portion of the second barrier pattern W2 that is not covered by the first barrier pattern W1 may include a pointed tip that is bent in the downward direction. (See reference) Figure 7 The described normal barrier WA-N may include the same tip portion as the boundary barrier WA-C3. In the case where the second barrier pattern W2 includes a tip portion, the common layers CL-G1 and CL-B (see reference) Figure 7It can be easily disconnected in the boundary barrier WA-C3.

[0251] Although embodiments of this disclosure have been described, it should be understood that this disclosure is not limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of this disclosure.

[0252] Therefore, the subject matter disclosed herein should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined by the claims.

Claims

1. An electronic device comprising: The processor is configured to provide image data; A display panel is connected to the processor; as well as A driver is configured to receive the image data and drive the display panel based on the image data, the display panel comprising: A substrate includes a display area and a non-display area, wherein the display area includes a light-emitting area and a non-light-emitting area, and the non-display area is adjacent to the display area and includes a contact area; A pixel defining layer, through which a first opening at least partially overlaps with the light-emitting region and a second opening at least partially overlaps with the contact region in a third direction perpendicular to the top surface of the substrate and a second direction parallel to the top surface of the substrate, the pixel defining layer being on the substrate; A light-emitting element includes a first electrode, at least a portion of which is exposed through the first opening; a second electrode on the first electrode; and a common layer between the first electrode and the second electrode; and A boundary barrier, on the pixel-defining layer, at least partially overlaps with the contact region in the third direction. In this configuration, at least a portion of the first electrode, which at least partially overlaps with the non-display area, is exposed through the second opening, and the second electrode at least partially covers the boundary barrier in the non-display area and is connected to the first electrode exposed through the second opening.

2. The electronic device according to claim 1, wherein, The boundary barrier includes: The first pattern is on the pixel-defining layer; The second pattern is on top of the first pattern; A first barrier pattern is on top of the second pattern; and The second barrier pattern is on top of the first barrier pattern.

3. The electronic device according to claim 2, wherein, The first barrier pattern comprises aluminum, and the second barrier pattern comprises titanium.

4. The electronic device according to claim 3, wherein, The first barrier pattern has a width smaller than that of the second barrier pattern, and the first barrier pattern has a thickness greater than that of the second barrier pattern.

5. The electronic device according to claim 2, wherein, The second pattern has a width greater than the width of the second barrier pattern.

6. The electronic device according to claim 2, wherein, The second pattern has a width that is greater than that of the first pattern.

7. The electronic device according to claim 2, further comprising: A dummy pattern, on the second barrier pattern, is at least partially covered by the second electrode, wherein the dummy pattern and the common layer comprise the same material.

8. The electronic device according to claim 7, further comprising: A protective layer is disposed between the dummy pattern and the second barrier pattern, and comprises inorganic material.

9. The electronic device according to claim 2, wherein, The second barrier pattern, which protrudes from the first barrier pattern, defines a downwardly protruding tip portion.

10. The electronic device according to claim 2, further comprising: A normal barrier, on the pixel-defining layer, at least partially overlaps with the non-light-emitting region in the third direction. The normal barrier is at least partially covered by the second electrode.

11. The electronic device according to claim 10, wherein, The normal barrier has the same shape as the boundary barrier.

12. The electronic device according to claim 10, wherein, The normal barrier and the boundary barrier are provided as a pattern integrally.

13. The electronic device according to claim 2, wherein, The second electrode has a thickness greater than that of the first pattern.

14. The electronic device according to claim 1, wherein, The boundary barrier does not overlap with the second opening in the third direction in the contact area.

15. The electronic device according to claim 14, wherein, The boundary barrier includes: The first portion extends in the first direction and is spaced apart from each other in the second direction; and The second part is positioned between the first parts that are adjacent to each other.

16. The electronic device according to claim 15, wherein, Each of the second parts has a stepped shape.

17. The electronic device according to claim 15, wherein, Each of the second parts extends in the second direction.

18. The electronic device according to claim 1, further comprising: The thin-film encapsulation layer includes a first inorganic layer that at least partially covers the light-emitting element, a second inorganic layer on the first inorganic layer, and an organic layer between the first inorganic layer and the second inorganic layer.

19. The electronic device according to claim 18, wherein, The display panel further includes a dam portion in the non-display area, and The dam portion surrounds at least a portion of the contact area and includes sequentially stacked organic patterns.

20. The electronic device according to claim 19, wherein, In the non-display area, the boundary of the organic layer is defined by the dam portion.

21. A display panel, comprising: A substrate includes a display area and a non-display area, wherein the display area includes a light-emitting area and a non-light-emitting area, and the non-display area is adjacent to the display area and includes a contact area; A pixel defining layer, through which a first opening at least partially overlaps with the light-emitting region and a second opening at least partially overlaps with the contact region in a third direction perpendicular to the top surface of the substrate and a second direction parallel to the top surface of the substrate, the pixel defining layer being on the substrate; A light-emitting element includes a first electrode whose at least a portion is exposed through the first opening, a second electrode on the first electrode, and a common layer between the first electrode and the second electrode; as well as A boundary barrier, on the pixel-defining layer, at least partially overlaps with the contact region in the third direction. In this configuration, at least a portion of the first electrode, which at least partially overlaps with the non-display area, is exposed through the second opening, and the second electrode at least partially covers the boundary barrier in the non-display area and is connected to the first electrode exposed through the second opening.

22. The display panel according to claim 21, wherein, The boundary barrier includes: The first pattern is on the pixel-defining layer; The second pattern is on top of the first pattern; A first barrier pattern is on top of the second pattern; and The second barrier pattern is on top of the first barrier pattern.

23. The display panel according to claim 22, wherein, The first barrier pattern comprises aluminum, and the second barrier pattern comprises titanium.

24. The display panel according to claim 23, wherein, The first barrier pattern has a width smaller than that of the second barrier pattern, and the first barrier pattern has a thickness greater than that of the second barrier pattern.

25. The display panel according to claim 22, wherein, The second pattern has a width greater than the width of the second barrier pattern.

26. The display panel according to claim 22, wherein, The second pattern has a width that is greater than that of the first pattern.

27. The display panel according to claim 22, further comprising: A dummy pattern, on the second barrier pattern, is at least partially covered by the second electrode, wherein the dummy pattern and the common layer comprise the same material.

28. The display panel according to claim 27, further comprising: A protective layer is disposed between the dummy pattern and the second barrier pattern, and comprises inorganic material.

29. The display panel according to claim 22, wherein, The second barrier pattern, which protrudes from the first barrier pattern, defines a downwardly protruding tip portion.

30. The display panel according to claim 22, further comprising: A normal barrier, on the pixel-defining layer, at least partially overlaps with the non-light-emitting region in the third direction. The normal barrier is at least partially covered by the second electrode.

Images