Magnetoresistive random access memory and manufacturing method thereof
By optimizing the metal interconnect structure and magnetic tunnel junction design of magnetoresistive memory, the problems of large chip area, high power consumption and insufficient sensitivity in the existing technology have been solved, realizing more efficient and lower cost magnetoresistive memory manufacturing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2024-11-15
- Publication Date
- 2026-05-08
AI Technical Summary
Existing magnetoresistive memory technology suffers from problems such as large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and susceptibility to temperature changes.
The design of the metal interconnects is optimized by first forming the metal interconnect structure and then forming the magnetic tunnel junction on the substrate. This is achieved through precise patterned masking and etching processes, including the material selection and layout of contact holes and trench conductors, which reduces the number of process steps and improves accuracy.
This has enabled magnetoresistive memories with smaller chip area, lower power consumption, and higher sensitivity, reducing sensitivity to temperature changes and improving the efficiency and cost-effectiveness of the manufacturing process.
Smart Images
Figure CN122003098A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a magnetoresistive random access memory (MRAM) device and its fabrication method. Background Technology
[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.
[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention
[0004] One embodiment of the present invention discloses a method for fabricating a magnetoresistive random access memory (MRAM) device. The method primarily involves first providing a substrate comprising an MRAM region and a logic region; then forming a first intermetallic dielectric layer on the substrate; removing the first intermetallic dielectric layer using a first patterned mask to form a first contact hole opening in the MRAM region and a second contact hole opening in the logic region; forming a metal nitride layer within the first and second contact hole openings; removing a portion of the metal nitride layer and a portion of the first intermetallic dielectric layer in the logic region to form a trench opening; forming a metal layer within the first, second, and trench openings to form a first metal interconnect in the MRAM region and a second metal interconnect in the logic region; and finally forming a magnetic tunneling junction (MTJ) on the first metal interconnect.
[0005] Another embodiment of the present invention discloses a magnetoresistive random access memory (MRAM) device, which mainly includes a substrate containing an MRAM region and a logic region, a first intermetallic dielectric layer disposed on the substrate, a first metal interconnect disposed within the first intermetallic dielectric layer of the MRAM region, a second metal interconnect disposed within the first intermetallic dielectric layer of the logic region, and a magnetic tunneling junction (MTJ) disposed on the first metal interconnect. The first metal interconnect includes a first contact hole conductor, and the second metal interconnect includes a second contact hole conductor and a trench conductor disposed on the second contact hole conductor, wherein the second contact hole conductor and the trench conductor are made of different materials. Attached Figure Description
[0006] Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention;
[0007] Figure 10 This is a schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention.
[0008] Symbol Explanation
[0009] 12: Base
[0010] 14: MRAM region
[0011] 16: Logical Area
[0012] 18: Interlayer dielectric layer
[0013] 20: Metal interconnect structure
[0014] 22: Metal interconnect structure
[0015] 24: Intermetallic dielectric layer
[0016] 26: Metal interconnects
[0017] 28: Stop Layer
[0018] 30: Intermetallic dielectric layer
[0019] 32: Metal interconnects
[0020] 34: Barrier Layer
[0021] 36: Metal layer
[0022] 38: MTJ stacked structure
[0023] 42: Lower electrode
[0024] 44: Fixed layer
[0025] 46: Barrier Layer
[0026] 48: Free Layer
[0027] 50: Upper electrode
[0028] 52:MTJ
[0029] 54: Covering layer
[0030] 56: Interstitial wall
[0031] 58: Intermetallic dielectric layer
[0032] 60: Barrier Layer
[0033] 62: Metal layer
[0034] 64: Metal interconnects
[0035] 66: Stop Layer
[0036] 72: Stop Layer
[0037] 74: Stop Layer
[0038] 76: Intermetallic Dielectric Layer
[0039] 78: Hard Mask
[0040] 80: Metal nitride layer
[0041] 82: Covering layer
[0042] 84: Patterned Mask
[0043] 88: Patterned Mask
[0044] 98: Contact hole opening
[0045] 100: Contact hole opening
[0046] 102: Groove opening
[0047] 104: Barrier Layer
[0048] 106: Metal layer
[0049] 108: Metal interconnects
[0050] 110: Contact hole conductor
[0051] 112: Contact hole conductor
[0052] 114: Trench conductor Detailed Implementation
[0053] Please refer to Figures 1 to 9 , Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.
[0054] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.
[0055] Then, a metal interconnect structure 20 is formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetallic dielectric layer 24 and metal interconnects 26 embedded in the intermetallic dielectric layer 24. In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and each metal interconnect 26 can be embedded in the intermetallic dielectric layer 24 and electrically connected to each other according to a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 may further include a barrier layer 34 and a metal layer 36. The barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalttungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or double-damascene fabrication processes are well known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, and the inter-metal dielectric layer 24 preferably contains silicon oxide, such as tetraethyl orthosilicate (TEOS), but is not limited thereto.
[0056] Next, a stop layer 72, another stop layer 74, an intermetallic dielectric layer 76, a hard mask 78, a cover layer 82, and a patterned mask 84 are sequentially formed on the intermetallic dielectric layer 24. The patterned mask 84 has openings (not shown) that expose the surfaces of the cover layer 82 of the MRAM region 14 and the logic region 16, respectively. In this embodiment, the stop layer 72 preferably comprises silicon carbide (SiCN), the stop layer 74 preferably comprises tetraethyl orthosilicate (TEOS), the intermetallic dielectric layer 76 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material such as, but not limited to, silicon carbide oxycarbonide (SiOC) or silicon carbide hydrogen oxycarbonide (SiOCH), the hard mask 78 comprises silicon oxynitride (SiON), the cover layer 82 comprises silicon oxide, and the patterned mask 84 may comprise a patterned photoresist.
[0057] Subsequently, using a patterned mask 84 as a mask, partial masking layer 82, partial hard mask 78, partial intermetallic dielectric layer 76, partial stop layer 74 and partial stop layer 72 of MRAM region 14 and logic region 16 are removed simultaneously by etching to form contact hole openings 98 and 100 to expose the underlying metal interconnects 26.
[0058] Then as Figure 2As shown, the patterned mask 84 is first removed, and then a metal nitride layer 80 is formed on the top surface of the cover layer 82, the sidewalls of the cover layer 82, the sidewalls of the hard mask 78, the sidewalls of the inter-metal dielectric layer 76, the sidewalls of the stop layer 74, and the sidewalls and bottom surface of the stop layer 72 in the MRAM region 14 and the logic region 16. Preferably, the metal nitride layer 80 fills the contact hole openings 98 and 100 but does not completely fill them. In this embodiment, the metal nitride layer 80 preferably comprises titanium nitride (TiN), but is not limited to this.
[0059] Then as Figure 3 As shown, another patterned mask 88 is formed in the MRAM region 14 and the logic region 16. The patterned mask 88 has an opening (not shown) that exposes a portion of the metal nitride layer 80 in the logic region 16, and the width of the opening is preferably larger than the width of the aforementioned contact hole opening 100. Then, using the patterned mask 88 as a mask, the portion of the metal nitride layer 80, the portion of the masking layer 82, the portion of the hard mask 78, and the portion of the intermetallic dielectric layer 76 in the logic region 16 that are not covered by the patterned mask 88 are removed by etching, so that the upper half of the contact hole opening 100 in the logic region 16 expands outward to form a trench opening 102.
[0060] Subsequently, as Figure 4 As shown, the patterned mask 88 is first removed, and then a barrier layer 104 and a metal layer 106 are sequentially formed and filled in the contact hole opening 98 of the MRAM region 14 and the contact hole opening 100 and trench opening 102 of the logic region 16. The barrier layer 104 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 106 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited to these.
[0061] Then as Figure 5 As shown, a planarization process is performed, such as chemical mechanical polishing (CMP) to remove part of the metal layer 106, part of the barrier layer 104, all the masking layers 82, and all the hard masks 78 to form metal interconnects 108 that electrically connect to the underlying metal interconnects 26. Preferably, the metal interconnects 108 of the MRAM region 14 include contact hole conductors 110, while the metal interconnects 108 of the logic region 16 include contact hole conductors 112 and trench conductors 114.
[0062] It is worth noting that the contact hole conductor 112 and the trench conductor 114 formed in the logic region 16 at this stage preferably contain different materials, while the contact hole conductor 112 of the logic region 16 and the contact hole conductor 110 of the MRAM region 14 contain the same material. More specifically, the contact hole conductor 110 of the MRAM region 14 includes a metal nitride layer 80, a barrier layer 104 disposed on the metal nitride layer 80, and a metal layer 106 disposed on the barrier layer 104. The contact hole conductor 112 of the logic region 16 also includes a metal nitride layer 80, a barrier layer 104 disposed on the metal nitride layer 80, and a metal layer 106 disposed on the barrier layer 104, while the trench conductor 114 of the logic region 16 only includes a barrier layer 104 and a metal layer 106 disposed on the barrier layer 104. In other words, the contact hole conductor 112 of logic region 16 contains three material layers, but the trench conductor 114 thereon contains only two material layers. The top surface of the metal nitride layer 80 of logic region 16 is preferably slightly lower than the top surface of the metal nitride layer 80 of MRAM region 14, while the top surfaces of the barrier layer 104 and metal layer 106 of logic region 16 are flush with the top surfaces of the barrier layer 104 and metal layer 106 of MRAM region.
[0063] Then, another metal interconnect structure 22 is formed on the metal interconnect 108 and the inter-metal dielectric layer 76. The metal interconnect structure 22 includes a stop layer 28, an inter-metal dielectric layer 30, and metal interconnect 32 embedded in the stop layer 28 and the inter-metal dielectric layer 30. It should be noted that although the width of the bottom surface and / or top surface of the metal interconnect 32 in this embodiment is slightly larger than the width of the metal interconnect 108 or the contact hole conductor 110 below it, it is not limited thereto. According to other embodiments of the present invention, the bottom surface or top surface of the metal interconnect 32 and the contact hole conductor 110 directly below it may have the same or different widths. These variations are all within the scope of the present invention.
[0064] Similar to the contact hole conductor 110 formed in the MRAM region 14, the metal interconnect 32 located directly above the contact hole conductor 110 in the metal interconnect structure 22 formed in this stage preferably also includes a contact hole conductor (via conductor), and the metal interconnect 32 can be embedded in the intermetallic dielectric layer 30 and / or the stop layer 28 according to a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single damascene or double damascene fabrication processes are well known in the art, they will not be described in detail here. Compared to the metal layer 36 in the metal interconnect 26, which preferably contains copper, and the metal layer 36 in the metal interconnect 32 formed in this stage, which preferably contains tungsten, the intermetallic dielectric layer 30 may contain silicon oxide, such as tetraethyl orthosilicate (TEOS), or an ultra-low dielectric constant dielectric layer, while the stop layer 28 may contain a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited to these.
[0065] like Figure 6 As shown, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are then formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 can be made of an antiferromagnetic (AFM) material, such as iron manganese (FeMn), platinum manganese (PtMn), iridium manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). xThe free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.
[0066] Subsequently, as Figure 7 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form an MTJ 52 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. In addition, when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can also be removed at the same time, so that the metal interconnects 32 form inclined or curved sidewalls near the junction of MTJ 62.
[0067] A masking layer 54 is then formed on the MTJ 52 and covers the surface of the intermetallic dielectric layer 30. In this embodiment, the masking layer 54 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.
[0068] like Figure 8 As shown, an etching process is then performed to remove part of the masking layer 54 to form a gap wall 56 surrounding the MTJ 52 and simultaneously covering and contacting the inclined sidewall of the metal interconnect 32.
[0069] Then as Figure 9As shown, another intermetallic dielectric layer 58 is first formed in the MRAM region 14 and the logic region 16. A planarization process such as CMP is used to align the upper surface of the intermetallic dielectric layer 58 with the upper surface of the upper electrode 50. Then, a pattern transfer or dual damascene fabrication process is performed. For example, a patterned mask can be used to remove part of the intermetallic dielectric layer 58 in the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 108. Then, the contact holes are filled with the required conductive material, such as a barrier layer 60 containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer 62 selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, such as chemical mechanical polishing (CMP) to remove some metal material to form metal interconnects 64 that electrically connect metal interconnects 108 within contact holes. Preferably, the metal interconnects 64, like the metal interconnects 108 below, include a contact hole conductor and a trench conductor. Then, a stop layer 66 is formed on the intermetallic dielectric layer 58 and the metal interconnects 64. The stop layer 66 may comprise silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN), and preferably silicon carbon nitride, but is not limited to these.
[0070] Please refer to again Figure 10 , Figure 10 A schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention is also disclosed. For example... Figure 10 As shown, compared to the previous embodiment where metal interconnects 108 are formed simultaneously in the inter-metal dielectric layer 76 of the MRAM region 14 and the logic region 16, the present invention can first be based on... Figures 1 to 5 The manufacturing process involves forming metal interconnects 108 only within the intermetallic dielectric layer 76 of logic region 14, and then waiting... Figure 5 After forming the intermetallic dielectric layer 30, metal interconnects 32 are formed in the MRAM region, and the metal interconnects 32 simultaneously penetrate the intermetallic dielectric layer 30, the stop layer 28, and the lower intermetallic dielectric layer 76, the stop layer 74, and the stop layer 72, and contact the even lower metal interconnect 26. Then, a comparison is made. Figures 6 to 9 The manufacturing process involves forming an MTJ 52 on the metal interconnect 32, forming an intermetallic dielectric layer 58 around the MTJ 52, and forming a metal interconnect 64 within the intermetallic dielectric layer 58 of the logic region 16.
[0071] In other words, compared to the aforementioned Figure 9In the two intermetallic dielectric layers 30 and 76 directly below the MTJ 52, two contact hole conductors 110 with the same or different widths are respectively provided to connect to the lower metal interconnect 26. In this embodiment, only a metal interconnect 32 composed of a single contact hole conductor 110 is provided directly below the MTJ 52, which simultaneously penetrates the two intermetallic dielectric layers 30 and 76 to connect the lower metal interconnect 26 and the MTJ 52. The bottom surface of the metal interconnect 32 preferably overlaps with the bottom surface of the metal interconnect 108 of the logic region 16, while the top surface of the metal interconnect 32 is higher than the bottom surface of the metal interconnect 64 of the logic region 16, but can be selected to be higher, flush with, or lower than the junction of the contact hole conductor and the trench conductor in the metal interconnect 64. As in the aforementioned embodiments, the metal interconnect 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 36 directly below the MTJ 52 preferably includes tungsten.
[0072] In summary, the present invention mainly adds an additional layer of metal interconnect 108 between the metal interconnect 32 directly below the MTJ 52 and the next-lower layer metal interconnect 26 in the MRAM region 14 and the logic region 16. Preferably, the metal interconnect 108 in the MRAM region located between the metal interconnect 26 and the metal interconnect 32 directly below the MTJ 52 is a contact hole conductor 110, while the metal interconnect 108 in the logic region on the same layer is a combination of a contact hole conductor 112 and a trench conductor 114. Furthermore, according to the present invention... Figure 10 In another embodiment, the present invention may select to form a single metal interconnect 32 composed of contact hole conductor 110 directly below MTJ 52, simultaneously penetrating two inter-metal dielectric layers 30 and 76 to connect the lower metal interconnect 26 to MTJ 52. According to a preferred embodiment of the present invention, the above design can improve the problem that after semiconductors transition from 22-nanometer manufacturing processes to 14-nanometer manufacturing processes, the increased loading of the inter-metal dielectric layer due to the IBE manufacturing process leads to an excessive height difference between the MRAM region and the logic region, requiring a reduction in the MTJ height.
[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A method for fabricating a magnetoresistive random access memory (MRAM) element, characterized in that, Include: The substrate includes an MRAM region and a logic region; A first intermetallic dielectric layer is formed on the substrate; The first intermetallic dielectric layer is removed using a first patterned mask to form a first contact hole opening in the MRAM region and a second contact hole opening in the logic region; A metal nitride layer is formed in the first contact hole opening and the second contact hole opening; Remove a portion of the metal nitride layer and a portion of the first intermetallic dielectric layer in the logic region to form a trench opening; A metal layer is formed in the first contact hole opening, the second contact hole opening, and the trench opening to form a first metal interconnect in the MRAM region and a second metal interconnect in the logic region; as well as A magnetic tunneling junction (MTJ) is formed on the first metal interconnect.
2. The method of claim 1, further comprising: A hard mask is formed on the first intermetallic dielectric layer; The hard mask and the first intermetallic dielectric layer are removed using the first patterned mask to form the first contact hole opening in the MRAM region and the second contact hole opening in the logic region; The metal nitride layer is formed in the first contact hole opening and the second contact hole opening; A portion of the metal nitride layer and a portion of the first intermetallic dielectric layer in the logic region are removed using a second patterned mask to form the trench opening; The metal layer is formed in the first contact hole opening, the second contact hole opening, and the trench opening; as well as The metal layer is planarized to form the first metal interconnect in the MRAM region and the second metal interconnect in the logic region.
3. The method of claim 2, wherein the first metal interconnect includes a first contact hole conductor.
4. The method of claim 3, wherein the first contact hole conductor comprises: The metal nitride layer; A barrier layer is disposed on the metal nitride layer; and The metal layer is disposed on the barrier layer.
5. The method of claim 2, wherein the second metal interconnect comprises: Second contact hole conductor; and A groove conductor is provided on the second contact hole conductor.
6. The method of claim 5, wherein the second contact hole conductor comprises: The metal nitride layer; A barrier layer is disposed on the metal nitride layer; and The metal layer is disposed on the barrier layer.
7. The method of claim 5, wherein the trench conductor comprises: Barrier layer; and The metal layer is disposed on the barrier layer.
8. The method of claim 1, further comprising: A second intermetallic dielectric layer is formed on the first intermetallic dielectric layer; A third metal interconnect is formed on the first metal interconnect; and The magnetic tunnel junction is formed on the third metal interconnect.
9. The method of claim 8, wherein the third metal interconnect includes a contact hole conductor.
10. The method of claim 1, wherein the metal nitride layer comprises titanium nitride.
11. A magnetoresistive random access memory (MRAM) device, characterized in that, Include: The substrate includes the MRAM region and the logic region; A first intermetallic dielectric layer is disposed on the substrate; A first metal interconnect is disposed within the first inter-metal dielectric layer of the MRAM region, wherein the first metal interconnect includes a first contact hole conductor. A second metal interconnect is disposed within the first inter-metal dielectric layer of the logic region, wherein the second metal interconnect includes: Second contact hole conductor; A trench conductor is disposed on the second contact hole conductor, wherein the second contact hole conductor and the trench conductor comprise different materials; and A magnetic tunneling junction (MTJ) is located on the first metal interconnect.
12. The MRAM element of claim 11, further comprising: A second intermetallic dielectric layer is disposed on the first intermetallic dielectric layer; A third metal interconnect is disposed on the first metal interconnect; and The magnetic tunneling junction is located on the third metal interconnect.
13. The MRAM element of claim 12, wherein the third metal interconnect includes a third contact hole conductor.
14. The MRAM element of claim 12, further comprising: A third intermetallic dielectric layer is disposed on the second intermetallic dielectric layer and surrounds the MTJ; and The fourth metal interconnect is disposed on the second metal interconnect.
15. The MRAM element of claim 14, wherein the fourth metal interconnect comprises: Fourth contact hole conductor; and The second trench conductor is disposed on the fourth contact hole conductor.
16. The MRAM element of claim 11, wherein the second contact hole conductor comprises: Metal nitride layer; A barrier layer is disposed on the metal nitride layer; and A metal layer is disposed on the barrier layer.
17. The MRAM element of claim 11, wherein the trench conductor comprises: Barrier layer; and A metal layer is disposed on the barrier layer.