Semiconductor chip and preparation method thereof

Abstract

The invention provides a semiconductor chip and a preparation method thereof, and belongs to the field of semiconductor devices. The semiconductor chip comprises an epitaxial layer, a passivation layer and a cutting channel reflective layer, the epitaxial layer is provided with an isolation groove; the passivation layer covers one side of the epitaxial layer and fills the isolation groove; the cutting channel reflective layer covers one side of the passivation layer and corresponds to the position of the isolation groove. According to the invention, the detection efficiency and accuracy of semiconductor chip cracking can be effectively improved.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductor devices, and in particular relates to a semiconductor chip and its fabrication method. Background Technology

[0002] Semiconductor chips are a common type of functional electronic device that is widely used in various sub-sectors.

[0003] In related technologies, in order to better display the cutting path and facilitate the dicing operation in subsequent processes, the residual photoresist outside the isolation trench is removed.

[0004] However, this design means that areas where the dicing was unsuccessful can only be inspected manually, which not only wastes manpower but is also inefficient and inaccurate. Summary of the Invention

[0005] This disclosure provides a semiconductor chip and its fabrication method, which can effectively improve the efficiency and accuracy of semiconductor chip cleavage detection. The technical solution is as follows: In a first aspect, embodiments of this disclosure provide a semiconductor chip, the semiconductor chip comprising: an epitaxial layer, a passivation layer, and a dicing reflective layer; The epitaxial layer has isolation trenches; The passivation layer covers one side of the epitaxial layer and fills the isolation trench; The reflective layer of the cutting track covers one side of the passivation layer and corresponds to the position of the isolation trench.

[0006] In one implementation of this disclosure, the isolation trench has marker points; The reflective layer of the cut track has holes that are opposite to the marker point to expose the marker point.

[0007] In one implementation of this disclosure, the marker point is located at the intersection between the two isolation trenches.

[0008] In one implementation of this disclosure, the thickness of the reflective layer of the cutting track is 1~10µm.

[0009] In one implementation of this disclosure, the orthographic projection of the cutting reflective layer onto the plane of the epitaxial layer is located within the isolation trench.

[0010] Secondly, embodiments of this disclosure provide a method for fabricating a semiconductor chip, the method comprising: An epitaxial layer is prepared, and isolation trenches are etched on the epitaxial layer; A passivation layer is prepared on one side of the epitaxial layer, and the passivation layer fills the isolation trench; A cutting track reflective layer is prepared on one side of the passivation layer, and the cutting track reflective layer is located at the position corresponding to the isolation trench; The dicing operation is performed along the reflective layer of the cutting track; Automated optical inspection is performed to determine whether there are crack marks at the reflective layer of the cutting track. If there are crack marks at the reflective layer of the cutting track, the cracking operation at the corresponding position is successful. If there are no crack marks at the reflective layer of the cutting track, the cracking operation at the corresponding position fails.

[0011] In one implementation of this disclosure, an epitaxial layer is prepared, and isolation trenches are etched on the epitaxial layer, including: During the etching of the isolation trenches, marker points are formed at the intersection of the two isolation trenches.

[0012] In one implementation of this disclosure, a slit reflective layer is prepared on one side of the passivation layer, comprising: A black adhesive is applied to one side of the passivation layer; The black adhesive is photolithographically processed to obtain the reflective layer of the cutting path. The reflective layer of the cutting path has holes that are opposite to the marker points to expose the marker points.

[0013] In one implementation of this disclosure, after preparing a kerf reflective layer on one side of the passivation layer, the preparation method includes: The reflective layer of the cutting track is etched to reduce its thickness to 1~10µm; The reflective layer of the cut track is soaked in an organic solution.

[0014] In one implementation of this disclosure, automated optical inspection is performed, including: Grayscale images of the light-emitting surface and the electrode surface of the semiconductor chip were captured separately. Check whether there are crack marks on the grayscale images of the light-emitting surface and the electrode surface at the positions corresponding to the reflective layer of the cutting path; If both the grayscale image of the luminescent surface and the grayscale image of the electrode surface show cracking marks, the cracking operation at the corresponding position is successful. If neither the grayscale image of the luminescent surface nor the grayscale image of the electrode surface shows cracking marks, the cracking operation at the corresponding position fails.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: In the semiconductor chip provided in this embodiment, the epitaxial layer has isolation trenches, and a passivation layer covers one side of the epitaxial layer and fills the isolation trenches, thereby providing a stable foundation for the dicing reflective layer. A dicing reflective layer is disposed on one side of the passivation layer, corresponding to the position of the isolation trenches. In this way, during the dicing process, the isolation trenches can be accurately diced using the dicing reflective layer as a reference. Furthermore, after the dicing process is completed, the semiconductor chip undergoes automated optical inspection. Since the dicing reflective layer can reflect the light source of the automated optical inspection, while the dicing gaps in the dicing reflective layer cannot reflect light, the grayscale images captured by the camera during automated optical inspection show a significant difference in grayscale levels between the dicing reflective layer and the dicing gaps, clearly revealing the dicing marks in the dicing reflective layer. Based on this, the success or failure of the dicing process can be determined efficiently and accurately.

[0016] In other words, by setting a reflective layer on the cutting path, the reference for the dicing operation can be accurately marked, and the success of the dicing operation can be determined by automated optical inspection after the dicing operation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a semiconductor chip provided in an embodiment of this disclosure; Figure 2 This is a top view of the semiconductor chip provided in an embodiment of this disclosure; Figure 3 This is a flowchart of a method for fabricating a semiconductor chip according to an embodiment of this disclosure; Figure 4 This is a flowchart of another method for fabricating a semiconductor chip provided in this embodiment.

[0019] The symbols in the diagram represent the following meanings: 10. Epitaxial layer; 20. Passivation layer; 30. Reflective layer for cutting track; 310. Holes; 40. Isolation trench; 50. Landmark point. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] MIP (MicroLED In Package) is an advanced packaging process used in the fabrication of micro LED chips.

[0022] In this process, in order to better display the cutting path and facilitate the dicing operation in subsequent processes, the residual photoresist outside the isolation trench will be removed.

[0023] However, this design means that areas where cleaving failed can only be inspected manually. During manual inspection, the inspector needs to hold up the carrier film with their hand and, using a light source at a specific angle, visually observe for differences in reflective brightness. This is not only wasteful of manpower but also inefficient and inaccurate.

[0024] To address the aforementioned technical problems, this disclosure provides a semiconductor chip. Figure 1 This is a schematic diagram of the semiconductor chip structure. (See attached diagram) Figure 1 In this embodiment, the semiconductor chip includes an epitaxial layer 10, a passivation layer 20, and a dicing reflective layer 30.

[0025] Figure 2 This is a top view of the semiconductor chip, combined with... Figure 2 The epitaxial layer 10 has an isolation trench 40, the passivation layer 20 covers one side of the epitaxial layer 10 and fills the isolation trench 40, and the dicing reflective layer 30 covers one side of the passivation layer 20 and corresponds to the position of the isolation trench 40.

[0026] In the semiconductor chip provided in this embodiment, the epitaxial layer 10 has an isolation trench 40, and the passivation layer 20 covers one side of the epitaxial layer 10 and fills the isolation trench 40, thereby providing a stable foundation for the dicing reflective layer 30. The dicing reflective layer 30 is disposed on one side of the passivation layer 20, corresponding to the position of the isolation trench 40. Thus, during the dicing process, the isolation trench 40 can be accurately diced using the dicing reflective layer 30 as a reference. Furthermore, after the dicing process is completed, the semiconductor chip undergoes automated optical inspection. Since the dicing reflective layer 30 can reflect the light source of the automated optical inspection, while the dicing gaps in the dicing reflective layer 30 cannot reflect light, the grayscale image captured by the camera during the automated optical inspection shows a significant difference in grayscale levels between the dicing reflective layer 30 and the dicing gaps, clearly revealing the dicing marks in the dicing reflective layer 30. Based on this, the success or failure of the dicing process can be determined efficiently and accurately.

[0027] In other words, by setting the reflective layer 30 of the cutting path, on the one hand, the benchmark of the dicing operation can be accurately marked, and on the other hand, it is convenient to determine whether the dicing operation was successful by using automated optical inspection after the dicing operation.

[0028] See also Figure 2 In this embodiment, the isolation trench 40 has a marker point 50, and the cutting reflective layer 30 has a hole 310, which is opposite to the marker point 50 to expose the marker point 50.

[0029] In the above implementation, the marker point 50 is set in the isolation trench 40 to provide an identification basis for equipment such as the dicing machine and the dicing machine in the dicing operation. Since the reflective layer 30 of the cutting track has a hole 310 and the hole 310 is opposite to the marker point 50, the hole 310 can expose the marker point 50, thus avoiding the reflective layer 30 of the cutting track from obstructing the marker point 50.

[0030] This design effectively improves the reliability of the fracturing operation.

[0031] For example, the marker 50 is located at the intersection between the two isolation trenches 40.

[0032] In the above implementation, the marker point 50 is set at the intersection between the two isolation trenches 40, so that the marker point 50 can play a positioning role for both isolation trenches 40, which effectively simplifies the arrangement of the marker point 50 and improves efficiency.

[0033] In this embodiment, the isolation trenches 40 are crisscrossed, that is, they include multiple parallel transversely extending isolation trenches 40 and multiple parallel longitudinally extending isolation trenches 40. The transversely extending isolation trenches 40 and the longitudinally extending isolation trenches 40 intersect perpendicularly, and the intersection of two isolation trenches 40 is cross-shaped, with a marker point 50 set at this position.

[0034] For example, marker 50 has a cross-shaped structure.

[0035] The marker 50 is designed as a cross-shaped structure, which can better fit the intersection between the two isolation trenches 40, thus making it easier to locate the marker 50.

[0036] As mentioned above, the reflective layer 30 of the cutting path can highlight the grayscale levels between itself and the gap between the fragments. The reflective layer 30 of the cutting path will be explained below.

[0037] In this embodiment, the thickness of the reflective layer 30 of the cutting path is 1~10µm.

[0038] In the above implementation, the thickness of the reflective layer 30 of the cutting track is designed to the above value. On the one hand, this ensures the functionality of the reflective layer 30 of the cutting track, that is, to highlight the gray level. On the other hand, it avoids the thickness being too large and affecting other film layers.

[0039] In this embodiment, the orthographic projection of the reflective layer 30 on the plane where the epitaxial layer 10 is located is within the isolation trench 40.

[0040] This design ensures complete alignment between the dicing reflective layer 30 and the isolation trench 40 in the direction perpendicular to the epitaxial layer 10. This effectively improves the reliability of the dicing reflective layer 30 as a dicing reference. Furthermore, this design also prevents the dicing reflective layer 30 from affecting the other film layers.

[0041] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor chip according to an embodiment of the present disclosure, in conjunction with... Figure 3 In this embodiment, the preparation method includes: Step 301: Prepare epitaxial layer 10 and etch isolation trenches 40 on epitaxial layer 10.

[0042] Step 302: A passivation layer 20 is prepared on one side of the epitaxial layer 10, and the passivation layer 20 fills the isolation trench 40.

[0043] Step 303: Prepare a slit reflective layer 30 on one side of the passivation layer 20. The slit reflective layer 30 is located at the position of the corresponding isolation trench 40.

[0044] Step 304: Perform the dicing operation along the reflective layer 30 of the cutting path.

[0045] Step 305: Perform automated optical inspection to determine whether there are crack marks at the reflective layer 30 of the cut path.

[0046] If there are crack marks at point 30 of the reflective layer of the cutting track, the cracking operation at the corresponding position is successful; if there are no crack marks at point 30 of the reflective layer of the cutting track, the cracking operation at the corresponding position fails.

[0047] During the dicing process, the reflective layer 30 of the dicing track serves as a reference, enabling accurate dicing of the isolation trench 40. Furthermore, after dicing, automated optical inspection of the semiconductor chip is performed. Because the reflective layer 30 of the dicing track reflects the light source used in the automated optical inspection, while the dicing gaps within the reflective layer 30 do not, the grayscale images captured by the camera during automated optical inspection show a significant difference in grayscale levels between the reflective layer 30 of the dicing track and the dicing gaps. This clearly reveals the dicing marks within the reflective layer 30 of the dicing track. Based on this, the success or failure of the dicing process can be determined efficiently and accurately.

[0048] In other words, by setting the reflective layer 30 of the cutting path, on the one hand, the benchmark of the dicing operation can be accurately marked, and on the other hand, it is convenient to determine whether the dicing operation was successful by using automated optical inspection after the dicing operation.

[0049] Figure 4 A flowchart illustrating another method for fabricating a semiconductor chip according to an embodiment of this disclosure, in conjunction with... Figure 4 In this embodiment, the preparation method includes: Step 401: Prepare epitaxial layer 10 and etch isolation trenches 40 on epitaxial layer 10.

[0050] For example, step 401 includes the following steps: Step 4011: Provide a substrate, and sequentially grow a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer on the substrate.

[0051] The epitaxial layer 10 consists of a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer.

[0052] For example, the substrate is a patterned sapphire substrate.

[0053] Step 4012: Etch epitaxial layer 10 to form isolation trench 40.

[0054] The etching process begins with etching down from the P-type semiconductor layer until the N-type semiconductor layer is reached, forming the active and isolation regions of the chip, thus preparing for subsequent processes.

[0055] Step 4013: Fabricate ohmic contact electrodes on the N-type semiconductor layer and the P-type semiconductor layer respectively.

[0056] For example, the ohmic contact layer must, on the one hand, ensure good contact with the N-type semiconductor layer and the P-type semiconductor layer to reduce contact resistance. On the other hand, it must have high reflectivity so that as much light incident on the surface of the ohmic contact electrode as possible can be reflected back to one side of the substrate to ensure good light extraction efficiency.

[0057] In this embodiment, the ohmic contact electrode is Ag or an Ag alloy.

[0058] Step 402: Marker point 50 is formed at the intersection of the two isolation trenches 40.

[0059] In the above implementation method, the marker point 50 can play a positioning role in subsequent processes.

[0060] In some examples, since the isolation trench 40 is generated by etching, its appearance is significantly different from that of the unetched area. Therefore, the intersection of the two isolation trenches 40 can naturally form a marker point 50 for subsequent scratch identification without the need for additional processing.

[0061] In other examples, while etching the isolation trench 40, a marker point 50 protruding from the bottom surface of the isolation trench 40 (i.e., less etching at the marker point 50) or a marker point 50 recessed into the bottom surface of the isolation trench 40 (i.e., more etching at the marker point 50) is formed at the bottom of the isolation trench 40 for subsequent scratch identification. This disclosure does not limit this.

[0062] Step 403: A passivation layer 20 is prepared on one side of the epitaxial layer 10, and the passivation layer 20 fills the isolation trench 40.

[0063] The passivation layer 20 can protect the chip surface from the influence of the external environment and can also isolate the electrodes and prevent short circuits.

[0064] Step 404: Prepare a slit reflective layer 30 on one side of the passivation layer 20. The slit reflective layer 30 is located at the position of the corresponding isolation trench 40.

[0065] In this embodiment, step 404 includes the following steps: First, black glue is applied to one side of the passivation layer 20.

[0066] In some examples, black vinyl is mainly composed of resin, photoacid generator (PAG), solvent, and additives.

[0067] In other examples, the black adhesive is primarily composed of silicone and epoxy resin. This disclosure does not limit this.

[0068] Then, photolithography is performed on the black resin to obtain a reflective layer 30 for the cutting path. The reflective layer 30 for the cutting path has holes 310, which are opposite to the marker point 50 to expose the marker point 50.

[0069] Step 405: Etch the reflective layer 30 of the cutting path to reduce the thickness of the reflective layer 30 of the cutting path to 1~10µm.

[0070] Step 406: Soak the reflective layer 30 of the cutting track in an organic solution.

[0071] In the above implementation, the photoresist in the corresponding area of ​​the black glue can be removed by soaking in an organic solution, so that the reflective layer 30 of the dicing channel can be exposed.

[0072] Step 407: Perform the dicing operation along the reflective layer 30 of the cutting path.

[0073] In this embodiment, step 407 includes the following steps: First, using marker point 50 as a reference, the wafer is laser-cut invisibly.

[0074] For example, a dicing machine is used to perform laser stealth dicing on the wafer. By controlling the depth and energy of the laser incident, the front-end photolithography marker 50 is identified, the dicing path is located and the horizontal correction is performed to ensure that all wafers can be diced to the required size.

[0075] Then, using marker point 50 as a reference, the wafer is split.

[0076] For example, a dicing machine is used to cleave a laser-cut wafer by cleaving along the cleaving mark 50 with a cleaving blade.

[0077] Step 408: Perform automated optical inspection to determine whether there are crack marks at the reflective layer 30 of the cut path.

[0078] In this embodiment, step 408 includes the following steps: Step 4081: Take grayscale images of the light-emitting surface and the electrode surface of the semiconductor chip respectively.

[0079] It is worth noting that the light-emitting surface refers to one side of the chip substrate, while the electrode surface refers to the one side of the chip electrode.

[0080] Step 4082: Check whether there are crack marks at the position of the reflective layer 30 corresponding to the cut path on the grayscale map of the light-emitting surface and the grayscale map of the electrode surface.

[0081] Due to the presence of the reflective layer 30 in the cutting path, the grayscale levels between the reflective layer 30 and the cleavage gap differ significantly, ranging from 30 to 100. Therefore, the presence or absence of a cleavage gap can be clearly observed.

[0082] If there are crack marks on both the grayscale images of the luminescent surface and the electrode surface, the cracking operation at the corresponding position is successful. If there are no crack marks on either the grayscale image of the luminescent surface or the grayscale image of the electrode surface, the cracking operation at the corresponding position fails.

[0083] In other words, the dicing process is successful only if dicing marks are present on both the grayscale images of the luminescent and electrode surfaces. If no dicing marks are present on either the luminescent or electrode grayscale images, the dicing process is considered a failure.

[0084] For example, if the grayscale image of the emitting side shows cracking marks, but the grayscale image of the electrode side does not, it means that one side of the chip substrate was successfully cracked, but the other side of the chip electrode was not. Therefore, the chip is considered not to have been completely cracked, and the cracking operation has failed. Conversely, if the grayscale image of the electrode side shows cracking marks, but the grayscale image of the emitting side does not, it means that one side of the chip electrode was successfully cracked, but the other side of the chip substrate was not. Therefore, the chip is considered not to have been completely cracked, and the cracking operation has failed.

[0085] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0086] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A semiconductor chip, characterized in that, include: Epitaxial layer (10), passivation layer (20) and cleavage reflective layer (30); The epitaxial layer (10) has isolation trenches (40); The passivation layer (20) covers one side of the epitaxial layer (10) and fills the isolation trench (40). The reflective layer (30) of the cutting channel covers one side of the passivation layer (20) and corresponds to the position of the isolation trench (40).

2. The semiconductor chip according to claim 1, characterized in that, The isolation trench (40) has marker points (50); The reflective layer (30) of the cutting track has holes (310) opposite to the marker (50) to expose the marker (50).

3. The semiconductor chip according to claim 2, characterized in that, The marker point (50) is located at the intersection between the two isolation trenches (40).

4. The semiconductor chip according to claim 1, characterized in that, The thickness of the reflective layer (30) of the cutting track is 1~10µm.

5. The semiconductor chip according to claim 1, characterized in that, The orthographic projection of the reflective layer (30) on the plane where the epitaxial layer (10) is located is within the isolation trench (40).

6. A method for fabricating a semiconductor chip, characterized in that, include: An epitaxial layer (10) is prepared, and isolation trenches (40) are etched on the epitaxial layer (10). A passivation layer (20) is prepared on one side of the epitaxial layer (10), and the passivation layer (20) fills the isolation trench (40). A slit reflective layer (30) is prepared on one side of the passivation layer (20), and the slit reflective layer (30) is located at the position corresponding to the isolation trench (40); The dicing operation is carried out along the reflective layer (30) of the cutting track; Automated optical inspection is performed to determine whether there are crack marks at the reflective layer (30) of the cutting track. If there are crack marks at the reflective layer (30) of the cutting track, the cracking operation at the corresponding position is successful. If there are no crack marks at the reflective layer (30) of the cutting track, the cracking operation at the corresponding position fails.

7. The preparation method according to claim 6, characterized in that, Fabricating an epitaxial layer (10) and etching isolation trenches (40) on the epitaxial layer (10) includes: During the etching of the isolation trenches (40), marker points (50) are formed at the intersection of the two isolation trenches (40).

8. The preparation method according to claim 7, characterized in that, A dicing reflective layer (30) is prepared on one side of the passivation layer (20), comprising: Black glue is applied to one side of the passivation layer (20); The black adhesive is photolithographically etched to obtain the dicing reflective layer (30), which has holes (310) opposite to the marker point (50) to expose the marker point (50).

9. The preparation method according to claim 6, characterized in that, After preparing a kerf reflective layer (30) on one side of the passivation layer (20), the preparation method includes: The reflective layer (30) of the cutting track is etched to reduce the thickness of the reflective layer (30) of the cutting track to 1~10µm; The reflective layer (30) of the cutting track is soaked in an organic solution.

10. The preparation method according to claim 6, characterized in that, Perform automated optical inspection, including: Grayscale images of the light-emitting surface and the electrode surface of the semiconductor chip were captured separately. Check whether there are crack marks at the position corresponding to the reflective layer (30) of the cutting path on the grayscale map of the light-emitting surface and the grayscale map of the electrode surface; If both the grayscale image of the luminescent surface and the grayscale image of the electrode surface show cracking marks, the cracking operation at the corresponding position is successful. If neither the grayscale image of the luminescent surface nor the grayscale image of the electrode surface shows cracking marks, the cracking operation at the corresponding position fails.

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