Semiconductor package

Abstract

The invention provides a semiconductor package. A semiconductor package may include a semiconductor die disposed on a first substrate and having at least a first contact on a first side and at least a second contact on a second side opposite the first side. An insulator, such as a dielectric material, may encapsulate the semiconductor die. The second substrate may be disposed on the first substrate with the semiconductor die between the first substrate and the second substrate. Either the first substrate or the second substrate may have cavities formed therein, and a semiconductor die may be disposed in one or both of the cavities. Through vias through the first substrate, the dielectric, and / or the second substrate may be used to connect to the semiconductor die, enabling formation of a redistribution layer. Magnetic elements and associated windings may also be used in place of the semiconductor die and associated contacts.

Description

Cross-references to related applications

[0001] This application claims the interests and priorities of U.S. Provisional Application No. 63 / 715,912, filed November 4, 2024, U.S. Provisional Application No. 63 / 736,415, filed December 19, 2024, and U.S. Non-Provisional Application No. 19 / 376,690, filed October 31, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This description relates to semiconductor device packages. Background Technology

[0003] Conventional packaging technologies for semiconductor devices have many drawbacks. These drawbacks are particularly problematic when packaging semiconductor power devices, as such devices typically have multiple requirements that must be met simultaneously by the chosen packaging technology.

[0004] For example, semiconductor power devices typically require high voltage and high temperature operation, necessitating high voltage isolation for safety reasons and high thermal conductivity to transfer heat to some type of heat sink. It is also generally desirable for power device packages to be low-cost and small in size, which further complicates meeting voltage / thermal requirements.

[0005] In a specific example, there is a desire to provide semiconductor modules for traction inverters in electric vehicles, which have low on-resistance and low circuit parasitics across many parallel devices, while maintaining the aforementioned requirements for low cost, small size, and voltage / thermal management. In another specific example, artificial intelligence (AI) data centers have massive power requirements, but current packaging technologies suffer from, for example, the complexity associated with multi-chip packaging within a small package footprint (exacerbated by the use of flip-chip technology), poor thermal conductivity of the molding compound used for sealing, and undesirable large package volumes due to the inclusion of bonding wires.

[0006] Recent approaches attempt to address the aforementioned and related challenges, such as embedding methods using printed circuit boards (PCBs). However, these methods can be expensive and complex, and still do not satisfactorily solve existing challenges. For example, PCB embedding typically requires expensive laser drilling for through-holes, while providing insufficient cooling. Summary of the Invention

[0007] According to one general aspect, a semiconductor package includes: a substrate; a semiconductor die disposed on the substrate and having at least a first contact on a first side and at least a second contact on a second side opposite to the first side; a dielectric sealing material sealing the semiconductor die and having a through-hole formed therein; and a redistribution layer formed on the dielectric sealing material and connected to the first and second contacts through the through-hole.

[0008] According to another general aspect, a method of manufacturing a semiconductor package includes: providing a semiconductor die on a substrate, the semiconductor die having at least a first contact on a first side and at least a second contact on a second side opposite to the first side; sealing the semiconductor die with a dielectric sealing material; forming a through-hole in the dielectric sealing material; and forming a redistribution layer on the dielectric sealing material, the redistribution layer being connected to the first and second contacts through the through-hole.

[0009] According to another general aspect, a semiconductor package includes: a first substrate; a semiconductor die disposed on the first substrate; a second substrate having a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, and the second substrate being attached to the first substrate through the second portion of the second substrate and with the semiconductor die disposed within the cavity; a through-hole formed through the first portion of the second substrate; and a contact portion disposed on the second substrate and electrically connected to the semiconductor die through the through-hole.

[0010] According to another general aspect, a method of manufacturing a semiconductor package includes: disposing a semiconductor die on a first substrate; forming a cavity in a second substrate defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth; attaching the second substrate to the first substrate through the second portion of the second substrate and with the semiconductor die disposed within the cavity; forming a through-hole through the first portion of the second substrate; and disposing a contact portion on the second substrate, the contact portion being electrically connected to the semiconductor die through the through-hole.

[0011] According to another general aspect, a semiconductor package includes: a substrate having a cavity formed therein; a magnetic element disposed in the cavity; a metal winding disposed on the substrate and surrounding the magnetic element; a dielectric sealing material sealing the magnetic element and the metal winding; and a contact portion electrically connected to the metal winding through a through-hole formed in the dielectric sealing material.

[0012] According to another general aspect, a method of manufacturing a semiconductor package includes: forming a cavity in a substrate; disposing a magnetic element in the cavity; providing a metal winding on the substrate and surrounding the magnetic element; sealing the magnetic element and the metal winding with a dielectric sealing material; forming a through-hole in the dielectric sealing material; and electrically connecting a contact to the metal winding through the through-hole.

[0013] According to another general aspect, a semiconductor package includes: a first substrate; a metal layer disposed on the first substrate; metal pillars disposed on the metal layer and defining a cavity; a semiconductor die disposed in the cavity, wherein a first surface of the semiconductor die is disposed on the metal layer; a sealing material sealing the semiconductor die (including a second surface of the semiconductor die opposite to the first surface) and at least a portion of the metal pillars; a second substrate formed on the sealing material and the metal pillars; and a redistribution layer formed on the second substrate and connected to at least one of the first surface of the semiconductor die, the second surface of the semiconductor die, and the metal pillars through a through-hole formed through the second substrate.

[0014] According to another general aspect, a method of manufacturing a semiconductor package includes: forming a metal layer on a first substrate; disposing metal pillars on the metal layer to define a cavity; disposing a semiconductor die in the cavity, wherein a first surface of the semiconductor die is disposed on the metal layer; sealing the semiconductor die (including a second surface of the semiconductor die opposite to the first surface) and at least a portion of the metal pillars with a sealing material; forming a second substrate on the sealing material and the metal pillars; forming a through-hole through the second substrate; and forming a redistribution layer on the second substrate, the redistribution layer being connected to at least one of the first surface of the semiconductor die, the second surface of the semiconductor die, and the metal pillars through the through-hole.

[0015] Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the specification, drawings, and claims. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of a semiconductor module according to an example embodiment.

[0017] Figure 2A It is used to form Figure 1 A cross-sectional view of an example processing stage of a semiconductor module.

[0018] Figure 2B It is used to form something similar to Figure 1 A cross-sectional view of an example processing stage of a semiconductor module.

[0019] Figure 2C It is used to form Figure 2BA cross-sectional view of an example processing stage of a semiconductor module.

[0020] Figure 2D It is used to form Figure 2B Another example of a processing stage of a semiconductor module is shown in the cross-sectional view.

[0021] Figure 2E It is used to form Figure 2D A cross-sectional view of an example processing stage of a semiconductor module, showing additional example optional contacts.

[0022] Figure 2F yes Figure 2B A cross-sectional view of the final processing stage of the semiconductor module.

[0023] Figure 3 This is a cross-sectional view of a cavity-based semiconductor module according to an example embodiment.

[0024] Figure 4 This is a cross-sectional view of an example embodiment having a second substrate.

[0025] Figure 5A It is used to form Figure 4 A cross-sectional view of the first processing stage of an example embodiment.

[0026] Figure 5B It is used to form Figure 4 A cross-sectional view of the second processing stage of an example embodiment.

[0027] Figure 6 This is a cross-sectional view of an example embodiment with a stacking device.

[0028] Figure 7 This is a cross-sectional view of an example embodiment with stacked modules.

[0029] Figure 8 This is a cross-sectional view of an example embodiment of a semiconductor module with back-side contacts.

[0030] Figure 9 This is an exemplary embodiment illustrating the ease of connection of a semiconductor module constructed using the described technology to provide a package footprint that matches existing packages.

[0031] Figure 10 This is a cross-sectional view of an example embodiment with nested modules.

[0032] Figure 11 It shows Figure 10 The first example usage instance of the example implementation.

[0033] Figure 12 It shows Figure 9The first example usage instance of the example implementation.

[0034] Figure 13 This is a circuit diagram illustrating the operation of a module that functions as a solid-state relay according to an example embodiment.

[0035] Figure 14 This is a top view of a portion of the wafer used to produce each module with four semiconductor dies.

[0036] Figure 15 yes Figure 14 A top view of the entire wafer.

[0037] Figure 16 This is an example implementation demonstrating dual thermal connections and electrical connections.

[0038] Figure 17 This is an alternative example implementation demonstrating dual thermal connections and electrical connections.

[0039] Figure 18 An example embodiment with multiple cavities is shown.

[0040] Figure 19 It shows those deployed together Figure 18 An example embodiment of an array of multiple modules.

[0041] Figure 20A This is an isometric view of an example embodiment with cooling blocks.

[0042] Figure 20B yes Figure 20A A cross-sectional view of an exemplary embodiment.

[0043] Figure 21 It is used for Figures 18 to 20B An example 3D exploded view of the assembly package of the embodiment.

[0044] Figure 22 An example of single-metal layer wiring for multiple dies is shown.

[0045] Figure 23 This is a cross-sectional view of an example dual-cavity embodiment.

[0046] Figure 24 This is a cross-sectional view of an alternative example dual-cavity embodiment.

[0047] Figure 25 This is a cross-sectional view of an example single-cavity embodiment on a metal.

[0048] Figure 26 This is a cross-sectional view of an example dual-cavity embodiment with silicon bonded to diamond.

[0049] Figure 27This is a cross-sectional view of an example dual-cavity embodiment with a drain-side redistribution layer.

[0050] Figure 28 This is a cross-sectional view of an alternative example dual-cavity embodiment with a drain-side redistribution layer.

[0051] Figure 29 This is a cross-sectional view of an example dual-cavity embodiment, in which one cavity is formed using a metal substrate and a substrate frame.

[0052] Figure 30 This is a cross-sectional view of an example dual-substrate, single-cavity embodiment.

[0053] Figure 31 This is a cross-sectional view of an example dual-cavity embodiment having a redistribution layer formed between substrates.

[0054] Figure 32 This is a cross-sectional view of an example dual-cavity embodiment with integrated passive devices.

[0055] Figure 33 This is a cross-sectional view of an example dual-cavity embodiment with integrated active circuitry.

[0056] Figure 34 This is a cross-sectional view of an example dual-cavity embodiment with integrated MEMS technology.

[0057] Figure 35 This is a cross-sectional view of an example dual-cavity embodiment with an integrated MEMS tube for liquid cooling.

[0058] Figure 36 This is a cross-sectional view of an alternative example dual-cavity embodiment with integrated MEMS technology and / or active circuitry.

[0059] Figure 37 This is a cross-sectional view of an example dual-cavity, dual-core embodiment.

[0060] Figure 38 It can be used Figure 37 and / or Figures 39 to 50 The example embodiments are top views of various example embodiments constructed in the example embodiments.

[0061] Figure 39 This is a cross-sectional view of an exemplary dual-die embodiment having a substrate with cavities in a metal to provide a common drain connection.

[0062] Figure 40 An example gate / source wiring is shown.

[0063] Figure 41 It shows the use of Figure 40 Example of gate / source / drain wiring.

[0064] Figure 42 This is a cross-sectional view of an example dual-cavity, dual-core embodiment with a single redistribution layer.

[0065] Figure 43 This is a cross-sectional view of an example stacked module with multiple dual-cavity, dual-die modules.

[0066] Figure 44 This is a cross-sectional view of an example stacked module in a half-bridge configuration.

[0067] Figure 45 This is a cross-sectional view of an alternative example stacked module in a half-bridge configuration.

[0068] Figure 46 This is a cross-sectional view of a second alternative example stacked module in a half-bridge configuration.

[0069] Figure 47 It has a busbar. Figure 46 A cross-sectional diagram of the example implementation.

[0070] Figure 48 yes Figure 47 A top view of an example embodiment.

[0071] Figure 49 This is a cross-sectional view of an additional example stacked module in a half-bridge configuration.

[0072] Figure 50 This is a circuit diagram for stacked modules used in a half-bridge configuration.

[0073] Figure 51 This is a cross-sectional view of a dual-cavity embodiment packaged with a printed circuit board and a heat sink.

[0074] Figure 52 This is a cross-sectional view of a single-cavity embodiment with alternative gate wiring and bonding interfaces.

[0075] Figure 53 This is a cross-sectional view of a single-cavity embodiment with alternative gate and source wiring to accommodate a heat sink.

[0076] Figure 54 This is a cross-sectional view of a single-cavity embodiment with alternative gate wiring.

[0077] Figure 55 This is a cross-sectional view of a single-cavity embodiment with embedded magnetic elements.

[0078] Figure 56 yes Figure 55 A top view of an example.

[0079] Figure 57A It shows Figure 55 and Figure 56 The first example embodiment of the example.

[0080] Figure 57B It shows Figure 55 and Figure 56 The second example embodiment of the example.

[0081] Figure 58 It shows Figure 55 and Figure 56 The third example embodiment of the example.

[0082] Figure 59 This is a cross-sectional view of an alternative single-cavity embodiment.

[0083] Figure 60 yes Figure 59 Example top view of an embodiment.

[0084] Figure 61A It shows the method for forming Figure 59 The first example process of the lower component.

[0085] Figure 61B It shows the method for forming Figure 59 The second example process for the lower component.

[0086] Figure 61C It shows the method for forming Figure 59 The third example process of the lower component.

[0087] Figure 61D It shows the method for forming Figure 59 The fourth example process of the lower component.

[0088] Figure 61E It shows the method for forming Figure 59 The fifth example process of the lower component.

[0089] Figure 61F It shows the method for forming Figure 59 The sixth example process of the lower component.

[0090] Figure 61G It shows the method for forming Figure 59 The seventh example procedure for the lower component.

[0091] Figure 62A It shows the method for forming Figure 59 The first example process of the upper component.

[0092] Figure 62B It shows the method for forming Figure 59 The second example process of the upper component.

[0093] Figure 62C It shows the method for forming Figure 59 The third example process of the upper component.

[0094] Figure 62D It shows the method for forming Figure 59 The fourth example process of the upper component.

[0095] Figure 63A A first example process for forming an alternative embodiment with metal pillars is shown.

[0096] Figure 63B A second example process for forming an alternative embodiment with metal pillars is shown.

[0097] Figure 63C A third example process for forming an alternative embodiment with metal pillars is shown.

[0098] Figure 63D A fourth example process for forming an alternative embodiment with metal pillars is shown.

[0099] Figure 63E A fifth example process for forming an alternative embodiment with metal pillars is shown.

[0100] Figure 63F A sixth example process for forming an alternative embodiment with metal pillars is shown.

[0101] Figure 63G A seventh example process for forming an alternative embodiment with metal pillars is shown.

[0102] Figure 63H An eighth example process for forming an alternative embodiment with metal pillars is shown.

[0103] Figure 63I A ninth example process for forming an alternative embodiment with metal pillars is shown.

[0104] Figure 63J A tenth example process for forming an alternative embodiment with metal pillars is shown.

[0105] Figure 64 This is a cross-sectional view of an example embodiment in which a heat sink is formed in a through hole.

[0106] Figure 65 An example process flow for forming a cavity that can be used with various embodiments is shown.

[0107] Figure 66 This is a first flowchart illustrating an example embodiment.

[0108] Figure 67 This is a second flowchart illustrating an example embodiment.

[0109] Figure 68This is a third flowchart illustrating an example embodiment.

[0110] Figure 69 This is a fourth flowchart illustrating an example embodiment. Detailed Implementation

[0111] The described power semiconductor packaging technology enables improvements over the aforementioned and other drawbacks of conventional technologies. For example, the described technology offers improved thermal characteristics (including double-sided cooling), reduced package parasitic effects, and simplified double-sided electrical / thermal paths. The described technology provides a more compact and reliable package while enabling the use of simplified manufacturing techniques that, among other advantages, still allow for a high degree of flexibility in constructing a wide range of semiconductor modules.

[0112] In the described example technology, at least one semiconductor die is disposed on a substrate and encapsulated or embedded within an insulator (such as a dielectric layer or air cavity). A second substrate may be positioned on the first substrate, wherein the semiconductor die and the insulator are positioned between the first and second substrates. Vias through the second substrate and / or through the dielectric layer may be used to provide a redistribution layer (RDL) that provides electrical access and control to the semiconductor die.

[0113] Using these and similar structures, many different manufacturing methods can be used to construct many different embodiments. For example, one or more semiconductor dies can be disposed within one or more cavities. For example, when a second substrate is used to enclose or package a semiconductor die located on or within a first substrate, one or more cavities can be formed in either or both of the first and second substrates.

[0114] An RDL (Representational Depth) can be provided for the semiconductor die at a single plane or layer within the resulting module. For example, when the semiconductor die includes a transistor, the source, gate, and drain contacts of the transistor can be redistributed to a single metallization layer. For example, when a second substrate is included, the RDL can be disposed at a layer of the module located on the surface of the second substrate opposite to the first substrate. In other examples, the RDL can be disposed at a layer of the module located between the first and second substrates. In other examples, contacts for the semiconductor die can be distributed to opposite sides of the module.

[0115] Example embodiments may have electrical connectivity on the top and / or bottom surfaces of the semiconductor module, and may also have thermal conductivity on the top and / or bottom surfaces of the semiconductor module. For example, the semiconductor module may have electrical connectivity on the top surface and thermal conductivity on the bottom surface.

[0116] Mechanical components can be fabricated within a semiconductor module and integrated with the semiconductor die. For example, microelectromechanical systems (MEMS) devices can be incorporated. For instance, MEMS devices can be incorporated to provide fast, current-isolated electromechanical solid-state relays, which can be used, for example, as circuit breakers that offer the advantages of both electromechanical and solid-state circuit breakers.

[0117] In other examples, instead of semiconductor devices, or in addition to semiconductor devices, magnetic elements may be included. Metal layers or metal traces may be used to provide windings around the magnetic elements, which enable the construction of transformers and other inductive devices.

[0118] Many different manufacturing techniques can be used. For example, when using standard dielectric and / or semiconductor materials, standard manufacturing techniques can be combined to enable the described device to be constructed in a fast, inexpensive, and reliable manner. For example, when the second substrate includes silicon, common etching techniques can be used to provide through-silicon vias (TSVs) for constructing the RDL. In contrast, as mentioned above, conventional embedded packaging techniques using organic materials or other sealing materials may require more expensive drilling techniques, such as laser drilling, to provide electrical connections.

[0119] In some embodiments, when silicon is used for both the first and second substrates, wafer-to-wafer bonding can be used, followed by separation of the individual semiconductor modules. In other embodiments, the semiconductor devices can be disposed on a wafer panel, then monolithically / diced, and then the second substrate can be added.

[0120] In this way, the second substrate and / or dielectric layer, along with the included vias for forming the RDL, can partially or completely replace wire bonding or other conventional interconnect technologies. Furthermore, since silicon or its variants (e.g., silicon carbide (SiC)) can be used to provide the second substrate, active or passive devices can be included within it, thereby increasing the flexibility of available design choices for the module while further reducing module size. Therefore, the described techniques can be used to enhance or replace conventional semiconductor packages, including semiconductor packages for high-power semiconductor devices and modules.

[0121] Figure 1 This is a cross-sectional view of a semiconductor module 100 according to an example embodiment. Figure 1In the example, semiconductor die 102 is shown as a transistor having a gate pad 104, a source pad 110, and a drain pad 116. For example, semiconductor die 102 may represent a silicon or gallium nitride-based transistor, which may have low on-resistance, reduced parasitic effects, fast and efficient switching, and other benefits described herein, including improved ability to operate in high-current, high-power, and high-temperature environments. In other embodiments, semiconductor die 102 may include an insulated-gate bipolar transistor (IGBT), a silicon carbide (SiC) diode, or a thyristor. Furthermore, these and other devices, and their various combinations, can benefit from the reliability and flexibility provided by the packaging and electrical wiring techniques described in more detail below.

[0122] For example, gate pad 104 is illustrated with a gate connection or gate contact 108 formed using a gate via 106. Similarly, source pad 110 is illustrated with a source connection or source contact 114 formed using a source via 112. Drain pad 116 is disposed on a metal layer 118 that extends beyond the semiconductor die 102 and beyond the via 120 to enable electrical contact with a drain connection or drain contact 122. Figure 1 In this process, any suitable metal (such as copper) can be used to form various electrical contacts and / or layers.

[0123] Therefore, the gate contact 108, source contact 114, and drain contact 122 can be included in the metallization layer providing RDL 124, which enables flexible and reliable connection of the semiconductor die 102 to other components within the aforementioned larger semiconductor module, and is shown and described in more detail in the various example embodiments provided below. In other words, RDL 124 provides easy and reliable contact with the semiconductor die 102, such as... Figure 9 and Figure 12 As shown.

[0124] In addition, Figure 1 In this package, dielectric 126 provides a package for semiconductor die 102. The package dielectric 126 can be provided using any suitable non-conductive dielectric material, including, for example, silicon oxide, silicon nitride, silicon oxynitride, or polyimide (PSP), to name a few. Such materials are widely used in semiconductor processing because of their ability to provide insulation, for example, when providing separation between metallization layers. However, in… Figure 1 In this embodiment, dielectric 126 provides complete encapsulation of semiconductor die 102, extending around semiconductor die 102 and vias 106, 112, 120, and around metal layer 118. Specifically, dielectric layer 128 provides separation between the encapsulated semiconductor die 102 and substrate 130.

[0125] The substrate 130 can be provided using any suitable material, including semiconductor materials such as silicon, or other suitable materials, including, for example, metals, ceramics, or glass. A heat sink 132 can be attached to the substrate 130. As mentioned earlier, in Figure 1 In this configuration, dielectric layer 128 provides electrical isolation between semiconductor die 102 and substrate 130, enabling the use of heat sink 132. In other embodiments, for example, such as... Figures 2B to 2F As shown in the example, the metal layer 118 can be formed directly on the substrate 130, for example, it may not be electrically isolated from the substrate 130.

[0126] The use of substrate 130 and encapsulation dielectric 126 enables the use of other standard technologies for manufacturing or processing semiconductor module 100, as described below. Figures 2A to 2F More detailed illustration and description are provided. Dielectric 126 is capable of being used as a sealing material, in part because of the excellent thermal management techniques described herein, including the potential for top-side and / or bottom-side cooling, wherein bottom-side cooling in... Figure 1 It is shown in the figure by using a dielectric layer 128 and a heat sink 132.

[0127] Figure 2A It is used to form Figure 1 A cross-sectional view of an example processing stage of a semiconductor module. Figure 2A In this context, substrate 202 can represent any suitable substrate, such as a silicon substrate. For example, a 300mm silicon wafer can be used, as per [reference to...]. Figure 14 and Figure 15 More detailed description.

[0128] Then, a dielectric layer 204 can be deposited across the silicon wafer using any suitable deposition technique. The dielectric layer 204 corresponds to... Figure 1 The dielectric layer 128 provides electrical isolation between the substrate 202 and the metal layer 206, wherein the metal layer 206 corresponds to Figure 1 Metal layer 118.

[0129] A metal layer 206 with desired thickness and patterning can be deposited throughout the silicon wafer. That is, Figure 2A A metal layer 204 on a mask of a wafer is shown, wherein the metal layer 204 can be replicated across the wafer a desired number of times to achieve, for a single wafer, such as Figure 1 Multiple examples of the semiconductor module 100.

[0130] exist Figures 2B to 2F In this configuration, the dielectric layer 204 is omitted, thereby achieving electrical connection with the substrate 202. That is, as... Figure 2BAs shown, metal layer 206 is formed directly on substrate 202. Then, semiconductor die 208 is attached (e.g., soldered or sintered) to metal layer 206. That is, for each semiconductor module to be formed, multiple instances of semiconductor die 208 can be attached to various locations on the wafer.

[0131] Then, corresponding to Figure 1 The dielectric layer 126 and the dielectric layer 210 can be deposited throughout the wafer, including Figure 2B The substrate 202 and the metal layer 206. Any desired patterning of the dielectric layer 210 throughout the wafer can be achieved using standard processing techniques, resulting in a substantially flat surface for the dielectric layer 210. Therefore, as per [the relevant information]... Figure 1 As described and shown, and as Figure 2B As shown, the semiconductor die 208 is fully encapsulated or embedded by the dielectric layer 210.

[0132] exist Figure 2C In this process, vias 212 are formed (e.g., etched) to establish contact with the semiconductor die 208. Then, in Figure 2D In, and with Figure 1 As with the example, metal can be deposited or otherwise provided within the via 212 to provide the gate contact 214, source contact 216, and drain contact 218. Also, regarding... Figure 1 The contacts 214, 216, and 218 provide an RDL 220, which enables flexible, reliable, and direct connection to the semiconductor die 208.

[0133] Figure 2E It is used to form Figure 2D A cross-sectional view of an example processing stage of the semiconductor module shows additional example optional contacts 222, 224, 226 formed in vias in dielectric layer 227 and providing electrical connections through dielectric layer 227. That is, contacts 222, 224, 226 represent metal contacts providing gate contact 222, source contact 224, and drain contact 226, which together provide a second RDL 228. Therefore, the second RDL 228 enables additional connection options for semiconductor die 208. More generally, any number or layers of such RDLs can be provided as needed to achieve desired connections to semiconductor die 208.

[0134] Figure 2F yes Figure 2B A cross-sectional view of the final processing stage of the semiconductor module. Figure 2F middle, Figure 2EThe substrate 202 undergoes grinding or other types of thinning to provide a thinned substrate 230. Backside metal 232 can then be added, for example, to enable further connections to the semiconductor die 208 (e.g., to its drain). Monolithization or other cutting can then be performed to obtain individual or grouped semiconductor modules. Thus, it can be observed that... Figure 2F The resulting example implementation is similar to Figure 1 and Figure 2A Example embodiments, but not by Figure 1 dielectric layer 128 or Figure 2A Electrical isolation is provided by the dielectric layer 204.

[0135] Figure 1 and Figures 2A to 2F The example embodiments described below, along with various other example embodiments, offer a number of benefits. For example, using a sufficiently high-quality dielectric as the sealing material ensures high-voltage isolation while maintaining good thermal conductivity, and in particular, provides excellent thermal properties for conventional substrates such as active metal brazing (AMB) or direct-bonded copper (DBC) substrates.

[0136] The described technology enables the formation of through-holes using etching techniques (instead of drilling, such as laser drilling), making through-hole formation inexpensive and offering excellent depth control. Furthermore, the described technology accelerates the time from request to delivery of modules. For example, builds can be performed using standard semiconductor manufacturing and testing techniques (and automation), without requiring different packaging processes or toolsets. Similarly, semiconductor design tools can be used for automation and for extracting electrical and mechanical properties such as device parasitic effects.

[0137] In addition to improved device parasitic effects, package parasitic effects are further improved through controlled and optimized impedance in the redistributed layout. Furthermore, the example embodiments offer excellent thermal performance, including the potential for dual-sided cooling using optimized thermal paths. The described modules can be readily extended to include multiple (identical or different) base devices, as well as embedded passive devices and active circuitry, including MEMS.

[0138] The above references Figure 1 and Figures 2A to 2FVarious components and elements are described below, but should be understood as being described by way of non-limiting example. For example, the substrate used may include Si, SiC, GaN, sapphire, diamond, or similar semiconductor or insulating materials. Thus, any particular property or characteristic (e.g., electrical, thermal, mechanical, chemical, or physical) of such a substrate can be designed / selected. The substrate may be processed at the wafer level with standard wafer diameters (e.g., 2”, 4”, 6”, 8”, 12”) and / or may be derived from a slicing ingot. The substrate may have an initial target thickness and may be thinned in further processing steps (e.g., after die attachment and interlayer dielectric (ILD) / RDL) to achieve the overall total thickness target of the final product. The substrate may be pre-treated to include semiconductor features (e.g., transistors manufactured by standard semiconductor wafer fabrication techniques such as doping or photolithography), and / or may be pre-treated to include other features such as MEMS structures or metal-insulator-metal (MIM) structures (such as MIM capacitors).

[0139] One or more of many types of back-side surface treatments can be applied. For example, back-side treatments can be provided using known / standard processing techniques (e.g., after wafer thinning). For example, copper or diamond can be used to provide good thermal conductivity and / or thermal diffusion. Metallization and / or inert dielectrics with plating can be provided for passivation. Mechanical bonding (e.g., welding, sintering, etching) can be used.

[0140] Mechanical bonding and / or electrical connection to the environment can be provided using, for example, soldering, sintering, and / or etching. Backside surface treatments also provide mechanical stress control, for example, to avoid wafer bending and match thermal expansion coefficients. For example, backside metals (e.g., copper or aluminum with plating / surface treatments such as silver or silver alloys for contact formation and / or copper or aluminum with non-conductive materials (e.g., dielectrics) for passivation) can be deposited using sputtering or similar techniques. In addition to controlling wafer bending and other mechanical stresses, metal layer thickness can be determined or optimized to achieve, for example, a minimum / maximum resistance value for a given layout (width, length), a target fusing current such as a minimum, target, or maximum value, and / or a cost target (e.g., using thinner layers to reduce costs).

[0141] As described above, the dielectric layer can be formed using any suitable dielectric material, which can be deposited using standard wafer processing techniques such as chemical vapor deposition (CVD), lamination, sputtering, or printing (e.g., screen printing), and related processing as needed, such as photolithography / development, etching, drilling, grinding, or polishing. The composition and thickness of each layer can correspond to and be adapted to the following objectives: target temporary overvoltages, potentials to be blocked, and / or leakage currents, for example, such that the embedded semiconductor die substantially determines the overall isolation voltage and / or leakage current (e.g., a thinner ILD for low-voltage applications and a thicker ILD for high-voltage applications).

[0142] In addition to the examples mentioned above, the embedded semiconductor dies that may be included in the described embodiments may include non-power semiconductor devices, such as digital integrated circuit (IC) devices, analog IC devices, or mixed-signal IC devices, such as gate driver ICs. Compound devices such as silicon-on-insulator (SOI) or GaN-on-Si may also be used, in addition to Si, SiC, or GaN. Embedded devices may also include non-semiconductor, passive electronic components, or discrete electronic components, such as resistors, capacitors, or inductors implemented in any form (e.g., semiconductor, thin film, multilayer ceramic chip (MLCC), or others). More generally, virtually any device having a thickness compatible with the described embedded technology may be used, some of which are described and shown below, including, for example, one or more MEMS components or copper blocks.

[0143] A single semiconductor die or multiple (potentially different) dies can be included in a single module. For example, a SiC transistor can be embedded in a single embedded module along with a Si gate driver IC and decoupling capacitors. This can include an entire sub-circuit, circuit, or even an entire system (e.g., a power system). Different dies can have different thicknesses, and die attachment can be performed using any known / common techniques. Such techniques may include, but are not limited to, soldering, diffusion soldering, sintering, epoxy / glue, or other methods to achieve mechanical bonding and / or conductivity. One or more dies can be flip-chip oriented (e.g., with...). Figure 1 and Figures 2A to 2F Examples (compared to inverted versions) are included, in which the metal is patterned accordingly. For example, for examples such as the following... Figure 3 In the cavity-based embodiment, the vertical current-flow MOSFET can be positioned such that the gate and source terminals face into the cavity, while the drain faces into / outside the cavity.

[0144] Vias can be formed using standard semiconductor manufacturing techniques at the wafer level, such as (photo)etching or other known / standard techniques. Etching can be performed using selective chemical processes, which have a faster etch rate in the dielectric than the metal used for contact, allowing for good depth control. Vias can have any shape and / or size found to be relevant to and / or most favorable for processing, cost, and electrical characteristics. Multiple vias can be formed in parallel to provide an array.

[0145] Each RDL can be formed as a single layer (e.g., a top metal) or can be any number of layers (e.g., an interleaved layer of ILD and RDL, where vias connect one metal layer to the next through the ILD). Similar to the other metal layers discussed above, each RDL can be formed using any metal (pure or alloyed) that is typically highly conductive and can be electroplated or surface-treated. The thickness of the metal used can be related to achieving specific target resistance, target fusing current, or target electromigration, for example, on the order of about 1µm to 50µm. The metal can be deposited using standard wafer processing techniques such as CVD, sputtering, or similar techniques, or can be formed by electroless plating, electroplating, or other known techniques.

[0146] RDLs can be passivated using conductive or non-conductive passivation materials / techniques. Known techniques can be used to process RDLs for purposes including, but not limited to, realizing MIM capacitors, embedded inductors or resistors, or MEMS. Many different use cases can be realized using such integration, some of which are described and illustrated below, such as integrated liquid cooling, sensors, or mechanical micro-relays.

[0147] Figure 3 This is a cross-sectional view of a semiconductor module 300 having cavity 334 according to an example embodiment. Similar to... Figure 1 , Figure 3 The device includes a semiconductor die 302 having a gate pad 304 connected to a gate contact 308 via a gate via 306, a source pad 310 connected to a source contact 314 via a source via 312, and a drain pad 316 connected to a metal layer 318 and thereby to a drain contact 322 via a drain via 320. In this manner, an RDL 324 is formed on the surface of a dielectric 326 that embeds and encapsulates the semiconductor die 302.

[0148] Dielectric layer 328 (similar to) Figure 1 dielectric layer 128 or Figure 2A The dielectric layer 204 separates the metal layer 318 from the substrate 330. The metal layer 332 is disposed on the surface of the substrate 330 opposite to the semiconductor die 302. Similar to... Figure 2EAs an example, additional example contacts 336, 338, and 340 are encapsulated within a dielectric layer 335. That is, contacts 336, 338, and 340 represent metal contacts providing a gate contact 336, a source contact 338, and a drain contact 340, which together provide a second RDL 341. Therefore, the second RDL 341 enables the provision of additional connectivity options for the semiconductor die 302. More generally, as per [reference to...] Figure 2E As noted, any number of such RDLs can be provided as needed to achieve the desired connection to semiconductor die 302.

[0149] Besides Figure 1 and Figures 2A to 2F In addition to being compatible with all potential variations of the embodiments, Figure 3 The embodiment includes a cavity 334 that enables precise and secure placement and embedding of the semiconductor die 302. Figure 3 Example embodiments can be very similar to Figures 2A to 2F Use examples to construct it. For example, in Figures 2A to 2F Before performing the operation, you can Figure 2A A cavity 334 is formed within the substrate 202, after which... Figures 2A to 2F The remaining operations.

[0150] exist Figure 3 In this process, cavity 334 can be formed using wafer processing techniques (or combinations thereof), including but not limited to the following techniques. For example, dry or wet etching techniques can be used, such as reactive ion etching (RIE) or tetramethylammonium hydroxide (TMAH)-based etching, respectively. Cavity 334 can also be formed using mechanical polishing, drilling, or punching. In other examples, instead of forming the cavity within an existing substrate, mesa creation can be performed on the surface of the substrate to define the cavity relative to mesa formed using deposition (e.g., by CVD, sputtering, or lamination).

[0151] although Figure 3 A single cavity with a single semiconductor die 302 is shown, but other example semiconductor modules may have multiple cavities, each with one or more semiconductor dies, and / or may have a single cavity with two or more dies. Different cavities in a single module / wafer may have different depths.

[0152] In other embodiments, a single cavity can be a localized region of varying depth. For example, one half of the cavity may have a depth to accommodate an embedded die, while the other half may be deeper to accommodate another embedded die of a different thickness. Figure 3 In this case, the depth of cavity 334 is similar to the thickness of semiconductor die 302. More generally, the depth of the cavity can substantially match the thickness of the embedded die, or the depth can be deeper or shallower.

[0153] When one or more embedded dies are disposed within one or more cavities, the semiconductor die can be embedded within the cavity, on the mesa (outside the cavity), and / or a combination thereof (if multiple dies are included). If multiple dies with multiple thicknesses are included, then, as mentioned above, the dies can be assembled in cavities of different depths, wherein each cavity depth is partially determined by the corresponding embedded die thickness. In other embodiments, dies(s) can be provided in a single cavity of uniform depth and / or in single cavities of varying depths.

[0154] Figure 4 This is a cross-sectional view of an example embodiment of a semiconductor module 400 having a second substrate. Similar to... Figure 1 and Figure 3 , Figure 4 The device includes a semiconductor die 402 having a gate pad 404 connected to a gate contact 408 via a gate via 406, a source pad 410 connected to a source contact 414 via a source via 412, and a drain pad 416 connected to a metal layer 418 and thereby to a drain contact 422 via a drain via 420. In this manner, an RDL 424 is formed on the surface of a dielectric 426b, which embeds and encapsulates the semiconductor die 402.

[0155] exist Figure 4 In, similar to Figures 2B to 2F In this example, metal layer 418 is directly disposed on substrate 430. Metal layer 432 is disposed on the surface of substrate 430 opposite to semiconductor die 402. Similar to... Figure 3 The semiconductor die 402 is disposed inside the cavity 434.

[0156] exist Figure 4 In the semiconductor module 400, a first portion 400a is provided on which a second portion 400b is disposed. As mentioned above and discussed in more detail below, the semiconductor module 400 can be formed using wafer-to-wafer bonding or at the panel / mask level.

[0157] In either case, dielectric layer 426a is bonded to dielectric layer 426b, as described below. Figure 5A This will be discussed in more detail. The second substrate 436 is adjacent to the dielectric layer 426a, and the dielectric layer 438 is disposed on the second substrate 436. Therefore, vias 406, 412, and 420 are formed through all dielectric layers 426a, 426b, the second substrate 436, and the dielectric layer 438, and RDL 424 is formed on... Figure 4 On the dielectric layer 438 in the middle.

[0158] Besides Figure 1 and Figures 2A to 2F In addition to being compatible with all potential variations of the embodiments, Figure 4 The inclusion of a second portion 400b in the embodiments allows for a variety of different embodiments to be obtained by replacing the materials and / or thicknesses used for the second portion 400b (e.g., for the second substrate 436). For example, when the second substrate 436 comprises silicon, one or more additional semiconductor dies may be included in the second substrate, such as in… Figure 7 As shown in the example embodiment. Such a die can then be connected to semiconductor die 402 to achieve design goals, such as using multiple interconnect devices to form a half-bridge.

[0159] Figure 5A and Figure 5B It is used to form Figure 4 Cross-sectional views of the first and second processing stages of an exemplary embodiment. Figure 5A In China, use Figure 2A and Figure 2B The first part of the technical structure 500a has the following features: Figure 3 The cavity. For example... Figure 5A As shown by the dashed lines and arrows, the second portion 500b is bonded to the first portion 500a. For example, the second portion 500b may be part of a cover wafer bonded to a wafer including the first portion 500a. For example, the opposing planar dielectric surfaces 526a, 526b of portions 500a, 500b may be bonded to each other to provide a second substrate 536 over the semiconductor die 402.

[0160] exist Figure 5B In the process, the gate via 406, source via 412, and drain via 420 are formed, for example, by etching through... Figure 5A The second substrate 536 is used to form Figure 4 The second substrate 436 is formed by etching through the bonded dielectric layers 526a, 526b. Figure 4 The etched dielectric layers 426a and 426b. Therefore, as... Figure 4 As shown, it can provide Figure 4 The gate contact 408, source contact 414, and drain contact 422 redistribute all electrical signals from the semiconductor die 402 to the top surface of the module 400, such as... Figure 4 RDL 424.

[0161] When wafer-to-wafer bonding is used, the second portion 500b can be understood as a portion of a cover wafer bonded to the top surface of the lower wafer of the first portion 500a. For example, such bonding can include any suitable bonding technique, including hybrid bonding (where electrical contacts are located between the substrate surface of the first portion 500a and the cover surface of the second portion 500b), or wafer bonding (such as a full oxide bonding between the flat surfaces of dielectric layers 526a, 526b, where electrical contacts are formed by vias after the bonding operation, such as...). Figure 5B (As shown).

[0162] Once created Figure 4 Given this structure, further processing can be performed. For example, it is possible to execute... Figure 2E Further processing includes adding additional RDLs. More generally, this may include the above-mentioned... Figures 1 to 3 All the variations discussed, as well as many other variations, some of which are discussed in the context of the other example embodiments below.

[0163] exist Figure 4 , Figure 5A and Figure 5B In example embodiments, (e.g., Figure 5A The second part (500b) of the wafer or cover wafer may include an unprocessed or processed version of substrate 436 / 536. For example, included or processed features may include any semiconductor circuitry and / or associated wafer processing, such as doping. Features may include passive components such as copper blocks, resistors, capacitors, or inductors. Features may include MEMS or any other devices that can be fabricated on the wafer.

[0164] Either substrate 430 and / or 436 / 536 can be made of, for example, an insulating material (e.g., sapphire), a semiconductor material (e.g., silicon or GaN), or a conductive material (e.g., a metal, such as copper). Substrates 430 and / or 436 / 536 can be the same or different materials among these or other materials. When the material includes silicon, various through-holes 406, 412, 420 can be formed as through-silicon vias (TSVs). The one or two wafers used can be of any desired and available thickness.

[0165] Figure 6 This is a cross-sectional view of an example embodiment with stacked devices. Figure 6The device includes a semiconductor die 602a having a gate pad 604a connected to a gate contact 608a via a gate via 606a, a source pad 610a connected to a source contact 614a via a source via 612a, and a drain pad 616a connected to a metal layer 618a via a drain via 620a and thereby connected to a drain contact 622a. In this manner, an RDL 624a is formed in a dielectric 626, which embeds and encapsulates the semiconductor die 602a.

[0166] exist Figure 6 In, similar to Figure 1 and Figure 2A In the example, metal layer 618a is disposed on dielectric layer 628, and dielectric layer 628 itself is disposed on substrate 630. Metal layer 632 is disposed on the surface of substrate 630 opposite to semiconductor die 602a.

[0167] Figure 6 Also shown is a semiconductor die 602b, which has a gate pad 604b connected to a gate contact 608b via a gate via 606b, a source pad 610b connected to a source contact 614b via a source via 612b, and a drain pad 616b connected to a metal layer 618b via a drain via 620b and thereby connected to a drain contact 622b. In this way, an RDL 624b is on the surface of a dielectric 626, which embeds and encapsulates the semiconductor die 602b.

[0168] Figure 6 Implementations and variations thereof can be achieved by using (e.g., iterating) the above regarding Figures 2A to 2F The described technique is used to form it. Other variations may be included; for example, any one or both of semiconductor dies 602a and 602b may be disposed within the cavity. Furthermore, although in Figure 6 Only semiconductor dies 602a and 602b are shown, but in practice any desired number of semiconductor dies may be included. The various semiconductor dies and associated layers can have any desired thickness and can be the same or different from each other. Figure 6 It can be used to implement a power half-bridge, but it can also be used to construct many other power or non-power circuits, such as full-bridge, T-type, parallel, anti-parallel, series, or anti-series.

[0169] Figure 7 This is a cross-sectional view of an exemplary embodiment of stacked modules 700a and 700b. Figure 7The stacked module 700a includes a semiconductor die 702a, the semiconductor die 702a having a gate pad 704a connected to a gate contact 708a via a gate via 706a, a source pad 710a connected to a source contact 714a via a source via 712a, and a drain pad 716a connected to a drain contact 722a via a drain via 720a. In this manner, it is similar to... Figure 4 In one embodiment, an RDL 724a is formed at the junction of dielectrics 726a and 726b, wherein dielectric 726a embeds and encapsulates semiconductor die 702a. As further illustrated, similar to... Figure 3 In one embodiment, the semiconductor die 702a is disposed within the cavity 734a.

[0170] exist Figure 7 In this embodiment, metal layer 718a is disposed on substrate 730a. Metal layer 732 is disposed on the surface of substrate 730a opposite to semiconductor die 702a.

[0171] Figure 7 A stacked module 700b is further shown having a semiconductor die 702b within a cavity 734b. The semiconductor die 702b has a gate pad 704b connected to a gate contact 708b via a gate via 706b, a source pad 710b connected to a source contact 714b via a source via 712b, and a drain pad 716b connected to a metal layer 718b via a drain via 720b and thereby connected to a drain contact 722b. In this manner, an RDL 724b is on the surface of a dielectric 726b, which embeds and encapsulates the semiconductor die 702b.

[0172] exist Figure 7 In this embodiment, a metal layer 718b is disposed on a substrate 730b. A via 715a passing through the substrate 730b and the dielectric 726b is used to establish a source contact 717a for a semiconductor die 702a. The via 715b passing through the substrate 730b and the dielectric 726b is used to establish a contact 717b, which is connected to the drain contact 722a and the source contact 714b of the semiconductor die 702a.

[0173] Figure 7 Implementations and variations thereof can be achieved by using (e.g., iterating) the above-mentioned Figures 2A to 2F and Figure 5A , Figure 5B The technology described is used to form it.

[0174] It can include other variations, for example, Figure 7Two stacked modules, 700a and 700b, are shown, but any number of modules can be stacked. Figure 7 In the stacked modules 700a and 700b, the same type of semiconductor dies 702a and 702b are included, but different devices can also be used. Similarly, the substrates 730a and 730b can have the same material and thickness or can be different.

[0175] The bonding techniques used for bonding modules 700a and 700b may include wafer bonding (e.g., dielectric-to-dielectric), hybrid bonding (e.g., a mixture of conductors and dielectrics, as shown), or any other suitable bonding method. In some embodiments, one wafer may be flip-chip mounted relative to another wafer (e.g., flip-chip mounting), or the wafers may have the same orientation as each other. Similarly, the wafers and included devices may have the same grid / rotation as each other, or may be rotated relative to each other at any arbitrary or desired target rotation angle.

[0176] Figure 8 This is a cross-sectional view of an example embodiment of a semiconductor module with back-side contacts. Figure 8 In this configuration, the semiconductor die 802 has a gate pad 804 connected to the gate contact 808 via a gate via 806, a source pad 810 connected to the source contact 814 via a source via 812, and a drain pad 816 connected to the metal layer 818 and thereby connected to the drain contact 822 via a drain via 820. In this manner, an RDL 824 is formed on the surface of a dielectric 826, which embeds and encapsulates the semiconductor die 402 within a cavity 834.

[0177] exist Figure 8 In this configuration, metal layer 816 is directly disposed on substrate 830 and on back-side contacts 836 and 838 connected to metal layer 832. As shown, through-hole 837 is used to form the back-side contacts. In this way, it is possible to... Figure 8 Electrical connections to the drain pad 816 are established on both surfaces of the module.

[0178] exist Figure 8 In similar examples, the back side (drain) of the semiconductor die 802 can be reached using various techniques. For example, wet or dry etching, or other techniques used for etching silicon, can be used. Mechanical techniques such as drilling, grinding, or milling / machining can be used. Other potential techniques include laser drilling or plasma drilling.

[0179] Figure 8 An example is shown in which parallel TSVs or other vias 837 are used to provide patterned metal contacts. In other examples, substrate 830 may be thinned to the point where metal layer 818 directly contacts metal layer 832.

[0180] In other aspects and examples, the semiconductor die 802 can be provided with a low-ohmic contact on the back side (e.g., the drain) by any suitable method. For example, conductor deposition techniques (e.g., patterned or unpatterned), such as CVD, sputtering, or electroplating, can be used. In other examples, die attachment of conductor plugs (e.g., copper disks) can be performed, for example, by soldering, diffusion soldering, sintering, or anisotropic conductive adhesive (ACA) bonding.

[0181] Different thickness levels can be selected for one or more of the metal layers 818, back contacts 836, 838, and / or metal layer 832. During etching, a stop material can be used at the bottom of cavity 834 for back-side operation; that is, a back-side etching stop can be provided. In other examples, a shim (e.g., a copper sheet) can be mounted between the semiconductor die and the bottom of cavity 834 to help stop back-side grinding / etching / drilling. In this way, access to drain contact 816 (or other conductive elements of semiconductor die 802) can be provided without completely drilling through semiconductor die 802 itself.

[0182] Figure 9 This demonstrates the ease of interconnecting semiconductor modules constructed using the described technology to provide a package form factor that matches existing packages (or other desired package form factors). Figure 9 In the middle, a similar example is shown. Figure 3 The embodiment does not have a semiconductor module 900a with insulating layer 328. Or, in other words, similar to... Figure 2F The embodiments, but with Figure 3 Cavity 334. However, Figure 9 The example module 900a is not limiting, and any described embodiment or variation thereof may replace module 900a.

[0183] exist Figure 9 In this module 900a, there are semiconductor die 902 and RDL 924. RDL 924 includes gate contact 908, source contact 914, and drain contact 922, which are constructed using the techniques described above. Other components of module 900a correspond to those previously described and are not separately labeled or described here for the sake of brevity.

[0184] Furthermore, in Figure 9 In the diagram, package 900b, constructed using module 900a, is shown as having a four-plane leadless (QFN) package profile. Figure 9The diagram illustrates that module 900a can be configured such that contacts 908, 914, and 922 and / or RDL 924 match the package outline and thus provide the package outline of package 900b (including contacts 901, 903, and 905). In other words, module 900a illustrates a design approach in which module 900a provides an embedded device designed to have the same physical and electrical layout as QFN package 900b.

[0185] More specifically, the QFN 900b package refers to a surface-mount integrated circuit package with no protruding leads, and electrical contacts 901, 903, and 905 are flat and located on the bottom surface, typically allowing direct soldering to a printed circuit board (PCB). Figure 9 (Not shown in the image). Therefore, by matching the package form factor of the QFN package 900b, module 900a can be seamlessly integrated into existing circuit board designs without requiring modifications to the board layout. This compatibility ensures that module 900a can replace or function interchangeably with conventionally packaged devices while maintaining the same or better electrical connections and performance characteristics. Figure 9 In the example, the specific QFN package shape shown in module 900b corresponds to a module with multiple different dies forming two half-bridges with corresponding gate drivers, while the example of embedded module 900a is simplified for simplicity and illustration, and the corresponding number and connection of embedded dies are not explicitly shown.

[0186] In one particular example embodiment, the embedded module 900a can be designed to replicate the package form factor of a power stage, which is a component including gate driver circuitry, a high-side (HS) switch, and a low-side (LS) switch. The gate driver is the circuitry that controls the switching of the power transistors, while the high-side and low-side switches are typically metal-oxide-semiconductor field-effect transistors (MOSFETs) used in power management applications such as voltage regulation or motor control. By matching this power stage package form factor, the embedded module 900a can serve as a direct replacement, acting as a second source compatible with QFN power stage products in terms of form-fit function. Therefore, the embedded module 900a fits the same physical space and pin layout while performing the same or better electrical functions, providing a reliable option that does not require redesigning existing circuit boards or other package components.

[0187] Furthermore, the embedded module 900a offers enhanced thermal performance compared to conventional QFN packages. For example, conventional packages can be molded using epoxy molding compound (EMC), a plastic material used to package chips but with relatively poor thermal conductivity. In contrast, in one embodiment and using the disclosed techniques, the embedded module 900a may include a heat sink attached to the surface of a substrate 930 of the module 900a, thereby enabling improved heat dissipation in directions away from the PCB. As described herein, the substrate 930 may include silicon or another material with high thermal conductivity, thereby transferring heat more effectively than EMC used in conventional packages. Therefore, the embedding process described herein effectively provides a package that enables the embedded module 900a to have the functionality of a conventional die, chip, system-on-a-chip (SoC), or system-in-package (SiP) while providing improved cooling and compatibility with standard QFN package form factors.

[0188] Figure 10 This is a cross-sectional view of an example embodiment with nested modules. Figure 10 In this process, module 1000 is formed according to the aforementioned technology. Specifically, module 1000 is similar to... Figure 9 The module 900a is formed, but any of the above modules or their variations can be used.

[0189] In addition, Figure 10 In this embodiment, module 1000 is disposed within cavity 1034 formed in substrate 1030, and intermediate metal layer 1032 is disposed on substrate 1030 and lining the walls and bottom surfaces of cavity 1034. Dielectric 1026 embeds module 1000. Gate contact 1036, source contact 1038, and drain contact 1040 provide RDL 1024 and can be formed using the techniques described above.

[0190] therefore, Figure 10 One or more semiconductor dies are shown to be embedded using the described technology, and further packaged to include further embedding into another embedded module. This recursive embedding can be provided any desired number of times. Further packaging can be provided using conventional packaging techniques such as leadframes, bonding wires, EMC and / or potting compound-filled modules, to name a few.

[0191] Further packaging can be provided using wafer-scale / wafer-level packaging technologies and / or panel-level packaging technologies. In other examples, PCB embedding technologies or any other packaging technologies may also be used.

[0192] Figure 11 It shows Figure 10 The first example use case of the example embodiment. Specifically, Figure 11The diagram shows that component 1102 is included and can be easily added / connected to. Figure 10 The module contacts 1036, 1038, and 1040 may be one or more of these. For example, component 1102 may represent a busbar or various types of electrical components, as discussed in more detailed examples below.

[0193] For example, as mentioned earlier, component 1102 can represent a busbar. In the context of semiconductor packaging, a busbar refers to a relatively thick conductive structure used to improve electrical performance. For example, a busbar may include a metal strip or bar (e.g., a highly conductive material such as copper or a copper alloy) used to carry high currents or efficiently distribute power.

[0194] If possible Figure 10 and Figure 11 It has been observed that contacts 1036, 1038, and 1040 can be formed with a greater thickness than the corresponding contacts of module 1000, where the thickness of the latter contact of module 1000 may be limited by dimensional or manufacturing constraints during the manufacturing process. Therefore, such relatively thin conductors produced during the wafer fabrication process may have relatively high resistance and / or be prone to problems such as overheating or electromigration. In contrast, busbars, such as those formed by component 1102, are thicker and can handle higher currents with lower resistance. Therefore, by attaching the busbar as component 1102 to the embedded module 1000, performance objectives (e.g., reduced resistance, increased fusing current, and reduced electromigration) can be met, thereby enhancing reliability and efficiency in applications such as power electronics or high-current systems.

[0195] exist Figure 11 In the diagram, component 1102 representing the busbar can be joined to contacts 1038, 1040, for example, using solder contact 1106 through opening 1108 in insulating layer 1104. More generally, any of welding, diffusion welding, sintering, or ACA bonding can be used.

[0196] Busbar integration can be achieved prior to encapsulation steps such as potting compound filling, injection molding, or transfer molding. By attaching the busbar before these steps, the embedded module 1000 achieves enhanced electrical performance while remaining compatible with standard packaging processes. This approach enables the module 1000 to function in high-power applications while providing superior current handling capabilities compared to conventional thin conductors.

[0197] In other examples, as described above, component 1102 can represent a variety of other electrical components. For example, such components may include negative temperature coefficient (NTC) thermistors, multilayer ceramic capacitors (MLCCs), resistors, inductors, gate driver integrated circuits (ICs), or any other active or passive circuitry soldered to or otherwise bonded to contacts 1036, 1038, 1040, as described above. These and other components can be integrated to add specific corresponding functions compatible with existing PCB assemblies, while also allowing for direct integration of various components into… Figure 11 On embedded modules, or any other example embodiments described herein, including Figures 1 to 9 Examples.

[0198] Other non-limiting examples of components that can be embedded as component 1102 include semiconductor components, passive electronic components, and sensors. For example, semiconductor components (such as transistors, diodes, microprocessors, or application-specific integrated circuits (ASICs)) can be used to add processing or switching capabilities. Gate driver ICs can be used to control power transistors in applications such as motor drives or inverters. Passive components such as resistors, capacitors, inductors, or transformers or copper blocks (e.g., as an alternative to busbars for low-resistance conduction) can be used to enhance or improve electrical performance. Sensors such as microelectromechanical systems (MEMS) or NTC thermistors enable environmental monitoring, including current monitoring (thus providing circuit breakers), and temperature sensing for thermal management in high-power systems. By bonding one or more such components prior to any final packaging step (e.g., potting compound filling or EMC packaging), a compact, multifunctional module can be created that is easily integrated into systems requiring high reliability and high performance.

[0199] Figure 12 It shows Figure 9 Example use cases for example embodiments. In Figure 12 In the process, the described technology is used to construct module 1200a to provide contacts 1208, 1214, 1222, and similar to Figure 9 Module 1200a can be included in a QFN package shown as module 1200b. Magnetic structure 1200c represents, for example, an inductor. The operation of modules 1200a and 1200b is shown in circuit diagram 1200d.

[0200] More specifically, the magnetic structure 1200c (such as an inductor) is shown connected to the side of module 1200a opposite to the side with RDL 1224. This connection allows module 1200c to be connected to the windings of the inductor, enabling power management functions to be directly and compactly integrated into the module, thereby reducing the need for external components and minimizing the overall system size.

[0201] As shown in circuit diagram 1200d, to Figure 12 The back-side connection of the switching node marked "1" (e.g., the midpoint of a half-bridge configuration) defines an electrical contact at which the inductor is connected, for example, to manage current or voltage fluctuations. The inductor windings are shown as dashed lines between nodes 1 and 2, nodes 3 and 4, and nodes 5 and 6. Conductive traces or thin metal paths connecting nodes 2 and 3 and nodes 4 and 5, as shown by the dashed lines, complete the windings of the magnetic structure 12000c (e.g., the mentioned inductor windings). These conductive traces effectively act as wires wound around or connected to the inductor core, enabling module 1200a to contribute to magnetic field generation. By integrating these windings directly onto the surface of module 1200a, assembly is simplified, parasitic losses (e.g., resistance or inductance from external connections) are reduced, and performance is enhanced in high-frequency or high-power applications. In other examples, separate instances of such magnetic elements can be similarly integrated where partial windings are not implemented in module 1200a.

[0202] Furthermore, the output of the magnetic structure can be redistributed, allowing the electrical output from the inductor (e.g., filtered or regulated current) to be rerouted within module 1200a / 1200b to other components such as filter capacitors, or externally routed via alternative paths outside module 1200a / 1200b. This redistribution can involve, for example, additional back-side traces or internal routing to optimize signal integrity or power delivery. For instance, the inductor's output can be connected to a filter capacitor within the module to stabilize the power supply to the embedded SoC or SiP, or it can be routed to an external capacitor outside the module for system design flexibility.

[0203] As described above, many other components and associated functions can be included in a semiconductor module constructed using the technology described above. For example, any substrate included in such a module can contain virtually any component / function available in a wafer processing environment. Examples include any active semiconductor element, passive element (e.g., resistors, inductors, or capacitors, including MIM capacitors), sensor, and MEMS element, including cooling channels and electromechanical relays.

[0204] In a specific example, Figure 13 This is a circuit diagram illustrating the operation of a module according to an exemplary embodiment, which functions as a solid-state relay, for example, for high-voltage direct current (DC) switching. Figure 13 In this context, control circuitry 1302 can represent integrated / embedded or external / discrete control circuitry, such as including gate driver circuitry. Control circuitry 1302 is connected to the gate of power transistor 1304, which can represent any of the various semiconductor dies discussed above (e.g., Figure 1(Semiconductor die 102). Control circuit 1302 also controls the actuation inputs of two electromechanical system (MEMS) relays 1306 and 1308, which are arranged along a current path from the input (In) node to the output (Out) node.

[0205] In addition, Figure 13 In this circuit, the source of transistor 1304 is connected to the In node, with MEMS relay 1306 positioned between the source and drain to provide current isolation between the IN and OUT terminals when the relay is in the off state. MEMS relay 1308 is connected between the drain of the transistor and the Out node, completing this path. When placed in the off state (e.g., in response to an overcurrent condition), control circuit 1302 sends a signal to disconnect the transistor and MEMS relays 1306 and 1308, thereby establishing current isolation between In and Out. When conduction between IN and OUT is required (e.g., when the relay is in the on state), MEMS relay 1308 ensures a conduction path with very low resistance, regardless of the transistor's on-state resistance (or voltage drop). The transistor ensures extremely fast response time and the ability to interrupt high DC currents that would otherwise cause degradation (arc formation) in purely mechanical relays. The switching sequence is, for example, to first close relay 1308 (no current flows), then close semiconductor 1304 (which establishes current flow, but without any arc / welding risk, etc.), and finally close relay 1306. This enhances current flow (reduces on-resistance) without any arc / welding risk because current flow has been established and the voltage across relay 1306 is essentially 0V when switched on. This switching sequence can occur much faster than conventional mechanical contactor operation. The disconnecting sequence is the reverse: first, relay 1306 disconnects, diverting current to the channel of semiconductor 1304, preventing arcing at the relay contacts. Semiconductor 1304 then disconnects to stop the current. Due to the semiconductor nature of the described embodiment, this disconnection does not present arcing or other problems. After the current is completely interrupted, relay 1308 disconnects, ensuring current isolation between IN and OUT. This disconnection occurs at 0A current, therefore not causing any arcing or other lifespan degradation issues with the relay. The disconnect sequence can occur much faster than traditional purely mechanical relay types, and the reliability / lifespan is significantly extended compared to purely mechanical relays, especially in terms of the number of disconnect / connect sequences that can be achieved before performance deteriorates adversely. Figure 13The configuration ensures safe, isolated operation because the MEMS relays 1306 and 1308 act as mechanical switches, which physically open or close the contacts, resulting in no electrical continuity between the input and output sides. Furthermore, because the components are integrated into an embedded module, the overall system size is extremely small and deployment is much simpler compared to, for example, non-integrated and / or non-embedded embodiments.

[0206] Power semiconductors (e.g., transistor 1304) can be, for example, embedded elements, external elements attached to the surface of the embedded module, or integrated as processed semiconductor elements in the substrate wafer (e.g., through doping). Similarly, control circuitry 1302 can be embedded elements attached to the surface of the embedded module, or it can be located externally (non-integrated). MEMS relays 1306 and 1308 can be implemented through wafer processing of the embedded wafer, or they can be embedded as dies attached to the surface of the embedded module, or they can be located externally.

[0207] During operation, upon receiving a switching command, if necessary, control circuitry 1302 first maintains the gate voltage to prepare transistor 1304, then actuates MEMS relays 1306 and 1308, sequentially closing their contacts. Thus, MEMS relay 1306 can be configured to shunt current around transistor 1304 for low-loss conduction, while MEMS relay 1308 directs current to the Out node. Opening MEMS relays 1306 and 1308 reverses this process, immediately isolating the path without residual voltage or current leakage due to mechanical disconnection.

[0208] therefore, Figure 13 The embodiments provide high-speed, low-conduction-loss (high-current), and very long-life solid-state relays capable of handling high-voltage DC and providing current isolation with minimal heat generation. The combination of the fast switching of transistors and the mechanical durability of MEMS relays achieves fast on / off times while handling high current and high voltage, surpassing the lifespan of traditional electromechanical relays. Current isolation from MEMS relays prevents high-voltage faults from propagating to the low-voltage control side, thereby enhancing the safety of applications such as electric vehicles or renewable energy inverters. Examples below address... Figures 34 to 36 supply Figure 13 Examples of specific implementations of the circuitry and other exemplary modules including MEMS devices.

[0209] Figure 14This is a top view of a portion 1400 of a wafer used to produce modules, each having four semiconductor dies. Specifically, module 1402 is shown as including four dies 1408, while module 1406 is shown as including four dies 1410. A scribing line 1404 defines a panel in which modules such as modules 1402 and 1406 can be formed. By providing multiple modules arranged in an array on the wafer, parallel / simultaneous processing of multiple modules is possible.

[0210] Figure 15 yes Figure 14 A top view of the entire wafer. Figure 15 An exemplary wafer layout for a 300mm wafer 1500 is shown. Figure 15 In the example, 89 modules or panels with a size of 25mm × 25mm can be mapped to wafer 1500. For example, panels 1502 and 1504 can correspond to... Figure 14 Modules 1402 and 1406 (i.e., providing the construction of modules 1402 and 1406). In Figure 15 In specific examples, for Figure 14 In this layout, each of the four dies, 1408 or 1410, can be constructed as a square element, for example, with each side being 5000 micrometers. Of course, many other sizes and dimensions can be used.

[0211] Figure 16 This is an exemplary implementation demonstrating dual thermal and electrical connections. Figure 16 In this context, the embedded module 1602 represents any of the many module implementations described above, for example... Figure 9 The QFN-compatible module 900b. As discussed above, for example, for... Figure 9 As discussed, the embedded module 1602 can be easily connected to the printed circuit board 1610 at its electrical side 1608, for example, using conventional connection techniques. The embedded module 1602 can also be connected to the heat sink 1606 on its opposing thermal side 1604. Therefore, through... Figure 16 The implementation provides an electrical connection with improved thermal management.

[0212] Therefore, the preceding exemplary embodiments illustrate an embedded module with an electrical surface that can be soldered to a PCB and / or other components. Similarly, lead frames, buses, copper blocks, or similar elements soldered to such embedded modules can themselves be connected to, for example, DC link capacitors, motors, gate driver ICs, or similar components.

[0213] The embedded modules described herein may be partially or completely covered by a dielectric material. Lead frames, buses, copper blocks, or similar components soldered to the electrical surfaces of such embedded modules may protrude from the dielectric material, thereby facilitating electrical connection to the embedded modules.

[0214] Figure 17 This is an alternative exemplary implementation demonstrating dual thermal and electrical connections. Figure 17 In this configuration, embedded modules 1702a and 1702b have solder connections 1704 leading to a heatsink 1706. Connection 1708 connects the embedded modules 1702a and 1702b to a printed circuit board 1710, which may also include any standard components 1714, such as integrated circuits, resistors, capacitors, or inductors. Therefore, Figure 17 The described implementations are shown to be easily scaled up, and in particular, to be effectively combined with each other to take advantage of the benefits provided.

[0215] Figure 18 An exemplary embodiment having multiple cavities is shown. Figure 18 The semiconductor die 1802 includes a gate pad 1804, a source pad 1810, and a drain pad 1816. The gate pad 1804 is connected to the gate contact 1808 through a gate via 1806, the source pad 1810 is connected to the source contact 1814 through a source via 1812, and the drain pad 1816 is connected to the drain contact 1822 through a drain via 1820.

[0216] exist Figure 18 In this embodiment, a semiconductor die 1802 is disposed between a first substrate 1830 having a first cavity 1827 and a second substrate 1836 having a second cavity 1829. The cavities 1827 and 1829 together form a cavity 1834, within which the semiconductor die 1802 is disposed. For example, the cavity 1834 may be an air cavity, or in other embodiments, the cavity 1834 may be filled with a dielectric material or other insulating material.

[0217] As in the earlier embodiments, substrates 1830 and 1836 can be formed using any suitable material, including any semiconductor material such as silicon or GaN. Therefore, cavities 1827 and 1829 and various vias 1806, 1812, and 1820 are directly formed, and substrates 1830 and 1836 are bonded to each other. Figure 18 In this embodiment, cavity 1827 is smaller than cavity 1829 (less deep). However, in other embodiments, cavity 1827 may be larger / deeper than cavity 1829, or cavities 1827 and 1829 may have substantially the same size.

[0218] exist Figure 18 In the example, as can be observed, the gate contact 1808 and the source contact 1814 are located on one surface, while the drain contact 1822 is located on the opposite surface. Therefore, various corresponding types of electrical connections can be made.

[0219] For example, such as Figure 19 As shown, multiple modules 1902, 1904, and 1906 can be joined and deployed together. For example, modules 1902, 1904, and 1906 can be joined and deployed using a common drain contact.

[0220] Figure 20A This is an isometric view of an exemplary embodiment having a cooling block. Figure 20B yes Figure 20A A cross-sectional view of an exemplary embodiment. Figure 20A and Figure 20B In this configuration, multiple thermally conductive through-holes 2014 thermally connect the cooling block 2012 to the embedded die 2008. The cooling block 2012 effectively diffuses the generated heat for placement on another heat sink attached to it. Heat is conducted in the x / y plane for diffusion and in the z direction for placement at the cooling block 2012 and / or other heat sinks / heat exchangers.

[0221] Figure 21 This is a 3D exploded view showing cavity 2114 located at the bottom of cap wafer 2104 and cavity 2112 located at the top of substrate wafer 2102. Electrical connection terminals for source 2106, drain 2108, and gate 2110 are redistributed to the bottom of substrate wafer 2102. Therefore, Figure 21 Provide for Figures 18 to 20B Example assembly and packaging of an embodiment.

[0222] Figure 22 An example of single-metal layer wiring for multiple dies is shown, wherein die 2218 has source pad 2212, which is routed to source platform 2206 via S1 wiring, providing electrical contact with module 2202. Die 2220 also has source pad 2212, which is routed to S platform 2206 via S2 wiring. Similarly, 2218 has a gate, which is routed to G platform 2210 via G1 wiring, while die 2220 has a gate, which is routed to the same G platform 2210 via G2 wiring. Finally, dies 2218 and 2220 have their common drain routed at the bottom of the package, as shown. Figure 22 As shown by the dashed line in the image.

[0223] Figure 23 This is a cross-sectional view of an exemplary dual-cavity embodiment. Figure 23A semiconductor die 2302 is shown, having a gate pad 2304, a source pad 2310, and a drain pad 2316. The gate pad 2304 is connected to the gate contact 2308 via a gate via 2306. The source pad 2310 is connected to the source contact 2314 via a source via 2312. The drain pad 2316 is connected to the metal layer 2318 and thus to the drain contact 2322 via a drain via 2320. Therefore, Figure 23 The module can be connected to other components using any suitable technology, including the components mentioned above, as well as Cu pillars, bond wires, or various other components.

[0224] exist Figure 23 In this configuration, a semiconductor die 2302 is disposed between a first substrate 2330 having a first cavity 2327 and a second substrate 2336 having a second cavity 2329. Cavities 2327 and 2329 together form cavity 2334, and the semiconductor die 2302 is disposed within cavity 2334. For example, as... Figure 18 In this embodiment, cavity 2334 may be an air cavity, or in other embodiments, cavity 2334 may be filled with dielectric material or other insulating material.

[0225] In addition, Figure 23 In this process, RDL 2324 is formed on the surface of the second substrate 2336. Therefore, and with... Figure 18 In contrast, a dielectric or other electrically insulating layer 2332 may be formed on the first substrate 2330, and a metal heat sink 2333 may be connected to the dielectric or other electrically insulating layer 2332.

[0226] exist Figure 23 In the example, the gate via 2306 and the source via 2312 are formed through a relatively thin portion of the second substrate 2336 located between the cavity 2334 and the gate contact 2308 / source contact 2314. Simultaneously, the drain via 2320 is formed through a thicker portion of the second substrate 2336 adjacent to the cavity 2334.

[0227] Metal attachment points 2335 are established to bond the semiconductor die 2302 to layer 2318 and thus to the first substrate 2330, and a second substrate 2336 is connected to the first substrate 2330 and to the semiconductor die 2302. Figure 23 In this context, metal attachment point 2335 is a metal-to-metal connection, but other connections can also be used. When connected to a lead of semiconductor die 2302, metal attachment point 2335 can be called a die attachment point, or when attached to the first substrate 2330 and / or the second substrate 2336, metal attachment point 2335 can be called a substrate attachment point. Figure 23As shown in the figure, cavity 2327 is shallower than cavity 2329, or in other words, cavity 2327 has a first depth that is less than the second depth of cavity 2329. For example, the overall structure of the shallower cavity 2327 and the first substrate 2330 can effectively facilitate heat transfer to the heat sink 2333.

[0228] If possible Figure 23 As observed, semiconductor die 2302 extends beyond cavity 2327 and into cavity 2329. Therefore, given the relative depths of cavities 2327 and 2329, metal attachment point 2335 appears... Figure 23 The exemplary module is located at three different levels or planes: a first level between the drain pad 2316 and the metal layer 2318, a second level between the two substrates 2330 and 2336, and a third level between the gate pad 2304 / source pad 2310 and the gate contact 2308 / source contact 2314. In other words, die attachment of substrates 2330 and 2336 occurs between substrates 2330 and 2336 and die attachment of gate pad 2304 / source pad 2310 / drain pad 2316.

[0229] Figure 24 This is a cross-sectional view of another exemplary dual-cavity embodiment. Figure 24 A semiconductor die 2402 is shown, having a gate pad 2404, a source pad 2410, and a drain pad 2416. The gate pad 2404 is connected to the gate contact 2408 via a gate via 2406. The source pad 2410 is connected to the source contact 2414 via a source via 2412. The drain pad 2416 is connected to the metal layer 2418 and thus to the drain contact 2422 via a drain via 2420. Therefore, similar to... Figure 23 The module, Figure 24 The module can be connected to other components using any suitable technology, including the components mentioned above, as well as Cu pillars, bond wires, or various other components.

[0230] exist Figure 24 In this configuration, a semiconductor die 2402 is disposed between a first substrate 2430 having a first cavity 2427 and a second substrate 2436 having a second cavity 2429. The cavities 2427 and 2429 together form a cavity 2434, such as a composite cavity or a combined cavity, and the semiconductor die 2402 is disposed within the cavity 2434.

[0231] In addition, Figure 24 In this process, RDL 2424 is formed on the surface of the second substrate 2436. A dielectric or other electrically insulating layer 2432 may be formed on the first substrate 2430, and a metal heat sink 2433 may be connected to the dielectric or other electrically insulating layer 2432.

[0232] exist Figure 24 In the example, such as Figure 23 As shown in the diagram, the gate via 2406 and the source via 2412 are formed through a relatively thin portion of the second substrate 2436 located between the cavity 2434 and the gate contact 2408 / source contact 2414. The drain via 2420 is formed through a thicker portion of the second substrate 2436 adjacent to the cavity 2434.

[0233] and Figure 23 Conversely, the cavity 2427 of the first substrate 2430 is larger / deeper than the cavity 2429 of the second substrate 2436. Drain redistribution occurs in part through additional drain vias 2417 and 2419 through the first substrate 2430, as shown in the figure.

[0234] Metal attachment points 2435 are established to bond the semiconductor die 2402 to layer 2418 and thus to the first substrate 2430, and a second substrate 2436 is connected to the first substrate 2430 and to the semiconductor die 2402. Figure 24 In this case, although cavity 2327 is deeper than cavity 2329, heat transfer is facilitated by back metal 2418, which is part of the drain redistribution. For example, back metal 2418 may be close to heat sink 2333 and separated only by electrical insulating layer 2432.

[0235] Figure 25 This is a cross-sectional view of an exemplary single-cavity embodiment on a metal. Figure 25 A semiconductor die 2502 is shown, having a gate pad 2504, a source pad 2510, and a drain pad 2516. The gate pad 2504 is connected to a gate contact 2508 via a gate via 2506, the source pad 2510 is connected to a source contact 2514 via a source via 2512, and the drain pad 2516 is connected to a lead frame 2530 (or other metal element) and thus to a drain contact 2522 via a drain via 2520. The semiconductor die 2502 is disposed between the lead frame 2530 and a substrate 2536 having a cavity 2534.

[0236] In addition, Figure 25 In this configuration, RDL 2524 is formed on the surface of substrate 2536. A dielectric or other electrically insulating layer 2532 may be formed on lead frame 2530, and a metal heat sink 2533 may be connected to the dielectric or other electrically insulating layer 2532.

[0237] exist Figure 25 In the example, such as Figure 23 and Figure 24As shown in the diagram, the gate via 2506 and the source via 2512 are formed through a relatively thin portion of the substrate 2536 located between the cavity 2534 and the gate contact 2508 / source contact 2514. The drain via 2520 is formed through a thicker portion of the substrate 2536 adjacent to the cavity 2534.

[0238] and Figure 23 and Figure 24 Conversely, cavity 2534 is the only included cavity. That is, lead frame 2530 has a flat surface and does not have a cavity. Drain redistribution occurs partially through lead frame 2530, as shown in the figure.

[0239] Metal attachment points 2535 are established to bond the semiconductor die 2502 to the lead frame 2530, and a substrate 2536 is connected to the lead frame 2530 and the semiconductor die 2502. Figure 25 In this process, heat transfer is facilitated by the metal lead frame 2530 and the heat sink 2533.

[0240] Figure 26 This is a cross-sectional view of an exemplary dual-cavity embodiment of silicon bonded to diamond. Figure 26 A semiconductor die 2602 is shown, which has a gate pad 2604, a source pad 2610, and a drain pad 2616. The gate pad 2604 is connected to the gate contact 2608 through a gate via 2606, the source pad 2610 is connected to the source contact 2614 through a source via 2612, and the drain pad 2616 is connected to the metal layer 2618 and thus to the drain contact 2622 through a drain via 2620.

[0241] exist Figure 26 In this configuration, a semiconductor die 2602 is disposed between a first substrate 2630 having a first cavity 2627 and a second substrate 2636 having a second cavity 2629. Cavities 2627 and 2629 together form cavity 2634, and the semiconductor die 2602 is disposed within cavity 2634.

[0242] Metal attachment points 2635 are established to bond semiconductor die 2602 to layer 2618 and thus to first substrate 2630, and second substrate 2636 is connected to first substrate 2630 and to semiconductor die 2602.

[0243] In addition, Figure 26 In this process, RDL 2624 is formed on the surface of the second substrate 2636. Layer 2632 may be made of an electrically insulating material with good thermal properties. For example, layer 2632 may be diamond directly bonded to the first substrate 2630.

[0244] Figure 27This is a cross-sectional view of an exemplary dual-cavity embodiment with a drain-side redistribution layer. Figure 27 A semiconductor die 2702 is shown. The semiconductor die 2702 has a gate pad 2704, which is connected to a gate contact 2708 via a gate via 2706 in a second substrate 2736, a die attachment 2735, and a gate via 2707 in a first substrate 2730. The semiconductor die 2702 also has a source pad 2710, which is connected to a source contact 2714 via a source via 2712 in the second substrate 2736, a die attachment 2735, and a source via 2713 in the first substrate 2730. A drain pad 2716 is connected to a metal layer 2718, thereby connecting to a drain contact 2722 via a drain via 2720.

[0245] exist Figure 27 In this configuration, a semiconductor die 2702 is disposed between a first substrate 2730 having a first cavity 2727 and a second substrate 2736 having a second cavity 2729. The cavities 2727 and 2729 are aligned with each other to form a cavity 2734, and the semiconductor die 2702 is disposed within the cavity 2734.

[0246] exist Figure 27 In this process, RDL 2724 is thus formed on the surface of the first substrate 2730, that is, with the previous Figure 23 , Figure 24 , Figure 25 , Figure 26 Compared to various RDLs 2324, 2424, 2524, and 2624 (as shown in the figure) formed on the top of the module, RDL2724 is formed on... Figure 27 The module shown is located on its bottom. Therefore, a dielectric or other electrically insulating layer 2732 can be formed on the second substrate 2736, and a metal heat sink 2733 can be connected to the dielectric or other electrically insulating layer 2732, i.e., located on... Figure 27 It is located at the top of the module, as shown in the figure.

[0247] Metal attachment points 2735 are established to bond semiconductor die 2702 to layer 2718 and thus to first substrate 2730, and second substrate 2736 is connected to first substrate 2730 and to semiconductor die 2702.

[0248] Figure 28 This is a cross-sectional view of an alternative exemplary dual-cavity embodiment with a drain-side redistribution layer. Figure 28A semiconductor die 2802 is shown. The semiconductor die 2802 has a gate pad 2804, which is connected to a metal layer 2805, a die attachment 2835, and a gate via 2806 in a first substrate 2830, thereby connecting to a gate contact 2808. The semiconductor die 2802 also has a source pad 2810, which is connected to a metal layer 2811, a die attachment 2835, and through a source via 2812 in the first substrate 2830, connecting to a source contact 2814. A drain pad 2816 is connected to a metal layer 2818, thereby connecting to a drain contact 2822 through a drain via 2820.

[0249] exist Figure 28 In this configuration, a semiconductor die 2802 is disposed between a first substrate 2830 having a first cavity 2827 and a second substrate 2836 having a second cavity 2829. Cavities 2827 and 2829 together form cavity 2834, and the semiconductor die 2802 is disposed within cavity 2834. Figure 28 In the various dual-cavity structures described herein, the cavities are not necessarily drawn to scale. For example, in a dual-cavity structure, the deeper cavity may be ten times larger than the shallower cavity (e.g., 150 micrometers, compared to 15 micrometers or less for the shallower cavity). More generally, any suitable size / depth and ratio can be chosen.

[0250] exist Figure 28 Therefore, RDL 2824 is formed on the surface of the first substrate 2830, that is, formed on... Figure 28 At the bottom of the module shown, similar to Figure 27 Examples. However, as shown and described, through-holes in the second substrate 2836 are formed without the need for them. Figure 28 RDL 2824.

[0251] A dielectric or other electrically insulating layer 2832 may be formed on the second substrate 2836. For example... Figure 27 As shown, the metal heat sink 2833 can be connected to a dielectric or other electrically insulating layer 2832, that is, located in Figure 28 It is located at the top of the module, as shown in the figure.

[0252] Figure 29 This is a cross-sectional view of an exemplary dual-cavity embodiment, in which one cavity is formed using a metal substrate and a substrate frame. Figure 29A semiconductor die 2902 is shown, which has a gate pad 2904, a source pad 2910, and a drain pad 2916. The gate pad 2904 is connected to the gate contact 2908 through a gate via 2906. The source pad 2910 is connected to the source contact 2914 through a source via 2912. The drain pad 2916 is connected to the lead frame 2918 and thus to the drain contact 2622 through a drain via 2917 in the first substrate 2930 and a drain via 2620 in the second substrate 2936.

[0253] exist Figure 29 In this configuration, a semiconductor die 2902 is disposed between a lead frame 2918, a first substrate 2930 defining a first cavity 2927, and a second substrate 2936 having a second cavity 2929. Cavities 2927 and 2929 together form cavity 2934, and the semiconductor die 2902 is disposed within cavity 2934.

[0254] More specifically, the first substrate 2930 may be formed as defining a frame (e.g., similar to a picture frame) around the outer periphery of the semiconductor die 2902. As shown, the lead frame 2918 may have a flat surface having a portion located below the first substrate 2930 and supporting the first substrate 2930.

[0255] Metal attachment points 2935 are established to bond the semiconductor die 2902 to the lead frame 2918, and a second substrate 2936 is connected to the first substrate 2930, the semiconductor die 2902 and the lead frame 2918.

[0256] Therefore, in Figure 29 In this process, RDL 2924 is formed on the surface of the second substrate 2936. Layer 2932 may be made of an electrically insulating material (e.g., silicon nitride, such as Si3N4), and heat sink 2933 may be attached to layer 2932.

[0257] Figure 30 This is a cross-sectional view of an exemplary dual-substrate, single-cavity embodiment. Figure 30 A semiconductor die 3002 is shown. The semiconductor die 3002 has a gate pad 3004, which is connected to a metal layer 3005, a die attachment 3035, and a gate via 3006 in a first substrate 3030, thereby connecting to a gate contact 3008. The semiconductor die 3002 also has a source pad 3010, which is connected to a metal layer 3011, a die attachment 3035, and through a source via 3012 in the first substrate 3030, connecting to a source contact 3014. A drain pad 3016 is connected to a metal layer 3018, thereby connecting to a drain contact 3022 through a drain via 3020.

[0258] exist Figure 30 In this embodiment, a semiconductor die 3002 is disposed between a first substrate 3030 and a second substrate 3036 having a cavity 3034. The second substrate 3036 has no cavity and provides a flat surface for connection to the gate contact 3005 and the source contact 3011. The second substrate 3036 may be appropriately thinned to ensure good thermal quality, so that heat is transferred through the electrical insulating layer 3032 and to the heat sink 3033.

[0259] exist Figure 30 In this process, RDL 3024 is formed on the surface of the first substrate 30, that is, formed on the surface of the substrate 30. Figure 30 At the bottom of the module shown, similar to Figure 27 and Figure 28 Examples. However, as shown and described, similar to Figure 28 For example, forming without requiring through holes in the second substrate 3036. Figure 30 RDL 3024. In Figure 30 In this embodiment, the metal attachment point is located on two layers or planes, namely, between the drain pad 3016 and the metal layer 3018, and between the first substrate 3030 and the second substrate 3036, and also includes a gate / source connection, as shown and described.

[0260] Figure 31 This is a cross-sectional view of an exemplary dual-cavity embodiment having a redistribution layer formed between substrates. Figure 31 A semiconductor die 3102 is shown. The die 3102 has a gate pad 3104, which is connected to a die attachment 3135 via a gate via 3106 in a second substrate 3136, and thus to a gate contact 3108. The die 3102 also has a source pad 3110, which is connected to the source contact 3114 via a source via 3112 in the second substrate 3136, through the die attachment 3135, and thus to a drain contact 3116. A drain pad 3116 is connected to a metal layer 3118 via the die attachment 3135 and a drain via 3117, and thus to a drain contact 3122 via a drain via 3120.

[0261] exist Figure 31 In this configuration, a semiconductor die 3102 is disposed between a first substrate 3130 having a first cavity 3127 and a second substrate 3136 having a second cavity 3129. Cavities 3127 and 3129 together form cavity 3134, and the semiconductor die 3102 is disposed within cavity 3134.

[0262] exist Figure 31RDL 3124 is therefore formed on the surface of the first substrate 3130, that is, formed between or in between the first substrate 3130 and the second substrate 3136, as shown. Therefore, a dielectric or other electrically insulating layer 3132a can be formed on the first substrate 3130, and a metal heat sink 3133a can be connected to the dielectric or other electrically insulating layer 3132a, that is, located in... Figure 31 The bottom of the module shown.

[0263] Because RDL 3124 is located in Figure 31 In the middle of the module, a dielectric or other electrically insulating layer 3132b can be formed on the second substrate 3136, and the metal heat sink 3133b can be connected to the dielectric or other electrically insulating layer 3132b, that is, located in the middle of the module. Figure 31 On the top of the module shown.

[0264] Figure 32 This is a cross-sectional view of an exemplary dual-cavity embodiment with integrated passive components. Figure 32 In similar figures described below, for the sake of brevity, many of the various components and elements described are neither listed nor discussed in detail. However, it should be understood that, in practice, any of the foregoing embodiments (e.g., the single-cavity embodiment) may have elements that are replaced or combined in the context of the various embodiments described below.

[0265] For example, in Figure 32 In the figure, gate contact 3208, source contact 3214, and drain contact 3222 form RDL 3224. RDL 3224 includes metal layers 3209a and 3209b connected to gate contact 3208 through gate via 3206, and metal layers 3215a and 3215b connected to source contact 3214 through source via 3212. Figure 32 The embodiments shown include the integration of passive devices, such as capacitor 3217, for example, a MIM capacitor (MIMCAP). Other types of passive devices, such as resistors or inductors, can also be easily integrated.

[0266] Figure 33 This is a cross-sectional view of an exemplary dual-cavity embodiment with integrated active circuitry. That is, similar to... Figure 32 Implementation examples, Figure 33 The embodiment shown includes an active circuit 3301. As shown, the active circuit 3301 can be connected to other circuits (not shown) via terminal 3303, and can be connected to gate contact 3308 and source contact 3314. Therefore, the active circuit 3301 can be connected in the context of RDL 3324 including drain contact 3322.

[0267] Furthermore, the active circuitry 3301 can be readily formed within the substrate 3336, for example, using conventional or future silicon processing / manufacturing techniques. Any suitable and available circuitry may be included. For a concrete example, a gate driver for the power discrete semiconductor die 3302 may be included.

[0268] Figure 34 This is a cross-sectional view of an exemplary dual-cavity embodiment with integrated MEMS technology. Similar to... Figure 32 The gate contact 3408, source contact 3414, and drain contact 3422 form an RDL 3424. The RDL 3424 includes metal layers 3409a and 3409b connected to the gate contact 3408 via a gate via 3406, and metal layers 3415a and 3415b connected to the source contact 3414 via a source via 3412. As shown in the figure... Figure 34 The embodiments illustrate MEMS technology, including various types of MEMS devices.

[0269] Figure 35 This is a cross-sectional view of an exemplary dual-cavity embodiment of an integrated MEMS tube for liquid cooling. That is, Figure 35 Provide more Figure 34 The example shown is a more specific example of MEMS technology. Specifically, Figure 35 Examples include microfluidic heat pipes 3501 and 3503 incorporated for double-sided liquid cooling.

[0270] Figure 36 This is a cross-sectional view of an alternative example dual-cavity embodiment with integrated MEMS technology and / or active circuitry 3601. Specifically, as shown in the figure, Figure 36 It shows something similar to Figure 31 In this embodiment, however, the gate contact 3608 and the source contact 3614 are connected to the MEMS technology / active circuitry 3601. For example, as described above and for... Figure 13 Detailed description Figure 36 The embodiments can be configured to provide fast and reliable solid-state relays.

[0271] Figure 37 This is a cross-sectional view of an exemplary dual-cavity, dual-core embodiment. Figure 37 Semiconductor die 3702a is shown. Semiconductor die 3702a has a gate pad 3704a, a source pad 3710a and a drain pad 3716a. The gate pad 3704a is connected to the gate contact 3708 through a gate via 3706a. The source pad 3710a is connected to the source contact 3714 through a source via 3712a. The drain pad 3716a is connected to the metal layer 3718a through a drain via 3720a and is thus connected to the drain contact 3722.

[0272] exist Figure 37 In this configuration, a semiconductor die 3702a is disposed between a first substrate 3730 having a cavity 3727a and a second substrate 3736 having a cavity 3729a. Cavities 3727a and 3729a together form cavity 3734a, and the semiconductor die 3702a is disposed within cavity 3734a.

[0273] In addition, Figure 37 In this process, RDL 3724 is formed on the surface of the second substrate 3736. A dielectric or other electrically insulating layer 3732 may be formed on the first substrate 3730, and a metal heat sink 3733 may be connected to the dielectric or other electrically insulating layer 3732.

[0274] Figure 37 Semiconductor die 3702b is also shown. Semiconductor die 3702b has a gate pad 3704b, a source pad 3710b and a drain pad 3716b. The gate pad 3704b is connected to the gate contact 3708 through a gate via 3706b. The source pad 3710b is connected to the source contact 3714 through a source via 3712b. The drain pad 3716b is connected to the metal layer 3718b through a drain via 3720b and is thus connected to the drain contact 3722.

[0275] Semiconductor die 3702b is disposed between a first substrate 3730 having cavity 3727b and a second substrate 3736 having cavity 3729b. Cavities 3727b and 3729b together form cavity 3734b, and semiconductor die 3702b is disposed within cavity 3734b.

[0276] Metal attachment points 3735 are established to bond semiconductor dies 3702a and 3702b to layer 3718 and thus to the first substrate 3730, and a second substrate 3736 is connected to the first substrate 3730 and to the semiconductor dies 3702a and 3702b.

[0277] Figure 38 It is possible to use, for example Figure 37 and / or Figures 39 to 50 and / or for example Figures 1 to 13 and / or Figures 23 to 26 A top view of an exemplary embodiment constructed from various exemplary embodiments in the exemplary embodiments of the present invention. Figure 38 Dies 3802, 3804, 3806, and 3808 are shown. As shown, gate connection 3809 connects all dies 3802, 3804, 3806, and 3808 to a common gate contact 3810.

[0278] Similarly, source connection 3811 connects all dies 3802, 3804, 3806, and 3808 to a common source contact 3812. Finally, drain connection 3813 connects all dies 3802, 3804, 3806, and 3808 to a common drain contact 3814.

[0279] As can be understood from the description above, and as shown and described in the various examples below, various connections 3809, 3811, and 3813 can be fabricated using substrate wiring (e.g., using TSV and RDL). Furthermore, dies 3802, 3804, 3806, and 3808 can be included in a compact form, wherein connections 3809, 3811, and 3813 are formed without requiring wire bonding or other conventional connection techniques. Therefore, Figure 38 An example could be a four-die module, which is small and reliable, has good thermal management, and is easy to manufacture. It should also be understood that while a parallel connection of four dies forming a single function switch is shown, many different connections can be formed to create the desired configuration. Such configurations may include, for example, a functional half-bridge, full-bridge, T-type, 6-pack, or anti-series bidirectional blocking configuration including high-side and low-side function switches (each function switch consisting of one or more dies). The foregoing configuration is provided by way of example only, and many other configurations are possible.

[0280] Figure 39 This is a cross-sectional view of an exemplary dual-die embodiment having a substrate with cavities in a metal to provide a common drain connection. Figure 39 In this configuration, the lead frame 3930 serves as a first surface or substrate, and an optional electrical isolation layer 3932 connects the lead frame 3930 to... Figure 39 The remainder of the example is electrically isolated. Cavities 3929a and 3929b are formed in substrate 3936. Therefore, in Figure 39 In this embodiment, the lead frame 3930 provides a common drain connection and can achieve the various advantages of the cavity-containing embodiments described herein by forming cavities 3929a, 3929b in a single substrate 3936 (e.g., a Si substrate) without having to form corresponding cavities in another substrate.

[0281] Figure 40 An exemplary gate / source wiring is shown, while Figure 41 An exemplary gate / source / drain wiring is shown. For example, Figure 40 Similar to Figure 22 Examples, but including additional routing / wiring 4002, 4004. Figure 41 Can be with Figure 22 or Figure 40The embodiments are used together, and example wiring for dies 4102a and 4102b is shown. For example, the source platform 4110 is connected to the source pad 4114 through a via 4112. The drain pad 4122 is connected to dies 4102a and 4102b through a via 4120. The gate platform 4104 is connected to the gate pad 4108 through a via 4106.

[0282] Figure 42 This is a cross-sectional view of an exemplary dual-cavity, dual-die embodiment with a single redistribution layer. Figure 42 In the process, semiconductor dies 4202a and 4202b have a common gate connection 4208. Semiconductor dies 4202a and 4202b have a common source connection 4214. Through metal layers 4218a and 4218b, semiconductor dies 4202a and 4202b have a common drain connection 4222.

[0283] exist Figure 42 In the example, RDL 4224 comprises three metal layers, as shown in the figure. Meanwhile, as already mentioned, the individual metal layers 4218a and 4218b are redistributed to... Figure 42 The upper or top surface of the die is included in the RDL 4224. In other examples, a single drain connection for the two dies 4202a, 4202b may be formed in... Figure 42 At the bottom of the exemplary module, or the drains of the two dies 4202a and 4202b, can be individually routed to the top of the module.

[0284] Figure 43 This is a cross-sectional view of an exemplary stacked module having multiple dual-cavity, dual-die modules. Figure 43 In the examples, each of modules 4300a and 4300b is similar to Figure 42 The module includes a gate connection 4308a in RDL 4324b of module 4300a, which provides a connection to the gate of module 4300a via RDL 4324a. RDL 4324b also includes the gate connection 4308b and the source connection 4314b of module 4300b.

[0285] exist Figure 43 In the example, the redistributed switch node 4322b is included within RDL 4324b, and the switch node 4322b is connected to the drain connection 4318b of module 4300b and the source connection 4314a of module 4300a. The drain connection 4322a within RDL 4324b provides a connection to the drain of module 4300a.

[0286] Figure 44 This is a cross-sectional view of an exemplary stacked module in a half-bridge configuration. Figure 44 Similar to Figure 43 It includes modules 4400a and 4400b, which have separate corresponding gate connections 4408a, 4408b, source connection 4414b, and redistributed switch nodes 4422b.

[0287] However, in Figure 43 In this module, modules 4300a and 4300b each include a dual-substrate and dual-cavity configuration. In contrast, module 4400a is a dual-substrate, dual-cavity module including a first substrate 4430a and a second substrate 4436a, but module 4400b includes a second substrate 4436b and uses module 4400a itself as the lower substrate. Further... Figure 43 In contrast, Figure 44 In this configuration, the drain connection 4422a of module 4400b is not routed to the RDL 4424 of module 4400b. Instead, the drain connection 4422a is configured as the input VDD, while the redistributed switching node 4422b is used as the output, and the source connection 4414b is used as the ground connection. Therefore, it can be observed that... Figure 44 A half-bridge configuration is provided, wherein the positive connection VDD is located on one surface, the negative / ground connection is located on the opposite surface, and the switch node 4422b is located between the two.

[0288] Figure 45 This is a cross-sectional view of an alternative exemplary stacked module in a half-bridge configuration. Figure 45 Similar to Figure 44 This includes modules 4500a and 4500b, each having a separate corresponding gate connection 4508a, 4508b, source connection 4514b (GND), and a redistributed switching node 4522b (OUT). However, in Figure 45 In this case, a lead frame (such as a copper plate) is used instead. Figure 44 The substrate 4430a is used to provide drain connection 4522a (VDD / IN).

[0289] Figure 46 This is a cross-sectional view of a second alternative exemplary stacked module in a half-bridge configuration. Figure 46 Similar to Figure 45 This includes modules 4600a and 4600b, each having a separate corresponding gate connection 4608a, 4608b, source connection 4614b (GND), and a redistributed switching node 4622b (OUT). Figure 45 As in the example, a lead frame (such as a copper plate) is used instead. Figure 44 The substrate 4430a is used to provide drain connection 4622a (VDD / IN).

[0290] However, in Figure 46 In this configuration, modules 4600a and 4600b are provided in a trapezoidal configuration relative to the leadframe / drain connection 4622a. That is, as shown, module 4600a is shorter / smaller than the leadframe 4622a, while module 4600b is shorter / smaller than module 4600a.

[0291] Therefore, although many embodiments in the described exemplary embodiments include bilateral electrical connections, such as Figure 46 Like the example, but Figure 46 The example also provides connection 4646. For example... Figure 47 as well as Figure 48 As shown in the top view, Figure 46 The embodiments enable direct connection of power buses 4702, 4704 and 4706, including the connection of power bus 4704 to connection 4646.

[0292] Figure 48 It shows Figure 47 A top-side view of an exemplary embodiment, wherein the switch node (OUT) bus is attached to the trapezoidal connection, and the VDD and GND buses are attached to the top and bottom surfaces. In this configuration, for Figure 47 The 4804 tap / bus corresponds to Figure 47 Bus 4706 is a bus that corresponds to bus 4704, and bus 4802 corresponds to bus 4702.

[0293] Figure 49 This is a cross-sectional view of an additional exemplary stacked module in a half-bridge configuration. Figure 49 Similar to Figure 45 However, it has Figures 46 to 48 The three-level or top / middle / bottom GND / OUT / VDD connection. Specifically, as shown in the figure, Figure 49 Includes modules 4900a and 4900b, each having a separate corresponding gate connection 4908a, 4908b and source connection 4914b (GND). A lead frame 4922a (e.g., a copper plate) provides a drain connection (VDD / IN). A redistributed switching node 4949 (OUT) is configured as a third power terminal.

[0294] Figure 50This is a circuit diagram for a stacked module in a half-bridge configuration, where the high-side function switch 5000a includes two power semiconductors (transistors) connected in parallel with input 5008a, and the low-side function switch 5000b includes two transistors connected in parallel with input 5008b. The drain of the HS function switch is VDD (or positive DC) terminal 5022a, and the source of the LS is GND (or negative DC) terminal 5014b. The common connection between the HS source and LS drain is switch node 5022b, which serves as the output. For example, in a traction inverter application, VDD is the positive terminal of the battery, GND is the negative terminal of the battery, and OUT is the phase node connected to one of the motor phases. A typical EV motor has 3 phases, each of which can be connected by a transistor in the position shown in the diagram. Figure 50 The half-bridge drive with a similar configuration shown includes HS and LS function switches comprising one or more (any number) semiconductors (transistors) connected in parallel.

[0295] Figure 51 This is a cross-sectional view of a dual-cavity embodiment packaged using a printed circuit board 5104 and a heat sink 5102. Figure 51 Multiple modules 5100a and 5100b are shown sharing a common heatsink 5102, each of which includes multiple dies. Furthermore, modules 5100a and 5100b can be connected to a common PCB 5104 using, for example, any standard assembly technique (e.g., soldering). Additional PCB components 5106 can also be easily included. In one example, three such half-bridge modules are combined, for instance, on a single cooling structure and / or control PCB to form a three-phase traction inverter power stage.

[0296] Figure 52 This is a cross-sectional view of a single-cavity embodiment with alternating gate wiring and junction interfaces. Figure 52 A semiconductor die 5202 is shown, having a sintered material, solder, or similar connection 5215 leading to a metal layer 5218. The semiconductor die 5202 has a gate pad 5204, a source pad 5210, and a drain pad 5216. The gate pad 5204 is connected to a gate contact 5208 via a gate via 5206, the source pad 5210 is connected to a source contact 5214 via a source via 5212, and the drain pad 5216 is connected to the metal layer 5218 and thus to a drain contact 5222 via a drain via 5220.

[0297] exist Figure 52 In this configuration, a semiconductor die 5202 is disposed between a first substrate 5230 and a second substrate 5236 having a cavity 5234. Similar to... Figure 3In an exemplary embodiment, a semiconductor die 5202 is encased within a dielectric 5226, which is disposed within a cavity 5234. Dielectric layers 5233 and 5237 are disposed on each surface of the second substrate 5236.

[0298] Gate connection 5208, source connection 5214, and drain connection 5222 are formed on dielectric layer 5237, thereby defining RDL 5224. Dielectric or other electrically insulating layer 5228 may be formed between first substrate 5230 and metal layer 5218, and lead frame 5232 may be mechanically connected to substrate 5230 on the side opposite to semiconductor die 5202, but not electrically connected to semiconductor die 5202.

[0299] Figure 52 An example is shown in which the bottom assembly 5200a includes a semiconductor die 5202 within a cavity 5234 and associated elements as described above. Meanwhile, the top wafer portion 5200b includes various vias and other connection points, also as described above. The bottom assembly 5200a and the top wafer portion 5200b can be joined and bonded at a bonding interface 5235.

[0300] Metal attachment points 5235 are established to connect the second substrate 2436 to the first substrate 2430 and the semiconductor die 2402. Therefore, in some examples, wafer-to-wafer bonding techniques (such as one or more of the techniques described above) can be used to construct... Figure 52 Examples of implementations.

[0301] In addition, Figure 52 In this embodiment, a wiring layer 5207 is used to route the gate connection 5208 from the gate via 5206 through the source via 5212, such that the gate connection 5208 is located on a different side of the source connection 5214 relative to the source pad 5210, compared to the gate pad 5204. It should be understood that an RDL using one or more metal layers can be used to reorder (redistribute) the order and physical location of the top connections, as illustrated herein.

[0302] Figure 53 This is a cross-sectional view of a single-cavity embodiment having alternating gate and source wiring to accommodate a heat sink 5301. Figure 53A semiconductor die 5302 is shown, having a sintered or soldered or similar connection 5315 leading to a metal layer 5318. The semiconductor die 5302 has a gate pad 5304, a source pad 5310, and a drain pad 5316. The gate pad 5304 is connected to a gate contact 5308 via a gate via 5306, the source pad 5310 is connected to a source contact 5314 via a source via 5312, and the drain pad 5316 is connected to the metal layer 5318 and thus to a drain contact 5322 via a drain via 5320.

[0303] A semiconductor die 5302 is disposed between a first substrate 5330 and a second substrate 5336 having a cavity 5334. The semiconductor die 5302 is encased within a dielectric 5326 disposed within the cavity 5334. Dielectric layers 5333 and 5337 are disposed on each surface of the second substrate 5336.

[0304] Gate connection 5308, source connection 5314, and drain connection 5322 are formed on dielectric layer 5337, thereby defining RDL 5324. Dielectric or other electrically insulating layer 5328 may be formed between first substrate 5330 and metal layer 5318, and lead frame 5332 may be mechanically connected to substrate 5330 on the side opposite to semiconductor die 5302, but not electrically connected to semiconductor die 5302.

[0305] In addition, Figure 53 In this configuration, wiring layer 5307 is used to route gate connection 5308 away from gate via 5306 and source via 5312, while wiring layer 5313 is used to route source connection 5314 away from source via 5312. Therefore, space for heat sink 5301 is created on the surface of dielectric layer 5337. Advantageously, in Figure 53 Therefore, the heat sink 5301 can be positioned directly above the semiconductor die 5302 or otherwise approach the semiconductor die 5302.

[0306] Wafer manufacturing technology can be used to construct Figure 53 An exemplary embodiment of the invention, without requiring wafer-to-wafer bonding. Figure 53 In the example, metal layer 5319 is added on a portion of metal layer 5318 and is coplanar with the platform pad 5304a of gate pad 5304 and the platform pad 5310a of source pad 5310 to maintain planarity for further construction of dielectric layer 5333 and Figure 53 The remaining layers of the example. It should be understood that the heat sink may be attached to both the thermal surface (5332) and the electrical surface (5301). Figure 53The exemplary embodiments described herein achieve double-sided cooling. Similarly, double-sided cooling can be similarly achieved by extension for any embodiments disclosed herein and any embodiments not disclosed herein.

[0307] Figure 54 This is a cross-sectional view of a single-cavity embodiment with alternative gate wiring. Figure 54 A semiconductor die 5402 is shown, having solder connections 5415 leading to a metal layer 5418. The semiconductor die 5402 has a gate pad 5404, a source pad 5410, and a drain pad 5416. The gate pad 5404 is connected to a gate contact 5408 via a gate via 5406, the source pad 5410 is connected to a source contact 5414 via a source via 5412, and the drain pad 5416 is connected to the metal layer 5418 and thus to a drain contact 5422 via a drain via 5420.

[0308] exist Figure 54 In this configuration, a semiconductor die 5402 is disposed between a first substrate 5430 and a second substrate 5436 having a cavity 5434. The semiconductor die 5402 is enclosed within a dielectric 5426, which is disposed within the cavity 5434.

[0309] Dielectric layers 5433 and 5437 are disposed on each surface of the second substrate 5436, wherein dielectric layer 5433 is disposed on insulating layer 5425. For example, dielectric layers 5433 and 5437 may be provided using the same or similar material as the encapsulating dielectric layer 5426.

[0310] Gate connection 5408, source connection 5414, and drain connection 5422 are formed on dielectric layer 5437, thereby defining RDL 5424. Dielectric or other electrically insulating layer 5428 may be formed between first substrate 5430 and metal layer 5418, and lead frame 5432 may be mechanically connected to substrate 5430 on the side opposite to semiconductor die 5402, but not electrically connected to semiconductor die 5402.

[0311] In addition, Figure 54 In this process, a wiring layer 5407 is used to route the gate connection 5408 from the gate via 5406 through the source via 5412, such that the gate connection 5408 is located on a different side of the source connection 5414 than the source pad 5410, relative to the gate pad 5404.

[0312] therefore, Figure 54 It shows a structure similar to Figure 52 Examples but using Figure 53 Examples of construction techniques. That is, silicon manufacturing techniques can be used to construct... Figure 54This is an example of an implementation that does not require wafer-to-wafer bonding.

[0313] Figure 55 This is a cross-sectional view of a single-cavity embodiment with embedded magnetic elements. For example, regarding... Figure 12 As described, various embodiments may include magnetic elements, in Figure 55 The image shows a magnetic element 5502, used in place of a semiconductor die of the type described herein (or as an addition thereof). For example, the magnetic element 5502 may comprise iron, an iron-containing material, or iron powder.

[0314] In addition, Figure 55 In the text, winding 5501 refers to a metal element embedded in a spiral pattern around magnetic element 5502. Figure 55 The remaining elements should be understood as representing non-limiting examples of the embodiments described herein, such that any suitable or desired embodiment of the described embodiments should be understood as being usable in conjunction with magnetic element 5502 and helical winding 5501.

[0315] therefore, Figure 55 For example, a cylindrical iron disk or a trivalent iron disk can be used as a magnetic core and can be positioned within the cavity 5534 of the module, completely encapsulated by an insulating dielectric layer 5526 to ensure electrical isolation while allowing thermal conduction.

[0316] The helical winding 5501 can be formed of a patterned metal layer and wound around the magnetic element 5502 in multiple turns. Figure 55 As not shown, the terminals of the helical winding 5501 can be connected to, for example, die contacts or external package leads to provide electrical access.

[0317] Figure 56 yes Figure 55 A top view of an example. Figure 56 A winding 5501 surrounding a magnetic element 5502 is shown. More specifically, the magnetic element 5502 is shown as a circular disk surrounded by the winding 5501, which is a series of concentric spiral tracks forming an inductive winding around the magnetic element 5502 for magnetic coupling. The spirals 5501 (e.g., copper or aluminum) are shown fanning out from an inner starting point near the edge of the magnetic element 5502 towards an outer terminal. Figure 56 Not shown in the text, but as from Figure 55 Understood, insulating dielectrics can be used to separate winding stages and prevent short circuits.

[0318] Figure 57A It shows Figure 55 and Figure 56 The first exemplary embodiment of the example. In Figure 57AIn this configuration, winding 5701a surrounds magnetic element 5702a, while winding 5702b surrounds magnetic element 5702b. Input 5700a is shown located at the innermost terminal of winding 5701a, while the output of winding 5701a is connected at the outermost terminal 5705 to the input at the outermost terminal 5707 of winding 5702b. Output 5700b is shown located at the innermost terminal of winding 5702b.

[0319] In Figure 57, for example, magnetic elements 5702a and 5702b may be arranged side-by-side in respective cavities, with windings 5701a and 5701b coiled in opposite directions to generate opposing magnetic fields. As shown in the isolated isometric view 5703, flux lines 5703a enter magnetic element 5702a vertically from the bottom (south pole) and similarly exit magnetic element 5702b, resulting in cancellation between magnetic elements 5702a and 5702b, which can be used, for example, in applications such as differential inductors or noise suppression. The spirals 5701a and 5701b allow current to be routed in opposite rotational paths, causing flux arrows 5703a to bend outward from magnetic element 5702a and inward toward magnetic element 5702b, thereby minimizing crosstalk while maintaining isolation through dielectric encapsulation.

[0320] Figure 57B It shows Figure 55 and Figure 56 A second exemplary embodiment of the example. In Figure 57B In the diagram, winding 5701c surrounds magnetic element 5702c, while winding 5702d surrounds magnetic element 5702d. Input 5700c is shown located at the innermost terminal of winding 5701c, while the output of winding 5701c is connected to the input at the innermost terminal 5710 of winding 5702d at the outermost terminal 5708. Output 5700d is shown located at the outermost terminal of winding 5702d.

[0321] As shown in the isolated isometric view 5704, the flux line 5703c enters the magnetic elements 5702c and 5702d vertically from the bottom (south pole) and similarly exits the magnetic elements 5702c and 5702d, thereby generating an additional field that amplifies the mutual inductance for coupled applications (e.g., common-mode chokes).

[0322] Figure 58 It shows Figure 55 and Figure 56 The third exemplary embodiment of the example. Figure 58 An application of an embedded transformer is shown, wherein magnetic element 5802a is surrounded by helical winding 5801a to provide a primary winding, and magnetic element 5802b is surrounded by helical winding 5801b to provide a secondary winding.

[0323] As shown in the corresponding circuit diagram 5800, the transformer can therefore be provided with a primary winding 5804, which has a 2:1 ratio with the secondary winding 5806 to achieve, for example, a desired step-down voltage ratio. Although not shown in... Figure 58 As explicitly shown, but as will be understood from this specification, through-holes can be used at the inner and outer terminals of windings 5801a and 5801b to establish electrical connections. In one exemplary application, the secondary output can be connected to a load resistor via a rectifier diode for DC conversion, thereby providing the desired voltage step within the power module, which can be used in applications such as isolated power delivery in traction inverters. As shown, the shape of the disk described and illustrated above can be essentially cylindrical, or it can be implemented using many other forms. Such forms can include, for example, candy bar shapes, donut shapes, U-shapes, E-shapes, or many other forms. Similarly, it should be understood that multi-layer windings (e.g., in applications such as...) can be implemented. Figure 3 In this embodiment or other embodiments, it is a helix in the form of multiple metal layers (e.g., using vias to appropriately interconnect the layers / windings). Although the winding is shown here as closed in a helical manner around the z-axis, it should be understood that multiple metal layers can also be used and vias can be used to connect the metal layers in the z-axis, thereby realizing windings in the x and / or y-axis, as can be seen from... Figure 12 This is as understood in the examples. Furthermore, inductors, coupled inductors, transformers, matrix transformers, and other magnetic structures can be implemented using the general techniques described herein.

[0324] Figure 59 This is a cross-sectional view of an alternative single-cavity embodiment. Figure 59 A semiconductor die 5902 is shown, having solder connections 5901 leading to a metal layer 5918. The semiconductor die 5902 has a gate pad 5904, which has solder connections 5906 leading to a metal layer 5903. The metal layer 5903 has solder connections 5905 leading to a metal layer 5907, and the metal layer 5907 has solder connections 5909 leading to a gate contact 5908. A source pad 5910 has solder connections 5912 leading to a metal layer 5911, and the metal layer 5911 has solder connections 5913 leading to a metal layer 5915. The metal layer 5915 is connected to the gate contact 5914 via solder connection 5917b. A drain pad 5916 is connected to the metal layer 5918 via solder connection 5901, thereby connecting to the gate contact 5914. Figure 59 The drain contact portion is not shown in the cross-section.

[0325] A semiconductor die 5902 is disposed between a first substrate 5930 and a second substrate 5936 having a cavity 5934. The semiconductor die 5902 is enclosed within a dielectric 5926 disposed within the cavity 5934. Dielectric layers 5931 and 5933 provide isolation for various metal layers 5918, 5903, and 5911, while dielectric layer 5935 electrically isolates the second substrate 5936.

[0326] In addition, Figure 59 In this configuration, back metal 5937 may be attached to the first substrate 5930, and / or back metal 5932 may be attached to the second substrate 5936. Sealing material 5938 may be used to isolate the gate contact 5908 from the second substrate 5936, while sealing material 5940 may be used to isolate the source contact 5914 from the second substrate 5936.

[0327] therefore, Figure 59 A lower or bottom component 5900a, covered by an upper or top component 5900b, is shown. The following describes in detail the method for forming... Figure 59 The examples provided are exemplary techniques, and other examples can also be constructed.

[0328] Figure 60 yes Figure 59 An exemplary top view of an embodiment. Figure 60 In, corresponding to Figure 59 The lower component 5900a and the lower component 6000a are shown as comprising four dies 6002, which may represent SiC or GaN power dies. Corresponding to Figure 59 The upper component 5900b and component 6000b are transparently shown as covering die 6002, and Figure 59 The implementation is consistent with the previous one.

[0329] Source lead 6014 and drain lead 6022 enable parallel current sharing / distribution for high-power applications, such as in a half-bridge configuration. Gate connection 6008 is also shown. Of course, many other layouts are possible.

[0330] Figures 61A to 61G It shows the method for forming Figure 59 Example process of the lower component. In Figure 61A In the process, cavity 6134 is etched in substrate 6130a. Dielectric layer 6128 is deposited, followed by conductive layer 6118a. Figure 61B In the process, the semiconductor die 6102 is soldered to the conductive layer 6118, which includes a gate pad 6104a and a source pad 6110a.

[0331] exist Figure 61C In the process, an electrically insulating / dielectric material 6126a is deposited, for example, excluding molding compound. In Figure 61D In the process, grinding and polishing are performed to provide a planar surface having dielectric material 6126, conductive layer 6118, gate pad 6108, source pad 6114 and conductive layer 6118.

[0332] exist Figure 61E In this process, the glass 6140 (or tape or other suitable material) can be bonded to the assembly using an adhesive layer 6138. In this way, the substrate 6130a is thinned to obtain a thinned substrate 6130. Chemical etching can be performed on the back side of the wafer to reduce grinding stress and prepare the surface for back-side metal deposition. Then, back-side metal 6132 can be added. Therefore, as... Figure 61G As shown, the glass 6140 can be removed to obtain the bottom component 6100.

[0333] Figures 62A-62D It shows the method for forming Figure 59 Example process of the upper component. In Figure 62A In this substrate 6236a, a dielectric layer 6235 is formed thereon. Figure 62B In this process, a patterned metal layer including metal layers 6211 and 6233 is added, which (e.g., can be obtained from...) Figure 59 (What is understood) can be used to Figure 61G The source / gate connection of the lower component 6100. Then, as shown, an electrical insulating layer 6233 can be added.

[0334] exist Figure 62C In this process, tape or glass 6240 is added to allow for the flipping and thinning of substrate 6236a. For example... Figure 62D As shown, after this thinning to obtain the thinned substrate 6236, a back metal layer 6232 can be added. Not shown separately, mounting tape and the associated frame can be applied, followed by debonding and cutting using a suitable encapsulation / underfill material for mounting (e.g., soldering). Figure 59 or Figure 61G On the lower component.

[0335] therefore, Figure 59 , Figure 60 , Figures 61A to 61G and Figures 62A to 62D The diagram generally illustrates that any desired die or other component can be bonded within the cavity of a first (bottom) wafer, and the wafer can be thinned, with back metal applied if desired. A second (top) wafer, constructed from a single-layer RDL (or more), can be thinned, and may also be provided with back metal if desired. The second wafer can then be diced, and the resulting diced chips can be bonded to the first wafer. Leadframe attachment and final sealing can then be completed to achieve, for example... Figure 60 An exemplary package.

[0336] Many variations of the resulting module are possible. For example, the second wafer and thus the diced wafers may have active devices mounted therein or on it. Similarly, temperature sensors (e.g., negative temperature coefficient (NTC) sensors or the like) and / or passive elements may be mounted on either or both of the first or second substrate.

[0337] Many processing variations are also possible. For example, one or two wafers can be thinned, and one or both sides of the module can have back metal. For example, the use of thinning / back metal can be selected to facilitate mechanical stress / bending control, as well as reliability in high temperatures and thermal cycling.

[0338] Figures 63A-63J An example process for forming an alternative embodiment with metal pillars is shown. Figure 63A In the process, the first or bottom / lower substrate 6330a (wafer) is cleaned, and a dielectric layer 6328 is formed thereon. Then, a metal layer 6318 is deposited on the dielectric layer 6328. Figure 63B In this process, metal pillars 6319 are formed (e.g., electroplated) on metal layer 6318. As described and shown below, the metal pillars 6319, in conjunction with metal layer 6318, effectively provide cavity 6334. Thus, for example, the height of metal pillar 6334 can be selected as the height of the semiconductor die or other element to be included within cavity 6334.

[0339] exist Figure 63C In this process, a semiconductor die 6302, having a gate pad 6304, a source pad 6310, and a drain pad 6316, is connected to a metal layer 6318 via solder bonding 6317 (or sintering bonding). Then, an electrically insulating material 6326a, such as silicon oxide or an oxide / nitride, is provided. Figure 63C In the process, etching is performed to form the electrical insulating layer 6326 and the ends 6327 of the metal pillars 6319, while exposing the gate pad 6304 and the source pad 6310. Thus, the bottom or component 6300a is formed.

[0340] exist Figure 63E In the middle, the second or top / upper wafer 6336a is cleaned, and a dielectric layer 6315 is formed thereon. For example... Figure 63F As shown, for example in a wafer-to-wafer bonding process, the second wafer 6336 can then be flipped and mounted onto the bottom assembly 6300a. As shown, a portion of the cavity 6334 can remain open or inflated. In the event of a future underfill process during subsequent dicing, the pillar 6319 can be formed without wrapping around the semiconductor die 6302, and the metal pillar 6319 is recessed from the outer edge of the module so as not to extend into the dicing channel.

[0341] exist Figure 63G In this process, the second wafer 6336a is thinned to provide a thinned second substrate 6336. Then, a gate via 6306 is formed to establish a gate contact 6308, a source via 6312 is formed to establish a source contact 6314, and a drain via 6320 is formed to establish a drain contact 6322. Thus, an RDL 6324 is established.

[0342] exist Figure 63H In the middle, attach adhesive tape 6340 (or glass adhesive), such as Figure 63I As shown, this thins the back side of the first substrate 6330a to obtain a thinned first substrate 6330. A metal layer 6332 can then be formed, for example, by sputtering or electroplating, wherein the metal layer 6332 can be patterned or uniform (e.g., depending on the cutting method to be used). Finally, in Figure 63J In this process, saw 6344 or other cutting methods can be used in conjunction with mounting belt 6342 to separate module 6300(1) and module 6300(2).

[0343] Figure 64 This is a cross-sectional view of an example embodiment having a heat sink 6404 formed in a through-hole 6402. (See also...) Figure 64 As shown, the additional heat sink 6404 can be formed as a dummy metal post in the through hole 6402. The through hole 6402 can be formed Figure 64 Other through-holes in the module are formed during this process, for example, simply by modifying a mask that has already been used to form the existing through-holes. Therefore, the heatsink 6404 can be formed at any desired location.

[0344] Figure 65 An example process flow for forming a cavity that can be used with various embodiments is shown. Figure 65 In process 6500a, a resist 6504 is provided to wafer 6502, and the resist 6504 is applied, exposed and developed to define an opening 6505.

[0345] Then, in process 6500b, a combination of anisotropic and isotropic reactive ion etching (RIE) processes can be performed to etch the cavity 6506 having inclined sidewalls 6508. The shape of the cavity can be controlled by changing process parameters (e.g., gas flow, pressure, power, bias voltage, or others). Finally, in process 6500c, after removing the resist 6504, a second RIE process is performed to smooth the inclined sidewalls 6508 after resist removal.

[0346] Therefore, the sidewall 6508 has a smooth and gradually sloping shape suitable for dielectric and metallic coverage, and can be used in any of the embodiments described herein.

[0347] Figure 66 This is a first flowchart illustrating an example embodiment. Figure 66 The illustrated example embodiment includes: providing a semiconductor die on a substrate, the semiconductor die having at least a first contact portion on a first side and at least a second contact portion on a second side opposite to the first side (6602), and sealing the semiconductor die with a dielectric sealing material (6604). Figure 66 Example embodiments further include forming a through-hole (6606) in the dielectric sealing material and forming a redistribution layer on the dielectric sealing material that is connected to the first contact and the second contact through the through-hole (6608).

[0348] Figure 67 This is a second flowchart illustrating an example embodiment. Figure 67 The exemplary embodiment shown includes: providing a semiconductor die (6702) on a first substrate and forming a cavity in a second substrate, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth (6704). Figure 67 Example embodiments further include attaching the second substrate to the first substrate (6706) through the second portion of the second substrate and with the semiconductor die disposed within the cavity, forming a through-hole (6708) through the first portion of the second substrate, and providing a contact portion on the second substrate, wherein the contact portion is electrically connected to the semiconductor die (6710) through the through-hole.

[0349] Figure 68 This is a third flowchart illustrating an example embodiment. Figure 68 The illustrated example embodiment includes: forming a cavity (6802) in a substrate, providing a magnetic element (6804) in the cavity, and providing a metal winding on the substrate, the metal winding surrounding the magnetic element (6806). Figure 68 Example embodiments further include sealing the magnetic element and the metal winding with a dielectric sealing material (6808) to form a through hole (6810) in the dielectric sealing material, and electrically connecting the contact portion to the metal winding (6812) through the through hole.

[0350] Figure 69 This is a fourth flowchart illustrating an example embodiment. Figure 69 The illustrated example embodiment includes forming a metal layer (6902) on a first substrate, providing metal pillars on the metal layer to define a cavity (6904), and providing a semiconductor die in the cavity, wherein a first surface is provided on the metal layer (6906). Figure 69 Example embodiments further include sealing at least a portion (6908) of a semiconductor die (including a second surface thereon opposite the first surface) and a metal pillar with a dielectric sealing material, and forming a second substrate (6910) on the dielectric sealing material and the metal pillar. Figure 69 Example embodiments further include forming a through-hole (6912) through the second substrate, and forming a redistribution layer on the second substrate, wherein the redistribution layer is connected through the through-hole to at least one of the first surface of the semiconductor die, the second surface of the semiconductor die, and the metal pillar (6914).

[0351] Therefore, as described herein, example embodiments may include devices embedded in a substrate to provide thermal diffusion, thermal expansion coefficient compatibility, lower package thermal / resistance, and other electrical or thermal properties. Devices may include semiconductor dies, packaged electronic devices, or multi-chip modules, and the substrate may include a semiconductor substrate. Devices and substrates may include silicon, silicon carbide, GaN, GaaS, other wide-bandgap materials, hybrid materials, or any other electronic / semiconductor material. The substrate may include one or more through-holes for electrical connection to one or more electrical interconnects on the device.

[0352] The device may include MOSFETs, IGBTs, or other power, sensor, processor, or other integrated circuits. The device may include one or more electrical interconnects, such as gates, sources, drains, other signaling, or dummy circuits, on the top and / or bottom main surfaces. The substrate includes one or more blocks integrated to form a larger substrate block having cavities, caps, top, and bottom surfaces. The substrate includes one or more redistribution layers on the top and / or bottom surfaces, wherein the RDL includes one or more exposed external electrical interconnect surfaces.

[0353] Non-conductive materials can be used for devices within a mounting cavity. Devices can be attached to a substrate, RDL, or vias using conductive materials. The cover wafer / substrate / assembly and / or RDL may include conductive and non-conductive layers. The substrate and / or device may include one or more patterned layers to form circuits, blind vias, and / or vias, and / or the substrate and / or device may include one or more electrical interconnects, including one or more wire bonds, clips, diffusion bonds, pillars, or combinations thereof. Non-conductive metal layers may include, for example, gold, silver, aluminum, titanium, nickel, TiW, copper, nickel-vanadium, or any combination or alloy thereof.

[0354] Various example embodiments may include arrays comprising one or more of the means described above. Various example embodiments may include methods for manufacturing the device or an array thereof and / or methods for assembling the device or an array thereof. Various example embodiments may include: an electric power system comprising one or more of the device or an array thereof, a traction motor system comprising one or more of the device or an array thereof, and / or a multiphase motor system comprising one or more of the device or an array thereof.

[0355] Example embodiments include those having a single silicon element (e.g., having a cavity) on top of a metal plate. Such embodiments may include a single device or multiple devices connected in parallel (e.g., having directly connected drains).

[0356] Embodiments may include one cavity per device or one cavity per die. A different number of cavities (of different sizes) may exist in the lower / bottom assembly compared to the upper / top assembly. One or more cavities in the lower / bottom assembly substrate may differ in depth from one or more cavities in the upper / top assembly. Different cavities in a single substrate may have different depths (e.g., to accommodate dies of different thicknesses), including cavities extending the depth completely through the substrate(s). One or more cavities may exist only in one of the lower / upper assemblies.

[0357] As described above, for example, using RDLs and through-holes (e.g., TSVs), electrical insulation and thermal conduction can be provided on one side of the example module, while all electrical conduction / connection is provided on the opposite side of the module. For example, the upper / top surface can provide electrical connections, while the lower / bottom surface provides thermal conduction, and vice versa. In other examples, the top or bottom can be conductive on a portion of the surface area, while another portion is electrically insulating (but thermally conductive), thus allowing partial double-sided cooling.

[0358] In an example embodiment, the signal is redistributed along the top surface of the lower / bottom substrate, wherein the upper / top substrate is recessed to provide electrical connection while achieving electrically insulating double-sided cooling. Alternatively, redistribution may occur along the bottom of the upper / top substrate.

[0359] The spacing of power discrete components in the substrate can be designed to optimize heat generation, heat diffusion, and / or thermal characteristics.

[0360] The embedded active circuitry can be in either or both of the top and bottom substrates. One of the top and bottom substrates may be recessed to provide an exposed intermediate surface for connection. The active circuitry may be included in a second embedded die, which is interconnected to the first embedded die via multiple redistribution layers.

[0361] The example embodiments provide the ability to interfacially bond one or two substrates to different materials, for example, to achieve thermal conduction while maintaining electrical insulation. For instance, direct bonding of silicon to diamond can be provided.

[0362] In some examples, chemical vapor deposition (CVD) diamond may be used. In some examples, the insulator used may be electrically insulating and highly thermally conductive. For example, such an insulator may include Si3N4 or CVD diamond.

[0363] In some examples, one or more cooling elements may be used, which may include thermoelectric coolers (TECs), heat sinks, or LTCC (low-temperature co-fired ceramic) cavities (hollow spaces created within a multilayer LTCC substrate; used to fabricate high-performance passive components such as filters and antennas). In this context, LTCC technology refers to a method of fabricating multilayer circuits based on a ceramic substrate. Example LTCC devices may include multiple dielectric layers, low-loss conductors screen-printed or optically imaged, embedded baluns, resistors and / or capacitors, and vias for interconnecting multiple layers. Other examples include thin-film substrates with microfluidic channels, flexible thermoelectric generator (TEG) cooling, one or more microfluidic channels (on any desired / available side of the device), liquid cooling, heat exchangers (e.g., evaporative heat exchangers), and / or air / refrigerant flow.

[0364] Various techniques can be used to connect two or more of the aforementioned cooling elements or portions thereof. For example, techniques and / or connecting components may include thermal clamps, through-hole and / or through-silicon vias (TSVs), thermal adhesives, heat rods, heat pipes, sintering, or welding.

[0365] Example embodiments may include conductive redistribution terminals soldered to a PCB using standard PCB manufacturing / assembly techniques and techniques such as soldering (e.g., reflow soldering and / or wave soldering). In other embodiments, such terminals may be soldered, welded, bolted, or otherwise connected (e.g., mechanically and electrically connected using ACA bonding) to any conductive conduit, such as a PCB, busbar, or the like.

[0366] Example embodiments may include embedded MEMS technology in one or both of the top / bottom substrates and / or in separate embedded dies. For example, MEMS technology may be integrated with power discrete dies (e.g., SiC or GaN power FETs), or may be further integrated with embedded active circuitry in one or both substrates. For example, MEMS technology and active circuitry may be embedded in one substrate, or there may be one substrate for MEMS and one substrate for analog / digital / mixed-signal ICs.

[0367] In example embodiments, semiconductor switching devices can be embedded / integrated in parallel with MEMS relays / contaminants (or multiple relays connected in series), allowing the semiconductor to establish and disconnect connections (without arcing), while the MEMS relays / contaminants can achieve very low (mechanical contact) resistance in the on-state. In one example embodiment, the MEMS relays / contaminants are connected in series with the semiconductor and provide electrical isolation in the off-state. In one example embodiment, the semiconductor has a parallel MEMS relay / contaminant and another MEMS relay / contaminant connected in series to achieve all the functions of a solid-state high-speed relay / contaminant with high DC voltage capability. In one example embodiment, MEMS technology may include microfluidics that allow liquid cooling of the module without the need for an external liquid cooling heatsink.

[0368] Example embodiments include embedded integrated passive devices (IPDs), such as MIMCAPs, for example, using multiple metal wiring layers / RDLs or other standard Si processes. Other types of integrated capacitors (such as MOSCAPs), as well as inductors and resistors, may be included. Such components may be in the lower / bottom and / or upper / top substrate, or in a second embedded die.

[0369] Redistributed routing with geometry / impedance control can be provided (manually or automatically). For example, a routing / terminating impedance target of 50 ohms or similar can be matched. Thus, specific propagation delay targets can be achieved, or the redistributed inductance / impedance of two paths / connections (such as parallel power semiconductors) can be matched. For example, automatic routing of an RDL that achieves a specified impedance target can be provided. In example embodiments, other implementations of machine learning (ML) and / or artificial intelligence (AI), such as generative AI, can be used for optimization and / or automation for specific targets (e.g., the size, cost, or number of metal layers).

[0370] Two or more dies may be embedded in a single substrate sandwich layer. Two or more power discrete dies may be connected in parallel via substrate redistribution wiring. Multiple devices or multiple sets of parallel devices may be present in a half-bridge configuration. For multiphase systems (e.g., 3-phase or 6-phase traction inverters), multiple devices or multiple sets of parallel devices / half-bridges forming 6 or higher half-bridge counts may be present. Different dies may be present for different purposes and made of different materials (such as SiIC dies embedded with SiC and / or GaN transistors). Such dies may have different thicknesses.

[0371] Each cavity can have one die or multiple dies in a single cavity. Each cavity in one substrate can have multiple dies, while each cavity in another substrate can have a single die. Two or more modules can be combined in an array (horizontally), or two or more modules can be stacked vertically to form a multilayer system. Modules using, for example, four, three, or two silicon substrates stacked vertically can exist. A "trapezoidal" implementation can exist, where one level is the POS terminal (VDD) of a half-bridge, the next level is the OUTPUT (switching node), and the top level is the NEG terminal (GND, Rtn). In other examples, the terminals can be in a different order.

[0372] Electrical wiring can be provided in either the middle layer or the top / bottom surfaces of the module, where the thermal interface (and electrical isolation) is partially or completely on one or both surfaces of the module. Vertically stacked "N" layers are possible. An example module can be electrically configured as a half-bridge configuration, with the positive terminal on one surface, the output in the middle, and the negative terminal on the other surface.

[0373] In the example embodiment, the finished module itself can be considered as a basic device and can be embedded or nested within a larger module.

[0374] As described above, various embodiments (single die, multiple die, multiple stacks) can be combined. Combining multiple dies, chips, modules, and systems (horizontally and / or vertically) allows for the formation of fully integrated, miniaturized systems. For example, such systems may include multiple power discrete dies (e.g., WBG devices such as SiC or GaN power transistors), MEMS relays, nanotubes (microfluidics), temperature sensors, drivers for power discrete operations, and other analog, digital, and mixed-signal ICs and / or passive devices (IPDs) for filtering functions, decoupling, local energy storage, and current limiting.

[0375] In a more specific example, a fully integrated, miniaturized traction motor driver for integration into a motor can be provided, including a power stage with driver, current sensing, feedback (shaft / rotor position), PWM generation, motor drive / control, filtering, decoupling, and local energy storage, as well as protection, where such protection may include temperature derating, overcurrent protection, short-circuit protection, or power rail electronic fuses (e.g., for an ultra-fast high-voltage DC circuit breaker with electrical isolation).

[0376] Small size can be achieved through higher switching frequencies (e.g., above 20 kHz) and multiple cooperating (low current) modules, such as combining advanced inverter topologies like multilevel (e.g., hybrid switched capacitor [HSC], flying capacitor multilevel [FCML], or similar).

[0377] Example embodiments may have a final total finished product thickness of less than, for example, 875 μm, which allows processing on standard wafer processing equipment.

[0378] The described techniques can be used to replace wire bonding and other conventional interconnect technologies in any context and are well-suited for power applications due to improvements in electrical and thermal properties, such as those described herein. The described techniques can be performed using standard semiconductor processing, such as photolithographic patterning, and can also utilize solder or polymer spraying, or screening through a metal mask.

[0379] In some embodiments, welding can be or can include a process of joining two surfaces (e.g., metal surfaces) together using a molten filler metal (e.g., a metal alloy, tin (Sn), lead (Pb), silver (Ag), copper (Cu)), which may be referred to as solder.

[0380] In some embodiments, sintering can be or can include a process of fusing particles together into a solid mass without melting the material using, for example, a combination of pressure and / or heat. In some embodiments, sintering can include agglomerating a material (e.g., a powder material) into a solid or porous substance by heating the material and typically also compressing it without dissolving it. In some embodiments, materials that can be used for sintering can include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some embodiments, sintered bonds can have desired electrical and / or thermal conductivity, durability, and a relatively high melting temperature.

[0381] In some embodiments, one or more of the components described herein may be coupled using materials such as solder, sintered (e.g., silver, copper) materials and / or other metal-to-metal type bonding materials.

[0382] In some implementations, coupling of components can be performed using, for example, welding processes, sintering processes (e.g., silver sintering, copper sintering) and / or other metal-to-metal bonding processes.

[0383] In some embodiments, the direct-bonded metal (DBM) substrate (e.g., direct-bonded copper (DBC)) may include an insulating layer disposed between the first metal layer and the second metal layer. The insulating layer may be, for example, a ceramic layer. In some embodiments, the insulating layer may be or may include a ceramic material, such as alumina (Al2O3) or aluminum nitride (AlN).

[0384] In some embodiments, the DBM substrate can be formed by bonding one or more metal layers (e.g., a first metal layer, a second metal layer) to an insulating layer. In some embodiments, one or more metal layers can be bonded to the insulating layer using, for example, a high-temperature process.

[0385] In some embodiments, the first metal layer and / or the second metal layer of the DBM substrate may be, or can be used as, a heat sink. In some embodiments, the first metal layer and / or the second metal layer may be coupled to a heat sink. In some embodiments, at least a portion of one or more of the first metal layer or the second metal layer may be exposed by a molding material.

[0386] In some embodiments, the first and / or second metal layers of the DBM substrate may be or may include patterned metal layers, which include one or more conductive lines. In some embodiments, the first and / or second metal layers may be or may include patterned layers configured to form one or more circuits, one or more conductive blind vias and / or through-holes, etc.

[0387] In some embodiments, the DBM substrate may be or may include a direct-bonded copper (DBC) substrate (e.g., a DBM having a copper metal layer). In some embodiments, such as in a DBC substrate embodiment, the first metal layer and / or the second metal layer is a copper layer.

[0388] In some embodiments, one or more semiconductor dies (e.g., one or more semiconductor components) may be or may include power semiconductor dies. In some embodiments, one or more semiconductor dies may be (e.g., a portion thereof) or may include one or more of the following: metal-oxide-semiconductor field-effect transistor (MOSFET) devices, insulated-gate bipolar transistors (IGBTs), integrated circuits (ICs), inverters, power conversion circuits, bridge circuits, fast recovery diodes (FRDs), diodes, etc. In some embodiments, one or more semiconductor dies may be (e.g., a portion thereof) or may include components for electric vehicles (EVs).

[0389] The embodiments described herein may include more than one semiconductor die. In some embodiments, different semiconductor dies may be fabricated using different semiconductor substrates (e.g., silicon carbide (SiC) substrates, silicon (Si) substrates, gallium nitride (GaN) substrates) (when more than one semiconductor die is included in some embodiments). In other words, different semiconductor dies may be fabricated, for example, on different semiconductor wafers or materials. This may be referred to as a hybrid die configuration. For example, a first semiconductor die may be formed using a SiC substrate, and a second semiconductor die (separate from the first semiconductor die) may be formed using a silicon substrate. As another example, an IGBT may be fabricated using a SiC substrate, while the controller may be fabricated using a silicon substrate.

[0390] In an example implementation, the first semiconductor die can be connected to the second semiconductor die, for example, via an electrical connection (e.g., wire bonding, electrical clamp) extending directly from the first die to the second die, or via a wiring connection formed in a first conductive layer (e.g., a metal layer) of the electronic power substrate. The first of a plurality of semiconductor dies can also be connected to a leadframe post via an electrical connection such as a wire bond or clamp.

[0391] In example embodiments, the package (e.g., a power module) may be a hybrid device package comprising a semiconductor die or multiple semiconductor dies integrated onto an integrated electronic power substrate (e.g., a ceramic substrate, a DBM or DBC substrate, an AMB substrate). In some embodiments, multiple semiconductor devices (e.g., fabricated on the same substrate such as a SiC substrate) are suitable for high-power applications.

[0392] Although referred to as a leadframe in at least some parts of this detailed description by way of example, a leadframe may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that can provide a connection point to the outside of the package. Therefore, a leadframe may be referred to as a conductive portion of the package.

[0393] In some implementations, one or more portions of the leadframe may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate.

[0394] The semiconductor device package described herein may include multiple signal terminals. These signal terminals may be power terminals, input signal terminals, output signal terminals, etc. In some embodiments, the multiple signal terminals may be included in a lead frame. In some embodiments, the lead frame may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that provides an external connection point to the package. Therefore, the lead frame may be referred to as a conductive portion of the package or assembly. In some embodiments, one or more portions of the lead frame may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate and / or the semiconductor die.

[0395] In some embodiments, the molding compound (e.g., molding material or molding compound, encapsulation material) may be or may include a non-conductive layer / material. In some embodiments, the molding compound is a non-conductive material, such as epoxy resin, which can be formed (applied, etc.) using transfer molding or compression molding processes. In some embodiments, the molding compound may include a separate plastic housing that is included in a semiconductor device assembly.

[0396] One or more bonding wires, including those in at least some of the embodiments described herein, may be replaced by conductive components. For example, in some embodiments, one or more bonding wires may be replaced by conductive clamps. Conductive clamps may be coupled to another component (e.g., attachment pads, lead frames, semiconductor dies, etc.) using, for example, solder (e.g., welding processes), sintering coupling (e.g., sintering processes), welding, etc. In some embodiments, one or more bonding wires and / or clamps may serve as input and / or output power terminals, signal terminals, power terminals, etc.

[0397] In some implementations, one or more semiconductor dies associated with the implementations described herein may be embedded within a layer (rather than surface-mounted). For example, one or more semiconductor dies may be disposed within a recess (or cavity) of a layer (e.g., a substrate, printed circuit board, conductive layer, insulating layer).

[0398] In some implementations, a module (e.g., a package including a semiconductor device) may be included within another module. A module may be referred to as a package. For example, one or more modules may be one or more sub-modules included within another module. In other words, a first module may be included as a sub-module within a second module.

[0399] In some embodiments, the spacer material may be epoxy resin, silicone adhesive, conductive material, non-conductive material, organic material, semiconductor material, metal alloy, metal foam, phase change material, etc.

[0400] In this specification, the semiconductor die that can be used can be any of a variety of semiconductor dies, including, by way of non-limiting example, power semiconductor dies, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), hybrid devices, rectifiers, random access memory, high electron mobility transistors, image sensors, wide-bandgap (WBG) semiconductor devices, hybrid devices, or any other semiconductor die / device type. Any of a variety of semiconductor substrate types can be used to package the semiconductor die using the semiconductor package designs disclosed herein, including, by way of non-limiting example, silicon, silicon carbide, gallium arsenide, gallium nitride, silicon on insulator, ruby, sapphire, or any other semiconductor material type. A wide variety of semiconductor package configurations can be formed using the principles disclosed herein.

[0401] It should be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to may be referred to in this way. The claims of this application, if possible, may be modified to refer to the exemplary relationships described in the specification or shown in the drawings.

[0402] As used in the specification and claims, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations depicted in the drawings, spatial relative terms (e.g., above, over, upper, below, under, lower, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, the term proximity may include lateral proximity or horizontal proximity.

[0403] Various semiconductor processing and / or packaging technologies can be used to implement certain implementations. Various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC), can be used to implement certain implementations.

[0404] Various example implementations are provided in the following list.

[0405] 1. A semiconductor package, comprising: substrate; A semiconductor die, the semiconductor die being disposed on the substrate and having at least a first contact portion on a first side and at least a second contact portion on a second side opposite to the first side; A dielectric sealing material that seals the semiconductor die and has a through-hole formed therein; and A redistribution layer is formed on the dielectric sealing material and connected to the first contact portion and the second contact portion through the through-hole.

[0406] 2. The semiconductor package according to Example 1 further includes a conductive layer electrically connected to the second contact and disposed between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer through at least one of the vias.

[0407] 3. The semiconductor package according to Example 1, wherein the substrate is electrically isolated from the semiconductor die by the dielectric sealing material.

[0408] 4. The semiconductor package according to Example 1, wherein the semiconductor die is disposed on a first surface of the substrate, and the semiconductor package further includes a heat sink disposed on a second surface of the substrate opposite to the first surface of the substrate.

[0409] 5. The semiconductor package according to Example 1, wherein the second contact of the semiconductor die is electrically connected to the substrate.

[0410] 6. The semiconductor package according to Example 1 further includes: An insulating layer, formed on the dielectric sealing material and the redistribution layer, the insulating layer having a second through-hole formed therein; and A second redistribution layer is formed on the insulating layer and connected to the redistribution layer through the second through-hole.

[0411] 7. The semiconductor package according to Example 1 further includes a cavity formed in the substrate, wherein the semiconductor die is disposed within the cavity.

[0412] 8. The semiconductor package according to Example 1 further includes: The second substrate is formed of a semiconductor material and disposed on a dielectric sealing material. The second substrate has a second through-hole formed therein. The redistribution layer is formed on the second substrate and connected to the first contact portion and the second contact portion through the through-hole and the second through-hole.

[0413] 9. The semiconductor package according to Example 1 further includes: A second semiconductor die is disposed on the redistribution layer; A second dielectric sealing material is formed on the redistribution layer and seals the second semiconductor die, the second dielectric sealing material having a second through-hole formed therein; and A second redistribution layer is formed on the second dielectric sealing material and is connected to the semiconductor die through the via and the second via, and is connected to the second semiconductor die through the second via.

[0414] 10. The semiconductor package according to Example 1 further includes: The second substrate is formed of a semiconductor material; The second semiconductor die is disposed on the first side of the second substrate facing the semiconductor die; A second dielectric sealing material, wherein the second dielectric sealing material at least partially seals the second semiconductor die; The second through hole is formed through the second dielectric sealing material, wherein the semiconductor die and the second semiconductor die are connected through the second through hole; A third through-hole is formed through the second dielectric sealing material and through the second substrate; A fourth through-hole, the fourth through-hole being formed through the second substrate; and The second redistribution layer is formed at least partially on a second side of the second substrate opposite to the first side of the second substrate, and is connected to the redistribution layer and the second semiconductor die through the second via, the third via and the fourth via.

[0415] 11. The semiconductor package according to Example 1 further includes: A second through-hole is formed through the substrate; and A conductive layer is formed on the substrate and connected to the semiconductor die through the second via.

[0416] 12. The semiconductor package according to Example 1, wherein each contact of the redistribution layer is positioned in a quadrilateral flat leadless coverage area.

[0417] 13. The semiconductor package according to Example 1, wherein each contact of the redistribution layer is electrically connected to a corresponding contact of the printed circuit board.

[0418] 14. The semiconductor package according to Example 1 further includes: A second substrate having a cavity formed therein, wherein the substrate is positioned within the cavity.

[0419] 15. The semiconductor package according to Example 1, wherein each contact of the redistribution layer is positioned in a quadrilateral flat lead-free coverage area, and further includes a magnetic structure disposed on a surface of the substrate opposite to the redistribution layer.

[0420] 16. A method for manufacturing a semiconductor package, comprising: A semiconductor die is provided on a substrate, the semiconductor die having at least a first contact portion on a first side and at least a second contact portion on a second side opposite to the first side; The semiconductor die is sealed with a dielectric sealing material; A through-hole is formed in the dielectric sealing material; and A redistribution layer is formed on the dielectric sealing material, and the redistribution layer is connected to the first contact portion and the second contact portion through the through hole.

[0421] 17. The method according to Example 16, comprising: A conductive layer is provided, the conductive layer being electrically connected to the second contact portion and disposed between the second contact portion and the substrate, wherein the conductive layer is electrically connected to the redistribution layer through at least one of the through-holes.

[0422] 18. The method according to Example 16, wherein the substrate is electrically isolated from the semiconductor die by the dielectric sealing material.

[0423] 19. The method according to Example 16 further includes: The semiconductor die is disposed on the first surface of the substrate; and A heat sink is disposed on a second surface of the substrate opposite to the first surface of the substrate.

[0424] 20. The method according to Example 16 further includes: An insulating layer is formed on the dielectric sealing material and the redistribution layer; A second through-hole is formed in the insulating layer; and A second redistribution layer is formed on the insulating layer and connected to the redistribution layer through the second through-hole.

[0425] 21. The method according to Example 16 further includes: A cavity is formed in the substrate; and The semiconductor die is disposed within the cavity.

[0426] 22. The method according to Example 16 further includes: A second substrate formed of a semiconductor material is disposed on the dielectric sealing material; A second through-hole is formed in the second substrate; and The redistribution layer is formed on the second substrate and connected to the first contact portion and the second contact portion through the through-hole and the second through-hole.

[0427] 23. The method according to Example 16 further includes: A second semiconductor die is disposed on the redistribution layer; A second dielectric sealing material is formed on the redistribution layer and the second semiconductor die is sealed. A second through-hole is formed in the second dielectric sealing material; and A second redistribution layer is formed on the second dielectric sealing material, the second redistribution layer being connected to the semiconductor die through the via and the second via, and being connected to the second semiconductor die through the second via.

[0428] 24. The method according to Example 16 further includes: The second semiconductor die is disposed on the first side of the second substrate formed of semiconductor material facing the semiconductor die; The second semiconductor die is at least partially sealed with a second dielectric sealing material; A second through-hole is formed through the second dielectric sealing material, wherein the semiconductor die and the second semiconductor die are connected through the second through-hole; A third through-hole is formed that passes through the second dielectric sealing material and through the second substrate; Forming a fourth through-hole through the second substrate; and A second redistribution layer is formed at least partially on a second side of the second substrate opposite to the first side of the second substrate, and is connected to the redistribution layer and the second semiconductor die through the second via, the third via, and the fourth via.

[0429] 25. The method according to Example 16 further includes: Forming a second through-hole through the substrate; and A conductive layer is formed on the substrate and connected to the semiconductor die through the second through-hole.

[0430] 26. The method according to Example 16 further includes: A cavity is formed in the second substrate; and The substrate is disposed within the cavity.

[0431] 27. A semiconductor package, comprising: First substrate; A semiconductor die, wherein the semiconductor die is disposed on the first substrate; The second substrate has a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, and the second substrate is attached to the first substrate through the second portion of the second substrate and when the semiconductor die is disposed in the cavity. A through-hole, the through-hole being formed through the first portion of the second substrate; and A contact portion is disposed on the second substrate and electrically connected to the semiconductor die through the through-hole.

[0432] 28. The semiconductor package according to Example 27, wherein the through-hole is a second through-hole, the contact portion is a second contact portion, and the semiconductor package further includes: The first through-hole formed through the first substrate; and The first contact portion is disposed on the first substrate and electrically connected to the semiconductor die through the first through-hole.

[0433] 29. The semiconductor package according to Example 27 further includes: The second through hole is formed through the second portion of the second substrate; A metal layer formed between the semiconductor die and the first substrate and extending between a second portion of the first substrate and the second substrate; and A redistribution layer is formed on the second substrate, the redistribution layer including the contact portion and a second contact portion electrically connected to the metal layer through the second via.

[0434] 30. The semiconductor package according to Example 27, wherein the cavity is a second cavity, and the semiconductor package further comprises: A first cavity is formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is disposed within the combined cavity.

[0435] 31. The semiconductor package according to Example 30, wherein the cavity has a first depth different from the second depth of the second cavity.

[0436] 32. The semiconductor package according to Example 27 further includes a redistribution layer on the second substrate and a heat sink on the first substrate.

[0437] 33. The semiconductor package according to Example 27 further includes: A first metal attachment point between the first substrate and the second substrate; The second metal attachment point between the semiconductor die and the second substrate; and A third metal attachment point between the semiconductor die and the first substrate.

[0438] 34. The semiconductor package according to Example 27, wherein the first substrate comprises a metal substrate.

[0439] 35. The semiconductor package according to Example 34 further includes: The second through hole is formed through the second portion of the second substrate; A third substrate, the third substrate being disposed around the periphery of the first substrate and having a third through-hole formed therethrough; and A redistribution layer is formed on the second substrate and connected to the first substrate and thereby to the semiconductor die via the second via and the third via.

[0440] 36. The semiconductor package according to Example 27, wherein the first substrate comprises a directly bonded metal substrate.

[0441] 37. The semiconductor package according to Example 27 further includes: A dielectric layer, the dielectric layer being formed on the second substrate; and A heat sink, which is formed on a dielectric layer.

[0442] 38. The semiconductor package according to Example 27 further includes: A first metal layer extends through the first substrate and is parallel to the surface of the semiconductor die, and is electrically connected to the semiconductor die; A second metal layer, the second metal layer including the contact portion and extending through the second substrate and parallel to the surface of the semiconductor die; The second through hole is formed through the second portion of the second substrate; A third through-hole, wherein the third through-hole is formed through the first substrate; and A redistribution layer is formed on the first substrate between the first substrate and the second substrate, and is electrically connected to the first metal layer through the third via and to the second metal layer through the second via.

[0443] 39. The semiconductor package according to Example 27, wherein the second substrate includes a semiconductor substrate, and the semiconductor package further includes electronic components formed in the second substrate and connected to the semiconductor die via the contact portion.

[0444] 40. The semiconductor package according to Example 27, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate, and the semiconductor package further includes a microelectromechanical system (MEMS) element formed in at least one of the first substrate and the second substrate and connected to the semiconductor die via the contact portion.

[0445] 41. The semiconductor package according to Example 40, wherein the semiconductor die and the microelectromechanical system element are combined to provide a relay.

[0446] 42. The semiconductor package according to Example 27, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate, and the semiconductor package further includes a microelectromechanical system microfluidic heat pipe formed in at least one of the first substrate and the second substrate.

[0447] 43. A method for manufacturing a semiconductor package, comprising: The semiconductor die is placed on the first substrate; A cavity is formed in a second substrate, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth; The second substrate is attached to the first substrate through the second portion of the second substrate and with the semiconductor die disposed within the cavity; Forming a through-hole through the first portion of the second substrate; and A contact portion is disposed on the second substrate, and the contact portion is electrically connected to the semiconductor die through the through hole.

[0448] 44. The method according to Example 43, wherein the through hole is a second through hole, the contact portion is a second contact portion, and the method further includes: Forming a first through-hole through the first substrate; and A first contact portion is disposed on the first substrate, and the first contact portion is electrically connected to the semiconductor die through the first through hole.

[0449] 45. The method according to Example 43 further includes: A second through-hole is formed through a second portion of the second substrate; A metal layer is formed between the semiconductor die and the first substrate, and the metal layer extends between a second portion of the first substrate and the second substrate; and A redistribution layer is formed on the second substrate, the redistribution layer including the contact portion and a second contact portion electrically connected to the metal layer through the second via.

[0450] 46. ​​The method according to Example 43, wherein the cavity is a second cavity, and the method further comprises: A first cavity is formed in the first substrate and the first cavity is aligned with the second cavity to form a combined cavity, wherein the semiconductor die is disposed within the combined cavity.

[0451] 47. The method according to Example 46, wherein the first cavity has a first depth, the first depth being different from the second depth of the second cavity.

[0452] 48. The method according to Example 43 further includes: A redistribution layer is formed on the second substrate; and A heat sink is provided on the first substrate.

[0453] 49. The method according to Example 43 further includes: A first metal attachment point is provided between the first substrate and the second substrate; A second metal attachment point is provided between the semiconductor die and the second substrate; and A third metal attachment point is provided between the semiconductor die and the first substrate.

[0454] 50. The method according to Example 43, wherein the first substrate comprises a metal substrate.

[0455] 51. The method according to Example 43 further includes: A second through-hole is formed through a second portion of the second substrate; A third substrate is disposed around the periphery of the first substrate; Forming a third through-hole through the third substrate; and A redistribution layer is formed on the second substrate, and the redistribution layer is connected to the first substrate through the second via and the third via, thereby connecting to the semiconductor die.

[0456] 52. The method according to Example 43 further includes: A first metal layer is provided, which extends through the first substrate and is parallel to the surface of the semiconductor die, and is electrically connected to the semiconductor die; A second metal layer is provided, the second metal layer including the contact portion and extending through the second substrate and parallel to the surface of the semiconductor die; A second through-hole is formed through the second portion of the second substrate; Forming a third through-hole through the first substrate; and A redistribution layer is formed on the first substrate between the first substrate and the second substrate, the redistribution layer being electrically connected to the first metal layer through the third via and electrically connected to the second metal layer through the second via.

[0457] 53. The method according to Example 43, wherein the second substrate comprises a semiconductor substrate, and the method further comprises: An electronic component is provided, which is formed in the second substrate and connected to the semiconductor die via the contact portion.

[0458] 54. The method according to Example 43, wherein at least one of the first substrate and the second substrate comprises a semiconductor substrate, and the method further comprises: Microelectromechanical system (MEMS) components are provided in at least one of the first substrate and the second substrate.

[0459] 55. A semiconductor package, comprising: A substrate having a cavity formed therein; Magnetic elements disposed in the cavity; A metal winding, the metal winding being disposed on the substrate and surrounding the magnetic element; A dielectric sealing material, wherein the dielectric sealing material seals the magnetic element and the metal winding; and The contact portion is electrically connected to the metal winding through a through-hole formed in the dielectric sealing material.

[0460] 56. The semiconductor package according to Example 55, wherein the magnetic element comprises a cylindrical iron disk.

[0461] 57. The semiconductor package according to Example 55, wherein the metal winding includes a patterned metal layer wound around the magnetic element in at least two turns.

[0462] 58. The semiconductor package according to Example 55, wherein the metal winding has an inner terminal adjacent to the edge of the magnetic element and spirally extends to an outer terminal away from the magnetic element.

[0463] 59. The semiconductor package according to Example 58, wherein the substrate includes a second cavity adjacent to the cavity, and the semiconductor package further includes: A second magnetic element is disposed in the second cavity; A second metal winding, wherein the second magnetic element is disposed on the substrate and surrounds the second magnetic element; and At least a second contact portion, which is electrically connected to the second metal winding through a second through-hole formed in the dielectric sealing material.

[0464] 60. The semiconductor package according to Example 59, wherein the second metal winding has a second inner terminal and a second outer terminal, and further wherein the outer terminal is electrically connected to the second inner terminal.

[0465] 61. The semiconductor package according to Example 59, wherein the second metal winding has a second inner terminal and a second outer terminal, and further wherein the inner terminal and the second inner terminal have a first common contact portion, and the outer terminal and the second outer terminal have a second common contact portion.

[0466] 62. The semiconductor package according to Example 59, wherein the metal winding has a first number of turns around the magnetic element, and the second metal winding has a second number of turns around the second magnetic element, the second number of turns being less than the first number of turns.

[0467] 63. A method for manufacturing a semiconductor package, comprising: A cavity is formed in the substrate; The magnetic element is placed in the cavity; A metal winding is provided on the substrate and around the magnetic element; The magnetic element and the metal winding are sealed with a dielectric sealing material; A through-hole is formed in the dielectric sealing material; and The contact portion is electrically connected to the metal winding through the through hole.

[0468] 64. The method of manufacturing a semiconductor package according to Example 63, wherein the magnetic element comprises a cylindrical iron disk.

[0469] 65. The method of manufacturing a semiconductor package according to Example 63 further includes: The metal winding is provided, the metal winding comprising a patterned metal layer coiled around the magnetic element in at least two turns.

[0470] 66. The method of manufacturing a semiconductor package according to Example 63, wherein the metal winding has an inner terminal that is close to the edge of the magnetic element and spirally extends to an outer terminal away from the magnetic element.

[0471] 67. The method of manufacturing a semiconductor package according to Example 66, wherein the substrate includes a second cavity adjacent to the cavity, and the method further includes: The second magnetic element is placed in the second cavity; A second metal winding is provided on the substrate and around the second magnetic element; Forming a second through-hole through the dielectric sealing material; and The second contact portion is electrically connected to the second metal winding through the second through hole.

[0472] 68. A method for manufacturing a semiconductor package according to Example 67, wherein the second metal winding has a second inner terminal and a second outer terminal, and the method further includes: The outer terminal is electrically connected to the second inner terminal.

[0473] 69. The method of manufacturing a semiconductor package according to Example 67, wherein the second metal winding has a second inner terminal and a second outer terminal, and the method further comprises: A first common contact is provided for the inner terminal and the second inner terminal; and A second common contact is provided for the outer terminal and the second outer terminal.

[0474] 70. The method of manufacturing a semiconductor package according to Example 67 further includes: Provide the metal winding with a first number of turns around the magnetic element; and The second metal winding is provided with a second number of turns around the second magnetic element, the second number of turns being less than the first number of turns.

[0475] 71. A semiconductor package, comprising: First substrate; A metal layer disposed on the first substrate; A metal pillar disposed on the metal layer and defining a cavity; A semiconductor die, wherein the semiconductor die is disposed in the cavity, and a first surface of the semiconductor die is disposed on the metal layer; A sealing material that seals the semiconductor die (including a second surface of the semiconductor die opposite to the first surface) and at least a portion of the metal pillar; A second substrate formed on the sealing material and the metal pillar; and A redistribution layer is formed on the second substrate and is connected to the first surface of the semiconductor die, the second surface of the semiconductor die, and at least one of the metal pillars through a via formed through the second substrate.

[0476] 72. A method for manufacturing a semiconductor package, comprising: A metal layer is formed on the first substrate; Metal pillars are disposed on the metal layer to define the cavity; A semiconductor die is disposed in the cavity, wherein a first surface of the semiconductor die is disposed on the metal layer; The semiconductor die (including the second surface of the semiconductor die opposite to the first surface) and at least a portion of the metal pillar are sealed with a sealing material; A second substrate is formed on the sealing material and the metal pillar; Forming through-holes through the second substrate; and A redistribution layer is formed on the second substrate, the redistribution layer being connected to the first surface of the semiconductor die, the second surface of the semiconductor die, and at least one of the metal pillars through the via.

[0477] While certain features of the described embodiments have been shown as described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the scope of the embodiments. It should be understood that they are presented by way of example only and not limitation, and various changes in form and detail may be made. Any part of the apparatus and / or methods described herein can be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0478] While certain features of the described embodiments have been shown as described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and alterations falling within the scope of the embodiments.

Claims

1. A semiconductor package, characterized in that, The semiconductor package includes: substrate; A semiconductor die, the semiconductor die being disposed on the substrate and having at least a first contact portion on a first side and at least a second contact portion on a second side opposite to the first side; A dielectric sealing material that seals the semiconductor die and has a through-hole formed therein; and A redistribution layer is formed on the dielectric sealing material and connected to the first contact portion and the second contact portion through the through-hole.

2. The semiconductor package according to claim 1, wherein, The semiconductor package further includes a conductive layer electrically connected to the second contact portion and disposed between the second contact portion and the substrate, wherein the conductive layer is electrically connected to the redistribution layer through at least one of the vias.

3. The semiconductor package according to claim 1, wherein, The semiconductor package further includes a cavity formed in the substrate, wherein the semiconductor die is disposed within the cavity.

4. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: The second substrate is formed of a semiconductor material and disposed on the dielectric sealing material. The second substrate has a second through-hole formed therein. The redistribution layer is formed on the second substrate and connected to the first contact portion and the second contact portion through the through-hole and the second through-hole.

5. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: A second semiconductor die is disposed on the redistribution layer; A second dielectric sealing material is formed on the redistribution layer and seals the second semiconductor die, the second dielectric sealing material having a second through-hole formed therein; and A second redistribution layer is formed on the second dielectric sealing material and is connected to the semiconductor die through the via and the second via, and is also connected to the second semiconductor die through the second via.

6. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: The second substrate is formed of a semiconductor material; The second semiconductor die is disposed on the first side of the second substrate facing the semiconductor die; A second dielectric sealing material, wherein the second dielectric sealing material at least partially seals the second semiconductor die; The second through hole is formed through the second dielectric sealing material, wherein the semiconductor die and the second semiconductor die are connected through the second through hole; A third through-hole is formed through the second dielectric sealing material and through the second substrate; A fourth through-hole, the fourth through-hole being formed through the second substrate; and The second redistribution layer is formed at least partially on a second side of the second substrate opposite to the first side of the second substrate, and is connected to the redistribution layer and the second semiconductor die through the second via, the third via and the fourth via.

7. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: A second substrate having a cavity formed therein, wherein the substrate is positioned within the cavity.

8. A semiconductor package, characterized in that, The semiconductor package includes: First substrate; A semiconductor die, wherein the semiconductor die is disposed on the first substrate; The second substrate has a cavity formed therein, the cavity defining a first portion of the second substrate having a first depth and a second portion of the second substrate having a second depth greater than the first depth, and the second substrate is attached to the first substrate through the second portion of the second substrate and when the semiconductor die is disposed in the cavity. A through-hole, the through-hole being formed through the first portion of the second substrate; and A contact portion is disposed on the second substrate and electrically connected to the semiconductor die through the through-hole.

9. The semiconductor package according to claim 8, wherein, The through-hole is a second through-hole, the contact portion is a second contact portion, and the semiconductor package further includes: A first through-hole, the first through-hole being formed through the first substrate; and The first contact portion is disposed on the first substrate and electrically connected to the semiconductor die through the first through-hole.

10. The semiconductor package according to claim 8, wherein, The semiconductor package further includes: The second through hole is formed through the second portion of the second substrate; A metal layer formed between the semiconductor die and the first substrate and extending between a second portion of the first substrate and the second substrate; and A redistribution layer is formed on the second substrate, the redistribution layer including the contact portion and a second contact portion electrically connected to the metal layer through the second via.

11. The semiconductor package according to claim 8, wherein, The cavity is a second cavity, and the semiconductor package further includes: A first cavity is formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is disposed within the combined cavity.

12. The semiconductor package according to claim 8, wherein, The semiconductor package further includes: A first metal attachment point between the first substrate and the second substrate; The second metal attachment point between the semiconductor die and the second substrate; and A third metal attachment point between the semiconductor die and the first substrate.

13. The semiconductor package according to claim 8, wherein, The semiconductor package further includes: A first metal layer extends through the first substrate and is parallel to the surface of the semiconductor die, and is electrically connected to the semiconductor die; A second metal layer, the second metal layer including the contact portion and extending through the second substrate and parallel to the surface of the semiconductor die; The second through hole is formed through the second portion of the second substrate; A third through-hole, wherein the third through-hole is formed through the first substrate; and A redistribution layer is formed on the first substrate between the first substrate and the second substrate, and is electrically connected to the first metal layer through the third via and to the second metal layer through the second via.

14. The semiconductor package according to claim 8, wherein, The second substrate includes a semiconductor substrate, and the semiconductor package further includes electronic components formed in the second substrate and connected to the semiconductor die via the contact portion.

15. The semiconductor package according to claim 8, wherein, At least one of the first substrate and the second substrate includes a semiconductor substrate, and the semiconductor package further includes a microelectromechanical system (MEMS) element formed in at least one of the first substrate and the second substrate and connected to the semiconductor die via the contact portion.

16. The semiconductor package of claim 15, wherein, The semiconductor die and the microelectromechanical system components are combined to provide a relay.

17. A semiconductor package, characterized in that, The semiconductor package includes: A substrate having a cavity formed therein; A magnetic element disposed in the cavity; A metal winding, the metal winding being disposed on the substrate and surrounding the magnetic element; A dielectric sealing material, wherein the dielectric sealing material seals the magnetic element and the metal winding; and The contact portion is electrically connected to the metal winding through a through-hole formed in the dielectric sealing material.

18. The semiconductor package of claim 17, wherein, The magnetic element includes a cylindrical iron disk.

19. The semiconductor package of claim 17, wherein, The metal winding includes a patterned metal layer that is coiled around the magnetic element in at least two turns.

20. The semiconductor package of claim 17, wherein, The metal winding has an inner terminal that is close to the edge of the magnetic element and spirals out to an outer terminal away from the magnetic element.

21. The semiconductor package of claim 20, wherein, The substrate includes a second cavity adjacent to the cavity, and further includes: A second magnetic element is disposed in the second cavity; A second metal winding, disposed on the substrate and surrounding the second magnetic element; and At least a second contact portion, which is electrically connected to the second metal winding through a second through-hole formed in the dielectric sealing material.

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