Host management of write buffer size for flash memory

Abstract

A host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD). The HCI is configured to obtain an indication that a size of a particular write buffer (WB) of the FMD is to increase. The FMD includes a plurality of memory resources including a plurality of logical units (LUs) and at least a particular WB. The HCI is also configured to select a particular memory resource for write buffer reallocation based at least in part on a particular usage metric for the particular memory resource.

Description

Cross-references to related applications

[0001] This application claims priority to jointly owned U.S. non-provisional patent application No. 18 / 481,616, filed on October 5, 2023, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates in its entirety to host management of write buffer size for flash memory devices. Background Technology

[0003] Technological advancements have led to smaller and more powerful computing devices. For example, a wide variety of portable personal computing devices exist today, including small, lightweight, and easily portable cordless phones (such as mobile and smartphones, tablets, and laptops). These devices can transmit voice and data packets over wireless networks. Furthermore, many of these devices incorporate additional functionality, such as digital still cameras, digital camcorders, digital recorders, and audio file players. Moreover, such devices can process executable instructions, including software applications such as web browsers for accessing the internet. Thus, these devices can include significant computing power.

[0004] Such computing devices typically incorporate functionality as host devices, allowing them to store and retrieve data from flash memory. For example, a host device can store audio, images, video, documents, etc., on a flash memory device. Before writing data to main memory cells, the flash memory device can use a write buffer as a temporary storage area for incoming data writes from the host device. Using a write buffer offers various advantages, such as reducing write latency perceived by the host device. When the write buffer is small, it may become unavailable as it fills to capacity, and data is flushed to main memory cells. Conversely, a larger write buffer consumes more memory that would otherwise be available for main memory. The utilization of the write buffer changes dynamically; therefore, a fixed-size write buffer may be too small when large or frequent writes are being performed, and too large when fewer and smaller writes are being performed. Summary of the Invention

[0005] According to one embodiment of this disclosure, a host device includes a host controller interface (HCI) configured to be coupled to a flash memory device (FMD) and configured to receive an indication that the size of a specific write buffer (WB) of the FMD is to be increased. The FMD includes a plurality of memory resources, which include a plurality of logical units (LUs) and at least the specific WB. The HCI is also configured to select the specific memory resource at least in part based on a specific usage metric for reallocating the write buffer.

[0006] According to another specific embodiment of this disclosure, a method includes obtaining at a host controller interface (HCI) an indication that the size of a particular write buffer (WB) of a flash memory device (FMD) is to be increased. The FMD includes multiple memory resources, which include multiple logical units (LUs) and at least the particular WB. The method also includes selecting the particular memory resource at the HCI based at least in part on a specific usage metric for the write buffer reallocation.

[0007] According to another embodiment of this disclosure, a non-transitory computer-readable medium is configured to store instructions that, when executed by one or more processors, cause the one or more processors to obtain at a host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) should be increased. The FMD includes a plurality of memory resources, which include a plurality of logical units (LUs) and at least the specific WB. The instructions also cause the one or more processors to select the specific memory resource at least in part based on a specific usage metric for reallocating the write buffer.

[0008] According to another embodiment of this disclosure, an apparatus includes components for obtaining, at a host controller interface (HCI), an indication that the size of a particular write buffer (WB) of a flash memory device (FMD) is to be increased. The FMD includes a plurality of memory resources, which include a plurality of logical units (LUs) and at least the particular WB. The apparatus also includes components for selecting the particular memory resource, at least in part, based on a specific usage metric for reallocating the write buffer.

[0009] Other aspects, advantages, and features of this disclosure will become apparent upon reading the entire application, which comprises the following sections: description of the drawings, detailed description, and claims. Attached Figure Description

[0010] Figure 1This is a block diagram illustrating a specific exemplary aspect of a system capable of operating to perform host management of a flash memory write buffer size, according to some examples of this disclosure.

[0011] Figure 2A Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates a specific aspect of the system's execution that obtains resizing instructions.

[0012] Figure 2B Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates another example of how the system executes to obtain resizing instructions.

[0013] Figure 2C Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates another example of how the system executes to obtain resizing instructions.

[0014] Figure 3 Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates an exemplary aspect of the write buffer allocation performed by the system.

[0015] Figure 4 This is based on some examples of the shared write buffer being executed. Figure 3 An illustrative diagram of the write buffer allocation.

[0016] Figure 5 This is based on some examples of the application of this disclosure to a dedicated write buffer. Figure 3 An illustrative diagram of the write buffer allocation.

[0017] Figure 6 Based on some examples of this disclosure and Figure 3 A ladder diagram illustrating the exemplary aspects of the operations associated with the write buffer allocation.

[0018] Figure 7 Based on some examples of this disclosure, it is possible to... Figure 1 This is another example of the write buffer allocation performed by the system.

[0019] Figure 8 This is based on some examples of the application of this disclosure to a dedicated write buffer. Figure 7 An illustrative diagram of the write buffer allocation.

[0020] Figure 9 Based on some examples of this disclosure and Figure 7 A ladder diagram illustrating the exemplary aspects of the operations associated with the write buffer allocation.

[0021] Figure 10Based on some examples of this disclosure, it is possible to... Figure 1 The diagram illustrates an exemplary aspect of the write buffer deallocation performed by the system.

[0022] Figure 11 Based on some examples of this disclosure and may be derived from Figure 1 A ladder diagram illustrating the exemplary aspects of the write buffer resizing operations performed by the system.

[0023] Figure 12 Based on some examples of this disclosure, it is possible to... Figure 1 A diagram illustrating a specific implementation of a host-managed method for allocating write buffers to flash memory during system execution.

[0024] Figure 13 This is a block diagram of a specific exemplary example of a device capable of operating to perform host management of a flash memory write buffer size, according to some examples of this disclosure. Detailed Implementation

[0025] Computing devices typically incorporate the functionality of storing and retrieving data from flash memory devices. For example, a host device may store audio, images, video, documents, etc., on a flash memory device. A flash memory device includes main memory cells of a first memory type (e.g., three-level cell (TLC)) for storing data. A flash memory device may also include one or more write buffers of memory cells of a second memory type (e.g., single-level cell (SLC)). In some examples, memory cells of the first memory type can store more data, while writes to memory cells of the second memory type are faster; therefore, memory cells of the first memory type are used as main memory cells to increase storage capacity, and memory cells of the second memory type are used as write buffers to reduce write latency. Memory cells can be converted from the first memory type to the second memory type, and vice versa.

[0026] Main memory is divided into logical cells for various purposes, such as wear leveling and managing the use of different types of memory. Typically, when a write buffer is filled to capacity, writes to the write buffer are disabled, and data from the write buffer is written to the corresponding logical cell in main memory. If the write buffer is frequently filled, writes to it must be disabled frequently. On the other hand, write buffers with a large amount of unused capacity waste resources because some of the memory cells assigned to the write buffer could otherwise be used as main memory cells.

[0027] Systems and methods for performing host management of write buffer size in flash memory are disclosed. The flash memory device includes memory resources such as multiple logical cells and at least one write buffer. The flash memory device maintains usage metrics for the memory resources. For example, a buffer usage metric for a specific write buffer indicates the utilization rate of that specific write buffer. As another example, a logical cell usage metric for a specific logical cell indicates the utilization rate of that specific logical cell.

[0028] In some examples, the host device receives an indication that the size of a specific write buffer should be increased. In one example, when the buffer usage metric of a specific write buffer indicates a usage rate exceeding a high usage threshold, an exception is generated at the flash memory device, and the flash memory device sends a notification to the host device that the size of the specific buffer should be increased. In another example, the host device sends a request to the flash memory device for a buffer usage metric of a specific write buffer, and in response to determining that the buffer usage metric indicates a usage rate exceeding a high usage threshold, determines that the size of the specific write buffer should be increased.

[0029] Based on the determination that the size of a particular write buffer needs to be increased, the host device selects a particular memory resource at least in part based on a usage metric of a particular memory resource used for write buffer reallocation. In the first example, the host device selects a particular logical unit based on a usage metric indicating the lowest utilization among a plurality of logical units. In the second example, the host device selects a second write buffer based on a usage metric indicating the lowest utilization among a plurality of write buffers.

[0030] The host device reallocates a portion of the selected memory resources to a specific write buffer. In a first example, the host device sends a request to the flash memory device indicating that a specific logical cell should be used for reallocation to the specific write buffer. Upon receiving the request, the flash memory device converts a portion of the specific logical cell from a first memory type (e.g., TLC) to a second memory type (e.g., SLC) and assigns the portion of the specific logical cell to the specific write buffer. In a second example, the host device sends a request to the flash memory device indicating that a second write buffer should be used for reallocation to the specific write buffer. Upon receiving the request, the flash memory device reallocates a portion of the second write buffer to the specific write buffer.

[0031] In some examples, the host device receives an indication that the size of a specific write buffer should be reduced. In one example, when the buffer usage metric indicates a usage rate below a low usage threshold, an exception is generated at the flash memory device, and the flash memory device sends a notification to the host device that the size of the specific buffer should be reduced. In another example, the host device sends a request to the flash memory device to obtain the buffer usage metric for a specific write buffer, and in response to determining that the buffer usage metric indicates a usage rate below a low usage threshold, determines that the size of the specific write buffer should be reduced.

[0032] In response to determining that the size of a specific write buffer needs to be reduced, the host device sends a request to the flash memory device to deallocate a portion of the specific write buffer. Upon receiving the request, the flash memory device deallocates that portion of the specific write buffer. In some examples, the flash memory device may reallocate that portion of the specific write buffer to one or more logical cells, one or more other write buffers, or a combination thereof. The advantage of dynamically adjusting the size of the write buffer based on write buffer utilization is that it allows for increased write buffer availability while saving write buffer memory allocation.

[0033] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For example, Figure 1 A memory mapping table 180 is depicted, which indicates that write buffer 182A corresponds to one or more memory address ranges. Figure 1 The term "memory address range" 184A indicates that in some respects, the write buffer 182A corresponds to a single memory address range 184A (e.g., a contiguous memory range), while in other respects, the write buffer 182A corresponds to multiple memory address ranges 184A (e.g., non-contiguous memory ranges). For ease of reference herein, such features are generally introduced as "one or more" features and are subsequently referred to in the singular or optional plural form (as indicated by "(multiple)"), unless the aspect relating to multiples of features is described.

[0034] In some figures, multiple instances of a particular type of feature are used. Although these features are physically and / or logically different, the same reference numerals are used for each feature, and these different instances are distinguished by adding letters to the reference numerals. Reference numerals are used without distinguishing letters when a feature is referenced herein as a group or a type of feature (e.g., when a specific feature among these features is not referenced). However, reference numerals are used with distinguishing letters when a specific feature among multiple features of the same type is mentioned herein. For example, see reference... Figure 1 Multiple logic units are illustrated and associated with reference numerals 168A, 168B, and 168C. ​​When referring to a specific logic unit among these logic units (such as logic unit 168A), the distinguishing letter "A" is used. However, when referring to any arbitrary logic unit among these logic units or when referring to these logic units as a group, reference numeral 168 is used without the distinguishing letter.

[0035] As used herein, the term "comprising" is used interchangeably with "including". Additionally, the term "in which" is used interchangeably with "wherein". As used herein, "exemplary" indicates an example, specific implementation, and / or aspect, and should not be construed as restrictive or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements (such as structures, components, operations, etc.) (e.g., "first", "second", "third", etc.) do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using ordinal terms). As used herein, the term "set" refers to one or more specific elements among specific elements, while the term "multiple" refers to multiple (e.g., two or more) specific elements.

[0036] As used herein, “coupling” can include “communicationally coupled,” “electrically coupled,” or “physically coupled,” and may also (or alternatively) include any combination thereof. Two devices (or components) may be directly or indirectly coupled (e.g., communicationally coupled, electrically coupled, or physically coupled) via one or more other devices, components, wires, buses, networks (e.g., wired networks, wireless networks, or combinations thereof). As an illustrative, non-limiting example, two electrically coupled devices (or components) may be included in the same device or in different devices and may be connected via electronics, one or more connectors, or inductive coupling. In some specific implementations, two communicationally coupled (such as electrical communication) devices (or components) may directly or indirectly transmit and receive signals (e.g., digital or analog signals) via one or more wires, buses, networks, etc. As used herein, “direct coupling” can include two devices coupled (e.g., communicationally coupled, electrically coupled, or physically coupled) without intermediate components.

[0037] In this disclosure, terms such as “determine,” “calculate,” “estimate,” “shift,” and “adjust” can be used to describe how one or more operations are performed. It should be noted that such terms should not be construed as restrictive, and similar operations can be performed using other techniques. Additionally, as mentioned herein, “obtain,” “generate,” “calculate,” “estimate,” “use,” “select,” “access,” and “determine” are used interchangeably. For example, “obtain,” “generate,” “calculate,” “estimate,” or “determine” a parameter (or signal) can refer to actively generating, estimating, calculating, or determining the parameter (or signal), or it can refer to using, selecting, or accessing a parameter (or signal) such as one already generated by another component or device.

[0038] refer to Figure 1 This illustrates a specific exemplary aspect of system 100, which is configured to perform host management of a flash memory write buffer size. System 100 includes a host device 102 configured to be coupled to flash memory device 104.

[0039] Flash memory device 104 includes a device controller 162 coupled to flash memory 164 (e.g., NAND memory), which includes memory cells 192. Device controller 162 has access to a memory mapping table 180. For example, memory mapping table 180 is stored in a portion of flash memory 164 or in static random access memory (SRAM) coupled to device controller 162. In some specific implementations, memory mapping table 180 corresponds to a logical-to-physical address mapping table.

[0040] Memory map 180 is configured to indicate memory cells of flash memory 164 assigned to one or more write buffers 182. For example, memory map 180 indicates that write buffer 182A corresponds to one or more memory address ranges 184A. In some specific implementations, memory map 180 indicates that write buffer 182B corresponds to one or more memory address ranges 184B, write buffer 182C corresponds to one or more memory address ranges 184C, and one or more additional write buffers correspond to corresponding memory address ranges or combinations thereof. Each particular memory address range 184 indicates a corresponding subset of memory cells 192, such as one or more ranges of the physical addresses of the corresponding subset of memory cells 192.

[0041] Memory map 180 is also configured to indicate memory cells of flash memory 164 assigned to logic units 168. For example, memory map 180 indicates that logic unit 168A corresponds to one or more memory address ranges 190A, logic unit 168B corresponds to one or more memory address ranges 190B, logic unit 168C corresponds to one or more memory address ranges 190C, and one or more additional logic units correspond to corresponding memory address ranges or combinations thereof. Each particular memory address range 190 indicates a corresponding subset of memory units 192, such as one or more ranges of the physical addresses of the corresponding subset of memory units 192.

[0042] In a specific aspect, each memory cell in a first subset of the memory cells 192 assigned to logic unit 168 has a first memory type (e.g., three-level cell (TLC)), and each memory cell in a second subset of the memory cells 192 assigned to write buffer 182 has a second memory type (e.g., single-level cell (SLC)). In a specific aspect, memory cells of the first memory type can store more data, while memory cells of the second memory type correspond to lower write latency.

[0043] Device controller 162 is configured to convert memory cell 192 from a first memory type to a second memory type and vice versa. For example, before reassigning a memory cell from logic cell 168 to write buffer 182, device controller 162 converts the memory cell from a first memory type (e.g., TLC) to a second memory type (e.g., SLC). As another example, before reassigning a memory cell from write buffer 182 to logic cell 168, device controller 162 converts the memory cell from a second memory type (e.g., SLC) to a first memory type (e.g., TLC).

[0044] Device controller 162 is configured to perform write operations to flash memory 164 according to one or more buffer modes. For example, the one or more buffer modes include write buffer mode 170, which indicates whether flash memory device 104 is configured to use one or more write buffers 182 as temporary storage for logic cells 168. For example, when write buffer mode 170 is enabled, one or more write buffers 182 are available and intended to be used as temporary storage for writing data to logic cells 168.

[0045] In one example, the one or more buffering modes include a shared buffering mode 172, which indicates whether a shared write buffer or a dedicated write buffer should be used. For example, when both write buffering mode 170 and shared buffering mode 172 are enabled, write buffer 182A is available and intended to be used as temporary storage for data writes across logic unit 168. When write buffering mode 170 is enabled and shared buffering mode 172 is disabled, dedicated write buffers are available and intended to be used as temporary storage for data writes to the corresponding logic unit 168. For example, write buffer 182A is intended to be used as temporary storage for data writes to logic unit 168A, write buffer 182B is intended to be used as temporary storage for data writes to logic unit 168B, write buffer 182C is intended to be used as temporary storage for data writes to logic unit 168C, and so on.

[0046] According to some specific implementations, the one or more buffering modes include a buffer reallocation mode 160, which indicates that an increase in the size of the write buffer 182 is to be performed by reallocating a portion of another write buffer (as referenced). Figures 7 to 9 (Further description) or it still needs to be performed by reallocating a portion of the logical unit (as described in the reference). Figures 3 to 6 (Further described). For example, when a dedicated write buffer is available and buffer reallocation mode 160 is enabled, an increase in the size of write buffer 182A is performed by reallocating a portion of write buffer 182B to write buffer 182A, as described in the reference. Figures 7 to 9 Further described. As another example, when write buffer 182A is a shared write buffer for logic unit 168, or when a dedicated write buffer is available and buffer reallocation mode 160 is disabled, the increase in the size of write buffer 182A is performed by reallocating a portion of logic unit 168 to write buffer 182A, as described in the reference. Figures 3 to 6 Further description.

[0047] In certain aspects, the one or more buffer modes (e.g., write buffer mode 170, shared buffer mode 172, buffer reallocation mode 160, or a combination thereof) are set based on default data, configuration settings, user input, commands from HCI 112, or a combination thereof. In certain aspects, one or more indicators of the one or more buffer modes are stored in a portion of flash memory 164, a register, or another type of data storage device, or a combination thereof. In certain aspects, one or more indicators of the one or more buffer modes are stored at host device 102.

[0048] It should be understood that the operations based on one or more buffering modes (e.g., write buffering mode 170, shared buffering mode 172, buffer reallocation mode 160, or combinations thereof) are described herein as illustrative examples. In some specific implementations, one or more of write buffering mode 170, shared buffering mode 172, buffer reallocation mode 160, or combinations thereof are optional. In some examples, one or more operations described herein may be performed based on one or more other parameters or combinations thereof.

[0049] According to some alternative embodiments, the flash memory device 104 may support fewer buffering modes than one or more buffering modes described herein (e.g., write buffering mode 170, shared buffering mode 172, buffer reallocation mode 160, or combinations thereof). For example, in some embodiments, the flash memory device 104 is configured to have a shared write buffer and not support a dedicated write buffer. In these embodiments, the flash memory device 104 may not include shared buffering mode 172 and perform one or more operations as if shared buffering mode 172 were enabled. Alternatively, in some embodiments, the flash memory device 104 is configured to have a dedicated write buffer and not support a shared write buffer. In these embodiments, the flash memory device 104 may not include shared buffering mode 172 and perform one or more operations as if shared buffering mode 172 were disabled.

[0050] In some implementations, the flash memory device 104 supports buffer reallocation but does not support reallocation from logical cells. In these implementations, the flash memory device 104 may not have buffer reallocation mode 160 and performs one or more operations as if buffer reallocation mode 160 were enabled. Alternatively, in some implementations, the flash memory device 104 supports reallocation from logical cells but does not support buffer reallocation. In these implementations, the flash memory device 104 may not have buffer reallocation mode 160 and performs one or more operations as if buffer reallocation mode 160 were disabled.

[0051] Device controller 162 is configured to maintain one or more buffer usage metrics 174. For example, device controller 162 is configured to maintain buffer usage metric 174A, which indicates the utilization rate of write buffer 182A. According to some specific implementations, device controller 162 is also configured to maintain buffer usage metric 174B for write buffer 182B, buffer usage metric 174C for write buffer 182C, one or more additional buffer usage metrics for one or more additional write buffers, or combinations thereof. In certain aspects, device controller 162 is coupled to or includes one or more registers configured to store one or more buffer usage metrics 174.

[0052] In certain respects, when write buffering mode 170 is enabled, device controller 162 maintains one or more buffer usage metrics 174. For example, when write buffering mode 170 is disabled, device controller 162 avoids updating one or more buffer usage metrics 174.

[0053] Host device 102 includes a host controller interface (HCI) 112 configured to couple to flash memory device 104. In one example, HCI 112 is configured to communicate with device controller 162 of flash memory device 104. According to some specific implementations, HCI 112 is configured to send one or more requests 166 to device controller 162, and device controller 162 is configured to send a response 176 to HCI 112 in response to receiving a request 166 from HCI 112.

[0054] HCI 112 is configured to obtain resizing indication 116A based on a comparison of buffer usage metric 174A with one or more thresholds. In some examples, HCI 112 is configured to obtain resizing indication 116A when write buffer mode 170 is enabled. In these examples, HCI 112 avoids obtaining resizing indication 116A when write buffer mode 170 is disabled.

[0055] According to some specific implementations, HCI 112 is configured to transmit request 166 to flash memory device 104, and device controller 162 is configured to transmit response 176 to host device 102 indicating buffer usage metric 174A, as referenced. Figure 2A and Figure 2BFurther described. In these embodiments, HCI 112 is configured to perform a comparison of buffer usage metric 174A with one or more thresholds to obtain a resizing indication 116A. According to some embodiments, device controller 162 is configured to generate a notification 178 based on the comparison of buffer usage metric 174A with one or more thresholds. In these embodiments, HCI 112 is configured to obtain the resizing indication 116A based on receiving notification 178, as referenced. Figure 2C Further description.

[0056] In some examples, device controller 162 is configured to generate notification 178 when write buffering mode 170 is enabled. In other examples, device controller 162 is configured to avoid generating notification 178 when write buffering mode 170 is disabled.

[0057] The resizing indicator 116A indicates whether the size of write buffer 182A should be increased, decreased, or remained unchanged. HCI 112 is configured to: in response to determining that the resizing indicator 116A indicates that the size of write buffer 182A should be increased, select memory resource 181 (e.g., another write buffer or logic unit) based on memory resource usage metric 118, and perform write buffer reallocation 114 to reallocate a portion of the selected memory resource 181 to write buffer 182A, as referenced. Figures 3 to 9 Further described. Alternatively, HCI 112 is configured to: in response to determining that the size of write buffer 182A is to be reduced according to resizing instruction 116A, perform write buffer deallocation 120 to deallocate a portion of write buffer 182A, as described in the reference. Figure 10 Further description.

[0058] In some examples, HCI 112 is configured to adjust the size of write buffer 182A when write buffer mode 170 is enabled. In these examples, HCI 112 avoids adjusting the size of write buffer 182A when write buffer mode 170 is disabled.

[0059] During operation, device controller 162 maintains buffer usage metric 174 when write buffer mode 170 is enabled. For example, device controller 162 updates buffer usage metric 174A based on the usage rate of write buffer 182A. For illustration, buffer usage metric 174A indicates the full buffer detection count of write buffer 182A. Device controller 162 initializes buffer usage metric 174A to an initial value (e.g., 0) and updates buffer usage metric 174A in response to detecting that write buffer 182A has reached full capacity and that data stored in write buffer 182A needs to be flushed to the corresponding logic unit 168. In some aspects, in response to adjusting the size of write buffer 182A, device controller 162 resets buffer usage metric 174A to an initial value (e.g., 0).

[0060] Example 150 depicts a write operation using write buffer 182A. Host device 102 (e.g., HCI 112) transmits a write request 152 to flash memory device 104. In a particular aspect, write request 152 indicates that data 154 is to be stored at a specific memory location of logic cell 168A. Based on the determination that write buffer mode 170 is enabled, flash memory device 104 (e.g., device controller 162) stores data 154 in write buffer 182A and transmits a response 176 indicating a successful write to host device 102.

[0061] According to some specific implementations, in response to determining that write buffer mode 170 is enabled, shared buffer mode 172 is enabled, and write buffer 182A corresponds to a shared write buffer, flash memory device 104 stores data 154 in write buffer 182A. Alternatively, in response to determining that write buffer mode 170 is enabled, shared buffer mode 172 is disabled, and write buffer 182A corresponds to a dedicated write buffer for logic cell 168A, flash memory device 104 stores data 154 in write buffer 182A. Writing to write buffer 182A can be faster than writing to logic cell 168A, thereby reducing the latency between host device 102 transmitting data 154 to flash memory device 104 and receiving response 176.

[0062] At a later time, flash memory device 104 (e.g., device controller 162) stores data 154 into storage device 186. For example, storage device 186 includes logic cell 168, and flash memory device 104 writes data 154 from write buffer 182A to a specific memory location of logic cell 168A. In a particular aspect, flash memory device 104 writes data 154 to logic cell 168A as part of performing a flush of data from write buffer 182A to storage device 186. For example, based at least in part on determining that write buffer 182A is full to capacity, flash memory device 104 (e.g., device controller 162) updates (e.g., increments by 1) buffer usage metric 174A and performs a flush of data from write buffer 182A to storage device 186.

[0063] In some implementations, device controller 162 maintains a logic cell usage metric for logic unit 168. In these implementations, device controller 162 updates the logic cell usage metric in response to writing data from write buffer 182A to one or more logic units in logic unit 168, as referenced... Figure 3 Further described. The HCI 112 obtains the logic unit 168 using the metric, as referenced. Figure 3 Further described. For example, HCI 112 receives a logic cell usage metric from device controller 162. As another example, HCI 112 maintains a local copy of the logic cell usage metric. For illustration, HCI 112 updates the logic cell usage metric of logic cell 168A based on a response 176 indicating a successful write to logic cell 168A by receiving indication data 154.

[0064] HCI 112 receives a resizing indication 116A indicating whether the size of write buffer 182A should be increased, decreased, or remained unchanged. According to some specific implementations, HCI 112 transmits a request 166 (e.g., a buffer usage metric request) to flash memory device 104, and in response 176 receives a buffer usage metric 174A from device controller 162, and compares the buffer usage metric 174A with one or more thresholds to obtain the resizing indication 116A, as referenced. Figures 2A to 2B Further described. In an alternative embodiment, device controller 162 generates notification 178 based on a comparison of buffer usage metric 174A with one or more thresholds, and HCI 112 obtains resizing indication 116A based on receiving notification 178, as referenced. Figure 2C Further described. In some respects, when write buffer mode 170 is enabled, device controller 162 generates notification 178, HCI 112 receives resizing instruction 116A, or both.

[0065] In response to the determination that the size of the write buffer 182A needs to be increased according to the resizing instruction 116A, HCI 112 performs a write buffer reallocation 114. For example, HCI 112 selects memory resource 181 based on the memory resource usage metric 118 for a specific memory resource 181, as referenced. Figures 3 to 9 Further described. For example, in response to determining that write buffer mode 170 is enabled and shared buffer mode 172 is enabled (indicating that write buffer 182A is being used as a shared write buffer), HCI 112 determines that one of the logic units 168 should be selected as memory resource 181 for write buffer reallocation 114, as referenced. Figures 3 to 4 Further described. In another example, in response to determining that write buffer mode 170 is enabled, shared buffer mode 172 is disabled, and buffer reallocation mode 160 is disabled (which indicates that a dedicated write buffer is in use and portions from the write buffer are not reallocated to other write buffers), HCI 112 determines that one of the logic units 168 should be selected as memory resource 181 for write buffer allocation 114, as referenced. Figure 3 and Figure 5 Further described. In response to determining that one of the logic units 168 is to be selected as a memory resource 181 for write buffer reallocation 114, HCI 112 selects a particular logic unit 168 based on determining that the particular logic unit 168 has a metric indicating the lowest utilization rate among the logic units 168, as referenced. Figures 3 to 6 Further description.

[0066] In a specific example, in response to determining that write buffer mode 170 is enabled, shared buffer mode 172 is disabled, and buffer reallocation mode 160 is enabled (which indicates that a dedicated write buffer is in use and a portion of the write buffer is to be reallocated to increase the size of other write buffers), HCI 112 determines that one of the write buffers 182 should be selected as memory resource 181 for write buffer reallocation 114, as referenced. Figures 7 to 9 Further described. In response to determining that one of the write buffers 182 is to be selected as memory resource 181 for write buffer reallocation 114, HCI 112 selects a particular write buffer 182 based on determining that the particular write buffer 182 has a buffer usage metric indicating the lowest utilization rate in the write buffer 182.

[0067] HCI 112 transmits a request 166 indicating that a specific memory resource 181 is to be used for write buffer reallocation 114 of write buffer 182A. In response to receiving request 166, device controller 162 allocates one or more portions of the specific memory resource 181 to write buffer 182A, as referenced. Figures 3 to 9 Further described. For example, device controller 162 updates memory mapping table 180 to indicate that one or more portions are deallocated from a specific memory resource 181 and allocated to write buffer 182A. According to some specific implementations, device controller 162 sends a response 176 to HCI 112 indicating that the write buffer reallocation 114 was successful.

[0068] In a specific aspect, in response to determining that the size of the write buffer 182A is to be reduced as indicated by the resizing instruction 116A, HCI 112 performs write buffer deallocation 120, as referenced. Figure 10 Further described. For example, HCI 112 transmits a request 166 indicating that write buffer deallocation 120 should be performed on write buffer 182A. In response to receiving request 166, device controller 162 deallocates one or more portions of write buffer 182A. For example, device controller 162 updates memory mapping table 180 to indicate that the one or more portions are deallocated from write buffer 182A. In some aspects, device controller 162 transmits a response 176 to HCI 112 indicating that write buffer deallocation 120 was successful.

[0069] In some aspects, device controller 162 resets buffer usage metric 174A in response to performing write buffer reallocation 114 or write buffer deallocation 120. According to some specific implementations, device controller 162 reassigns the one or more portions of write buffer 182A that have been deallocated to one or more memory resources in memory resource 181 (other than write buffer 182A). For example, device controller 162 selects the one or more memory resources in memory resource 181 based on memory resource usage metric 118 (e.g., buffer usage metric 174, logic cell usage metric, or a combination thereof).

[0070] Device controller 162 updates the usage metrics of any resized memory resources. For example, device controller 162 resets (e.g., resets to 0) the buffer usage metric 174 of any resized write buffer 182. In a particular aspect, device controller 162 recalculates the logical unit usage metric of any resized logical unit 168, as referenced. Figure 3 Further description.

[0071] The technical advantage of adjusting the size of write buffer 182A based on buffer usage metric 174A includes dynamically adjusting the size of write buffer 182A in response to changes in usage. For example, when the usage rate of write buffer 182A is above a high usage threshold, more memory space can be allocated to write buffer 182A to reduce the frequency at which write buffer 182A reaches full capacity and becomes unavailable for additional data writes before a refresh of write buffer 182A is performed. Alternatively, when the usage rate of write buffer 182A is below a low usage threshold, less memory space can be allocated to write buffer 182A so that more memory space can be available for other uses.

[0072] It should be understood that the specific order of operations in the examples above or other examples described herein is provided for illustrative purposes and not for limitation. In other examples, two or more operations may be performed in a different order. In some examples, device controller 162 may push information to host device 102. For illustration, device controller 162 provides host device 102 with memory resource usage metric 118, notification 178, or both, independently of HCI 112 transmitting requests. In some examples, HCI 112 may pull information from flash memory device 104. For illustration, device controller 162 provides host device 102 with one or more buffer usage metrics 174, memory resource usage metric 118, or a combination thereof in response to receiving one or more requests 166 from host device 102. In some examples, HCI 112 may maintain information locally. For illustration, HCI 112 may maintain memory resource usage metric 118 and access memory resource usage metric 118 when notification 178 is received.

[0073] refer to Figure 2A This shows that it can be generated by Figure 1 The system 100 performs a specific exemplary aspect of obtaining an adjustment instruction, as illustrated in diagram 200. The host device 102 includes a buffer coupled to the HCI 112 using a threshold register 272.

[0074] The buffer usage threshold register 272 is configured to store a low buffer usage threshold 242, a high buffer usage threshold 244, or both. In one example, the buffer usage threshold register 272 has a specific size (e.g., 16 bits). The first half of the buffer usage threshold register 272 (e.g., bits 0 to 7) is used to store the low buffer usage threshold 242, and the second half of the buffer usage threshold register 272 (e.g., bits 8 to 15) is used to store the high buffer usage threshold 244.

[0075] It should be understood that the buffer usage threshold register 272, which stores the buffer usage low threshold 242, the buffer usage high threshold 244, or both, is provided as an illustrative example. In other examples, the buffer usage threshold register 272 may be included in HCI 112, or another type of data storage device coupled to (or included in) HCI 112 may be used to store the buffer usage low threshold 242, the buffer usage high threshold 244, or both. In a particular aspect, the buffer usage low threshold 242, the buffer usage high threshold 244, or both are based on user input, default data, configuration settings, or a combination thereof.

[0076] According to some specific implementations, HCI 112 transmits a buffer usage metric initialization request 274 to device controller 162 to initialize one or more buffer usage metrics 174. In response to receiving the buffer usage metric initialization request 274, device controller 162 sets each of the one or more buffer usage metrics 174 to an initial value (e.g., 0) and monitors the full detection of one or more write buffers 182 to update one or more buffer usage metrics 174 when write buffer mode 170 is enabled. For example, in response to detecting that write buffer 182A has reached full capacity and that data from write buffer 182A is to be flushed to the corresponding logic unit in logic unit 168, device controller 162 updates (e.g., increments by 1) the buffer usage metric 174A of write buffer 182A. Therefore, buffer usage metric 174A indicates the full buffer detection count of write buffer 182A.

[0077] HCI 112 may periodically or at different times transmit buffer usage metric requests 276 (e.g., write booster buffer full count READ instructions or write booster buffer full count ALL READ instructions) to device controller 162. In some implementations, when shared buffer mode 172 is enabled, the write booster buffer full count READ instruction corresponds to a request for buffer usage metrics for a single shared write buffer. When shared buffer mode 172 is disabled (e.g., dedicated buffer mode is enabled), the write booster buffer full count READ instruction specifically identifies one or more dedicated write buffers requesting their buffer usage metrics. The write booster buffer full count ALL READ instruction corresponds to a request for buffer usage metrics for all write buffers (such as a single shared write buffer when shared buffer mode 172 is enabled, or all dedicated write buffers when shared buffer mode 172 is disabled). When shared buffer mode 172 is enabled, the write booster buffer full count ALL READ instruction therefore corresponds to the write booster buffer full count READ instruction.

[0078] In response to receiving a buffer usage metric request 276, device controller 162 transmits a buffer usage metric 174A for write buffer 182A to host device 102. In some implementations, device controller 162 transmits buffer usage metric 174A to host device 102 in response to determining the buffer usage rate of write buffer 182A indicated by buffer usage metric request 276 (e.g., a write booster buffer full count READ instruction). Alternatively, write buffer 182A corresponds to a shared write buffer (e.g., a single write buffer), and device controller 162 transmits buffer usage metric 174A to host device 102 in response to receiving buffer usage metric request 276 (e.g., a write booster buffer full count READ instruction or a write booster buffer full count ALL READ instruction).

[0079] HCI 112 compares buffer usage metric 174A with a low buffer usage threshold 242, a high buffer usage threshold 244, or both, to obtain a resizing indication 116A. In a particular aspect, the low buffer usage threshold 242 corresponds to a lower limit of the usage rate that triggers write buffer resizing. For example, in response to determining that buffer usage metric 174A is less than the low buffer usage threshold 242, HCI 112 generates a reduction resizing indication 214 as a resizing indication 116A indicating that the size of write buffer 182A should be reduced.

[0080] In a specific aspect, the high threshold 244 for buffer usage corresponds to the upper limit of the usage rate that triggers write buffer resizing. For example, in response to determining that the buffer usage metric 174A is greater than the high threshold 244, HCI 112 generates an increase size indication 216 as a resizing indication 116A indicating that the size of write buffer 182A should be increased. In another example, in response to determining that the buffer usage metric 174A is greater than or equal to the low threshold 242 for buffer usage and less than or equal to the high threshold 244 for buffer usage, HCI 112 generates a no change indication 218 as a resizing indication 116A indicating that the size of write buffer 182A should remain unchanged.

[0081] Therefore, HCI 112 can obtain the buffer usage metric 174A of the write buffer 182A and perform a comparison of the buffer usage metric 174A with the buffer usage low threshold 242, the buffer usage high threshold 244, or both to generate a resizing indication 116A.

[0082] refer to Figure 2B This shows that it can be generated by Figure 1The system 100 executes a specific exemplary aspect of obtaining an adjustment instruction, as illustrated in Figure 250. HCI 112 may periodically or at different times transmit buffer usage metric requests 276 to device controller 162. In response to receiving buffer usage metric request 276 (e.g., a write buffer full count ALL READ instruction), device controller 162 transmits buffer usage metric 174 to host device 102.

[0083] HCI 112 compares buffer usage metric 174 with a low buffer usage threshold 242, a high buffer usage threshold 244, or both to generate a resizing indication 116. For example, HCI 112 generates a resizing indication 116A for write buffer 182A based on a comparison of buffer usage metric 174A with a low buffer usage threshold 242, a high buffer usage threshold 244, or both, as referenced. Figure 2A As described. As another example, HCI 112 generates a resizing indication 116B for writing buffer 182B based on a comparison of buffer usage metric 174B with a low buffer usage threshold 242, a high buffer usage threshold 244, or both. Similarly, in some specific implementations, HCI 112 generates one or more additional resizing indications, such as a resizing indication 116C for writing buffer 182C, based on a comparison of buffer usage metric 174C with a low buffer usage threshold 242, a high buffer usage threshold 244, or both.

[0084] Therefore, HCI 112 can obtain buffer usage metrics 174 for multiple write buffers 182 and perform a comparison of buffer usage metrics 174 with a low buffer usage threshold 242, a high buffer usage threshold 244, or both to generate a resizing instruction 116. (See reference...) Figures 2A to 2B The technical advantages described above for performing comparisons at HCI 112 may include support for flash memory devices (e.g., legacy devices) that are not configured to perform comparisons with buffer usage low threshold 242, buffer usage high threshold 244, or both.

[0085] According to some specific implementations, HCI 112 performs write buffer reallocation 114 on one or more write buffers in write buffer 182 that have an increment size indication 216. For example, in response to determining that write buffer 182A has an increment size indication 216, HCI 112 selects a specific memory resource 181 based on memory resource usage metric 118 and sends a request 166 to device controller 162 to reallocate one or more portions of the specific memory resource 181 to write buffer 182A, as referenced. Figure 1As described. Similarly, in response to determining that write buffer 182B has an increase size indication 216, HCI 112 selects a specific memory resource 181 (which has not been resized after the resizing indication 116 was generated) based on memory resource usage metric 118, and transmits a request 166 to device controller 162 to reallocate one or more portions of the specific memory resource 181 to write buffer 182B.

[0086] According to some specific implementations, HCI 112 performs write buffer reallocation 120 on any write buffer 182 that has a reduction size indication 214 and has not been reduced in size during write buffer reallocation 114. For example, in response to determining that write buffer 182C has a reduction size indication 214 and that the size of write buffer 182C has not been reduced to increase the size of write buffer 182A or write buffer 182B, HCI 112 transmits a request 166 to device controller 162 to deallocate one or more portions of write buffer 182C, as referenced. Figure 10 Further described. Device controller 162 updates usage metrics for any resized memory resources.

[0087] refer to Figure 2C This shows that it can be generated by Figure 1 The system 100 performs a specific exemplary aspect of obtaining resizing instructions, as illustrated in Figure 280. The flash memory device 104 includes a buffer using a threshold register 282 coupled to the device controller 162.

[0088] The buffer usage threshold register 282 is configured to store a low buffer usage threshold 242, a high buffer usage threshold 244, or both. In one example, the buffer usage threshold register 282 has a specific size (e.g., 16 bits). The first half of the buffer usage threshold register 282 (e.g., bits 0 to 7) is used to store the low buffer usage threshold 242, and the second half of the buffer usage threshold register 282 (e.g., bits 8 to 15) is used to store the high buffer usage threshold 244.

[0089] It should be understood that the buffer usage threshold register 282, which stores the buffer usage low threshold 242, the buffer usage high threshold 244, or both, is provided as an illustrative example. In other examples, the buffer usage threshold register 282 may be included in the device controller 162, or another type of data storage device coupled to (or included in) the device controller 162 may be used to store the buffer usage low threshold 242, the buffer usage high threshold 244, or both.

[0090] Depending on the specific implementation, HCI 112 transmits request 166 to device controller 162 (e.g., Figure 2A The buffer usage metric initialization request 274 or another request is used to activate buffer usage notification. In an exemplary embodiment, request 166 includes an attribute (e.g., an attribute indicating whether low buffer usage notification is enabled, such as a write buffer full count low enable bit) and a second field indicating whether high buffer usage notification is enabled, such as a write buffer full count high enable bit, or both.

[0091] In response to determining that the first field has a first value (e.g., 1), device controller 162 enables low usage notification mode 230, which indicates that when buffer usage metric 174 is less than buffer usage low threshold 242, device controller 162 will send buffer usage notification 284 to host device 102 (e.g., Figure 1 Notification 178). In response to determining that the second field has a first value (e.g., 1), device controller 162 enables high usage notification mode 232, which indicates that device controller 162 will send buffer usage notification 284 (e.g., ...) to host device 102 when buffer usage metric 174 is greater than buffer usage high threshold 244. Figure 1 Notice 178).

[0092] Device controller 162 may (e.g., in response to a buffer usage metric update) periodically or at different times compare one or more buffer usage metrics 174 with a low buffer usage threshold 242, a high buffer usage threshold 244, or both. For example, in response to an update to buffer usage metric 174A and determining that low usage notification mode 230 is enabled, device controller 162 compares buffer usage metric 174A with the low buffer usage threshold 242.

[0093] In some specific implementations, an exception is triggered based on a comparison of buffer usage metric 174A performed at device controller 162 with a buffer usage low threshold 242. For example, an exception is triggered when buffer usage metric 174A is less than buffer usage low threshold 242. In response to detecting an exception, device controller 162 determines that buffer usage metric 174A is less than buffer usage low threshold 242.

[0094] In response to determining that low usage notification mode 230 is enabled and that buffer usage metric 174A is less than buffer usage low threshold 242, device controller 162 generates buffer usage notification 284 and transmits buffer usage notification 284 to host device 102. Buffer usage notification 284 indicates that buffer usage metric 174A written to buffer 182A is less than buffer usage low threshold 242.

[0095] In an exemplary implementation, buffer usage notification 284 includes an attribute (e.g., an exception event status attribute) having a first field (e.g., write buffer full count low bit) for indicating whether the buffer usage metric is less than a buffer usage low threshold 242. For example, device controller 162 generates buffer usage notification 284 where the first field (e.g., write buffer full count low bit) is set to a first value (e.g., 1) to indicate that the buffer usage metric 174A for writing to buffer 182A is below the buffer usage low threshold 242. In one example, buffer usage notification 284 also includes an identifier for writing to buffer 182A.

[0096] In response to receiving a buffer usage notification 284 indicating that the buffer usage metric 174A of the write buffer 182A is below the buffer usage low threshold 242, HCI 112 generates a reduction size indication 214 as an adjustment size indication 116A for the write buffer 182A.

[0097] In another example, in response to an update of the buffer usage metric 174A and determination that high usage notification mode 232 is enabled, device controller 162 compares the buffer usage metric 174A with a buffer usage high threshold 244. Depending on some specific implementations, an exception is triggered based on the comparison of buffer usage metric 174A with the buffer usage high threshold 244 performed at device controller 162. For example, an exception is triggered when the buffer usage metric 174A is greater than the buffer usage high threshold 244. In response to detecting an exception, device controller 162 determines that the buffer usage metric 174A is greater than the buffer usage high threshold 244.

[0098] In response to determining that the buffer usage metric 174A is greater than the buffer usage high threshold 244, the device controller 162 generates a buffer usage notification 284 indicating that the buffer usage metric 174A is greater than the buffer usage high threshold 244 when written to buffer 182A.

[0099] In response to determining that high usage notification mode 232 is enabled and buffer usage metric 174A is greater than buffer usage high threshold 244, device controller 162 generates buffer usage notification 284 and transmits buffer usage notification 284 to host device 102. Buffer usage notification 284 indicates that buffer usage metric 174A written to buffer 182A is greater than buffer usage low threshold 242.

[0100] In an exemplary implementation, buffer usage notification 284 includes an attribute (e.g., an exception event status attribute) having a second field (e.g., a write buffer full count high bit) for indicating whether the buffer usage metric is greater than the buffer usage high threshold 244. For example, device controller 162 generates buffer usage notification 284 in which the second field (e.g., write buffer full count high bit) is set to a first value (e.g., 1) to indicate that the buffer usage metric 174A for writing to buffer 182A is higher than the buffer usage high threshold 244. In one example, buffer usage notification 284 also includes an identifier for writing to buffer 182A.

[0101] In response to receiving a buffer usage notification 284 indicating that the buffer usage metric 174A of the write buffer 182A is greater than the buffer usage high threshold 244, HCI 112 generates an increase size indication 216 as an adjustment size indication 116A for the write buffer 182A.

[0102] Therefore, HCI 112 may receive buffer usage notification 284 based on a comparison of one or more buffer usage metrics 174 performed at flash memory device 104 with a buffer usage low threshold 242, a buffer usage high threshold 244, or both. HCI 112 may generate one or more resizing instructions 116 based on one or more buffer usage notifications 284. The technical advantage of enabling device controller 162 to perform the comparison locally may include: transmitting notifications to host device 102 when buffer usage metrics 174 are outside the buffer usage threshold using fewer communication resources compared to transmitting one or more buffer usage metrics 174 to host device 102 for each comparison with the buffer usage threshold.

[0103] Figures 3 to 6 An example is shown where the logic unit is used to write buffer reallocation 114. Figure 3 An example of a component of system 100 that can use logic units for write buffer reallocation 114 is illustrated. Figure 4 An example is shown of using a logic unit to reallocate a write buffer 114 to a shared write buffer. Figure 5 An example is shown of using logic units to reallocate write buffer 114 to a dedicated write buffer. Figure 6 A ladder diagram including an illustrative example of using logic units for write buffer reallocation 114.

[0104] refer to Figure 3 This shows that it can be generated by Figure 1Figure 300 illustrates an illustrative aspect of the write buffer allocation 114 performed by system 100. HCI 112 receives an increase-size indication 216 as an adjustment-size indication 116A for write buffer 182A, as shown in the reference. Figures 2A to 2C As described.

[0105] HCI 112 determines whether a logic cell or write buffer is to be used for write buffer reallocation 114. Depending on some specific implementations, HCI 112 may access indicators (e.g., copies thereof) of write buffer mode 170, shared buffer mode 172, and buffer reallocation mode 160 of the flash memory device 104. In response to determining that shared buffer mode 172 is enabled or that shared buffer mode 172 is disabled and buffer reallocation mode 160 is disabled, HCI 112 determines that a logic cell is to be used for write buffer reallocation 114. Alternatively, in response to determining that shared buffer mode 172 is disabled and buffer reallocation mode 160 is enabled, HCI 112 determines that a write buffer is to be used for write buffer reallocation 114.

[0106] In response to determining that a logic cell is to be used for write buffer reallocation 114, HCI 112 obtains the logic cell usage metric 318 of logic cell 168. In a particular aspect, the logic cell usage metric 318 includes the logic cell usage metric 318A of logic cell 168A, the logic cell usage metric 318B of logic cell 168B, the logic cell usage metric 318C of logic cell 168C, one or more additional logic cell usage metrics of one or more additional logic cells, or a combination thereof.

[0107] In certain aspects, logical unit usage metric 318 includes an availability metric, a utilization metric, or both for logical unit 168. For example, logical unit usage metric 318A includes an availability metric, a utilization metric, or both for logical unit 168A. In certain aspects, the availability metric for logical unit 168A corresponds to the unused storage capacity of logical unit 168A. In certain aspects, the utilization metric for logical unit 168A is based on the data access count at logical unit 168A.

[0108] According to some specific implementations, HCI 112 maintains a logic cell usage metric 318 during operation of the flash memory device 104. For example, in response to accessing data stored in logic cell 168A, HCI 112 updates (e.g., increments by 1) the utilization metric indicated by logic cell usage metric 318A. In one aspect, HCI 112 updates the utilization metric indicated by logic cell usage metric 318A in response to a request 166 to be transmitted to the flash memory device 104 to access (e.g., read or write) data at a memory location in logic cell 168A. In another aspect, HCI 112 updates the utilization metric indicated by logic cell usage metric 318A in response to a response 176 to receiving data from the flash memory device 104 to access a memory location in logic cell 168A (e.g., reading the data from or writing the data to the memory location).

[0109] In one example, in response to writing data to a previously unused portion of logic unit 168A, HCI 112 decreases the availability metric indicated by metric 318A used by the logic unit. Alternatively, in response to deleting data from a portion of logic unit 168A, HCI 112 increases the availability metric indicated by metric 318A used by the logic unit.

[0110] In a particular aspect, HCI 112 updates the utilization metric indicated by metric 318A of the logic cell in response to allocating or deallocating one or more portions of the memory to logic cell 168A. In one example, HCI 112 maintains a partial utilization metric. HCI 112 increases the utilization metric indicated by metric 318A of the logic cell based on the partial utilization metric of the portion reassigned to logic cell 168A. Alternatively, HCI 112 decreases the utilization metric indicated by metric 318A of the logic cell based on the partial utilization metric of the portion deallocated from logic cell 168A.

[0111] In a particular aspect, HCI 112 updates the availability metric indicated by the logic cell using metric 318A in response to allocating or deallocating one or more portions of memory to logic cell 168A. For example, HCI 112 increases the availability metric indicated by the logic cell using metric 318A based on the size of one or more portions reallocated to logic cell 168A. As another example, HCI 112 decreases the availability metric indicated by the logic cell using metric 318A based on the size of one or more portions deallocated from logic cell 168A.

[0112] According to some specific implementations, device controller 162 maintains logic cell usage metric 318, and HCI 112 obtains logic cell usage metric 318 from device controller 162. In one example, in response to accessing data stored in logic cell 168A, device controller 162 updates (e.g., increments by 1) the utilization metric indicated by logic cell usage metric 318A. In a particular aspect, device controller 162 updates the utilization metric indicated by logic cell usage metric 318A in response to accessing (e.g., reading or writing) data at a memory location in logic cell 168A. In a particular aspect, device controller 162 performs operations similar to those described with reference to HCI 112 to update the utilization metric, availability metric, or both indicated by logic cell usage metric 318A in response to allocating or deallocating one or more portions of memory to logic cell 168A.

[0113] In some specific implementations where the logic unit uses metric 318 to maintain the logic unit at device controller 162, HCI 112, in response to determining that resizing instruction 116A indicates that the size of write buffer 182A needs to be increased and that the logic unit needs to be used for write buffer reallocation 114, transmits a request 166 for the logic unit to use metric 318. Device controller 162 transmits a response 176 to host device 102 instructing the logic unit to use metric 318.

[0114] HCI 112 uses metric 318 based on the logic unit to generate resizing metric 320. For example, resizing metric 320 includes resizing metric 320A for write buffer 182A, resizing metric 320B for write buffer 182B, resizing metric 320C for write buffer 182C, one or more additional resizing metrics for one or more additional write buffers, or combinations thereof.

[0115] The size adjustment metric 320A is based on an availability metric, utilization metric, or both indicated by the logic unit using metric 318A. In a particular implementation, the size adjustment metric 320A corresponds to a weighted sum of the availability metric and the utilization metric. For example, R = W1 A - W2 U, where R corresponds to the size adjustment metric, A corresponds to the availability metric, U corresponds to the utilization metric, W1 and W2 correspond to the weights, and " "Indicates a multiplication operation. In response to receiving an increase size indication 216 for write buffer 182A and determining that a logic cell is to be used for write buffer reallocation 114, HCI 112 selects a logic cell from logic cells 168 based on adjustment size metric 320. For example, HCI 112 selects logic cell 168B in response to determining that adjustment size metric 320B has the highest value in adjustment size metric 320 (which indicates that logic cell 168B has the lowest utilization rate among logic cells 168)."

[0116] In Example 350, HCI 112 initiates a conversion of a portion 352 of logic cell 168B from a first memory type (e.g., TLC) to a second memory type (e.g., SLC) and reallocates the portion 352 of logic cell 168B to write buffer 182A. For example, HCI 112 transmits a request 166 (e.g., a query request indicating WRITE write enhancer buffer resizing enable and the identifier (LUID) of logic cell 168B) to flash memory device 104, instructing logic cell 168B to be used for write buffer reallocation 114 of write buffer 182A. In response to receiving request 166, device controller 162 selects a portion 352 of logic cell 168B that is available (e.g., not used for storing data) and has a predetermined size for write buffer reallocation 114. In one example, portion 352 corresponds to one or more memory address ranges 190BA.

[0117] Device controller 162 releases portion 352 from logic unit 168B. For example, device controller 162 updates memory mapping table 180 to remove one or more memory address ranges 190BA from one or more memory address ranges 190B allocated to logic unit 168B. Device controller 162 converts memory cells corresponding to one or more memory address ranges 190BA from having a first memory type (e.g., TLC) to a second memory type (e.g., SLC).

[0118] Device controller 162 reassigns portion 352 to write buffer 182A. For example, device controller 162 updates memory mapping table 180 to add one or more memory address ranges 190BA (in addition to one or more memory address ranges 184A) to be assigned to write buffer 182A. Device controller 162 sends response 176 to HCI 112 to indicate that one or more memory address ranges 190BA have been reassigned from logic cell 168B to write buffer 182A.

[0119] In some implementations, HCI 112 may activate buffer resizing notification at flash memory device 104. For example, HCI 112 sends request 166 to device controller 162 (e.g., Figure 2A The buffer uses a metric initialization request 274 or another request to enable buffer resizing notification. In an exemplary implementation, request 166 includes an attribute (e.g., an exception event control attribute) with a specific field (e.g., a resizing request completion enable bit) indicating whether buffer resizing notification should be enabled.

[0120] In response to determining that a specific field has a first value (e.g., 1), device controller 162 enables resizing notification mode 370, which indicates that when a buffer resizing operation is completed at device controller 162, device controller 162 will send a buffer resizing notification 378 to host device 102 (e.g., ...). Figure 1 Notification 178). For example, in response to performing a write buffer reallocation 114 of write buffer 182A when resizing notification mode 370 is enabled, device controller 162 transmits a buffer resizing notification 378 to host device 102 indicating that the write buffer reallocation 114 of write buffer 182A has been successful. In some specific implementations, buffer resizing notification 378 indicates that one or more memory address ranges 190BA have been reallocated from logic unit 168B to write buffer 182A.

[0121] In an exemplary implementation, the buffer resizing notification 378 includes attributes (e.g., an exception event status attribute) having specific fields (e.g., a resizing request completion bit) for indicating whether the buffer resizing was successful. For example, when resizing notification mode 370 is enabled, the device controller 162 transmits the buffer resizing notification 378 after performing a write buffer reallocation 114, wherein the specific field (e.g., the resizing request completion bit) is set to a first value (e.g., 1).

[0122] exist Figure 4 The diagram shows the execution of a shared write buffer. Figure 3 Figure 400 illustrates an exemplary aspect of the write buffer reallocation 114. For example, write buffer 182A is a shared write buffer used as a temporary storage device for logic unit 168, and a portion 352 of logic unit 168B is reallocated to write buffer 182A.

[0123] exist Figure 5 The diagram shows the execution of a dedicated write buffer. Figure 3Figure 500 illustrates an exemplary aspect of write buffer allocation 114. For example, write buffer 182A is a dedicated write buffer used as a temporary storage device for logic unit 168A, and a portion 352 of logic unit 168B is reallocated to write buffer 182A. Any logic unit in logic unit 168 can be used to perform write buffer reallocation 114 on any write buffer in write buffer 182 based on logic unit usage metric 318.

[0124] refer to Figure 6 It shows the relationship with Figure 3 A step diagram 600 illustrates the aspects of the operation associated with write buffer allocation 114. At 610, HCI 112 determines the identifier of the logic cell 168 having the highest adjustment size metric among the adjustment size metric 320. For example, in response to obtaining an increase size indication 216 as an adjustment size indication 116A for write buffer 182A and determining that a logic cell is to be used for write buffer reallocation 114, HCI 112 selects the logic cell 168B having the highest adjustment size metric 320B among the adjustment size metric 320, as referenced. Figure 3 As described. HCI 112 determines the identifier of logic unit 168B.

[0125] HCI 112 sends request 602 to flash memory device 104 (e.g., device controller 162). In one example, request 602 (e.g., write enhancer buffer resizing enable WRITE instruction) instructs logic cell 168B (e.g., identifier (LUID) of logic cell 168B). In a particular aspect, request 602 also instructs write buffer 182A (e.g., identifier of write buffer 182A).

[0126] At 612, device controller 162 reallocates memory from logic cell 168B of a first memory type (e.g., TLC) to write buffer 182A of a second memory type (e.g., SLC). For example, device controller 162 deallocates one or more memory address ranges 190BA from logic cell 168B, converts one or more memory address ranges 190BA from the first memory type (e.g., TLC) to the second memory type (e.g., SLC), and reallocates one or more memory address ranges 190BA to write buffer 182A, as referenced. Figure 3 As described.

[0127] Device controller 162 transmits a response 604 to host device 102 (e.g., HCI 112) indicating that write buffer reallocation 114 was successful. In a particular aspect, response 604 indicates that one or more memory address ranges 190BA are reallocated from logic cell 168B to write buffer 182A. In a particular aspect, response 604 corresponds to Figure 3 Buffer resizing notification 378.

[0128] The technical advantages of using logical units for write buffer reallocation 114 may include enabling write buffer reallocation when a single shared write buffer exists. The technical advantages of using logical units for write buffer reallocation 114 when multiple dedicated write buffers exist may include fewer resizing operations that must be performed at write buffer 182. For example, deallocating a portion of a particular write buffer to increase the size of another write buffer can cause that particular write buffer to be filled to capacity more frequently and subsequently require resizing.

[0129] Figures 7 to 9 An example is shown in which a write buffer is used to reallocate a write buffer 114 to another write buffer. Figure 7 An example of a component of a system 100 that can use a write buffer to reallocate a write buffer 114 to another write buffer is illustrated. Figure 8 An example is shown of using a write buffer to reallocate a write buffer 114 to a dedicated write buffer. Figure 9 A ladder diagram including an illustrative example of using a write buffer to reallocate a write buffer 114 to another write buffer.

[0130] refer to Figure 7 This shows that it can be generated by Figure 1 Figure 700 illustrates an exemplary aspect of the write buffer allocation performed by system 100. HCI 112 obtains an increase-size indication 216 as an adjustment-size indication 116A for write buffer 182A, as referenced. Figures 2A to 2C As described.

[0131] HCI 112 determines whether a logic cell or write buffer should be used for write buffer reallocation 114, as referenced. Figure 3 As described. For example, in response to determining that shared buffer mode 172 is disabled and buffer reallocation mode 160 is enabled, HCI 112 determines that the write buffer is to be used for write buffer reallocation 114.

[0132] In response to determining that a write buffer is to be used for write buffer reallocation 114, HCI 112 obtains one or more buffer usage metrics 174 from device controller 162. For example, in response to determining that resizing instruction 116A indicates that the size of write buffer 182A is to be increased and that the write buffer is to be used for write buffer reallocation 114, HCI 112 transmits a request 166 to flash memory device 104 for one or more buffer usage metrics 174. Device controller 162 transmits a response 176 to host device 102 indicating one or more buffer usage metrics 174.

[0133] In response to receiving an increase size indication 216 for write buffer 182A and determining that a write buffer is to be used for write buffer reallocation 114, HCI 112 selects one of the write buffers 182 based on one or more buffer usage metrics 174. For example, HCI 112 selects write buffer 182B in response to determining that buffer usage metric 174B indicates that write buffer 182B has the lowest utilization rate among the write buffers 182.

[0134] In a particular aspect, HCI 112 further selects write buffer 182B based on determining that buffer usage metric 174B is less than or equal to buffer usage high threshold 244. Alternatively, in response to determining that buffer usage metric 174B indicates the lowest utilization of write buffer 182B but buffer usage metric 174B is higher than buffer usage high threshold 244, HCI 112 determines that the size of all write buffers needs to be increased and that no write buffer is available for reallocation. In some aspects, HCI 112 provides an alert to host device 102 in response to determining that the size of all write buffers needs to be increased and that no write buffer is available for reallocation. In some specific implementations, in response to determining that the size of all write buffers needs to be increased and that no write buffer is available for reallocation, HCI 112 disables buffer reallocation mode 160, such that write buffer reallocation 114 can be performed using a logical unit, as referenced. Figure 3 As described. At a later time, HCI 112 may enable buffer reallocation mode 160 in response to determining that at least one write buffer 182 has a buffer usage metric 174 that is less than a buffer usage low threshold 242.

[0135] In Example 750, in response to selecting write buffer 182B for write buffer reallocation 114, HCI 112 initiates a reallocation of a portion 752 of write buffer 182B to write buffer 182A. For example, HCI 112 transmits a request 166 (e.g., a query request indicating WRITE write enhancer buffer resizing enable and the identifier (WBID) of write buffer 182B) to flash memory device 104, indicating that write buffer 182B should be used for write buffer reallocation 114 of write buffer 182A. Upon receiving request 166, device controller 162 selects a portion 752 of write buffer 182B with a predetermined size for write buffer reallocation 114. The portion 752 corresponds to one or more memory address ranges 184BA.

[0136] Device controller 162 deals with write buffer 182B from write buffer 182B. For example, device controller 162 updates memory mapping table 180 to remove one or more memory address ranges 184BA from one or more memory address ranges 184B allocated to write buffer 182B. In a particular aspect, device controller 162 performs a refresh of write buffer 182B before dealing with write buffer 182B from write buffer 182B. For example, device controller 162 performs a refresh of write buffer 182B in response to determining that portion 752 is being used to store data.

[0137] Device controller 162 reassigns portion 752 to write buffer 182A. For example, device controller 162 updates memory mapping table 180 to add one or more memory address ranges 184BA (in addition to one or more memory address ranges 184A) to be assigned to write buffer 182A. Device controller 162 sends response 176 to HCI 112 to indicate that one or more memory address ranges 184BA have been reassigned from write buffer 182B to write buffer 182A.

[0138] In some examples, in response to performing a write buffer reallocation 114 of write buffer 182A when resizing notification mode 370 is enabled, device controller 162 transmits a buffer resizing notification 378 to host device 102 indicating that the write buffer reallocation 114 of write buffer 182A was successful. In some specific implementations, buffer resizing notification 378 indicates that one or more memory address ranges 184BA have been reallocated from write buffer 182B to write buffer 182A. For example, when resizing notification mode 370 is enabled, device controller 162 transmits buffer resizing notification 378 after performing write buffer reallocation 114, wherein a specific field (e.g., resizing request complete bit) is set to a first value (e.g., 1).

[0139] exist Figure 8 The diagram shows the execution of a dedicated write buffer. Figure 7 Figure 800 illustrates an exemplary aspect of the write buffer allocation 114. For example, write buffer 182A is a dedicated write buffer used as a temporary storage device for logic unit 168A, write buffer 182B is a dedicated write buffer used as a temporary storage device for logic unit 168B, and a portion 752 of write buffer 182B is reassigned to write buffer 182A.

[0140] refer to Figure 9 It shows the relationship with Figure 7 A ladder diagram 900 illustrates the illustrative aspects of the operation associated with the write buffer allocation 114. HCI 112 transmits a request 902 (e.g., write buffer full count ALL READ instruction) to flash memory device 104 (e.g., device controller 162) for buffer usage metric 174.

[0141] At 910, in response to receiving request 902, device controller 162 sends response 904 to host device 102 (e.g., HCI 112) indicating buffer usage metric 174. For example, response 904 includes an identifier for writing to buffer 182 and the corresponding buffer usage metric 174.

[0142] At 912, HCI 112 identifies the identifier of the write buffer with the lowest buffer usage metric among buffer usage metrics 174. For example, in response to obtaining an increase size indication 216 as an adjustment size indication 116A for write buffer 182A and determining that a write buffer is to be used for write buffer reallocation 114, HCI 112 selects the write buffer 182B with the lowest buffer usage metric 174B among buffer usage metrics 174, as referenced. Figure 7As described. HCI 112 identifies the identifier for write buffer 182B.

[0143] HCI 112 sends request 906 to flash memory device 104 (e.g., device controller 162). In one example, request 906 (e.g., write booster buffer resizing enable WRITE instruction) instructs write buffer 182B (e.g., the identifier (WBID) of write buffer 182B). In a particular aspect, request 906 also instructs write buffer 182A (e.g., the identifier of write buffer 182A).

[0144] At 914, device controller 162 reallocates memory from write buffer 182B of the second memory type (e.g., SLC) to write buffer 182A of the second memory type (e.g., SLC). For example, device controller 162 releases one or more memory address ranges 184BA from write buffer 182B of portion 752 and allocates one or more memory address ranges 184BA to write buffer 182A, as referenced. Figure 7 As described, device controller 162 transmits a response 908 to host device 102 (e.g., HCI 112) indicating that write buffer reallocation 114 was successful. In a particular aspect, response 908 indicates that one or more memory address ranges 184BA are reallocated from write buffer 182B to write buffer 182A. In a particular aspect, response 908 corresponds to buffer resizing notification 378, as referenced. Figure 7 As described.

[0145] The technical advantages of using write buffers for write buffer reallocation 114 may include setting a predetermined memory space for write buffers, which can be dynamically allocated among write buffers based on buffer utilization. In some aspects, when no write buffer is available for write buffer reallocation 114, buffer reallocation mode 160 can be disabled to use logic units for write buffer reallocation 114.

[0146] refer to Figure 10 This shows that it can be generated by Figure 1 The illustration 1000 shows an example of the write buffer deallocation performed by the system 100. HCI 112 obtains a reduction indication 214 as a resizing indication 116A for the write buffer 182A, as shown in the reference. Figures 2A to 2C As described.

[0147] In Example 1050, in response to receiving a reduction instruction 214, HCI 112 initiates a deallocation of a portion 1052 of write buffer 182A. For example, HCI 112 transmits a request 166 (e.g., a query request indicating write booster buffer resizing enable and the identifier (WBID) of write buffer 182A) to flash memory device 104, indicating that write buffer deallocation 120 of write buffer 182A should be performed. Upon receiving request 166, device controller 162 selects a portion 1052 of write buffer 182B with a predetermined size for write buffer deallocation 120. Portion 1052 corresponds to one or more memory address ranges 184AA.

[0148] Device controller 162 deals with write buffer 182A from write buffer 182A in section 1052. For example, device controller 162 updates memory mapping table 180 to remove one or more memory address ranges 184AA from one or more memory address ranges 184A allocated to write buffer 182A. In a particular aspect, device controller 162 performs a refresh of write buffer 182A prior to deallocation section 1052. For example, device controller 162 performs a refresh of write buffer 182A in response to determining that section 1052 is being used to store data.

[0149] Device controller 162 sends a response 176 to host device 102 indicating that write buffer deallocation 120 was successful. In some implementations, response 176 indicates that one or more memory address ranges 184AA are deallocated from write buffer 182A.

[0150] In some implementations, in response to performing write buffer deallocation 120 on write buffer 182A when resizing notification mode 370 is enabled, device controller 162 transmits a buffer resizing notification 378 to host device 102 indicating that write buffer deallocation 120 on write buffer 182A was successful. For illustration, buffer resizing notification 378 indicates that one or more memory address ranges 184AA have been deallocated from write buffer 182A. For example, device controller 162 transmits buffer resizing notification 378 after performing write buffer deallocation 120, wherein a specific field (e.g., resizing request complete bit) is set to a first value (e.g., 1).

[0151] According to some specific implementations, in response to determining that shared buffer mode 172 is disabled, device controller 162 reallocates portion 1052 to another write buffer based on buffer usage metric 174. For example, device controller 162 selects buffer usage metric 174B that has the highest utilization rate among buffer usage metrics 174 and reallocates portion 1052 to write buffer 182B. For illustration, device controller 162 updates memory mapping table 180 to add one or more memory address ranges 184AA (in addition to one or more memory address ranges 184B) to be allocated to write buffer 182B. In these specific implementations, response 176 (e.g., buffer resizing notification 378) indicates that one or more memory address ranges 184AA are reallocated to write buffer 182B.

[0152] According to some specific implementations, in response to determining that shared buffer mode 172 is enabled or disabled and that buffer usage metric 174B (e.g., highest buffer usage metric) is below a certain threshold, device controller 162 allocates portion 1052 to logical unit 168B. For example, device controller 162 selects logical unit 168B in response to determining that resizing metric 320B is the lowest resizing metric among resizing metrics 320 (e.g., indicating highest utilization) and allocates portion 1052 to logical unit 168B. For illustration, device controller 162 converts memory cells of one or more memory address ranges 184AA from a second memory type (e.g., SLC) to a first memory type (e.g., TLC) and updates memory mapping table 180 to add one or more memory address ranges 184AA (in addition to one or more memory address ranges 190B) to be allocated to logical unit 168B. In these specific implementations, response 176 (e.g., buffer resizing notification 378) instructs one or more memory address ranges 184AA to be reassigned to logical unit 168B.

[0153] refer to Figure 11 It shows that it can be generated by Figure 1 The step diagram 1100 illustrates an exemplary aspect of the write buffer resizing operations performed by the system. In a particular aspect, one or more of the operations illustrated in step diagram 1100 are performed by… Figure 1 The HCI 112, host device 102, device controller 162, flash memory 164, flash memory device 104, system 100, or a combination thereof, shall be used to perform this action.

[0154] At 1120, device controller 162 determines that buffer usage metric 174A is less than buffer usage low threshold 242. For example, device controller 162 detects an exception that triggers an indication that buffer usage metric 174A is less than buffer usage low threshold 242. Device controller 162 transmits buffer usage metric notification 1102 (e.g., write buffer full count low notification) to host device 102 (e.g., HCI 112). Buffer usage metric notification 1102 indicates that buffer usage metric 174A for write buffer 182A is less than buffer usage low threshold 242.

[0155] At 1122, in response to receiving buffer usage metric notification 1102, HCI 112 determines that a reduction indication 214 has been received as a resizing indication 116A for write buffer 182A. In response to receiving the reduction indication 214 for write buffer 182A, HCI 112 suspends write commands to flash memory device 104 to perform write buffer deallocation 120. In a particular aspect, HCI 112 suspends write commands to flash memory device 104 in response to determining that the command queue at host device 102 is low (e.g., empty) or that the command queue includes few (e.g., none) write commands for flash memory device 104.

[0156] HCI 112 transmits a write buffer reduction request 1104 to flash memory device 104 (e.g., device controller 162). In a particular aspect, the write buffer reduction request 1104 indicates write buffer 182A (e.g., an identifier of write buffer 182A).

[0157] At 1124, in response to receiving a write buffer reduction request 1104, device controller 162 releases portion 1052 of write buffer 182A, as referenced. Figure 10 As described. Device controller 162 sends a response 1106 to host device 102 (e.g., HCI 112) indicating successful write buffer deallocation 120. At 1126, in response to receiving response 1106, HCI 112 resumes sending write commands to flash memory device 104. In a particular aspect, response 1106 corresponds to buffer resizing notification 378, as referenced. Figure 10 As described.

[0158] Subsequently, at 1128, device controller 162 determines that buffer usage metric 174A is greater than buffer usage high threshold 244. For example, device controller 162 detects an exception that indicates buffer usage metric 174A is greater than buffer usage high threshold 244. Device controller 162 transmits buffer usage metric notification 1112 (e.g., write buffer full count high notification) to host device 102 (e.g., HCI 112). Buffer usage metric notification 1112 indicates that buffer usage metric 174A for write buffer 182A is greater than buffer usage high threshold 244.

[0159] At 1130, in response to receiving a buffer usage metric notification 1102, HCI 112 determines that an increase size indication 216 has been received as a resizing indication 116A for write buffer 182A. In response to receiving the increase size indication 216 for write buffer 182A, HCI 112 suspends write commands to flash memory device 104 to perform write buffer reallocation 114. In a particular aspect, HCI 112 suspends write commands to flash memory device 104 in response to determining that the command queue at host device 102 is low (e.g., empty) or that the command queue includes few (e.g., none) write commands for flash memory device 104.

[0160] HCI 112 transmits a write buffer increment request 1114 to flash memory device 104 (e.g., device controller 162). In a particular aspect, write buffer increment request 1114 indicates write buffer 182A (e.g., an identifier of write buffer 182A).

[0161] At 1132, in response to receiving a write buffer increment request 1114, device controller 162 allocates portion 352 of logic unit 168B to write buffer 182A (as referenced). Figure 3 (as described), or allocate portion 752 of write buffer 182B to write buffer 182A (as referenced). Figure 7 (As described). In a particular implementation, HCI 112 selects either logic cell 168B or write buffer 182B for write buffer reallocation 114, as referenced. Figures 3 to 9 As described, the write buffer increment request 1114 instructs either logic unit 168B or write buffer 182B as selected. In another specific embodiment, in response to receiving the write buffer increment request 1114, device controller 162 executes a reference... Figures 3 to 9The HCI 112 describes one or more operations to select either logic unit 168B or write buffer 182B for write buffer reallocation 114. Device controller 162 performs write buffer reallocation 114 to reallocate a portion of logic unit 168B or write buffer 182B to write buffer 182A, as referenced. Figures 3 to 9 As described.

[0162] Device controller 162 transmits a response 1116 to host device 102 (e.g., HCI 112) indicating that write buffer reallocation 114 was successful. In a particular aspect, response 1116 indicates that portion 352 is reassigned from logic unit 168B to write buffer 182A or portion 752 is reassigned from write buffer 182B to write buffer 182A. In a particular aspect, response 1116 corresponds to buffer resizing notification 378, as referenced. Figure 3 and Figure 7 As described. At 1134, in response to receiving response 1116, HCI 112 resumes transmitting write commands to flash memory device 104.

[0163] Figure 12 Based on some examples of this disclosure, it is possible to... Figure 1 A diagram illustrating a specific implementation of a host-managed method 1200 for allocating write buffers to flash memory during system execution. In a particular aspect, one or more operations of method 1200 are performed by… Figure 1 The HCI 112, host device 102, device controller 162, flash memory 164, flash memory device 104, system 100, or a combination thereof, shall be used to perform this action.

[0164] Method 1200 includes: at block 1202, obtaining at a host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) is to be increased, the FMD including multiple memory resources including multiple logical units (LUs) and at least the specific WB. For example, HCI 112 obtains an increase size indication 216 indicating that the size of write buffer 182A of flash memory device 104 is to be increased, as referenced. Figures 2A to 2C As described, the flash memory device 104 includes a memory resource 181, which includes logic cells 168 and at least a write buffer 182A.

[0165] Method 1200 further includes: at block 1204, selecting the particular memory resource at the HCI based at least in part on a particular usage metric for a particular memory resource used for write buffer reallocation. For example, HCI 112 selects logic cell 168B as the particular memory resource 181 for write buffer reallocation 114 based on logic cell usage metric 318, as referenced. Figures 3 to 6 As described. As another example, HCI 112 uses metric 174 based on one or more buffers to select write buffer 182B as a specific memory resource 181 for write buffer reallocation 114, as referenced. Figures 7 to 9 As described.

[0166] Therefore, method 1200 enables the size of write buffer 182A to be dynamically increased based on memory resource usage metrics. For example, a portion of the memory resources corresponding to low utilization can be reallocated to the write buffer 182A to be increased.

[0167] Figure 12 Method 1200 can be implemented by a field-programmable gate array (FPGA) device, an application-specific integrated circuit (ASIC), a processing unit (such as a central processing unit (CPU)), a digital signal processor (DSP), a controller, another hardware device, a firmware device, or any combination thereof. As an example, Figure 12 Method 1200 can be executed by a processor that executes instructions, such as reference Figure 13 As described.

[0168] refer to Figure 13 This is a block diagram depicting a specific exemplary example of the device, and is generally designated as 1300. In various specific implementations, device 1300 may have... Figure 13 The illustrated components may be more or fewer than the number of components. In an exemplary embodiment, device 1300 may correspond to host device 102. In an exemplary embodiment, device 1300 may perform reference... Figures 1 to 12 One or more operations as described.

[0169] In a particular implementation, device 1300 includes a processor 1306 (e.g., a CPU). Device 1300 may include one or more additional processors 1310 (e.g., one or more DSPs). Processor 1310 may include a speech and music decoder-decoder (codec) 1308, which includes a voice decoder (“vocoder”) encoder 1336, a vocoder decoder 1338, or both. Processor 1310 may include an HCI 112 configured to be coupled to flash memory device 104.

[0170] Device 1300 may include memory 1332 and codec 1334. Memory 1332 may include instructions 1356 that can be executed by one or more additional processors 1310 (or processor 1306) to implement the functionality described with reference to HCI 112. Device 1300 may include a modem 1370 coupled to antenna 1352 via transceiver 1350.

[0171] Device 1300 may include a display 1328 coupled to display controller 1326. One or more speakers 1392 and one or more microphones 1394 may be coupled to codec 1334. Codec 1334 may include digital-to-analog converter (DAC) 1302, analog-to-digital converter (ADC) 1304, or both. In a particular embodiment, codec 1334 may receive analog signals from microphone 1394, convert these analog signals to digital signals using ADC 1304, and provide these digital signals to speech and music codec 1308. Speech and music codec 1308 may process digital signals. In a particular embodiment, speech and music codec 1308 may provide digital signals to codec 1334. Codec 1334 may use ADC 1302 to convert digital signals to analog signals and may provide analog signals to speaker 1392.

[0172] In a particular embodiment, device 1300 may be included in a system-in-package (SiP) or system-on-a-chip (SoC) 1322. In a particular embodiment, memory 1332, processor 1306, processor 1310, display controller 1326, codec 1334, and modem 1370 are included in the SiP or SoC 1322. In a particular embodiment, input device 1330, power supply 1344, and flash memory device 104 are coupled to the SiP or SoC 1322. Furthermore, in a particular embodiment, such as... Figure 13 As illustrated, the display 1328, input device 1330, speaker 1392, microphone 1394, antenna 1352, flash memory device 104, and power supply 1344 are external to the system-in-package or system-on-chip device 1322. In a particular implementation, each of the display 1328, input device 1330, speaker 1392, microphone 1394, antenna 1352, flash memory device 104, and power supply 1344 may be coupled to a component of the system-in-package or system-on-chip device 1322, such as an interface or controller. For example, the flash memory device 104 may be coupled to HCI 112.

[0173] Device 1300 may include smart speakers, speaker bars, mobile communication devices, smartphones, cellular phones, laptops, computers, tablets, personal digital assistants, display devices, televisions, game consoles, music players, radios, digital video players, digital video disc (DVD) players, tuners, cameras, navigation devices, vehicles, headsets, augmented reality headsets, mixed reality headsets, virtual reality headsets, air vehicles, home automation systems, voice-activated devices, wireless speakers and voice-activated devices, portable electronic devices, automobiles, computing devices, communication devices, Internet of Things (IoT) devices, virtual reality (VR) devices, base stations, mobile devices, or any combination thereof.

[0174] In conjunction with the described specific embodiment, an apparatus includes components for obtaining an indication at a host controller interface (HCI) that the size of a particular write buffer (WB) of a flash memory device (FMD) is to be increased. The FMD includes multiple memory resources, which include multiple logical units (LUs) and at least the particular WB. For example, the components for obtaining the indication may correspond to... Figure 1 HCI 112, host device 102, system 100, processor 1306, processor 1310, one or more other circuits or components, or any combination thereof, configured to receive the instruction.

[0175] The device also includes components for selecting the specific memory resource for write buffer reallocation based at least in part on a specific usage metric for the specific memory resource used for write buffer reallocation. For example, the components for selecting the specific memory resource may correspond to... Figure 1 The HCI 112, host device 102, system 100, processor 1306, processor 1310, one or more other circuits or components, or any combination thereof, configured to select specific memory resources for write buffer reallocation.

[0176] In some implementations, a non-transitory computer-readable medium (e.g., a computer-readable storage device, such as memory 1332) includes instructions (e.g., instruction 1356) that, when executed by one or more processors (e.g., one or more processors 1310 or processor 1306), cause the one or more processors to obtain at a host controller interface (HCI) (e.g., HCI 112) an indication (e.g., resizing instruction 116A, increasing size instruction 216, or both) to increase the size of a specific write buffer (WB) (e.g., write buffer 182A) of a flash memory device (FMD) (e.g., flash memory device 104). The FMD includes multiple memory resources (e.g., memory resource 181) that include multiple logic units (LUs) (e.g., logic unit 168) and at least the specific WB. The instruction also enables the one or more processors to select the particular memory resource for write buffer reallocation (e.g., write buffer reallocation 114) based at least in part on a particular memory resource (e.g., logic cell 168B or write buffer 182B) based on a particular usage metric (e.g., resizing metric 320B or buffer usage metric 174B).

[0177] Specific aspects of this disclosure are described below in a collection of related embodiments: According to Embodiment 1, a host device includes: a host controller interface (HCI) configured to be coupled to a flash memory device (FMD) and configured to: obtain an indication that the size of a specific write buffer (WB) of the FMD is to be increased, the FMD including a plurality of memory resources, the plurality of memory resources including a plurality of logical units (LUs) and at least the specific WB; and select the specific memory resource at least in part based on a specific usage metric for reallocating the specific memory resource for the write buffer.

[0178] Example 2 includes the host device according to Example 1, wherein the HCI is configured to, based on obtaining the indication,: obtain a usage metric of the plurality of LUs; select a specific LU as the specific memory resource for write buffer allocation based on the usage metric; and reallocate a portion of the specific LU to the specific WB.

[0179] Example 3 includes a host device according to Example 1 or Example 2, wherein the HCI is configured to reallocate a portion of the particular LU, including a three-level cell (TLC) memory, to the particular WB, including a single-level cell (SLC) memory.

[0180] Example 4 includes a host device according to Example 2 or Example 3, wherein the HCI is configured to maintain the usage metric during operation of the FMD, and wherein the usage metric includes utilization metrics, availability metrics, or both of the plurality of LUs.

[0181] Example 5 includes a host device according to any one of Examples 2 to 4, wherein the HCI is configured to: generate a sizing metric for the plurality of LUs based on the usage metric; and select the particular LU having a particular sizing metric indicating the lowest usage among the plurality of LUs.

[0182] Example 6 includes the host device according to Example 5, wherein the particular sizing metric is based on the availability metric, utilization metric, or both of the particular LU.

[0183] Example 7 includes the host device according to Example 6, wherein the availability metric corresponds to the unused storage capacity of the particular LU.

[0184] Example 8 includes a host device according to Example 6 or Example 7, wherein the utilization metric is based on data access counts at the specific LU.

[0185] Example 9 includes a host device according to any one of Examples 6 to 8, wherein the specific adjustment size metric corresponds to a weighted sum of the availability metric and the utilization metric.

[0186] Example 10 includes a host device according to Example 1, wherein the HCI is configured to, based on obtaining the instruction,: obtain a buffer usage metric of a plurality of WBs of the FMD, wherein the buffer usage metric is maintained at the FMD; select a first WB as the specific memory resource for write buffer allocation based on the buffer usage metric; and reallocate a portion of the first WB to the specific WB.

[0187] Example 11 includes the host device according to Example 10, wherein the HCI is configured to select the first WB having a first buffer usage metric indicating the lowest usage among the plurality of WBs.

[0188] Example 12 includes the host device according to Example 11, wherein the first buffer uses a metric to indicate the full buffer detection count of the first WB.

[0189] Example 13 includes a host device according to any one of Examples 1 to 12, wherein the HCI is configured to deallocate a portion of the second specific WB based on a second indication that the size of the second specific WB is to be reduced.

[0190] Example 14 includes a host device according to any one of Examples 1 to 13, wherein the HCI is configured to obtain the indication by comparing the buffer usage metric of the particular WB with one or more thresholds.

[0191] Example 15 includes the host device according to Example 14, wherein the buffer usage metric includes the full buffer detection count of the particular WB.

[0192] Example 16 includes a host device according to Example 14 or Example 15, wherein one or more thresholds include an upper limit, a lower limit, or both.

[0193] Example 17 includes a host device according to any one of Examples 1 to 16, wherein the HCI is configured to: transmit a buffer usage request to the FMD; receive a buffer usage metric for the specific WB from the FMD in response to the buffer usage request; and generate the indication based on a comparison of the buffer usage metric performed at the HCI with one or more thresholds.

[0194] Example 18 includes the host device according to Example 17, wherein the buffer usage request includes a Write Enhancer Buffer Full Count ALL READ instruction to retrieve the buffer usage metric for each WB of the FMD.

[0195] Example 19 includes a host device according to any one of Examples 1 to 16, wherein the HCI is configured to obtain the indication based on an anomaly triggered by a comparison of a buffer usage metric of the particular WB buffer at the FMD with one or more thresholds.

[0196] Example 20 includes the host device according to Example 19, wherein one or more thresholds are stored in the register of the FMD.

[0197] According to embodiment 21, a method includes: obtaining at a host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) is to be increased, the FMD including a plurality of memory resources including a plurality of logical units (LUs) and at least the specific WB; and selecting the specific memory resource at the HCI based at least in part on a specific usage metric for reallocating the specific memory resource for the write buffer.

[0198] Example 22 includes the method according to Example 21, the method further comprising, based on obtaining the indication,: obtaining a usage metric of the plurality of LUs; selecting a specific LU as the specific memory resource for write buffer allocation based on the usage metric; and reallocating a portion of the specific LU to the specific WB.

[0199] Example 23 includes the method according to Example 21 or Example 22, wherein the portion of the particular LU includes a three-level cell (TLC) memory and wherein the particular WB includes a single-level cell (SLC) memory.

[0200] Example 24 includes the method according to Example 22 or Example 23, and the method further includes maintaining the usage metric during the operation of the FMD, wherein the usage metric includes utilization metric, availability metric, or both of the plurality of LUs.

[0201] Example 25 includes the method according to any one of Examples 22 to 24, and the method further includes generating a sizing metric for the plurality of LUs based on the usage metric, wherein the particular LU is selected based on determining that the particular LU has a particular sizing metric indicating the lowest usage among the plurality of LUs.

[0202] Example 26 includes the method according to Example 25, wherein the particular adjustment size metric is based on the availability metric, utilization metric, or both of the particular LU.

[0203] Example 27 includes the method according to Example 26, wherein the availability metric corresponds to the unused storage capacity of the particular LU.

[0204] Example 28 includes the method according to Example 26 or Example 27, wherein the utilization metric is based on the data access count at the particular LU.

[0205] Example 29 includes the method according to any one of Examples 26 to 28, wherein the specific adjustment size metric corresponds to a weighted sum of the availability metric and the utilization metric.

[0206] Example 30 includes the method according to Example 21, and the method further includes, based on obtaining the instruction, obtaining a buffer usage metric of a plurality of WBs of the FMD, wherein the buffer usage metric is maintained at the FMD; selecting a first WB as the specific memory resource for write buffer allocation based on the buffer usage metric; and reallocating a portion of the first WB to the specific WB.

[0207] Example 31 includes the method according to Example 30, wherein the first WB is selected based on determining that the first WB has a first buffer usage metric indicating the lowest usage among the plurality of WBs.

[0208] Example 32 includes the method according to Example 31, wherein the first buffer uses a metric to indicate the full buffer detection count of the first WB.

[0209] Example 33 includes the method according to any one of Examples 21 to 32, and the method further includes releasing a portion of the second specific WB based on a second indication that the size of the second specific WB is to be reduced.

[0210] Example 34 includes the method according to any one of Examples 21 to 33, wherein the indication is based on a comparison of the buffer usage metric of the particular WB with one or more thresholds.

[0211] Example 35 includes the method according to Example 34, wherein the buffer usage metric includes the full buffer detection count of the particular WB.

[0212] Example 36 includes the method according to Example 34 or Example 35, wherein the one or more thresholds include an upper limit, a lower limit, or both.

[0213] Example 37 includes the method according to any one of Examples 21 to 36, and the method further includes: transmitting a buffer usage request from the HCI to the FMD; receiving a buffer usage metric for the specific WB from the FMD at the HCI in response to the buffer usage request; and generating the indication based on a comparison of the buffer usage metric performed at the HCI with one or more thresholds.

[0214] Example 38 includes the method according to Example 37, wherein the buffer usage request includes a write enhancer buffer full count ALL READ instruction to retrieve a buffer usage metric for each WB of the FMD.

[0215] Example 39 includes the method according to any one of Examples 21 to 36, wherein the indication is obtained based on an anomaly triggered by a comparison of the buffer usage metric of the particular WB buffer at the FMD with one or more thresholds.

[0216] Example 40 includes the method according to Example 39, wherein one or more thresholds are stored in a register of the FMD.

[0217] According to embodiment 41, an apparatus includes: a memory configured to store instructions; and a processor configured to execute the instructions to perform a method according to any one of embodiments 21 to 40.

[0218] According to Embodiment 42, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform a method according to any one of Embodiments 21 to 40.

[0219] According to embodiment 43, an apparatus includes components for performing the method according to any one of embodiments 21 to 40.

[0220] According to embodiment 44, a non-transitory computer-readable medium stores instructions that, when executed by one or more processors, cause the one or more processors to: obtain at a host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) should be increased, the FMD including a plurality of memory resources, the plurality of memory resources including a plurality of logical units (LUs) and at least the specific WB; and select the specific memory resource at least in part based on a specific usage metric for reallocating the specific memory resource for the write buffer.

[0221] According to embodiment 45, an apparatus includes: components for obtaining at a host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) is to be increased, the FMD including a plurality of memory resources including a plurality of logical units (LUs) and at least the specific WB; and components for selecting the specific memory resource based at least in part on a specific usage metric for reallocating the specific memory resource for the write buffer.

[0222] Those skilled in the art will also understand that the various exemplary logic blocks, configurations, modules, circuits, and algorithm steps described in connection with the specific embodiments disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of both. The various exemplary components, blocks, configurations, modules, circuits, and steps have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or processor-executable instructions depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, and such implementation decisions shall not be construed as departing from the scope of this disclosure.

[0223] The steps of the methods or algorithms described in conjunction with the specific embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, compressed optical disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal. Alternatively, the processor and storage medium may reside as discrete components in a computing device or a user terminal.

[0224] The prior description of the disclosed aspects is provided to enable those skilled in the art to make or use the disclosed aspects. Various modifications to these aspects will be apparent to those skilled in the art, and the principles defined herein can be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but should be granted the broadest scope that may be consistent with the principles and novel features as defined by the following claims.

Claims

1. A host device, the host device comprising: A host controller interface (HCI) is configured to be coupled to a flash memory device (FMD) and is configured to: Obtain an indication that the size of a specific write buffer (WB) of the FMD should be increased, the FMD comprising multiple memory resources including multiple logical units (LUs) and at least the specific WB; as well as The specific memory resource is selected based at least in part on a specific usage metric for the specific memory resource used for write buffer reallocation.

2. The host device of claim 1, wherein the HCI is configured to: Obtain usage metrics for the multiple LUs; Based on the usage metric, a specific LU is selected as the specific memory resource for write buffer allocation; as well as A portion of the specific LU is reassigned to the specific WB.

3. The host device of claim 2, wherein the HCI is configured to reallocate the portion of the particular LU including three-level cell (TLC) memory to the particular WB including single-level cell (SLC) memory.

4. The host device of claim 2, wherein the HCI is configured to maintain the usage metric during operation of the FMD, and wherein the usage metric includes utilization metrics, availability metrics, or both of the plurality of LUs.

5. The host device according to claim 2, wherein the HCI is configured as follows: Based on the usage metric, the resizing metric of the plurality of LUs is generated; and Select the specific LU that has a specific adjustment size metric indicating the lowest usage rate among the plurality of LUs.

6. The host device of claim 5, wherein the particular sizing metric is based on an availability metric, a utilization metric, or both of the particular LU.

7. The host device of claim 6, wherein the availability metric corresponds to the unused storage capacity of the particular LU.

8. The host device of claim 6, wherein the utilization metric is based on data access counts at the particular LU.

9. The host device of claim 6, wherein the specific sizing metric corresponds to a weighted sum of the availability metric and the utilization metric.

10. The host device of claim 1, wherein the HCI is configured to: Obtain buffer usage metrics for multiple WBs of the FMD, wherein the buffer usage metrics are maintained at the FMD; The first WB is selected as the specific memory resource for write buffer allocation based on the buffer usage metric. as well as A portion of the first WB is reassigned to the specific WB.

11. The host device of claim 10, wherein the HCI is configured to select the first WB having a first buffer usage metric indicating the lowest usage among the plurality of WBs.

12. The host device of claim 11, wherein the first buffer uses a metric to indicate the full buffer detection count of the first WB.

13. The host device of claim 1, wherein the HCI is configured to deallocate a portion of the second specific WB based on a second indication that the size of the second specific WB is to be reduced.

14. The host device of claim 1, wherein the HCI is configured to obtain the indication by comparing a buffer usage metric with one or more thresholds based on the particular WB.

15. The host device of claim 14, wherein the buffer usage metric includes a full buffer detection count for the particular WB.

16. The host device of claim 14, wherein the one or more thresholds include an upper limit, a lower limit, or both.

17. The host device according to claim 1, wherein the HCI is configured as follows: Send a buffer usage request to the FMD; In response to the buffer usage request, receive the buffer usage metric for the specific WB from the FMD; and The indication is generated based on a comparison of the buffer usage metric performed at the HCI with one or more thresholds.

18. The host device of claim 17, wherein the buffer usage request includes a write booster buffer full count ALL READ instruction to retrieve a buffer usage metric for each WB of the FMD.

19. The host device of claim 1, wherein the HCI is configured to obtain the indication based on an anomaly triggered by a comparison of a buffer usage metric of the particular WB buffer at the FMD with one or more thresholds.

20. The host device of claim 19, wherein one or more thresholds are stored in a register of the FMD.

21. A method comprising: At the host controller interface (HCI), an indication is obtained that the size of a specific write buffer (WB) of a flash memory device (FMD) is to be increased, the FMD comprising multiple memory resources including multiple logical units (LUs) and at least the specific WB; as well as The specific memory resource is selected at the HCI based at least in part on a specific usage metric for the specific memory resource used for write buffer reallocation.

22. The method of claim 21, further comprising, based on obtaining the instruction, to: Obtain usage metrics for the multiple LUs; Based on the usage metric, a specific LU is selected as the specific memory resource for write buffer allocation; as well as A portion of the specific LU is reassigned to the specific WB.

23. The method of claim 22, wherein the portion of the particular LU comprises a three-level cell (TLC) memory and wherein the particular WB comprises a single-level cell (SLC) memory.

24. The method of claim 22, further comprising maintaining the usage metric during operation of the FMD, wherein the usage metric includes utilization metrics, availability metrics, or both of the plurality of LUs.

25. The method of claim 22, further comprising generating a sizing metric for the plurality of LUs based on the usage metric, wherein a particular LU is selected based on determining that the particular LU has a particular sizing metric indicating the lowest usage among the plurality of LUs.

26. The method of claim 25, wherein the particular sizing metric is based on an availability metric, a utilization metric, or both of the particular LU.

27. The method of claim 26, wherein the availability metric corresponds to the unused storage capacity of the particular LU.

28. The method of claim 26, wherein the utilization metric is based on the data access count at the particular LU.

29. A non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: Obtain at the host controller interface (HCI) an indication that the size of a specific write buffer (WB) of a flash memory device (FMD) is to be increased, the FMD comprising multiple memory resources including multiple logical units (LUs) and at least the specific WB; and The specific memory resource is selected based at least in part on a specific usage metric for the specific memory resource used for write buffer reallocation.

30. An apparatus comprising: Components for obtaining an indication at the host controller interface (HCI) of the size of a specific write buffer (WB) of a flash memory device (FMD) to be increased, the FMD including multiple memory resources including multiple logical units (LUs) and at least the specific WB; as well as A component for selecting a particular memory resource based at least in part on a specific usage metric for a particular memory resource used for write buffer reallocation.

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