Semiconductor aging test method and system

Abstract

The invention relates to the technical field of semiconductor testing, and discloses a semiconductor element aging test method and system, and the method is applied to an aging test system comprising an aging test board, a test station, and an automatic feeding and discharging mechanism. The method comprises the following steps: completing feeding and test station butt joint of an aging test board loaded with a to-be-tested element, starting an aging test process, and collecting test parameters of the to-be-tested element in real time; performing multi-level cross validation on the test parameters, and outputting a grading result including individual failure judgment and board-level fault judgment; executing hierarchical control according to a hierarchical result, synchronously executing power cut-off and physical isolation actions when an individual fails, and triggering a fault board to be automatically replaced when a board-level fault occurs; and after the test is completed, finished product discharging and new board feeding are executed. According to the invention, the judgment precision and operation safety of the aging test are improved, automatic continuous operation of the test process is realized, and the test efficiency is effectively improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, specifically to a semiconductor aging test method and system. Background Technology

[0002] In the semiconductor component manufacturing process, aging testing is a core process for screening component reliability and ensuring mass production quality. However, existing semiconductor component aging testing technologies still have significant shortcomings in batch testing applications: Existing technologies mostly use a single threshold comparison mode to determine the failure of the component under test, which is easily affected by the test environment and may lead to misjudgment. They cannot accurately distinguish between individual component failures and test board-level faults, making it difficult to adapt to the graded handling requirements of batch testing. At the same time, existing technologies have limited fault protection methods and cannot reliably isolate failed components, which can easily lead to fault propagation and damage to components and test equipment. Furthermore, the fault protection process is disconnected from the loading and unloading operations, and board-level faults require manual shutdown intervention. It is difficult to balance the operational safety and continuous testing efficiency of aging testing, and thus cannot meet the mass production application requirements of large-scale semiconductor component aging testing. Summary of the Invention

[0003] To solve or at least partially solve the above-mentioned technical problems, this application provides a semiconductor aging test method and system.

[0004] In a first aspect, this application provides a semiconductor device aging test method, applied to an aging test system including an aging test board, a test station, and an automatic loading and unloading mechanism, comprising the following steps: S1. Load the aging test board containing the components under test and connect it with the test station. Start the preset aging test process and collect the test parameters of each component under test on the aging test board in real time. S2. Perform multi-level cross-validation on the collected test parameters, distinguish and output graded judgment results, including individual failure judgment and board-level fault judgment. S3. Execute hierarchical control according to the hierarchical judgment result. If the output is determined to be an individual failure, the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test are executed simultaneously. If the output is determined to be a board-level failure, the automatic loading and unloading mechanism is triggered to execute the fault board replacement process. S4. After the aging test board completes the preset aging test process, the automatic loading and unloading mechanism is triggered to execute the finished product unloading process, and the automatic loading of the next aging test board is completed simultaneously.

[0005] Optionally, the multi-level cross-validation includes an initial screening step for individual anomalies of a single device under test, which specifically includes: The test parameters of a single component under test are collected synchronously, including static electrical parameters, dynamic functional parameters, and timing consistency parameters. The currently collected test parameters are cross-compared with the power-on initial reference parameters of the component under test and the pre-calibration standard parameters of components in the same batch. When multiple types of parameters show abnormal deviations simultaneously, the component under test is marked as having a preliminary abnormal state.

[0006] Optionally, the multi-level cross-validation further includes an anomaly type determination step for the device under test (DUT) marked as having a preliminary anomalous state. The anomaly type determination step specifically includes: The test parameters of the test component marked as having a preliminary abnormal state are cross-compared with the normal parameters of the cluster of adjacent test components of the same specification in the aging test board and the reference parameters of the preset standard reference channel without test components in the board. If only the test parameters of the component under test are abnormal, it is determined that the component under test is abnormal; if the test parameters of multiple components under test in the same area show abnormal deviations simultaneously, and the reference parameters of the standard reference channel are also abnormal, it is determined that the aging test board-level environment is abnormal.

[0007] Optionally, for devices under test (DUTs) determined to be individually abnormal, multi-node cross-validation is performed. The multi-node cross-validation specifically includes the following steps: The test parameters for each node are obtained by sequentially performing a light load test mode retest, a static parameter retest, and a power-off restart retest on the component under test. Cross-validate the backtesting parameters of each node. When the test results of all backtesting nodes confirm anomalies, output the individual failure determination result.

[0008] Optionally, for the aging test board containing the component under test that is determined to have an abnormal board-level environment, board-level failure trend cross-validation is performed. The board-level failure trend cross-validation specifically includes the following steps: Collect data from the aging test board, including the distribution location of abnormal test components, abnormal parameter types, and abnormal occurrence sequence within the aging test board. At the same time, obtain failure data from aging test boards of the same batch at other workstations on the same machine. The data collected from the aging test board is cross-compared with the failure data of the same batch of aging test boards at other workstations on the same machine. If the aging test board shows a concentrated area of ​​batch anomalies, synchronous anomalies of the same type of parameters, or an overall failure rate exceeding the preset threshold, and other aging test boards in the same batch do not show corresponding anomalies, then the final result of the board-level fault determination is output.

[0009] Optionally, the synchronous execution of the power cut-off action for the corresponding test channel and the physical isolation action of the test socket for the corresponding component under test specifically includes the following steps: The power cut-off action and the sinking physical isolation action are executed synchronously, and the execution time difference between the two actions is less than a preset time difference threshold. A secondary test is performed on the power-off state of the corresponding test channel and the sinking state of the corresponding test socket. The results of the secondary test are cross-validated with the individual failure judgment results. If the verification fails, a system alarm is triggered and the test process of the aging test board is suspended.

[0010] Optionally, the method further includes performing abnormal state tracking on the device under test marked as transient interference during the multi-level cross-validation process, wherein the abnormal state tracking specifically includes the following steps: Increase the sampling frequency and cross-validation frequency of the test parameters of the device under test (DUT) marked as transient interference, and continuously collect and analyze the changing trend of the test parameters of the DUT. If the test parameters of the component under test become abnormal again, the multi-node back-check cross-validation is performed.

[0011] Optionally, the method further includes executing corresponding control actions based on the real-time failure rate of the aging test board, specifically including the following steps: When the real-time failure rate of the aging test board reaches the warning threshold, the system will issue a pre-alarm and retrieve the spare aging test board to the waiting material position in advance. When the real-time failure rate of the aging test board reaches the replacement threshold, or when the board-level fault determination result is output, the automatic loading and unloading mechanism is triggered to execute the fault board replacement process.

[0012] Optionally, the triggering of the automatic loading and unloading mechanism to execute the faulty board replacement process specifically includes the following steps: First, disconnect the main power supply to the faulty aging test board, and then unlock the docking mechanism between the faulty aging test board and the test station. The faulty aging test board is taken out from the test station by the automatic loading and unloading mechanism and transferred to the faulty storage location to complete the unloading and storage. The spare aging test board is retrieved by the automatic loading and unloading mechanism and transferred to the test station to complete the docking and power-on self-test. Once the backup aging test board passes the self-test, the aging test process for this test station is initiated.

[0013] Secondly, this application also provides a semiconductor device aging test system, comprising: The test station is used to load the aging test board and is electrically connected to the loaded aging test board to provide a test environment and electrical signal path for the aging test of the component under test. The parameter acquisition unit is located at the test station. The signal acquisition end of the parameter acquisition unit is electrically connected to each component under test on the aging test board. The signal output end of the parameter acquisition unit is communicatively connected to the main control unit. It is used to acquire the test parameters of each component under test on the aging test board in real time and transmit the acquired test parameters to the main control unit. The channel protection execution unit is connected to the main control unit. The execution end of the channel protection execution unit corresponds one-to-one with the test channel and test socket of each component under test on the aging test board. It is used to synchronously execute the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test according to the control command issued by the main control unit. The automatic loading and unloading mechanism is connected to the main control unit and is used to perform the docking operation between the aging test board and the test station, the unloading operation of the aging test board, and the replacement operation of the faulty aging test board according to the control instructions issued by the main control unit. The main control unit is connected to the parameter acquisition unit, the channel protection execution unit, and the automatic loading and unloading mechanism. It is used to receive test parameters transmitted by the parameter acquisition unit and output graded control commands to the channel protection execution unit and the automatic loading and unloading mechanism.

[0014] The method provided in this application has the following beneficial effects: The semiconductor device aging test method disclosed in this application processes the collected test parameters through multi-level cross-validation, which can accurately distinguish and output the classification results of individual failure judgment and board-level fault judgment, effectively improving the accuracy of failure judgment during aging testing and reducing misjudgments during the testing process. Based on the classification judgment results, corresponding classification control is executed. When an individual failure is determined, the power supply to the corresponding test channel and the physical isolation action of the test socket are simultaneously executed, which can reliably isolate the failed component under test, prevent the fault range from spreading, and protect the component under test and the test equipment from damage. When a board-level fault is determined, a faulty board replacement process is triggered. After the aging test board completes the test, the finished product unloading and new board loading are automatically executed, which can reduce manual intervention during the testing process, realize the continuous operation of the aging test process, and improve the operational efficiency of batch aging testing.

[0015] By cross-comparing multiple test parameters of a single component under test (DUT) through an initial screening step for individual anomalies, preliminary anomaly screening can be completed, improving the rigor of anomaly judgment. The anomaly type determination step distinguishes between individual DUT anomalies and board-level environmental anomalies, accurately locating the root cause of the anomaly and providing an accurate basis for subsequent graded handling. Multi-node backtesting and cross-validation retests and verifies DUTs with individual anomalies, avoiding misjudgments caused by transient parameter anomalies and further ensuring the accuracy of individual failure judgment. Cross-validation of board-level failure trends ensures accurate determination of board-level faults, avoiding accidental triggering of whole-board replacement operations and balancing test safety and operational efficiency. Synchronous control and secondary verification of protection actions ensure reliable execution of protection actions, reducing the safety risk of protection failure. Tracking the abnormal state of DUTs experiencing transient interference allows for timely detection of potential failure risks, improving test reliability. By implementing graded control based on the real-time failure rate of the aging test board, backup boards can be prepared in advance, shortening the time spent on fault handling and improving the continuity of the testing process. Through a standardized fault board replacement process, the operational safety of the replacement process can be guaranteed, adapting to the application requirements of multi-station batch aging tests. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a semiconductor device aging test method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a semiconductor device aging test system provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0018] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0019] See Figure 1 This application provides a semiconductor device aging test method, applied to an aging test system including an aging test board, a test station, and an automatic loading and unloading mechanism, comprising the following steps: S1. Load the aging test board containing the components under test and connect it with the test station. Start the preset aging test process and collect the test parameters of each component under test on the aging test board in real time. S2. Perform multi-level cross-validation on the collected test parameters, distinguish and output graded judgment results, including individual failure judgment and board-level fault judgment. S3. Execute hierarchical control based on the hierarchical judgment result. If the output individual fails, the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test are executed simultaneously. If the output board level fails, the automatic loading and unloading mechanism is triggered to execute the fault board replacement process. S4. After the aging test board completes the preset aging test process, the automatic loading and unloading mechanism is triggered to execute the finished product unloading process, and the automatic loading of the next aging test board is completed simultaneously.

[0020] Specifically, the semiconductor device aging test method is implemented based on an aging test system that includes an aging test board, a test station, and an automated loading and unloading mechanism. Before implementation, the components under test (DUTs) are fixed and electrically connected to the aging test board, ensuring that each DUT is connected to its corresponding test path. Then, the automated loading and unloading mechanism transfers the aging test board to its corresponding installation position at the test station, completing the mechanical fixing and electrical connection between the aging test board and the test station. After confirming that the connection is correct, the pre-set aging test process is initiated. Throughout the entire aging test cycle, test parameters generated by each DUT on the aging test board during the test are continuously collected according to preset acquisition rules.

[0021] The collected test parameters undergo multi-level cross-validation. Pre-set validation rules are used to comprehensively verify and analyze the test parameters, distinguishing different anomaly types that occur during testing and outputting corresponding graded judgment results. These graded judgment results include individual failure judgments for single components under test (DUTs) and board-level fault judgments for the entire board. Based on the output graded judgment results, corresponding graded control actions are executed. When an individual failure judgment is output, two corresponding actions are executed simultaneously: first, the power supply to the corresponding DUT's test channel is cut off, stopping the test power supply to that channel; second, the test socket of the corresponding DUT is driven to perform a downward physical isolation action, completing the physical isolation of the failed component from the test path. When a board-level fault judgment is output, an automatic loading and unloading mechanism is triggered to execute the faulty board replacement process, replacing the faulty aging test board.

[0022] When all components under test (DUTs) on the aging test board have completed the preset aging test process or reached the preset test termination conditions, the automatic loading and unloading mechanism is triggered to execute the finished product unloading process. The completed aging test board is removed from the testing station and transferred to the corresponding storage location. Simultaneously, the automatic loading operation of the next aging test board is completed, achieving continuous connection of the testing process. Through this complete implementation process, accurate differentiation and hierarchical control of abnormal situations can be achieved throughout the entire semiconductor component aging test process. This effectively prevents the spread of abnormal situations during testing, ensures the continuous and stable operation of the aging test process, improves the safety of the aging test process and the reliability of the test results, and optimizes the overall operating efficiency of the aging test.

[0023] In some implementations, multi-level cross-validation includes an initial screening step for individual anomalies of a single device under test (DUT), which specifically includes: The test parameters of a single component under test are collected synchronously. The test parameters include static electrical parameters, dynamic functional parameters, and timing consistency parameters. The currently collected test parameters are cross-compared with the power-on initial reference parameters of the component under test and the pre-calibration standard parameters of components in the same batch. When multiple types of parameters show abnormal deviations simultaneously, the component under test is marked as having a preliminary abnormal state.

[0024] In the implementation of semiconductor device aging test methods, multi-level cross-validation is first performed by conducting an initial screening step for individual anomalies of each device under test (DUT). For each DUT connected to the test path, multiple types of test parameters are simultaneously collected at the same time point during the test process. The collected test parameters specifically include static electrical parameters, dynamic functional parameters, and timing consistency parameters, ensuring that the collected parameters correspond to the same test condition and guaranteeing the consistency of the parameter comparison benchmark.

[0025] After completing the synchronous acquisition of multiple test parameters, the initial power-on reference parameters of the device under test are first acquired at the beginning of the aging test process and after the power-on state is stable. At the same time, the pre-calibration standard parameters of the batch of devices under test are acquired before the test starts. The multiple test parameters acquired synchronously are cross-compared with the initial power-on reference parameters and the pre-calibration standard parameters of the same batch of devices to complete the multi-dimensional parameter verification.

[0026] During the cross-comparison process, when multiple test parameters collected at the same time point all show abnormal deviations exceeding the preset range, the component under test is marked as having a preliminary abnormal state, completing the entire process of initial screening for individual abnormalities. Through the complete implementation of this step, preliminary and accurate identification of abnormal states of the component under test can be achieved, providing a reliable foundation for subsequent abnormality classification and judgment, effectively avoiding judgment bias caused by fluctuations in a single parameter, and improving the stability and accuracy of abnormality identification during aging testing.

[0027] During the implementation of the above-mentioned initial screening steps for individual anomalies, a full-channel pre-parameter calibration operation can be completed before simultaneously collecting multiple types of test parameters. Using the preset standard reference channel within the aging test board, baseline parameters under corresponding operating conditions are collected. The initial parameters of all test components corresponding to their respective test channels are cross-compared with the baseline parameters of the standard reference channel to complete the temperature drift compensation calibration for all channels. This generates a suitable parameter comparison baseline for each test channel, ensuring the baseline accuracy of subsequent parameter comparisons.

[0028] Simultaneously, during the cross-comparison process, a trend cross-validation operation with a time dimension can be added. For a single component under test (DUT), in addition to cross-comparing the currently acquired parameters with fixed benchmark parameters, test parameters acquired within multiple consecutive time windows prior to the current time point can also be obtained. This allows for cross-comparison of parameter change trends at different time points on the same channel. Only when multiple types of currently acquired test parameters show abnormal deviations exceeding preset ranges, and the corresponding parameter change trends exhibit continuous abrupt changes, is the DUT marked as having a preliminary abnormal state. Through these supplementary operations, the interference from instantaneous parameter jumps caused by fluctuations in operating conditions during testing can be further filtered out, further improving the accuracy of initial screening for individual anomalies and providing a more reliable foundation for subsequent anomaly determination.

[0029] In some implementations, multi-level cross-validation further includes an anomaly type determination step for components under test (DUTs) marked as having a preliminary anomalous state. The anomaly type determination step specifically includes: The test parameters of the test components marked as initially abnormal are cross-compared with the normal parameters of the cluster of adjacent test components of the same specification in the aging test board and the baseline parameters of the preset standard reference channel without test components in the board. If only the test parameters of the component under test are abnormal, it is determined that the component under test is abnormal; if the test parameters of multiple components under test in the same area show abnormal deviations simultaneously, and the reference parameters of the standard reference channel are also abnormal, it is determined that the aging test board level environment is abnormal.

[0030] In the implementation of semiconductor device aging test methods, after initial screening of individual anomalies for a single device under test (DUT) and marking the corresponding DUT as having a preliminary abnormal state, multi-level cross-validation also includes an anomaly type determination step for the DUT marked as having a preliminary abnormal state. When implementing this step, corresponding data is first acquired as a comparison benchmark. This includes: 1) the cluster normal parameters of multiple DUTs adjacent to the DUT, with identical specifications, and not marked as abnormal within the aging test board containing the DUT marked as having a preliminary abnormal state; and 2) the benchmark parameters of the pre-set standard reference channel within the aging test board that is not loaded with DUTs. All acquired parameters correspond to the same test time node and test condition as the test parameters of the DUT, ensuring the consistency of the comparison benchmark.

[0031] After acquiring the baseline parameters, the test parameters of the device under test (DUT) marked as initially abnormal are cross-compared with the acquired normal cluster parameters and the baseline parameters of the standard reference channel to complete the verification and analysis of the source of the anomaly. After the cross-comparison is completed, the anomaly type is determined based on the comparison results. If only the test parameters of the DUT marked as initially abnormal have an abnormal offset, and the normal cluster parameters and the baseline parameters of the standard reference channel of adjacent DUTs of the same specification are within the normal range, then it is determined to be an individual DUT anomaly. If the test parameters of multiple DUTs in the same area show abnormal offsets simultaneously, and the baseline parameters of the standard reference channel also show abnormalities simultaneously, then it is determined to be an abnormal board-level environment of the aging test board.

[0032] By implementing this step, the source of abnormal situations during the testing process can be clearly distinguished, providing an accurate basis for subsequent graded control actions, effectively avoiding misjudgment of abnormal types, improving the accuracy of abnormal judgment during aging testing, and ensuring the stable operation of the aging testing process.

[0033] During the implementation of the above-mentioned anomaly type determination steps, a group parameter acquisition operation within the board dimension can be added to the step of acquiring comparison benchmark parameters. For the test components marked as having a preliminary abnormal state, in addition to acquiring the cluster normal parameters of adjacent test components of the same specification, all test components on the aging test board can be divided into multiple corresponding groups according to the spatial distribution of the test components on the aging test board, their power supply domain, and the test temperature zone. The normal parameters within the same group as the test components marked as having a preliminary abnormal state, as well as those of test components not marked as having an abnormal state, can be collected. All collected normal parameters within the group correspond to the same test time node and test condition, further enriching the dimensions of the comparison benchmark.

[0034] Simultaneously, during the cross-comparison process, cross-validation operations for parameters within the same group can be added. The test parameters of the components under test (DUTs) marked as initially abnormal are cross-compared in multiple dimensions with normal parameters within the same group, normal parameters in different groups, and baseline parameters of the standard reference channel to further clarify the coverage of abnormal parameters. If only the parameters of a single DUT are abnormal, while parameters within the same group and other groups are within the normal range, then the individual DUT abnormality is further confirmed. If multiple DUTs within the same group simultaneously exhibit abnormal parameters, and the abnormal range perfectly matches the corresponding power domain, temperature zone, or spatial distribution area, while the baseline parameters of the standard reference channel also simultaneously exhibit abnormalities, then the board-level environment of the aging test board is further confirmed to be abnormal. Through these supplementary operations, the location range of the abnormality source can be further narrowed, avoiding misjudging local board-level environmental abnormalities as individual DUT abnormalities, further improving the accuracy and reliability of abnormality type determination, and providing a more accurate basis for subsequent graded control actions.

[0035] In some implementations, for devices under test (DUTs) determined to be individually abnormal, multi-node cross-validation is performed. Multi-node cross-validation specifically includes the following steps: The test parameters for each node are obtained by sequentially performing light load test mode retest, static parameter retest, and power-off restart retest on the component under test. Cross-validate the backtesting parameters of each node. When the test results of all backtesting nodes confirm anomalies, output the result of the individual failure determination.

[0036] In the implementation of the semiconductor device aging test method, after the anomaly type is determined and the corresponding device under test is identified as having an individual anomaly, multi-node back-check cross-validation is performed on the device under test. The authenticity of the anomaly state is confirmed through repeated verification under multiple operating conditions, avoiding the judgment error caused by the deviation of a single test.

[0037] When performing multi-node cross-validation, the cross-validation operations of the three nodes are completed sequentially according to the preset procedure. First, the operating conditions of the aging test are adjusted and switched to the light load test mode. After the light load test mode enters a stable operating state, the corresponding test parameters of the component under test are collected to complete the light load test mode cross-validation. After the light load test mode cross-validation is completed, the basic test conditions are restored, the dynamic test process of the component under test is paused, and the static electrical parameters of the component under test are collected to complete the static parameter retest. After the static parameter retest is completed, the temporary power supply to the corresponding test channel of the component under test is cut off, and after a preset time, the power is turned on again. After the power-on state is stable, all test parameters of the component under test are collected again to complete the power-off and restart retest. After all cross-validation operations are completed in sequence, the cross-validation test parameters of each node are obtained.

[0038] The retest parameters collected at each node are cross-validated with the initial baseline parameters of the component under test (DUT) and the pre-calibration standard parameters of components in the same batch to verify the consistency of abnormal states of the parameters at each node. When the test results of all retest nodes confirm that the parameters of the DUT have abnormal deviations, the individual failure judgment result of the DUT is output. Through multi-node, multi-condition retest cross-validation, abnormal misjudgments caused by operating condition fluctuations and instantaneous interference during the testing process can be effectively filtered out, ensuring the accuracy and reliability of the individual failure judgment results, providing accurate judgment basis for subsequent control actions, and improving the operational stability of the aging test process.

[0039] During the implementation of the above multi-node re-inspection and cross-validation steps, after completing the preset three-node re-inspection operations and obtaining the re-inspection test parameters for each node, a cross-batch traceability cross-validation operation can be added. When implementing this operation, first obtain two sets of traceability comparison benchmark parameters. One set is the historical stable test benchmark parameters of the same specification aging test board and the same test channel in the same test batch under the same test machine and test station. The other set is the normal test parameters of the same batch of components under test under the same operating conditions on other test stations and normal aging test boards of the same specification. All obtained traceability benchmark parameters correspond to the same test conditions and component specifications, ensuring the compatibility of the comparison benchmarks. After obtaining the traceability benchmark parameters, cross-compare the re-inspection test parameters of each node of the component under test with the two sets of traceability benchmark parameters to clarify the source of abnormal parameters and distinguish whether the abnormality stems from the performance failure of the component under test itself, or from inherent deviations of the test station or hardware abnormalities of the corresponding channel of the aging test board.

[0040] Simultaneously, in the cross-validation stage, multi-dimensional linkage cross-comparison operations can be added. In addition to cross-comparing the retest parameters with the initial baseline parameters and the pre-calibrated standard parameters of the same batch, the retest parameters at each node can also be linked with the continuous time window parameter change trends collected during the initial screening of individual anomalies for the component under test (DUT), and the normal parameters within the same group collected during the anomaly type determination stage, to further verify the consistency of the anomaly state throughout the entire process. Only when cross-batch traceability cross-validation confirms that the anomaly originates from the DUT itself, and the entire process linkage cross-validation confirms that the anomaly state is consistent throughout, will the final individual failure determination result for the DUT be output. Through the above supplementary operations, the risk of misjudgment caused by hardware deviations in the test station and aging board can be further filtered, the location range of the anomaly source can be further narrowed, the logic of individual failure determination can be made more rigorous, and the results more reliable, providing a more accurate basis for subsequent protection and control actions.

[0041] In some implementations, for the aging test board containing the component under test (SUT) that is determined to have an abnormal board-level environment, board-level failure trend cross-validation is performed. The board-level failure trend cross-validation specifically includes the following steps: Collect data from the aging test board, including the distribution location of abnormal test components, abnormal parameter types, and abnormal occurrence sequence within the aging test board. At the same time, obtain failure data from aging test boards of the same batch at other workstations on the same machine. The data collected from the aging test board is cross-compared with the failure data of the same batch of aging test boards at other workstations on the same machine. If the aging test board shows a concentrated area of ​​batch anomalies, synchronous anomalies of the same type of parameters, or an overall failure rate exceeding the preset threshold, and other aging test boards in the same batch do not show corresponding anomalies, then the final result of the board-level fault determination is output.

[0042] In the implementation of the semiconductor component aging test method, after the anomaly type is determined and it is confirmed that there is an abnormality in the aging test board of the corresponding component under test, the board-level failure trend cross-verification is performed on the aging test board to complete the final determination of the board-level fault.

[0043] When implementing this verification step, the corresponding data collection and organization are completed first. For aging test boards with abnormal board-level environments, relevant data of all test components with abnormal parameters on the board are collected. Specifically, this includes the distribution location of the abnormal test components on the aging test board, the type of the corresponding abnormal parameter, and the timing information of the first occurrence of the abnormal state. At the same time, failure-related data of aging test boards produced in the same batch and loaded on other test stations in the same test machine are collected. All collected data correspond to the same test cycle and the same test operation conditions to ensure the consistency of the benchmark for data comparison.

[0044] After data collection and processing, the collected data from aging test boards exhibiting board-level environmental anomalies are cross-compared with failure data from aging test boards of the same batch at other workstations on the same machine to analyze the correlation and specificity of the anomalies. Following the comparison analysis, a final judgment is made based on the comparison results. If the aging test board shows a concentrated area of ​​batch of abnormal components under test (SUTs), multiple channels simultaneously exhibiting the same type of parameter anomaly, or the proportion of abnormal SUTs on the entire board exceeding a preset threshold, while other aging test boards of the same batch at other workstations on the same machine do not show similar anomalies, then the final board-level fault determination result for the aging test board is output.

[0045] By implementing this step, it is possible to clearly distinguish between board-level faults and batch component abnormalities or machine operating conditions that cause judgment deviations. This provides an accurate basis for subsequent faulty board replacement operations, effectively avoiding unnecessary whole-board replacement operations. At the same time, it can promptly identify the faults of the aging test board itself, ensuring the operational stability of the aging test process and the accuracy of the test results.

[0046] In some implementations, the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test are performed simultaneously, specifically including the following steps: The power cut-off action and the physical isolation action are executed synchronously, and the time difference between the two actions is less than the preset time difference threshold. A secondary test is performed on the power-off state of the corresponding test channel and the sinking state of the corresponding test socket. The results of the secondary test are cross-validated with the individual failure judgment results. If the verification fails, a system alarm is triggered and the test process of the aging test board is suspended.

[0047] During the implementation of the semiconductor device aging test method, after an individual failure is determined, the corresponding protection control action of the device under test (DUT) is executed, simultaneously executing the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the DUT. When implementing this protection control action, based on the result of the individual failure determination, the test channel to which the DUT belongs and the test socket matching the DUT are locked. Simultaneously, execution commands are sent to the power control unit of the test channel and the drive unit of the test socket, ensuring that the timing of the two commands is consistent. This ensures that the power cut-off action and the physical isolation action are started synchronously, while controlling the time difference between the completion of the two actions to be less than a preset time difference threshold, avoiding potential risks caused by premature execution of a single action.

[0048] After the two actions are completed, a secondary test is immediately performed. First, the continuity of the power supply circuit to the corresponding test channel is checked to confirm whether the power supply to the test channel is completely cut off. Second, the downward travel position of the corresponding test socket is checked to confirm whether the physical isolation action is performed correctly. The results of both secondary tests are then obtained. These results are cross-checked against the action execution requirements corresponding to the individual failure determination to verify the effectiveness of the protection actions. If the verification confirms that both actions are performed correctly and fully meet the preset requirements, the current isolation protection state is maintained, and the aging test process for other normal components under test on the aging test board continues. If the verification finds that any action fails to meet the preset execution requirements, a system alarm is immediately triggered, and the aging test process corresponding to that aging test board is paused, pending investigation and handling of the anomaly.

[0049] By implementing this step, the synchronicity and reliability of the protection actions of the failed components can be ensured, the risks of live isolation and the spread of abnormal states during the test can be avoided, and abnormalities in the execution of protection actions can be identified in a timely manner, effectively improving the safety and operational stability of the aging test process.

[0050] During the implementation of the aforementioned protection and control actions, pre-verification logic for triggering the actions can be added. The synchronously executed power cut-off and physical isolation actions will only be triggered after the device under test (DUT) has undergone multi-level cross-verification throughout the entire process, including initial screening of individual anomalies, anomaly type determination, and multi-node cross-verification, and finally outputs the individual failure determination result. In the intermediate stages of the full-process cross-verification, if only a preliminary abnormal state is marked, or if the DUT is determined to be an individual anomaly but the final failure confirmation has not been completed, only pre-protection actions such as current limiting protection and signal path disconnection of the corresponding channel are triggered. Power cut-off and physical isolation operations are not performed to avoid unnecessary interruptions to the test process.

[0051] Simultaneously, a closed-loop timing control operation for dual actions can be added to the execution phase of synchronous actions. When issuing two execution commands, in addition to maintaining consistent command issuance timing, the loop status feedback signal of the power cut-off action and the travel feedback signal of the test socket retraction action can be collected in real time. Based on the two real-time feedback signals, the drive parameters are dynamically fine-tuned to ensure that the time difference between the completion of the two actions is always within a preset threshold range, preventing the premature completion of a single action. In the secondary detection and verification phase, in addition to verifying the execution status of the action, the timing compliance during the action execution process can also be verified. Only when the action is executed in place and the timing meets the preset requirements is the protection action deemed to have been effectively executed. Through the above supplementary operations, the protection control action and the core multi-level cross-verification system can form a complete closed loop, avoiding the potential risks of live isolation and abnormal state propagation, while further improving the accuracy and reliability of protection action execution and ensuring the safe and stable operation of the aging test process.

[0052] In some implementations, the method further includes performing anomaly tracking on the device under test (DUT) marked as transient interference during multi-level cross-validation. The anomaly tracking specifically includes the following steps: Increase the sampling frequency and cross-validation frequency of the test parameters of the device under test (DUT) marked as transient interference, and continuously collect and analyze the changing trend of the test parameters of the DUT. If the test parameters of the component under test become abnormal again, multi-node cross-validation is performed.

[0053] During the implementation of semiconductor device aging test methods, in the process of completing multi-node re-inspection cross-verification, the re-inspection test parameters of each node are cross-compared. When the device under test only shows abnormal parameter deviation in a single re-inspection node, and the test parameters of the other re-inspection nodes are all within the normal range and the conditions for individual failure judgment are not met, the device under test is marked as transient interference. Abnormal state tracking is performed on the device under test marked as transient interference, and the aging test process corresponding to the device under test is not interrupted throughout the entire process, ensuring the continuity of the test process.

[0054] When performing anomaly tracking, the test parameter acquisition rules for the device under test (DUT) marked as experiencing transient interference are first adjusted. This increases the sampling frequency and cross-validation frequency of the DUT's test parameters. Compared to the standard acquisition rules for other normal DUTs in the same batch, the time interval between single parameter acquisitions is shortened, increasing the number of parameter acquisitions per unit time, while simultaneously increasing the frequency of cross-validation. After each parameter acquisition, the acquired test parameters are cross-compared with the initial baseline parameters of the DUT and the pre-calibration standard parameters of components in the same batch. The changes in the test parameters of the DUT during subsequent testing are continuously collected and analyzed, and parameter fluctuations are monitored in real time.

[0055] If the test parameters of the component under test (DUT) deviate abnormally from the preset range again during continuous tracking, the regular tracking process will be immediately paused, and multi-node cross-validation will be performed on the DUT to confirm the authenticity of the abnormal state through repeated verification under multiple operating conditions. If the tracking continues to the preset node of the test process and the test parameters of the DUT remain within the normal range without any abnormal deviation, the regular parameter acquisition and cross-validation rules for the DUT will be restored, and the remaining aging test process will continue.

[0056] By implementing this step, full-process monitoring of nondeterministic parameter fluctuations can be achieved, which can not only avoid misjudgment of failure caused by single instantaneous fluctuations, but also capture potential failure risks of the component under test in a timely manner, improve the accuracy of aging test anomaly judgment, and ensure the stable and continuous operation of the test process.

[0057] In some implementations, the method further includes performing corresponding control actions based on the real-time failure rate of the aging test board, specifically including the following steps: When the real-time failure rate of the aging test board reaches the warning threshold, the system will issue a pre-alarm and retrieve the spare aging test board to the waiting material position in advance. When the real-time failure rate of the aging test board reaches the replacement threshold, or when the board-level fault determination result is output, the automatic loading and unloading mechanism is triggered to execute the fault board replacement process.

[0058] During the implementation of semiconductor device aging test methods, the real-time failure rate of the corresponding aging test board is continuously calculated throughout the entire aging test process, providing real-time data for the hierarchical control of the test process. In the process of calculating the real-time failure rate, the number of devices under test (DUTs) on the aging test board that have undergone multi-level cross-validation for individual failure determination is updated in real time. Simultaneously, the total number of DUTs pre-loaded on the aging test board is verified. The real-time failure rate of the aging test board is then calculated accordingly. This statistical process proceeds synchronously with the test process, ensuring the real-time nature and accuracy of the failure rate data.

[0059] Based on the test specifications of the component under test and the control requirements of aging tests, failure rate grading thresholds for the aging test board are set in advance. These thresholds include warning thresholds and replacement thresholds. The warning threshold is the critical value for triggering preparatory actions, and the replacement threshold is the critical value for triggering the replacement of the entire board. During the aging test process, the real-time failure rate of the aging test board is continuously compared with the preset grading thresholds, and corresponding control actions are executed based on the comparison results.

[0060] When the real-time failure rate of the aging test board reaches the warning threshold, the system immediately triggers a pre-alarm, indicating that the failure rate of the current aging test board has reached the warning level. Simultaneously, a pre-preparation instruction is sent to the automatic loading and unloading mechanism to retrieve a spare aging test board matching the current test specifications. The spare aging test board is then transferred to the corresponding loading position at the testing station, completing the preparation work before replacement. When the real-time failure rate of the aging test board reaches the replacement threshold, or when a board-level fault determination result is output for that aging test board, a control instruction is immediately sent to the automatic loading and unloading mechanism, triggering it to execute the faulty board replacement process and replace the currently running aging test board.

[0061] By implementing this step, the operating status of the aging test board can be managed hierarchically, preparations for fault replacement can be made in advance, the operation time for fault handling can be effectively shortened, the interruption time of the test process can be reduced, and aging test boards with a high failure rate or board-level faults can be replaced in a timely manner to avoid abnormal situations from affecting the test results, thereby improving the operating efficiency of the aging test process and the reliability of the test results.

[0062] During the implementation of the above-mentioned failure rate classification and control steps, a full-process cross-validation logic for failure rate statistics can be added. The number of individual failures included in the real-time failure rate statistics must be the result of individual failures of the tested components that have been confirmed through multi-level cross-validation of the entire process, including initial screening of individual anomalies, determination of anomaly type, and multi-node back-checking. Preliminary anomalies marked in the intermediate links of the full-process cross-validation and individual anomalies that are yet to be confirmed are not included in the failure rate statistics. This is to avoid errors in failure rate statistics due to misjudgment of anomalies, which could trigger unnecessary early warnings and board replacement operations, and ensure the accuracy of failure rate data and the rationality of control actions.

[0063] Simultaneously, the system can be supplemented with linkage logic between tiered control actions and board-level cross-validation results. During the comparison of real-time failure rate and tiered thresholds, differentiated control actions are executed simultaneously based on the anomaly type determination of the aging test board and the results of board-level failure trend cross-validation. When the real-time failure rate reaches the warning threshold, but board-level cross-validation does not detect board-level environmental anomalies or a concentrated distribution of abnormal components under test, only routine pre-alarms and basic pre-preparation actions for the spare board are triggered. When the real-time failure rate reaches the warning threshold, and board-level cross-validation confirms the existence of board-level environmental anomalies or a concentrated distribution of abnormal components under test, pre-alarms are triggered, and pre-power-on calibration and docking parameter pre-configuration of the spare board are completed simultaneously, further shortening the interruption time of subsequent board replacement operations. Only when the real-time failure rate reaches the replacement threshold, or when board-level cross-validation finally outputs the board-level fault determination result, is the complete fault board replacement process triggered. Through the above supplementary operations, a complete closed loop can be formed between the failure rate classification control and the core multi-level cross-validation system, avoiding unnecessary board replacement operations caused by abnormal misjudgment. At the same time, the control actions can be optimized according to the actual situation of board-level anomalies, further shortening the interruption time of the test process, improving the continuity and overall efficiency of batch aging test tasks, and making the classification control logic more rigorous and adaptable.

[0064] In some implementations, the automatic loading and unloading mechanism is triggered to perform a faulty board replacement process, which specifically includes the following steps: First, disconnect the main power supply to the faulty aging test board, and then unlock the docking mechanism between the faulty aging test board and the test station. The faulty aging test board is taken out from the test station by the automatic loading and unloading mechanism and transferred to the faulty storage location to complete the unloading and storage. The spare aging test board is retrieved by the automatic loading and unloading mechanism and transferred to the test station to complete the docking and power-on self-test. Once the backup aging test board passes the self-test, the aging test process for this test station is initiated.

[0065] During the implementation of the semiconductor component aging test method, after the automatic loading and unloading mechanism is triggered to execute the fault board replacement process, the entire replacement operation is completed according to the preset operation sequence. First, a control command is sent to the power supply control unit of the test station to cut off the total power supply of the faulty aging test board. After confirming that the power supply to all test channels of the faulty aging test board is completely disconnected, a control command is sent to the mechanical docking mechanism of the test station to unlock the mechanical fixing structure and electrical docking interface between the faulty aging test board and the test station. After confirming that the unlocking status is correct, the unloading operation is prepared.

[0066] After the unlocking operation is completed, the actuator of the automatic loading and unloading mechanism moves to the corresponding installation position of the test station, completes the clamping and fixing with the faulty aging test board, and after confirming that the clamping state is stable and without deviation, the faulty aging test board is smoothly removed from the installation position of the test station and transferred to the pre-set fault storage position according to the preset transfer path, completing the unloading and storage of the faulty aging test board. At the same time, the number of the faulty aging test board and the corresponding fault information are recorded to facilitate subsequent fault investigation and handling.

[0067] After the failure aging test board is unloaded, the automatic loading and unloading mechanism immediately retrieves the pre-prepared spare aging test board and smoothly moves it to the corresponding installation position at the test station. After mechanical fixing and electrical connection are completed, the preset power-on self-test process is started to comprehensively verify the on / off status of each test channel, the reliability of electrical connection, and the connection status of the component under test on the spare aging test board. After confirming that all self-test results meet the test operation requirements, the aging test process of the test station is automatically started to continue the batch test task.

[0068] By implementing this process, the safety and accuracy of the replacement process can be guaranteed, the risk of equipment and component damage caused by live operation can be avoided, the test process of the test station can be restored quickly, the test interruption time can be effectively shortened, the continuous and stable progress of batch aging test tasks can be guaranteed, and the overall operating efficiency of aging test can be improved.

[0069] During the implementation of the above-mentioned faulty board replacement process, pre-verification logic can be added to trigger the replacement process. This faulty board replacement process will only be triggered when the aging test board has undergone multi-level cross-verification throughout the entire process, including anomaly type determination and board-level failure trend cross-verification, and the final output of the board-level failure determination result, or when the real-time failure rate obtained from the individual failure count confirmed by the entire process cross-verification reaches the replacement threshold. Preliminary board-level environment anomalies and batch parameter anomalies marked in the intermediate links of the entire process cross-verification will not trigger the complete faulty board replacement process, but will only trigger corresponding early warning and pre-preparation actions to avoid unnecessary test process interruptions and board replacement operations, and ensure the continuity of batch test tasks.

[0070] Simultaneously, cross-validation and calibration operations before and after the replacement process can be added. In the pre-preparation stage of the spare aging test board, the full-process cross-validation data of the failed aging test board can be reused. Combined with the historical benchmark parameters of the test station, the full-channel temperature drift compensation pre-calibration of the spare aging test board can be completed in advance, generating a dedicated parameter comparison benchmark adapted to this test station, avoiding benchmark deviations after board replacement. In the power-on self-test stage of the spare aging test board, in addition to completing the routine continuity and connection status verification, a pre-cross-validation operation of the board's channels can be added. The initial parameters of each channel of the spare aging test board are cross-compared with the benchmark parameters of the standard reference channel and the parameters under the same operating conditions of normal aging test boards in the same batch. After confirming that the parameters of each channel are within the normal range, the aging test process is started. After completing the board replacement and restart test, the initial parameters of the newly started test process can be cross-validated with the normal test parameters of the failed aging test board before failure and the parameters under the same operating conditions of other test stations in the same batch, ensuring the consistency of the test benchmark and avoiding the impact of the board replacement operation on the accuracy of the test results. The above supplementary operations allow the fully automated fault board replacement process to form a complete closed loop with the core multi-level cross-validation system, further ensuring the rationality of the replacement operation and the consistency of the test benchmark. This not only avoids unnecessary board replacement operations but also further shortens the interruption time of the test process, improving the operational stability of batch aging test tasks and the reliability of test results.

[0071] This application also provides a semiconductor device aging test system, including: Test station 100 is used to load the aging test board 600 and is electrically connected to the loaded aging test board 600 to provide a test environment and electrical signal path for the aging test of the component under test. The parameter acquisition unit 200 is set at the test station 100. The signal acquisition end of the parameter acquisition unit 200 is electrically connected to each component under test on the aging test board 600. The signal output end of the parameter acquisition unit 200 is communicatively connected to the main control unit 500. It is used to acquire the test parameters of each component under test on the aging test board 600 in real time and transmit the acquired test parameters to the main control unit 500. The channel protection execution unit 300 is connected to the main control unit 500. The execution end of the channel protection execution unit 300 corresponds one-to-one with the test channel and test socket of each component under test on the aging test board 600. It is used to synchronously execute the power cut-off action of the corresponding test channel and the sinking physical isolation action of the test socket of the corresponding component under test according to the control command issued by the main control unit 500. The automatic loading and unloading mechanism 400 is connected to the main control unit 500 and is used to perform the docking operation between the aging test board 600 and the test station 100, the unloading operation of the aging test board 600, and the replacement operation of the faulty aging test board 600 according to the control instructions issued by the main control unit 500. The main control unit 500 is communicatively connected to the parameter acquisition unit 200, the channel protection execution unit 300, and the automatic loading and unloading mechanism 400, respectively. It is used to receive test parameters transmitted by the parameter acquisition unit 200 and output graded control commands to the channel protection execution unit 300 and the automatic loading and unloading mechanism 400.

[0072] The semiconductor component aging test system is used to complete the entire aging test process for semiconductor components. The system comprises a test station, parameter acquisition unit, channel protection execution unit, automatic loading and unloading mechanism, and main control unit. These units communicate and exchange signals via pre-defined communication links, collaboratively completing the entire aging test process. The test station is positioned at a corresponding location on the testing machine and is used to load the aging test board. Once loaded, the test station establishes a stable electrical connection with the board, providing a suitable testing environment and a stable electrical signal path for the components under test, ensuring the normal operation of the aging test process.

[0073] The parameter acquisition unit is fixedly installed at the corresponding position of the test station. The signal acquisition end of the parameter acquisition unit can form a one-to-one electrical connection with each component under test on the aging test board that is mounted in place. The signal output end of the parameter acquisition unit forms a stable communication connection with the main control unit through a communication link. Throughout the entire cycle of the aging test process, the parameter acquisition unit can collect the test parameters generated by each component under test on the aging test board in real time according to the preset acquisition rules, and transmit the collected test parameters completely to the main control unit, providing complete and continuous data support for subsequent abnormal state judgment.

[0074] The channel protection execution unit establishes a stable communication connection with the main control unit via a communication link. The execution end of the channel protection execution unit can form a one-to-one linkage relationship with the test channels and test sockets of each component under test on the mounted aging test board. Based on control commands issued by the main control unit, it can synchronously complete the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test, achieving reliable isolation protection for the failed component under test. The automatic loading and unloading mechanism also establishes a stable communication connection with the main control unit via a communication link. Based on control commands issued by the main control unit, it can complete the smooth transfer of the aging test board, the docking and fixing of the aging test board to the test station, the unloading and transfer of the completed aging test board, and the complete replacement of faulty aging test boards, achieving fully automated operation of the aging test board loading and unloading process.

[0075] As the core control unit of the system, the main control unit forms a stable communication connection with the parameter acquisition unit, the channel protection execution unit, and the automatic loading and unloading mechanism through the communication link. It can receive the test parameters of the component under test transmitted by the parameter acquisition unit, and after completing the parameter verification and analysis, it outputs the corresponding hierarchical control commands to the channel protection execution unit and the automatic loading and unloading mechanism to control each unit to complete the corresponding operation. At the same time, it can monitor the operating status of the entire system in real time to ensure the stable and coordinated operation of each unit.

[0076] This system enables the automated operation of the entire semiconductor component aging test process. It allows for the accurate identification and hierarchical control of abnormal situations during testing, ensuring the continuous and stable operation of the aging test process, improving the safety of the aging test process and the reliability of the test results. At the same time, it can reduce the frequency of manual intervention, optimize the overall operating efficiency of the aging test, adapt to the aging test requirements of semiconductor components of different specifications, and has good operational stability and scenario adaptability.

[0077] The above description is merely a preferred embodiment and the technical principles employed in this application. This application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions that can be made by those skilled in the art will not depart from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application.

Claims

1. A semiconductor device aging test method, applied to an aging test system including an aging test board, a test station, and an automatic loading and unloading mechanism, characterized in that, Includes the following steps: S1. Load the aging test board containing the components under test and connect it with the test station. Start the preset aging test process and collect the test parameters of each component under test on the aging test board in real time. S2. Perform multi-level cross-validation on the collected test parameters, distinguish and output graded judgment results, including individual failure judgment and board-level fault judgment. S3. Execute hierarchical control according to the hierarchical judgment result. If the output is determined to be an individual failure, simultaneously execute the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test. If the output is determined to be a board-level failure, trigger the automatic loading and unloading mechanism to execute the fault board replacement process. S4. After the aging test board completes the preset aging test process, the automatic loading and unloading mechanism is triggered to execute the finished product unloading process, and the automatic loading of the next aging test board is completed simultaneously.

2. The method according to claim 1, characterized in that, The multi-level cross-validation includes an initial screening step for individual anomalies of a single device under test, which specifically includes: The test parameters of a single component under test are collected synchronously, including static electrical parameters, dynamic functional parameters, and timing consistency parameters. The currently collected test parameters are cross-compared with the power-on initial reference parameters of the component under test and the pre-calibration standard parameters of components in the same batch. When multiple types of parameters show abnormal deviations simultaneously, the component under test is marked as having a preliminary abnormal state.

3. The method according to claim 2, characterized in that, The multi-level cross-validation also includes an anomaly type determination step for the device under test (DUT) marked as having a preliminary anomaly state. The anomaly type determination step specifically includes: The test parameters of the test component marked as having a preliminary abnormal state are cross-compared with the normal parameters of the cluster of adjacent test components of the same specification in the aging test board and the reference parameters of the preset standard reference channel without test components in the board. If only the test parameters of the component under test are abnormal, it is determined that the component under test is abnormal; if the test parameters of multiple components under test in the same area show abnormal deviations simultaneously, and the reference parameters of the standard reference channel are also abnormal, it is determined that the aging test board-level environment is abnormal.

4. The method according to claim 3, characterized in that, For devices under test (DUTs) determined to be individually abnormal, multi-node cross-validation is performed. The multi-node cross-validation specifically includes the following steps: The test parameters for each node are obtained by sequentially performing a light load test mode retest, a static parameter retest, and a power-off restart retest on the component under test. Cross-validate the backtesting parameters of each node. When the test results of all backtesting nodes confirm anomalies, output the individual failure determination result.

5. The method according to claim 3, characterized in that, For the aging test board containing the component under test (SUT) that is determined to have an abnormal board-level environment, cross-validation of board-level failure trends is performed. The cross-validation of board-level failure trends specifically includes the following steps: Collect data from the aging test board, including the distribution location of abnormal test components, abnormal parameter types, and abnormal occurrence sequence within the aging test board. At the same time, obtain failure data from aging test boards of the same batch at other workstations on the same machine. The data collected from the aging test board is cross-compared with the failure data of the same batch of aging test boards at other workstations on the same machine. If the aging test board shows a concentrated area of ​​batch anomalies, synchronous anomalies of the same type of parameters, or an overall failure rate exceeding the preset threshold, and other aging test boards in the same batch do not show corresponding anomalies, then the final result of the board-level fault determination is output.

6. The method according to claim 1, characterized in that, The synchronous execution of the power cut-off action for the corresponding test channel and the physical isolation action of the test socket for the corresponding component under test specifically includes the following steps: The power cut-off action and the sinking physical isolation action are executed synchronously, and the execution time difference between the two actions is less than a preset time difference threshold. A secondary test is performed on the power-off state of the corresponding test channel and the sinking state of the corresponding test socket. The results of the secondary test are cross-validated with the individual failure judgment results. If the verification fails, a system alarm is triggered and the test process of the aging test board is suspended.

7. The method according to claim 4, characterized in that, The method further includes performing abnormal state tracking on the device under test marked as transient interference during the multi-level cross-validation process, and the abnormal state tracking specifically includes the following steps: Increase the sampling frequency and cross-validation frequency of the test parameters of the device under test (DUT) marked as transient interference, and continuously collect and analyze the changing trend of the test parameters of the DUT. If the test parameters of the component under test become abnormal again, the multi-node back-check cross-validation is performed.

8. The method according to claim 1, characterized in that, The method further includes executing corresponding control actions based on the real-time failure rate of the aging test board, specifically including the following steps: When the real-time failure rate of the aging test board reaches the warning threshold, the system will issue a pre-alarm and retrieve the spare aging test board to the waiting material position in advance. When the real-time failure rate of the aging test board reaches the replacement threshold, or when the board-level fault determination result is output, the automatic loading and unloading mechanism is triggered to execute the fault board replacement process.

9. The method according to claim 8, characterized in that, The process of triggering the automatic loading and unloading mechanism to perform the faulty board replacement includes the following steps: First, disconnect the main power supply to the faulty aging test board, and then unlock the docking mechanism between the faulty aging test board and the test station. The faulty aging test board is taken out from the test station by the automatic loading and unloading mechanism and transferred to the faulty storage location to complete the unloading and storage. The spare aging test board is retrieved by the automatic loading and unloading mechanism and transferred to the test station to complete the docking and power-on self-test. Once the backup aging test board passes the self-test, the aging test process for this test station is initiated.

10. A semiconductor device aging test system, characterized in that, include: The test station is used to load the aging test board and is electrically connected to the loaded aging test board to provide a test environment and electrical signal path for the aging test of the component under test. The parameter acquisition unit is located at the test station. The signal acquisition end of the parameter acquisition unit is electrically connected to each component under test on the aging test board. The signal output end of the parameter acquisition unit is communicatively connected to the main control unit. It is used to acquire the test parameters of each component under test on the aging test board in real time and transmit the acquired test parameters to the main control unit. The channel protection execution unit is connected to the main control unit. The execution end of the channel protection execution unit corresponds one-to-one with the test channel and test socket of each component under test on the aging test board. It is used to synchronously execute the power cut-off action of the corresponding test channel and the physical isolation action of the test socket of the corresponding component under test according to the control command issued by the main control unit. The automatic loading and unloading mechanism is connected to the main control unit and is used to perform the docking operation between the aging test board and the test station, the unloading operation of the aging test board, and the replacement operation of the faulty aging test board according to the control instructions issued by the main control unit. The main control unit is connected to the parameter acquisition unit, the channel protection execution unit, and the automatic loading and unloading mechanism. It is used to receive test parameters transmitted by the parameter acquisition unit and output graded control commands to the channel protection execution unit and the automatic loading and unloading mechanism.

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