Low-noise time quantization circuit suitable for laser radar focal plane detector
By employing a low-noise time quantization circuit based on the correlation double sampling principle in the lidar focal plane detector, the noise interference problem of the time-to-analog conversion circuit is solved by buffering the reset voltage and the effective signal voltage and calculating the difference. This achieves low-noise, low-power time quantization and improves the imaging signal-to-noise ratio.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SOUTH WEST INST OF TECHN PHYSICS
- Filing Date
- 2025-12-25
- Publication Date
- 2026-05-12
AI Technical Summary
The time-to-analog conversion circuit of existing lidar focal plane detectors is susceptible to interference from 1/f noise, KCT noise and fixed-mode noise, resulting in a reduced signal-to-noise ratio and making it difficult to achieve low-noise and low-power time quantization.
A low-noise time quantization circuit is adopted. The reset voltage and effective signal voltage are cached in the pre-storage circuit in the pixel unit using the correlation double sampling principle. The difference is read from the column bus to the correlation double sampling circuit to reduce the impact of noise. At the same time, the bias current source is controlled to be turned on only when the pre-storage circuit is working, and the column bus bias current source is shared to reduce power consumption.
It effectively reduces the impact of 1/f noise, KCT noise and array fixed mode noise, improves the signal-to-noise ratio of focal plane imaging, and reduces the power consumption of time quantization and readout circuits.
Smart Images
Figure CN122017791A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of readout circuit technology for lidar focal plane detectors, and specifically relates to a low-noise time quantization circuit suitable for lidar focal plane detectors. Background Technology
[0002] Traditional munitions are inexpensive to manufacture but suffer from poor accuracy and low cost-effectiveness. In contrast, precision-guided weapons in modern weaponry offer high accuracy and cost-effectiveness, attracting increasing attention in the field of weaponry. Currently, lidar focal plane arrays have been successfully applied to modern precision-guided weapons, showing broad application prospects in fire control systems, target identification, and ballistic interception. Lidar focal plane arrays feature long detection range, rapid target acquisition, and high frame rate, enabling them to quickly track various high-speed moving military targets and provide reliable imaging data for defense systems.
[0003] LiDAR focal plane array detectors commonly use avalanche diodes (APDs) as the front-end detection device. Based on their operating state, APDs can be divided into linear-mode APDs and Geiger-mode APDs. Linear-mode APD focal plane array detectors convert laser echo pulses into voltage pulse signals using a transimpedance amplifier (TIA) and comparator; Geiger-mode APD focal plane array detectors convert laser echo pulses into voltage pulse signals using a quenching circuit and a digital pulse shaping circuit (such as an inverter). In lidar focal plane array detectors, the distance to the reflector is typically measured using direct time-of-flight measurement to achieve three-dimensional imaging. Time-to-digital converters (TDCs) and time-to-analog converters (TACs) are two common time measurement circuits. TDC circuits directly convert time information into digital information, possessing strong noise suppression and anti-interference capabilities. However, they have complex structures, high power consumption, and large layout areas. Furthermore, TDC circuits are typically implemented based on high-frequency clocks or multi-phase clock detection methods. High-frequency clock flipping can cause severe interference to power and ground signals. In linear mode APD focal plane detectors, high-frequency power and ground noise can severely interfere with analog circuits such as TIAs and comparators, leading to a decrease in detection performance.
[0004] Compared to time-to-digital converters (TDCs), circuits based on time-to-analog converters (TACs) avoid the use of numerous digital units and do not require high-frequency or multi-phase clock signals. Their area and power consumption are significantly smaller than TDC circuits, which is beneficial for improving the pixel fill factor. Furthermore, in linear-mode APD focal plane detectors, TAC circuits do not cause excessive interference to the power supply and ground signals, thus reducing the power supply rejection ratio requirements of analog front-end circuits such as TIAs and comparators, which helps improve the overall signal-to-noise ratio of the pixel front-end circuit. However, TAC circuits also have some problems. First, the analog voltage signal generated by the TAC circuit is susceptible to interference from 1 / f noise, KCT noise, etc. Second, trace errors on the analog readout bus and threshold voltage deviations of the source follower in the pixel readout circuit can further cause fixed-mode noise, leading to a decrease in the signal-to-noise ratio of array imaging. How to achieve low-noise time quantization and readout of lidar focal plane detectors based on TAC circuits is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] (a) Technical problems to be solved The technical problem to be solved by the present invention is to provide a low-noise time quantization circuit suitable for lidar focal plane detectors, in order to meet the requirements of small size, low noise and low power consumption of large array focal plane detectors.
[0006] (II) Technical Solution To address the aforementioned technical problems, this invention provides a low-noise time quantization circuit suitable for lidar focal plane detectors, comprising an input logic unit, a time-to-analog conversion circuit, a pre-storage circuit within a pixel unit, a column bus, a column-parallel correlated double sampling circuit, and an analog-to-digital conversion circuit. The input logic unit receives a trigger signal TRG and an enable signal EXP_EN, and correspondingly generates a conversion time gate signal GATE. The time-to-analog conversion circuit includes a timing capacitor C0, used to convert the pulse width of the conversion time gate signal GATE into a voltage signal on the timing capacitor C0. The pre-storage circuit within the pixel unit stores the reset voltage V on the timing capacitor C0. RST0 and effective signal voltage V SIG0 The data is then read from the column bus onto the column parallel correlated double sampling circuit, which is used to measure the reset voltage V. RST0 and effective signal voltage V SIG0 By subtracting the values, we obtain the voltage change V across the timing capacitor C0. RST0 -V SIG0 The analog-to-digital converter further converts the output voltage of the parallel correlation double sampling circuit into a digital signal D. OUT Output.
[0007] The present invention also provides a method for operating the circuit, comprising the following steps: (1) Reset phase: Before detection, the enable signal EXP_EN is low, the reset signal RSTN is set low, and the D flip-flop is reset, so that it... The output is high; simultaneously, the PMOS reset transistor M is enabled. RST0 Reset the timing capacitor C0 to a high-level voltage V. RST0 Subsequently, the reset signal RSTN is set to high level, turning off the reset transistor M. RST0 The base signal EN2 of T1, the gate signal EN1 of NM2, and the base signal EN3 of T2 are set to high level. Capacitor C1 samples and stores the reset voltage on timing capacitor C0 through source follower SF1. Then, control signal EN3 returns to low level, turning off transmission transistor T2. (2) Global detection phase: The trigger signal TRG is initially low, the work enable signal EXP_EN is set to high, the conversion time gate signal GATE in the input logic unit is high, the NM1 transistor is turned on, and the timing capacitor C0 is discharged through the adjustable current I0; when the pixel front-end circuit detects the photon signal and generates a corresponding high-level pulse signal TRG, the rising edge of the signal TRG triggers the D flip-flop to latch the high level. When the terminal signal goes low, the GATE signal goes low, NM1 is turned off, and the timing capacitor C0 stops discharging. When EXP_EN goes low, the detection ends. Then, the base signal EN4 of T3 is set to high. Capacitor C2 samples and stores the voltage on the timing capacitor C0 through the source follower SF1. After completion, the signal EN4 is set low, turning off the transmission transistor T3. The EN1 signal is set low, turning off the bias current I1. (3) Row pixel readout sampling stage: After the global detection is completed, the voltage signals on capacitors C1 and C2 are read out row by row. When the first row of pixels is read out, the corresponding working sequence is as follows: First, the reset signal RSTN is set to low level; the column bus transmission tube control signal EN5 in the first row of pixels is set to high level, and the T4 tube is turned on. The signal EN5 in the other rows of pixels is kept at low level, and EN5 is input from the base of T4; the signal EN1 in the first row of pixel readout unit is set to high level, and the bias current source I1 is turned on. The parasitic capacitance at point X of the emitter of T1 is pre-charged through the source follower tube SF1 and the transmission tube T1; then the signals EN2 and EN1 are set to low level in sequence, and the transmission tube T1 is turned off; the signal EN3 is set to high level, and the reset voltage signal V stored on capacitor C1 is read out. RST0 Read out via the column bus, at this time the gate F of T5 in the column parallel correlated double sampling circuit. R When the signal is set to high, transistor T5 is turned on, and the sampling capacitor C... R V on capacitor C1 RST0The signal is sampled; after sampling, EN3, F R The signal is set to low level; then EN1 and EN2 signals are set to high level again to recharge the parasitic capacitance at point X. After precharging, EN2 and EN1 signals are set to low level in sequence; then EN4 at the base of T3 in the pre-storage circuit within the pixel unit and F at the gate of T7 in the column-parallel correlated dual sampling circuit... S The signal is set to high level, and the sampling capacitor C S V on capacitor C2 SIG0 The signal is sampled; after sampling, EN4, F S The signal is set to low level, F CDS When the signal is set to high, the correlated double sampling circuit uses a difference circuit based on a switched-capacitor amplifier to sample capacitor C. R C S The effective signal V is obtained by subtracting the voltages on the input voltage. RST0 -V SIG0 ; (4) Analog-to-digital conversion stage: The analog-to-digital conversion circuit converts the signal V RST0 -V SIG0 Converted to digital signal D OUT The signal is then output to an external or on-chip digital signal processing unit via a digital bus. (5) Row rolling readout stage: Repeat stages (3) and (4), drive the control signals EN1, EN2, EN3, EN4 and EN5 in the pixel array by row, and configure the column parallel related dual sampling circuit and analog-to-digital conversion circuit according to the corresponding timing to realize the signal readout and conversion of the entire pixel array.
[0008] (III) Beneficial Effects The low-noise time quantization circuit for lidar focal plane detectors provided by this invention has the following advantages: Compared with the traditional TAC architecture, this invention is based on the correlation double sampling principle. It utilizes the noise correlation between the reset signal and the effective signal in the same pixel readout circuit, uses the pre-storage circuit in the pixel readout unit to buffer the reset voltage and the effective signal voltage, and reads them to the correlation double sampling circuit through the column bus to perform the difference. This greatly reduces the influence of noise such as 1 / f noise, KCT noise, and array fixed mode noise, and improves the signal-to-noise ratio of focal plane imaging.
[0009] In terms of circuit implementation, by controlling the bias current source I1 in the pre-storage circuit to be turned on only when the pre-storage circuit is working, and by sharing the column bus bias current source I2 with a column of readout circuits, the power consumption of time quantization and readout circuits is reduced, thus realizing a low-noise, low-power time quantization circuit with strong application transformation value. Attached Figure Description
[0010] Figure 1 A topology diagram of a low-noise time quantization circuit suitable for a lidar focal plane detector provided in an embodiment of the present invention; Figure 2 The timing diagram of the control signal for a low-noise time quantization circuit suitable for a lidar focal plane detector is provided for embodiments of the present invention. Detailed Implementation
[0011] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0012] Example 1: As Figure 1 As shown, this embodiment 1 provides a low-noise time quantization circuit suitable for lidar focal plane detectors, including an input logic unit, a time-to-analog conversion circuit, a pre-storage circuit within a pixel unit, a column bus, a column-parallel correlated double sampling circuit, and an analog-to-digital conversion circuit. The input logic unit receives a trigger signal TRG and an enable signal EXP_EN, and generates a corresponding conversion time gate signal GATE. The time-to-analog conversion circuit converts the pulse width of the GATE signal into a voltage signal on capacitor C0. The pre-storage circuit within the pixel unit stores the reset voltage V on capacitor C0. RST0 and effective signal voltage V SIG0 Subsequently, the data is read through the column bus to the column parallel correlated double sampling circuit, which then processes the reset voltage V. RST0 and effective signal voltage V SIG0 By taking the difference, we obtain the voltage change V across capacitor C0. RST0 - V SIG0 Furthermore, it eliminates related noise such as 1 / f noise, KCT noise, and array fixed-mode noise; the analog-to-digital converter further converts the output voltage of the related dual-sampling circuit into a digital signal D. OUT Output.
[0013] The input logic unit consists of a D flip-flop and an AND gate. The reset signal RSTN resets the input logic unit before operation begins. The avalanche pulse input signal TRG is connected to the clock port CK of the D flip-flop and the inverting output terminal of the D flip-flop. The input of the AND gate is connected to the enable signal EXP_EN, and the output of the AND gate is the time-gated signal GATE. The time analog conversion circuit consists of a timing capacitor C0 and a reset transistor M. RST0 It consists of an adjustable current source I0 and a switching transistor NM1; the reset signal RSTN is connected to the reset transistor M. RST0 When the RSTN signal is low, the timing capacitor C0 is reset to high level. The pre-storage circuit within the pixel unit consists of a source follower transistor SF1, a bias current source I1, a current switch transistor NM2, transmission transistors T1, T2, and T3, and capacitors C1 and C2; wherein the transmission transistors T2 and T3, and capacitors C1 and C2 are the same size and dimensions, and are symmetrically laid out.
[0014] The column bus consists of a source follower transistor SF2, a transmission transistor T4, and a column shared current source I2; the gate of the source follower transistor is connected to the output of the pre-storage circuit; the output of the column bus is connected to the input of the correlated dual sampling circuit.
[0015] The related dual-sampling circuit consists of a switching transistor, a sampling capacitor, and an operational amplifier; the switching transistor T5 and the sampling capacitor C... R Sample the reset voltage; switch T7, sampling capacitor C S Sampling of signal voltage; F CDS After the control switches T6 and T8 are turned on, the operational amplifier calculates the difference between the voltage across the sampling capacitor to obtain the effective signal V. RST0 -V SIG0 .
[0016] The input of the analog-to-digital converter is connected to the output V of the correlated double sampling circuit. RST0 -V SIG0 And convert it into a digital signal D OUT Output the results.
[0017] This embodiment 1 provides a low-noise time quantization circuit suitable for lidar focal plane detectors, such as... Figure 2 As shown, the workflow is as follows: (1) Reset phase: Before detection, the enable signal EXP_EN is low, the reset signal RSTN is set low, and the D flip-flop is reset, so that it... The output is high; simultaneously, the PMOS reset transistor M is enabled. RST0 Reset the timing capacitor C0 to a high-level voltage V. RST0 Subsequently, the reset signal RSTN is set to high level, turning off the reset transistor M. RST0 When EN1, EN2, and EN3 signals are set to high level, capacitor C1 samples and stores the reset voltage on timing capacitor C0 through source follower SF1. Then, control signal EN3 returns to low level, turning off transmission transistor T2. (2) Global detection phase: The trigger signal TRG is initially low, the work enable signal EXP_EN is set to high, the AND gate output signal GATE in the input logic unit is high, the NM1 pipe is turned on, and the timing capacitor C0 is discharged through the adjustable current I0; when the pixel front-end circuit detects the photon signal and generates a corresponding high-level pulse signal TRG, the rising edge of this signal triggers the D flip-flop to latch the high level. When the terminal signal goes low, the GATE signal then goes low, NM1 is turned off, and the timing capacitor C0 stops discharging. When EXP_EN goes low, the detection ends, and the EN4 signal goes high. Capacitor C2 samples and stores the voltage on the timing capacitor C0 through the source follower SF1. After this is completed, the EN4 signal goes low, turning off the transmission transistor T3; the EN1 signal goes low, turning off the bias current I1. (3) Row pixel readout sampling stage: After the global detection is completed, the pixel readout unit array reads out the voltage signals on capacitors C1 and C2 row by row. When the first row of pixels is read out, the corresponding working sequence is as follows: First, the reset signal RSTN is set to low level; the column bus transmission tube control signal EN5 in the first row of pixels is set to high level, and the T4 tube is turned on, while EN5 in the other rows of pixels remains low level; the signal EN1 in the first row of pixel readout unit is set to high level, and the bias current source I1 is turned on, and the parasitic capacitance of node X is pre-charged through the source follower tube SF1 and the transmission tube T1 to avoid the error caused by the charge sharing effect of the node parasitic capacitance; then the signals EN2 and EN1 are set to low level in sequence, and the transmission tube T1 is turned off; the signal EN3 is set to high level, and the reset voltage signal V stored on capacitor C1 is read out. RST0 Read out via the column bus, at which point F in the relevant double sampling circuit... R When the signal is set to high, transistor T5 is turned on, and the sampling capacitor C... R V on capacitor C1 RST0 The signal is sampled; after sampling, EN3, F R The signal is set low; then EN1 and EN2 are set high again to recharge the parasitic capacitance of node X. After precharging, EN2 and EN1 are set low in sequence; then EN4 in the pre-storage circuit and the gate F of T7 in the related dual sampling circuit are... S The signal is set to high level, and the sampling capacitor C S V on capacitor C2 SIG0 The signal is sampled; after sampling, EN4, F S The signal is set to low level, F CDS When the signal is set to high, the correlated double sampling circuit uses a difference circuit based on a switched-capacitor amplifier to sample capacitor C. R C S The effective signal V is obtained by subtracting the voltages on the input voltage. RST0 -V SIG0 ; (4) Analog-to-digital conversion stage: The analog-to-digital conversion circuit converts the signal V RST0 -V SIG0 Converted to digital signal D OUTThe signal is then output to an external or on-chip digital signal processing unit via a digital bus; after analog-to-digital conversion, the signal F... CDS Both the row selection signal EN5 and the row selection signal EN5 are set to low level; (5) Row rolling readout stage: Repeat stages (3) and (4), drive the control signals EN1, EN2, EN3, EN4 and EN5 in the pixel array row by row, and configure the relevant dual sampling circuit and analog-to-digital conversion circuit according to the corresponding timing to realize the signal readout and conversion of the entire pixel array.
[0018] In summary, this invention provides a low-noise time quantization circuit suitable for lidar focal plane detectors, comprising: the input logic unit, a time-to-analog conversion circuit, a pre-storage circuit within the pixel unit, a column bus, a column-parallel correlated double sampling circuit, and an analog-to-digital conversion circuit. Compared with the traditional TAC architecture, this invention, based on the correlated double sampling principle, utilizes the noise correlation between the reset signal and the effective signal in the same pixel readout circuit. The pre-storage circuit within the pixel readout unit buffers the reset voltage and the effective signal voltage, and reads them out via the column bus to the correlated double sampling circuit for subtraction. This significantly reduces the impact of correlated noise such as 1 / f noise, KCT noise, and array fixed-mode noise, thereby improving the signal-to-noise ratio of focal plane imaging. In terms of circuit implementation, by controlling the bias current source I1 in the pre-storage circuit to only be activated when the pre-storage circuit is working, and by sharing the column bus bias current source I2 among all readout circuits, the power consumption of the time quantization and readout circuits is reduced, achieving a low-noise, low-power time quantization circuit with strong application transformation value.
[0019] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A low-noise time quantization circuit suitable for lidar focal plane detectors, characterized in that, The system includes an input logic unit, a time-to-analog converter circuit, a pre-storage circuit within each pixel unit, a column bus, a column-parallel correlated double sampling circuit, and an analog-to-digital converter circuit. The input logic unit receives a trigger signal TRG and an enable signal EXP_EN, and generates a corresponding conversion time gate signal GATE. The time-to-analog converter circuit includes a timing capacitor C0, which converts the pulse width of the conversion time gate signal GATE into a voltage signal on the timing capacitor C0. The pre-storage circuit within each pixel unit stores the reset voltage V on the timing capacitor C0. RST0 and effective signal voltage V SIG0 The data is then read from the column bus onto the column parallel correlated double sampling circuit, which is used to measure the reset voltage V. RST0 and effective signal voltage V SIG0 By subtracting the values, we obtain the voltage change V across the timing capacitor C0. RST0 -V SIG0 The analog-to-digital converter further converts the output voltage of the parallel correlation double sampling circuit into a digital signal D. OUT Output.
2. The circuit as described in claim 1, characterized in that, The input logic unit consists of a D flip-flop and an AND gate. The reset signal RSTN resets the input logic unit before operation. The trigger signal TRG is an avalanche pulse input signal, connected to the clock port CK of the D flip-flop and the inverting output terminal of the D flip-flop. The input of the AND gate is connected to the enable signal EXP_EN, and the output of the AND gate is the time-gated signal GATE.
3. The circuit as described in claim 2, characterized in that, The time analog conversion circuit consists of a timing capacitor C0 and a reset transistor M. RST0 It consists of an adjustable current source I0 and a switching transistor NM1; the reset signal RSTN is connected to the reset transistor M. RST0 The gate of the switching transistor NM1 is connected to the gate of the switching transistor NM1. The source of the switching transistor NM1 is connected to one end of C0, the drain is connected to one end of I0, and the other end is connected to M. RST0 At the drain and the other end of C0, when the reset signal RSTN is low, the timing capacitor C0 is reset to high.
4. The circuit as described in claim 3, characterized in that, The pre-storage circuit within the pixel unit consists of a source follower transistor SF1, a bias current source I1, a current switch transistor NM2, transmission transistors T1, T2, and T3, and capacitors C1 and C2; wherein the drain of SF1 is connected to M RST0 The source and gate are connected to the other end of C0. The source is connected to one end of I1 and the collector of T1. The other end of I1 is connected to the drain of NM2. The source of NM2 is grounded. The emitter of T1 is connected to the collector of T3 and the collector of T2. The emitter of T2 is connected to one end of C1. The other end of C1 is grounded. The emitter of T3 is connected to one end of C2. The other end of C2 is grounded.
5. The circuit as described in claim 4, characterized in that, The column bus consists of a source follower transistor SF2, a transmission transistor T4, and a column shared current source I2. The gate of the source follower transistor SF2 is connected to the output of the pre-storage circuit in the pixel unit, i.e., the emitter of T1. The source of the source follower transistor SF2 is connected to the collector of T4. The emitter of T4 is connected to one end of I2 and serves as the output of the column bus. The other end of I2 is grounded. The output of the column bus is connected to the input of the column parallel correlated dual sampling circuit.
6. The circuit as described in claim 5, characterized in that, The parallel correlation dual sampling circuit consists of switching transistors T5~T8 and sampling capacitor C. S C R It consists of an operational amplifier; the source of T5 is connected to one end of I2, and the drain is connected to C. R One end of T6 is connected to the source, and the drain of T6 is connected to the first input terminal of the operational amplifier. The source of T7 is connected to one end of I2, and the drain is connected to C. S One end, the source of T8, and the drain of T8 are connected to the second input terminal of the operational amplifier. The output terminal of the operational amplifier is the output terminal of the column-parallel correlated double sampling circuit. The gates of T6 and T8 are connected. C S C R The other end is grounded; switch T5, sampling capacitor C R For reset voltage V RST0 Sampling; switching transistor T7, sampling capacitor C S For the effective signal voltage V SIG0 Sampling; Signal F at gate T8 CDS After the control switches T6 and T8 are turned on, the operational amplifier calculates the difference between the voltages across the two sampling capacitors to obtain the effective signal V. RST0 -V SIG0 .
7. The circuit as described in claim 6, characterized in that, The input of the analog-to-digital converter is connected to the parallel correlated double sampling circuit output V. RST0 -V SIG0 And convert it into a digital signal D OUT Output the results.
8. The circuit as described in claim 7, characterized in that, Transmission tubes T2 and T3 are the same size and dimensions, and capacitors C1 and C2 are the same size and dimensions.
9. A method of operating the circuit as described in claim 7 or 8, characterized in that, Includes the following steps: (1) Reset phase: Before detection, the enable signal EXP_EN is low, the reset signal RSTN is set low, and the D flip-flop is reset, so that it... The output is high; simultaneously, the PMOS reset transistor M is enabled. RST0 Reset the timing capacitor C0 to a high-level voltage V. RST0 Subsequently, the reset signal RSTN is set to high level, turning off the reset transistor M. RST0 The base signal EN2 of T1, the gate signal EN1 of NM2, and the base signal EN3 of T2 are set to high level. Capacitor C1 samples and stores the reset voltage on timing capacitor C0 through source follower SF1. Then, control signal EN3 returns to low level, turning off transmission transistor T2. (2) Global detection phase: The trigger signal TRG is initially low, the work enable signal EXP_EN is set to high, the conversion time gate signal GATE in the input logic unit is high, the NM1 transistor is turned on, and the timing capacitor C0 is discharged through the adjustable current I0; When the pixel front-end circuit detects a photon signal and generates a corresponding high-level pulse signal TRG, the rising edge of the TRG signal triggers a D flip-flop to latch a high level. When the terminal signal goes low, the GATE signal goes low, NM1 is turned off, and the timing capacitor C0 stops discharging. When EXP_EN goes low, the detection ends. Then, the base signal EN4 of T3 is set to high. Capacitor C2 samples and stores the voltage on the timing capacitor C0 through the source follower SF1. After completion, the signal EN4 is set low, turning off the transmission transistor T3. The EN1 signal is set low, turning off the bias current I1. (3) Row pixel readout sampling stage: After the global detection is completed, the voltage signals on capacitors C1 and C2 are read out row by row. When the first row of pixels is read out, the corresponding working sequence is as follows: First, the reset signal RSTN is set to low level; the column bus transmission tube control signal EN5 in the first row of pixels is set to high level, and the T4 tube is turned on. The signal EN5 in the other rows of pixels is kept at low level, and EN5 is input from the base of T4; the signal EN1 in the first row of pixel readout unit is set to high level, and the bias current source I1 is turned on. The parasitic capacitance at point X of the emitter of T1 is pre-charged through the source follower tube SF1 and the transmission tube T1; then the signals EN2 and EN1 are set to low level in sequence, and the transmission tube T1 is turned off; the signal EN3 is set to high level, and the reset voltage signal V stored on capacitor C1 is read out. RST0 Read out via the column bus, at this time the gate F of T5 in the column parallel correlated double sampling circuit. R When the signal is set to high, transistor T5 is turned on, and the sampling capacitor C... R V on capacitor C1 RST0 The signal is sampled; after sampling, EN3, F R The signal is set to low level; then EN1 and EN2 signals are set to high level again to recharge the parasitic capacitance at point X. After precharging, EN2 and EN1 signals are set to low level in sequence; then EN4 at the base of T3 in the pre-storage circuit within the pixel unit and F at the gate of T7 in the column-parallel correlated dual sampling circuit... S The signal is set to high level, and the sampling capacitor C S V on capacitor C2 SIG0 The signal is sampled; after sampling, EN4, F S The signal is set to low level, F CDS When the signal is set to high, the correlated double sampling circuit uses a difference circuit based on a switched-capacitor amplifier to sample capacitor C. R C S The effective signal V is obtained by subtracting the voltages on the input voltage. RST0 -V SIG0 ; (4) Analog-to-digital conversion stage: The analog-to-digital conversion circuit converts the signal V RST0 -V SIG0 Converted to digital signal D OUT The signal is then output to an external or on-chip digital signal processing unit via a digital bus. (5) Row rolling readout stage: Repeat stages (3) and (4), drive the control signals EN1, EN2, EN3, EN4 and EN5 in the pixel array by row, and configure the column parallel related dual sampling circuit and analog-to-digital conversion circuit according to the corresponding timing to realize the signal readout and conversion of the entire pixel array.
10. The method as described in claim 9, characterized in that, After the analog-to-digital conversion is completed, signal F CDS The row select signal EN5 at the base of T4 is set to low level.