SAR imaging parallel processing method and device based on FT-M6678

Abstract

The invention discloses an SAR imaging parallel processing method and device based on FT-M6678, and belongs to the field of radar signal and information processing, and the method comprises the following steps: S1, building a board card composed of a multi-core FT-M6678 chip and an FPGA chip, forming a board card cluster by a plurality of board cards, and distributing an ID; s2, an FT-M6678 chip of each board card is started; and S3, starting a two-stage parallel processing program which comprises a data transmission program linked with the FPGA chips on the plurality of board cards and a data processing program linked with the plurality of kernels on each board card so as to cooperatively complete the SAR imaging processing and SAR image splicing processing flow. According to the SAR imaging parallel processing method and device based on FT-M6678, SAR imaging is completed through a two-stage parallel processing method between board cards and between board cores, the imaging real-time performance is high, and products are autonomous and controllable, reliable in supply and convenient to maintain.

Description

Technical Field

[0001] This invention relates to the field of radar signal and information processing technology, and in particular to a parallel processing method and device for SAR imaging based on FT-M6678. Background Technology

[0002] Synthetic Aperture Radar (SAR), as an all-weather, all-time observation method, has the characteristics of strong penetration, high resolution, rich feature information and wide application. Currently, the core processor of some airborne SAR products uses imported single-core DSP chips.

[0003] However, due to the inherent characteristics of SAR imaging, such as high algorithm complexity, large data scale, and heavy computational load, it places stringent requirements on hardware processing capabilities and real-time performance. Even when using imported single-core DSP chips, their limited processing performance cannot meet the high-efficiency computational needs of SAR imaging, resulting in untimely data processing, poor real-time performance, and high power consumption. Summary of the Invention

[0004] The purpose of this invention is to provide a parallel processing method and device for SAR imaging based on FT-M6678, thereby solving the aforementioned technical problems.

[0005] To achieve the above objectives, this invention provides a parallel processing method for SAR imaging based on FT-M6678, comprising the following steps: S1. Construct a board consisting of a multi-core FT-M6678 chip and an FPGA chip for data transmission. Multiple boards form a board cluster and are assigned IDs according to their slots. S2. Start the FT-M6678 chip on each board to complete the hardware resource initialization configuration; S3. Based on the received data, start a two-level parallel processing program. The two-level parallel processing program includes a data transmission program that links multiple FPGA chips on multiple boards and a data processing program that links multiple cores on each board, so as to collaboratively complete the SAR imaging processing and SAR image stitching processing flow.

[0006] Preferably, the specific steps of step S3 are as follows: S31. The externally input I / Q echo data and auxiliary data are sequentially passed through the FPGA chips on each board. and circuit board ; S32, board The FPGA chip on the board transmits the data stream to the FT-M6678 chip for use on the board. SAR imaging algorithms run synchronously on the FT-M6678 chip; S33. The SAR imaging results data and auxiliary data obtained in step S32 are sent back to the board. The FPGA chip on the board enables SAR imaging results data and auxiliary data to be transmitted along the board. The path is returned to the board. On the FPGA chip; S34. Return the data from step S33 to the board. SAR imaging results and auxiliary data on the FPGA chip are transmitted to the board. The FT-M6678 chip is used for splicing, and the spliced ​​image data is reported to the display control for real-time display.

[0007] Preferably, each board's FT-M6678 chip includes 8 cores, and their IDs are sequentially encoded as follows: Among them, the kernel The kernel performs data receiving and sending tasks. Perform data processing tasks.

[0008] Preferably, the specific steps of the imaging operation in step S32 are as follows: S321, based on board The core of the FT-M6678 chip The echo data belonging to this board's processing is extracted from the data stream, preprocessed, and then stored in a ping-pong manner on the storage medium; and the kernel... Set a preprocessing completion flag, and use this flag as the kernel... Status indicators for the running imaging algorithm; S322, based on board The core of the FT-M6678 chip Read separately by The preprocessing completion flag is set, and the SAR imaging algorithm is executed in parallel in an inter-kernel synchronous manner to obtain SAR imaging result data and store it in the storage medium; and the kernel controls this process. Set an imaging completion flag, and use this flag as the kernel. The system returns a status indicator of the imaging results data and then returns to continue reading the next data. The preprocessing completion indicator is set; S323, based on board The core of the FT-M6678 chip Read by kernel The set imaging completion flag sends the imaging result data to the corresponding FPGA via the chip's SRIO bus and returns echo data to await the next processing by this board.

[0009] Preferably, during the SAR imaging stitching process, the board... FPGA chip receiving board inside The imaging results data from the FPGA chip are transmitted to the FT-M6678 readable storage medium via the chip's SRIO interface.

[0010] Preferably, the specific steps of the SAR imaging stitching operation in step S34 are as follows: S341, based on board The core of the FT-M6678 chip The identifier to be stitched is set based on the received imaging data; this identifier serves as the kernel. Status indicators for running the splicing algorithm; S342, based on board The core of the FT-M6678 chip Read separately by The set stitching identifier is used to execute the SAR stitching algorithm in parallel with inter-core synchronization, and the stitched image data is stored in the storage medium; and the kernel... Set a completion flag, and use this flag as the kernel identifier. The system returns a status indication of the image data and then returns to continue reading the next data. The set identifier for the parts to be assembled; S343, based on board The core of the FT-M6678 chip Read by kernel Once the stitching completion indicator is set, the stitched image data is sent to the display and control system for real-time display, and then the system returns to continue receiving data from the board. The returned imaging results data.

[0011] The SAR imaging parallel device based on FT-M6678 includes: A board cluster consisting of multiple boards, each board adopts a hardware framework integrating an FT-M6678 chip and an FPGA chip, and each board has the same matching software design. They are distinguished by an assigned ID so that the boards can be interchanged. Hardware resources that match the board include clock, timer, double data rate synchronous dynamic random access memory, cache memory, high-speed serial interface, direct memory access module, general purpose input / output interface and serial peripheral interface.

[0012] Preferably, the domestically produced core processing device DSP chip is FT-M6678, and the FPGA chip model is SMQ7K325T.

[0013] Therefore, the present invention employs the above-mentioned parallel processing method and device for SAR imaging based on FT-M6678, and has the following beneficial effects: 1. Through a two-level parallel architecture of collaborative imaging task distribution and result aggregation between boards and synchronous parallel core processing between cores, combined with the 8-core parallel computing power, three-level cache and built-in FFT accelerator of the FT-M6678 chip, the data access latency and computation time are significantly reduced. Data streams are directly transmitted between boards through FPGA, and high-speed transmission is achieved within the board through the SRIO interface. Data interaction between cores is achieved without CPU intervention by leveraging EDMA resources. This avoids the efficiency bottleneck of traditional serial processing or single parallel mode. It can quickly complete complex calculations such as range / azimuth pulse compression and frequency offset estimation in SAR imaging algorithms, as well as matrix correlation in SAR stitching algorithms, making it perfectly suitable for application scenarios with strict real-time requirements.

[0014] 2. The solution employing the domestically produced multi-core FT-M6678 chip in conjunction with the FPGA chip (SMQ7K325T) significantly improves computational efficiency and data transmission rate compared to traditional imported single-core DSP chips. This is achieved by leveraging the FT-M6678's 8-core parallel computing power, three-level cache architecture, and built-in FFT accelerator, combined with the FPGA's high-speed parallel processing and high-speed interface pass-through capabilities. This effectively addresses the core requirements of complex SAR imaging algorithms and large data volumes, resolving the issues of untimely processing and poor real-time performance of imported single-core DSPs. Furthermore, the fully domestically produced hardware combination enables independent control of core components, completely eliminating dependence on foreign technology and avoiding the risks of unstable supply and high maintenance risks associated with imported components. It also boasts low power consumption, making it suitable for airborne applications. The flexibility of the FPGA and the scalability of the board cluster further enhance system adaptability, providing reliable support for the promotion of SAR imaging technology in airborne products.

[0015] 3. Based on the floating-point computing power of the FT-M6678 chip, the high-precision operation of the FFT accelerator, and the parameter consistency brought by the inter-core identification synchronization mechanism, the multi-core parallel processing capability of SAR imaging or SAR stitching is improved.

[0016] 4. All hardware boards adopt a unified hardware structure and software program. The splicing boards and imaging boards can be flexibly divided by slot ID. The number of boards can be increased or decreased according to the imaging task requirements, which is highly scalable. The collaboration between boards and cores is realized through a standardized identification mechanism and high-speed interface, which reduces the failure points in the data transmission and operation process. In addition, the combination of multi-core parallelism and dedicated hardware acceleration reduces the load pressure on individual components, extends the service life of the equipment, and reduces the later maintenance costs.

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the two-stage parallel processing principle of the SAR imaging parallel processing method based on FT-M6678 of the present invention.

[0019] Figure 2 This is a flowchart illustrating the implementation of the parallel processing method for SAR imaging based on FT-M6678 according to the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of the present invention and are not intended to limit the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of this application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0021] It should be noted that the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as a process, method, system, product, or server that includes a series of steps or units, not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or device.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] In existing technologies, SAR imaging, due to its complex algorithms and large data volume, places stringent demands on hardware processing performance and real-time performance. However, some current airborne SAR products rely on imported single-core DSPs, whose limited processing capabilities lead to untimely data processing, poor real-time performance, and high power consumption. At the same time, the import of core components results in strong external dependence, posing risks of unstable supply and high maintenance risks. Furthermore, existing related technologies have not yet formed a fully domestically produced hardware adaptation solution suitable for airborne scenarios, and lack an efficient processing system that can balance low power consumption, high real-time performance, and independent controllability, thus restricting the further promotion and application of SAR imaging technology in airborne products.

[0024] Based on the above analysis, this invention is designed, see appendix. Figure 1-2 A parallel processing method for SAR imaging based on FT-M6678 includes the following steps: S1. Construct a board consisting of a multi-core FT-M6678 chip and an FPGA chip for data transmission. Multiple boards form a board cluster and are assigned IDs according to their slots. The FPGA chip, model SMQ7K325T, perfectly matches the parallel processing requirements of the FT-M6678 chip. Its integrated high-speed serial transceiver and high-speed interface ensure low-latency data transmission between boards and chips, supporting a two-level parallel processing architecture for the board cluster. Simultaneously, its flexible programmability adapts to unified software design, and its board ID differentiation and interchangeability capabilities reduce hardware and software adaptation costs. Furthermore, its fully domestically produced nature complements the FT-M6678 chip, mitigating the risk of dependence on imported components, enhancing system supply reliability and ease of maintenance, and fully meeting the core requirements of airborne SAR imaging for high performance, low power consumption, and independent controllability.

[0025] S2. Start the FT-M6678 chip on each board to complete the hardware resource initialization configuration; S3. Based on the received data, start a two-level parallel processing program. The two-level parallel processing program includes a data transmission program that links multiple FPGA chips on multiple boards and a data processing program that links multiple cores on each board, so as to collaboratively complete the SAR imaging processing and SAR image stitching processing flow.

[0026] Each board's FT-M6678 chip includes 8 cores, each with a uniquely encoded ID. Among them, the kernel The kernel performs data receiving and sending tasks. Perform data processing tasks.

[0027] The specific steps of step S3 are as follows: S31. The externally input I / Q echo data and auxiliary data are sequentially passed through the FPGA chips on each board. and circuit board ; S32, board The FPGA chip on the board transmits the data stream to the FT-M6678 chip for use on the board. SAR imaging algorithms run on the FT-M6678 chip; During SAR imaging processing, the FT-M6678 chip core of the board preprocesses the echo data and auxiliary data transmitted from the FPGA chip, stores them in a ping-pong manner in double-rate synchronous dynamic random access memory, and sets a preprocessing completion flag according to the data reception status to enable the core to... Read After the preprocessing and identification are completed, the imaging operation is performed simultaneously, and the kernel... Set an imaging completion flag to enable the kernel After reading the imaging completion marker, the imaging result data is sent back to the corresponding FPGA chip; The specific steps of the imaging operation in step S32 are as follows: S321, based on board The core of the FT-M6678 chip The echo data belonging to this board's processing is extracted from the data stream, preprocessed, and then stored in a ping-pong manner on the storage medium; and the kernel... Set a preprocessing completion flag, and use this flag as the kernel... Status indicators for the running imaging algorithm; S322, based on board The core of the FT-M6678 chip Read separately by The preprocessing completion flag is set, and the SAR imaging algorithm is executed in parallel in an inter-kernel synchronous manner to obtain SAR imaging result data and store it in the storage medium; and the kernel controls this process. Set an imaging completion flag, and use this flag as the kernel. The system returns a status indicator of the imaging results data and then returns to continue reading the next data. The preprocessing completion indicator is set; S323, based on board The core of the FT-M6678 chip Read by kernel The set imaging completion flag sends the imaging result data to the corresponding FPGA via the chip's SRIO bus and returns echo data to await the next processing by this board.

[0028] S33. The SAR imaging results data and auxiliary data obtained in step S32 are sent back to the board. The FPGA chip on the board enables SAR imaging results data and auxiliary data to be transmitted along the board. The path is returned to the board. On the FPGA chip; S34. Return the data from step S33 to the board. SAR imaging results and auxiliary data on the FPGA chip are transmitted to the board. The image data is stored in the FT-M6678 readable storage medium for stitching processing, and the stitched image data is reported to the display control for real-time display.

[0029] The specific steps of the SAR imaging stitching operation in step S34 are as follows: S341, based on board The core of the FT-M6678 chip The identifier to be stitched is set based on the received imaging data; this identifier serves as the kernel. Status indicators for running the splicing algorithm; S342, based on board The core of the FT-M6678 chip Read separately by The set stitching identifier is used to execute the SAR stitching algorithm in parallel with inter-core synchronization, and the stitched image data is stored in the storage medium; and the kernel... Set a completion flag, and use this flag as the kernel identifier. The system returns a status indication of the image data and then returns to continue reading the next data. The set identifier for the parts to be assembled; S343, based on board The core of the FT-M6678 chip Read by kernel Once the stitching completion indicator is set, the stitched image data is sent to the display and control system for real-time display, and then the system returns to continue receiving data from the board. The returned imaging results data.

[0030] The SAR imaging parallel device based on FT-M6678 includes: This system comprises multiple domestically produced hardware boards, each employing a hardware framework integrating the FT-M6678 chip and an FPGA chip. Each board shares the same software design and is distinguished by assigned IDs, ensuring interchangeability. This fully domestic hardware combination achieves independent control over core components, completely eliminating reliance on foreign technology and mitigating the issues of unstable imported component supply and high maintenance risks. Furthermore, the unified hardware and software design and interchangeability significantly reduce maintenance costs and downtime in case of board failures, improving system ease of maintenance. It also supports flexible addition or removal of boards based on the scale of SAR imaging tasks, enhancing system scalability. Combined with the parallel processing advantages of multi-core chips and FPGAs, it further ensures real-time imaging and processing efficiency. The unified design reduces R&D, production, and subsequent upgrade costs, providing reliable support for the large-scale application of SAR imaging technology in airborne and other scenarios.

[0031] The hardware resources matched with the board include clock, timers, double-rate synchronous dynamic random access memory (DDR), cache, high-speed serial interface (SRIO), direct memory access module (EDMA), general purpose input / output interface (GPIO), and serial peripheral interface (SPI). Each hardware resource is precisely matched to the parallel processing requirements of SAR imaging. The clock and timers ensure synchronous collaboration between boards and cores. DDR and cache provide large-capacity, low-latency data storage support. The high-speed serial interface and EDMA enable high-speed data transmission without CPU intervention. GPIO and SPI flexibly adapt to various peripherals, jointly providing underlying hardware support for the parallel processing of the FT-M6678 chip and FPGA, further improving imaging real-time performance and data processing efficiency. At the same time, the standardized hardware resource configuration fits the unified hardware and software design and interchangeability of the board, reducing R&D adaptation costs, enhancing system compatibility and ease of operation and maintenance. Moreover, all hardware is domestically produced, ensuring independent control of core resources, avoiding the risk of import dependence, and fully adapting to the multiple requirements of airborne scenarios for stability, real-time performance, and scalability.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A parallel processing method for SAR imaging based on FT-M6678, characterized in that: Includes the following steps: S1. Construct a board consisting of a multi-core FT-M6678 chip and an FPGA chip for receiving and transmitting data. Multiple boards form a board cluster and are assigned IDs according to their slots. S2. Start the FT-M6678 chip on each board to complete the hardware resource initialization configuration; S3. Based on the received data, start a two-level parallel processing program. The two-level parallel processing program includes a data transmission program that links multiple FPGA chips on multiple boards and a data processing program that links multiple cores on each board, so as to collaboratively complete the SAR imaging processing and SAR image stitching processing flow.

2. The SAR imaging parallel processing method based on FT-M6678 according to claim 1, characterized in that: The specific steps of step S3 are as follows: S31. The externally input I / Q echo data and auxiliary data are sequentially passed through the FPGA chips on each board. and circuit board ; S32, board The FPGA chip on the board transmits the data stream to the FT-M6678 chip for use on the board. SAR imaging algorithms run synchronously on the FT-M6678 chip; S33. The SAR imaging results data and auxiliary data obtained in step S32 are sent back to the board. The FPGA chip on the board enables SAR imaging results data and auxiliary data to be transmitted along the board. The path is returned to the board. On the FPGA chip; S34. Return the data from step S33 to the board. SAR imaging results and auxiliary data on the FPGA chip are transmitted to the board. The FT-M6678 chip is used for splicing, and the spliced ​​image data is reported to the display control for real-time display.

3. The SAR imaging parallel processing method based on FT-M6678 according to claim 2, characterized in that: Each board's FT-M6678 chip includes 8 cores, each with a uniquely encoded ID. Among them, the kernel The kernel performs data receiving and sending tasks. Perform data processing tasks.

4. The SAR imaging parallel processing method based on FT-M6678 according to claim 3, characterized in that: The specific steps of the imaging operation in step S32 are as follows: S321, based on board The core of the FT-M6678 chip The echo data belonging to this board's processing is extracted from the data stream, preprocessed, and then stored in a ping-pong manner on the storage medium; and the kernel... Set a preprocessing completion flag, and use this flag as the kernel... Status indicators for the running imaging algorithm; S322, based on board The core of the FT-M6678 chip Read separately by The preprocessing completion flag is set, and the SAR imaging algorithm is executed in parallel in an inter-kernel synchronous manner to obtain SAR imaging result data and store it in the storage medium; and the kernel controls this process. Set an imaging completion flag, and use this flag as the kernel. The system returns a status indicator of the imaging results data and then returns to continue reading the next data. The preprocessing completion indicator is set; S323, based on board The core of the FT-M6678 chip Read by kernel The set imaging completion flag sends the imaging result data to the corresponding FPGA via the chip's SRIO bus and returns echo data to await the next processing by this board.

5. The SAR imaging parallel processing method based on FT-M6678 according to claim 4, characterized in that: During SAR imaging stitching, the board FPGA chip receiving board inside The imaging results data from the FPGA chip are transmitted to the FT-M6678 readable storage medium via the chip's SRIO interface.

6. The SAR imaging parallel processing method based on FT-M6678 according to claim 5, characterized in that: The specific steps of the SAR imaging stitching operation in step S34 are as follows: S341, based on board The core of the FT-M6678 chip The identifier to be stitched is set based on the received imaging data; this identifier serves as the kernel. Status indicators for running the splicing algorithm; S342, based on board The core of the FT-M6678 chip Read separately by The set stitching identifier is used to execute the SAR stitching algorithm in parallel with inter-core synchronization, and the stitched image data is stored in the storage medium; and the kernel... Set a completion flag, and use this flag as the kernel identifier. The system returns a status indication of the image data and then returns to continue reading the next data. The set identifier for the parts to be assembled; S343, based on board The core of the FT-M6678 chip Read by kernel Once the stitching completion indicator is set, the stitched image data is sent to the display and control system for real-time display, and then the system returns to continue receiving data from the board. The returned imaging results data.

7. A parallel SAR imaging device based on FT-M6678, characterized in that, include: A cluster of multiple boards, each board adopts a hardware framework integrating FT-M6678 chip and FPGA chip, and each board has the same matching software design. They are distinguished by assigned IDs so that the boards can be interchanged. Hardware resources that match the board include clock, timer, double data rate synchronous dynamic random access memory, cache memory, high-speed serial interface, direct memory access module, general purpose input / output interface and serial peripheral interface.

8. The SAR imaging parallel device based on FT-M6678 according to claim 7, characterized in that: The domestically produced core processing device is the FT-M6678 DSP chip and the SMQ7K325T FPGA chip.

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