Silicon optical chip, wafer and test method

CN122018085APending Publication Date: 2026-05-12武汉钧恒科技有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
武汉钧恒科技有限公司
Filing Date
2025-12-19
Publication Date
2026-05-12

AI Technical Summary

Technical Problem

Existing technologies waste a significant amount of usable area on silicon photonic chip wafers, leading to increased costs and hindering efficient use of wafer space.

Method used

A groove is formed on the edge of the fourth side surface of the silicon photonic chip. When the groove is rotated 90° counterclockwise, it covers the input waveguide and the output waveguide. The silicon photonic chips are arranged in a multi-row, multi-column array in groups of four. The input waveguide and output waveguide of adjacent silicon photonic chips correspond to the groove. The test light probe is coupled in the dicing channel and the groove to reduce the design of photolithography grooves.

Benefits of technology

This effectively reduces wasted wafer area, improves wafer utilization, and lowers production costs.

✦ Generated by Eureka AI based on patent content.

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    Figure CN122018085A_ABST
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Abstract

A light-in waveguide and a light-out waveguide are arranged on the side face of a first side edge, a plurality of DC bonding pads are arranged on the upper surface of a second side edge, a plurality of RF bonding pads are arranged on the upper surface of a third side edge, a groove for an optical probe to enter is formed in the edge of the upper surface of a fourth side edge, and the groove is lower than the light-in waveguide and the light-out waveguide. When the groove rotates 90 degrees anticlockwise, the light inlet waveguide and the light outlet waveguide are located in the coverage range of the groove. According to the wafer, four silicon optical chips form a group and are distributed in an array in a multi-row and multi-column manner; the four silicon optical chips in each group are distributed around the center in a rotating mode, and the light inlet waveguide and the light outlet waveguide of one silicon optical chip in every two adjacent silicon optical chips are right opposite to the groove of the other silicon optical chip. Cutting channels are arranged between every two adjacent columns of silicon optical chips and between every two adjacent rows of silicon optical chips. The method has the beneficial effects that the wafer waste area is effectively reduced, the wafer area utilization rate is maximized, and the cost is reduced.
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