Storage device and method of operating storage device

Abstract

The invention relates to a data storage device and an operating method thereof. The data storage device may include a memory device and a controller. The memory device may include a compressed memory region in which data is stored in a compressed state and an uncompressed memory region in which data is stored in an uncompressed state. The controller may: receive, from a host, a speculative memory read command indicating a likelihood that target data corresponding to a target logical address has to be read; in response to receiving the speculative memory read command, searching for whether a location where the target data is stored in the memory device is a compressed memory region or a non-compressed memory region; and determining whether to store the target data in a cache configured to store data read from the memory device, based on whether the location at which the target data is stored in the memory device is a compressed memory region or a non-compressed memory region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0158774, filed on November 11, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology relate to a data storage device and a method for operating the data storage device. Background Technology

[0004] Storage devices are used to store data based on requests from external devices, such as computers, mobile devices (e.g., smartphones or tablets), and similar devices.

[0005] The storage device may include a memory device and a controller. The memory device is used for data storage, and the controller is used for managing the memory device. The memory device may be a volatile memory device or a non-volatile memory device. The controller may receive commands from an external device (e.g., a host) and perform operations on the memory device based on the received commands, such as reading data, writing data, or erasing data.

[0006] To make more efficient use of memory devices, storage devices can compress data before storing it in memory. Summary of the Invention

[0007] The disclosed technology can be implemented in some embodiments to provide a data storage device and a method of operation thereof, which is designed to prevent reduced cache hit rate and degraded read performance caused by decompressing low-usage data and storing the decompressed data in a cache.

[0008] In one aspect, a storage device may include: a memory device including a compressed memory region where data is stored in a compressed state and an uncompressed memory region where data is stored in an uncompressed state (e.g., data is stored at its original size); and a controller configured to: receive a speculative memory read command from a host, the speculative memory read command indicating that there is a possibility that target data corresponding to a target logical address will be read (e.g., the probability that the target data corresponding to the target logical address will be read is greater than a reference probability value); in response to receiving the speculative memory read command, determine whether the location in the memory device where the target data is stored is a compressed memory region or an uncompressed memory region; and based on whether the location in the memory device where the target data is stored is a compressed memory region or an uncompressed memory region, determine whether to store the target data in a cache, the cache being configured to store data read from the memory device.

[0009] In another aspect, a method for operating a storage device may include: receiving a speculative memory read command from a host, the speculative memory read command indicating that there is a possibility that target data corresponding to a target logical address will be read (e.g., the probability that the target data corresponding to the target logical address will be read is greater than a reference probability value); determining the location in which the target data is stored in the memory device, the memory device including a compressed memory region where the data is stored in a compressed state and an uncompressed memory region where the data is stored in an uncompressed state (e.g., the data is stored at its original size); and determining whether to store the target data in a cache, the cache being configured to store data read from the memory device, based on whether the location in which the target data is stored in the memory device is a compressed memory region or an uncompressed memory region.

[0010] In another aspect, a computationally high-speed link (CXL) device may include: a memory device including a compressed memory region where data is stored in a compressed state and an uncompressed memory region where data is stored in an uncompressed state (e.g., data is stored at its original size); and a CXL controller configured to: receive a speculative memory read command from a host via a CXL interface, the speculative memory read command indicating that there is a possibility that target data corresponding to a target logical address will be read (e.g., the probability that the target data corresponding to the target logical address will be read is greater than a reference probability value); in response to receiving the speculative memory read command, determine whether the location in the memory device where the target data is stored is a compressed memory region or an uncompressed memory region; and based on whether the region in the memory device where the target data is stored is a compressed memory region or an uncompressed memory region, determine whether to store the target data in a cache, the cache being configured to store data read from the memory device.

[0011] In some embodiments of the disclosed technology, the data storage device and its operating method can prevent reduced cache hit rate and degraded read performance caused by decompressing low-usage data and storing the decompressed data in a cache. Attached Figure Description

[0012] Figure 1 This is a schematic configuration diagram of a storage device according to an embodiment of the disclosed technology.

[0013] Figure 2 It is shown schematically. Figure 1 A block diagram of the memory.

[0014] Figure 3 This is a diagram illustrating a schematic structure of a storage device based on some embodiments of the disclosed technology.

[0015] Figure 4 This is a diagram illustrating the operation of a storage device based on some embodiments of the disclosed technology, using a compression mapping table to search for target data stored in a compressed memory region.

[0016] Figure 5 This is a flowchart illustrating the operation of a storage device, based on some embodiments of the disclosed technology, in determining the region where target data is stored.

[0017] Figure 6 This is a diagram illustrating the operation of a storage device based on some embodiments of the disclosed technology storing compressed mapping entries corresponding to a target logical address in a cache.

[0018] Figure 7 This is a diagram illustrating an example of an operation in which a storage device, based on some embodiments of the disclosed technology, determines whether to store target data in a cache.

[0019] Figure 8 This is a diagram illustrating another example of the operation of a storage device, based on some embodiments of the disclosed technology, determining whether to store target data in a cache.

[0020] Figure 9 This is a flowchart illustrating the operation of a storage device based on some embodiments of the disclosed technology to determine whether to store target data in a cache based on the compressed size of the target data.

[0021] Figure 10 This is a diagram illustrating a method of operating a storage device based on some embodiments of the disclosed technology. Detailed Implementation

[0022] The methods, processes, and / or operations described herein can be performed by code or instructions executable by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may include the computer, processor, controller, or other signal processing device described herein, or may be elements other than those described herein. Given the detailed description of the algorithms underlying these methods (or the operation of the computer, processor, controller, or other signal processing device), the code or instructions used to implement these methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0023] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0024] Figure 1 This is a schematic configuration diagram of a storage device 100 according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The storage device 100 may include a memory 110 and a controller 120. The memory 110 stores data, and the controller 120 is connected to communicate with and control the memory 110.

[0026] The memory 110 includes multiple memory blocks and operates in response to control by the controller 120. Operation of the memory 110 may include, for example, read operations, programming operations (also known as write operations), and erase operations performed in response to control signals from the controller 120.

[0027] The memory 110 may include a memory cell array that includes a plurality of memory cells (also simply referred to as "cells") for storing data.

[0028] For example, memory 110 can be implemented as various types of memory such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Fourth Generation Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-transfer torque random access memory (STT-RAM).

[0029] The memory 110 can be implemented as a three-dimensional array structure. For example, embodiments of this disclosure can be applied to charge-fetch flash memory (CTF) where the charge storage layer is configured by a dielectric layer and to flash memory where the charge storage layer is configured by a conductive floating gate.

[0030] The memory 110 can receive commands for an operation and an address associated with that operation from the controller 120, and can access a region in the memory cell array selected by that address. In other words, the memory 110 can perform the operation instructed by the command on the region selected by the address.

[0031] The memory 110 can perform programming, reading, and erasing operations. For example, when performing a programming operation, the memory 110 can program data into an area selected by an address. When performing a reading operation, the memory 110 can read data from the area selected by an address. In an erasing operation, the memory 110 can erase the data stored in the area selected by an address.

[0032] The controller 120, which communicates with the memory 110, can control write (programming) operations, read operations, erase operations, and background operations in the memory 110. For example, background operations may include at least garbage collection (GC) operations, wear leveling (WL) operations, read recycling (RR) operations, bad block management (BBM) operations, etc.

[0033] The controller 120 can control the operation of the memory 110 based on a request from a device located outside the storage device 100 (e.g., a host). However, the controller 120 can also control the operation of the memory 110 regardless of a host request or without a host request.

[0034] As a non-limiting example, the host can be a computer, an ultra-mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage device constituting a data center, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID (Radio Frequency Identification) device, and a mobile device capable of driving or driving autonomously under human control (e.g., a vehicle, a robot, or a drone). Optionally, the host can be a virtual reality (VR) device that provides 2D or 3D virtual reality images or an augmented reality (AR) device that provides augmented reality images. The host can be any of various electronic devices requiring a storage device 100 capable of storing data.

[0035] The host may include at least one operating system (OS). The operating system typically manages and controls the host's functions and operations, and controls the interoperability between the host and storage device 100. Based on the host's mobility, operating systems can be categorized into general-purpose operating systems and mobile operating systems.

[0036] In implementations, the controller 120 and the host can be configured in various ways. For example, in some implementations, the controller 120 and the host are separate from each other, or in other implementations, the controller 120 and the host can be integrated into a single device. In the following specific examples, for ease of illustration, the controller 120 and the host will be described as separate devices.

[0037] Reference Figure 1 The controller 120 may include a memory interface 122 that interfaces with or communicates with the memory device 110 and the control circuit 123, and may further include a host interface 121 that interfaces with or communicates with a host device that can access the memory device 110 via the controller 120.

[0038] Host interface 121 provides an interface for communicating with a host and can use various interface protocols, including, for example: USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI (Peripheral Component Interconnect) protocol, PCI-E (High-Speed ​​PCI) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, IDE (Integrated Drive Electronics) protocol, or proprietary protocols.

[0039] When receiving a command from the host, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0040] Memory interface 122 can be coupled to memory 110 to provide an interface for communicating with memory 110. That is, memory interface 122 can be configured to provide an interface between memory 110 and controller 120 in response to control of control circuitry 123.

[0041] Control circuit 123 performs general control operations of controller 120 to control the operation of memory 110. For this purpose, for example, control circuit 123 may include at least one of processor 124 and working memory 125, and may optionally include error detection and correction circuitry (ECC circuitry) 126.

[0042] The processor 124 can control the general operation of the controller 120 and can perform logical calculations. The processor 124 can communicate with the host through the host interface 121 and with the memory 110 through the memory interface 122.

[0043] Processor 124 can perform the logical operations required to execute the functions of the Flash Translation Layer (FTL). Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) through the Flash Translation Layer. The Flash Translation Layer can receive logical block addresses and translate them into physical block addresses using a mapping table.

[0044] Depending on the mapping unit, there are various address mapping methods in the flash translation layer. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0045] Processor 124 can randomize data received from the host. For example, processor 124 can randomize data received from the host by using a set randomization seed. The randomized data can be provided to memory 110 and can be programmed into the memory cell array of memory 110.

[0046] During a read operation, processor 124 can derandomize data received from memory 110. For example, processor 124 can derandomize data received from memory 110 using a derandomization seed. The derandomized data can then be output to the host.

[0047] Processor 124 can run firmware to control the operation of controller 120. That is, in order to control the general operation of controller 120 and perform logical calculations, processor 124 can run (drive) firmware loaded into working memory 125 at startup. In the following, the operation of storage device 100 based on some embodiments of this disclosure will be described as implementing processor 124, which runs firmware defining the corresponding operations.

[0048] Firmware, which serves as a program to run in storage device 100 to drive storage device 100, may include various functional layers. For example, firmware may include binary data that defines code for running each functional layer.

[0049] For example, the firmware may include, for instance, a flash translation layer, a host interface layer (HIL), and / or a flash interface layer (FIL), wherein the flash translation layer performs the translation function between the logical address requested from the host to the storage device 100 and the physical address of the memory 110, the host interface layer (HIL) is used to analyze the command requested from the host to the storage device 100 as a storage device and transmit the command to the flash translation layer, and the flash interface layer (FIL) transmits the command indicated by the flash translation layer to the memory 110.

[0050] This firmware can be loaded into working memory 125 from, for example, memory 110 or a separate non-volatile memory (e.g., ROM or NOR flash memory) located outside memory 110. When a boot operation is performed after power-on, processor 124 may load all or part of the firmware into working memory 125 first.

[0051] Processor 124 can execute logical calculations defined in firmware loaded into working memory 125 to control the general operation of controller 120. Processor 124 can store the results of executing the logical calculations defined in the firmware in working memory 125. Processor 124 can control controller 120 based on the results of executing the logical calculations defined in the firmware, causing controller 120 to generate commands or signals. When a portion of the firmware defining the logical calculation to be executed is stored in memory 110 but not loaded into working memory 125, processor 124 can generate an event (e.g., an interrupt) to load the corresponding portion of the firmware from memory 110 into working memory 125.

[0052] The processor 124 can load the metadata required for the driver firmware from the memory 110. The metadata used to manage the data in the memory 110 may include, for example, management information about the user data stored in the memory 110.

[0053] Firmware can be updated during the manufacture of storage device 100 or during operation of storage device 100. Controller 120 can download new firmware from outside storage device 100 and update existing firmware using the new firmware.

[0054] To drive the controller 120, the working memory 125 can store necessary firmware, program code, commands, and data. The working memory 125 can be volatile memory, including one or more of, for example, SRAM (static RAM), DRAM (dynamic RAM), or SDRAM (synchronous DRAM). Alternatively, in addition to the working memory 125, the controller 120 can also use separate volatile memory (e.g., SRAM, DRAM) located externally to the controller 120.

[0055] The error detection and correction circuit 126 can detect and correct error bits in the target data using error correction codes. The target data can be, for example, data stored in the working memory 125 or data read from the memory 110.

[0056] Error detection and correction circuit 126 can decode data using error correction codes. Error detection and correction circuit 126 can be implemented by various code decoders. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0057] For example, when each read data consists of multiple sectors, the error detection and correction circuit 126 can detect error bits in each read data on a sector-by-sector basis. A sector can represent a data unit smaller than a page, where a page is the read unit of flash memory. The sectors that make up each read data can be matched with each other using addresses.

[0058] The error detection and correction circuit 126 can calculate the bit error rate (BER) on a sector-by-sector basis and determine whether an error is correctable. For example, when the bit error rate is higher than a reference value, the error detection and correction circuit 126 can determine, decide, or consider the corresponding sector to be uncorrectable or "failed". On the other hand, when the bit error rate is lower than the reference value, the error detection and correction circuit 126 can determine, decide, or consider the corresponding sector to be correctable or pass.

[0059] Error detection and correction circuit 126 can sequentially perform error detection and correction operations on all read data. If a sector in the read data is correctable, error detection and correction circuit 126 can omit the error detection and correction operation for the corresponding sector for the next read data. If error detection and correction operations for all read data are completed in this manner, error detection and correction circuit 126 can detect the last uncorrectable sector in the read data. One or more sectors may be identified or considered uncorrectable. Error detection and correction circuit 126 can transmit information (e.g., address information) about the identified or considered uncorrectable sectors to processor 124.

[0060] Bus 127 can be configured to provide a channel between components 121, 122, 124, 125, and 126 of controller 120. Bus 127 may include, for example, a control bus for transmitting various control signals, commands, etc., and a data bus for transmitting various data.

[0061] Some of the components 121, 122, 124, 125, and 126 of the controller 120 may be omitted, or some of the components 121, 122, 124, 125, and 126 of the controller 120 may be integrated into one component. In addition to the components 121, 122, 124, 125, and 126 of the controller 120, one or more other components may be added.

[0062] In the following text, reference will be made to Figure 2 The memory 110 is described in more detail.

[0063] Figure 2 It is shown schematically. Figure 1 Block diagram of memory 110.

[0064] Reference Figure 2 According to embodiments of the present disclosure, the memory 110 may include a memory cell array 210, an address decoder 220, a read and write circuit 230, control logic 240, and a voltage generation circuit 250.

[0065] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz (where z is a natural number of 2 or greater).

[0066] Multiple word lines (WL) and bit lines (BL) can be set in multiple memory blocks BLK1 to BLKz, and multiple memory cells can be arranged.

[0067] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read and write circuitry 230 via multiple bit lines BL.

[0068] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be configured from non-volatile memory cells with a vertical channel structure.

[0069] The memory cell array 210 can be configured as a two-dimensional memory cell array or as a three-dimensional memory cell array.

[0070] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) storing one bit of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) storing two bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) storing three bits of data. In another example, each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) storing four bits of data. In yet another example, the memory cell array 210 may include a plurality of memory cells, each of which stores five or more bits of data.

[0071] The number of bits of data stored in each of multiple memory cells can be dynamically determined. For example, a single-level cell storing 1 bit of data can be changed to a three-level cell storing 3 bits of data.

[0072] Reference Figure 2 The address decoder 220, read and write circuit 230, control logic 240 and voltage generation circuit 250 can be operated as peripheral circuits to drive the memory cell array 210.

[0073] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0074] Address decoder 220 can be configured to operate in response to control of control logic 240.

[0075] Address decoder 220 can receive addresses through input / output buffers in memory 110. Address decoder 220 can be configured to decode block addresses in the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0076] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0077] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL in the selected memory block, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0078] In the programming verification operation, the address decoder 220 can apply the verification voltage generated in the voltage generation circuit 250 to the selected word line WL in the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0079] Address decoder 220 can be configured to decode the column address in the received address. Address decoder 220 can transmit the decoded column address to read and write circuitry 230.

[0080] Read and programming operations on memory 110 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include, for example, a block address, a row address, and / or a column address.

[0081] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read and write circuitry 230.

[0082] Address decoder 220 may include one or more of, for example, block decoder, row decoder, column decoder and / or address buffer.

[0083] The read and write circuitry 230 may include multiple page buffers PB. The read and write circuitry 230 may operate as a read circuit in the read operation of the memory cell array 210 and as a write circuit in the write operation of the memory cell array 210.

[0084] The aforementioned read and write circuit 230 can also be referred to as a page buffer circuit or a data register circuit that includes multiple page buffers PB. The read and write circuit 230 may include a data buffer responsible for data processing functions, and may further include a cache buffer responsible for caching functions.

[0085] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. During read and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can hold or latch data by sensing changes in the current through sensing nodes, the changes in the current depending on the programming state of the corresponding memory cell.

[0086] The read and write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0087] During a read operation, the read and write circuit 230 temporarily stores the read data by sensing data in the memory cell, and then outputs the data DATA to the input / output buffer of the memory 110. As an exemplary embodiment, in addition to the page buffer PB or the page register, the read and write circuit 230 may also include column select circuitry.

[0088] Control logic 240 can be connected to address decoder 220, read and write circuitry 230, and voltage generation circuitry 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory 110.

[0089] Control logic 240 can be configured to control the general operation of memory 110 in response to control signal CTRL. Control logic 240 can output control signals for adjusting the precharge potential levels of the sensing nodes of multiple page buffers PB.

[0090] Control logic 240 can control read and write circuit 230 to perform read operations on memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used in the read operation in response to voltage generation circuit control signals output from control logic 240.

[0091] Each memory block of the aforementioned memory 110 can consist of multiple pages corresponding to multiple word lines WL and multiple strings corresponding to multiple bit lines BL.

[0092] Within a storage block BLK, multiple word lines (WL) and multiple bit lines (BL) can be configured to intersect each other. For example, each of the multiple word lines (WL) can be configured along the row direction, and each of the multiple bit lines (BL) can be configured along the column direction. In another example, each of the multiple word lines (WL) can be configured along the column direction, and each of the multiple bit lines (BL) can be configured along the row direction.

[0093] A memory cell can be connected to one of multiple word lines (WL) and one of multiple bit lines (BL). Each memory cell can contain a transistor.

[0094] For example, a transistor disposed in each memory cell may include a drain, a source, and a gate. The drain (or source) of the transistor may be connected directly or via another transistor to the corresponding bit line BL. The source (or drain) of the transistor may be connected directly or via another transistor to the source line (which may be ground). The gate of the transistor may include a floating gate and a control gate, the floating gate being surrounded by a dielectric, and a gate voltage being applied from the word line WL to the control gate.

[0095] In each memory block, a first select line (also referred to as a source select line or drain select line) may be additionally located outside the first outermost word line of the two outermost word lines, closer to the first outermost word line of the read and write circuit 230, and a second select line (also referred to as a drain select line or source select line) may be additionally located outside the second outermost word line of the two outermost word lines.

[0096] At least one additional dummy character line can be set between the first outermost character line and the first selection line. At least one additional dummy character line can also be set between the second outermost character line and the second selection line.

[0097] The read and program (write) operations of the aforementioned storage blocks can be performed on a page-by-page basis, and the erase operation can be performed on a block-by-block basis.

[0098] Figure 3 This is a schematic diagram illustrating the structure of a storage device 100 based on some embodiments of the disclosed technology.

[0099] Reference Figure 3 The storage device 100 may include a memory 110 and a controller 120.

[0100] The memory 110 may include a compressed memory region COMP_AREA and a non-compressed memory region NON_COMP_AREA. The compressed memory region COMP_AREA is an area where data is stored in a compressed state, and the non-compressed memory region NON_COMP_AREA is an area where data is stored in an uncompressed state (e.g., data is stored at its original size). In some embodiments, the term "compressed memory region" may be used to refer to the compressed memory region COMP_AREA, and the term "non-compressed memory region" may be used to refer to the non-compressed memory region NON_COMP_AREA.

[0101] When data is stored in the compressed storage area COMP_AREA, the size of the compressed data is reduced, thus reducing the storage capacity required to store the data. However, when reading data stored in the compressed storage area COMP_AREA, a decompression operation is required to perform the decompression operation on the compressed data.

[0102] On the other hand, when storing data in the uncompressed memory area NON_COMP_AREA, the required storage capacity does not decrease. However, since no decompression operation is required when reading data stored in the uncompressed memory area NON_COMP_AREA, the stored data can be read much faster.

[0103] The ratio of the compressed memory region COMP_AREA and the non-compressed memory region NON_COMP_AREA in memory 110 can be set during the startup process of storage device 100.

[0104] Controller 120 can receive speculative memory read commands SPEC_RD_CMD from the host. In some implementations, speculative memory read is a mechanism by which the processor predicts the likelihood that data will be used.

[0105] The controller 120 can receive the speculative memory read command SPEC_RD_CMD from the host using a predefined interface.

[0106] The speculative memory read command SPEC_RD_CMD can include a target logical address TGT_LA. The speculative memory read command SPEC_RD_CMD can indicate that target data corresponding to the target logical address TGT_LA may be read. Therefore, the controller 120 can speculatively determine that target data may be read.

[0107] The host can transmit speculative memory read commands SPEC_RD_CMD to storage device 100 to reduce the latency between post-processing operations (e.g., cache consistency management, data copying operations, etc.) after data read and subsequent data read operations.

[0108] The speculative memory read command SPEC_RD_CMD only indicates that the target data corresponding to the target logical address TGT_LA may be read, but does not require that the target data be actually read.

[0109] Therefore, the host does not need to respond to the speculative memory read command SPEC_RD_CMD, and the controller 120 does not transmit a response to the received speculative memory read command SPEC_RD_CMD to the host.

[0110] After receiving the speculative memory read command SPEC_RD_CMD, the controller 120 can determine the region where the target data is stored. The region where the target data is stored can be either the compressed memory region COMP_AREA or the uncompressed memory region NON_COMP_AREA.

[0111] Controller 120 can determine whether the target data is stored in the compressed memory region COMP_AREA or the uncompressed memory region NON_COMP_AREA.

[0112] In some implementations, the controller 120 can determine the location in the cache where the data is stored, based on whether the data is stored in a compressed storage region COMP_AREA or a non-compressed storage region NON_COMP_AREA. In some implementations, the cache can be divided into a region for caching data stored in the compressed storage region COMP_AREA and a region for caching data stored in the non-compressed storage region NON_COMP_AREA. For example, the cache may include a first region and a second region, wherein data stored in the compressed storage region COMP_AREA is cached in the first region, and data stored in the non-compressed storage region NON_COMP_AREA is cached in the second region.

[0113] Therefore, the cache can be implemented as physically separate sub-caches. For example, the cache can include a first sub-cache and a second sub-cache. The first sub-cache can cache data stored in the non-compressed storage area NON_COMP_AREA, and the second sub-cache can cache data stored in the compressed storage area COMP_AREA.

[0114] The cache can store data read from memory 110. Figure 3 An example is shown where the cache is located inside the controller 120, but the cache can be located outside the controller 120.

[0115] Caching can be implemented in various ways.

[0116] For example, the cache can be a working memory included in the controller 120 (see...). Figure 1 (125).

[0117] As another example, the cache can be a separate volatile memory located inside or outside the controller 120.

[0118] The storage device 100 and the memory 110 and controller 120 included in the storage device 100 can be implemented in various ways.

[0119] For example, storage device 100 can be implemented as a CXL device that supports the CXL (Compute High-Speed ​​Link) interface. Storage device 100 can allow a host to access storage device 100 through a "CXL.mem" transaction on the CXL interface.

[0120] Controller 120 may be a CXL controller that supports the CXL specification. Controller 120 may receive the aforementioned speculative memory read command SPEC_RD_CMD from the host via the CXL interface. For example, storage device 100 may include a plurality of memory devices 110, each of which includes DRAM and may be used as a memory expansion device for the host.

[0121] The following section describes the operation of storage device 100 in searching for target data corresponding to the target logical address TGT_LA.

[0122] Figure 4 This is a diagram illustrating the operation of a storage device 100 based on some embodiments of the disclosed technology, using a compression mapping table COMP_MAP_TBL to search for target data TGT_DATA stored in a compressed memory region COMP_AREA.

[0123] Reference Figure 4 The controller 120 of the storage device 100 can determine whether the compression mapping entry corresponding to the target logical address TGT_LA exists in the compression mapping table COMP_MAP_TBL, which includes multiple compression mapping entries COMP_MAP_ENT.

[0124] The compression mapping table COMP_MAP_TBL can be stored in memory 110. Controller 120 can load the compression mapping table COMP_MAP_TBL from memory 110 and search for the compression mapping entry corresponding to the target logical address TGT_LA.

[0125] Each of the multiple compression mapping entries in COMP_MAP_ENT can indicate the mapping relationship between logical addresses and physical addresses in the compressed memory region COMP_AREA.

[0126] exist Figure 4 In the configuration, multiple compression mapping entries COMP_MAP_ENT indicate that logical address LA1 corresponds to physical address PA1, logical address LA2 corresponds to physical address PA2, and logical address LA3 corresponds to physical address PA3.

[0127] Because the data size decreases during data compression, the size of the unit region corresponding to the logical address in each compression mapping entry is greater than or equal to the size of the unit region corresponding to the physical address.

[0128] For example, if the size of the unit region corresponding to logical address LA1 is 16KB, the size of the unit region corresponding to physical address PA1 can be 4KB. This means that the 16KB of data corresponding to logical address LA1 has been compressed into 4KB and stored at physical address PA1.

[0129] Each compression map entry may also include information indicating the size of the compressed data.

[0130] exist Figure 4 In this context, the target logical address TGT_LA is logical address LA1. Therefore, the controller 120 can search for the compression mapping entry corresponding to logical address LA1 in the compression mapping table COMP_MAP_TBL.

[0131] The controller 120 can access the compression mapping entry corresponding to the logical address LA1 and obtain the physical address PA1, which is the physical address within the compressed memory region COMP_AREA that is mapped to the logical address LA1.

[0132] In this way, the controller 120 can search for and locate the target data TGT_DATA at physical address PA1 within the compressed memory region COMP_AREA. Since the target data TGT_DATA is stored in a compressed state, a decompression process is required to read the target data TGT_DATA.

[0133] Figure 5 This is a flowchart illustrating the operation of a storage device 100, based on some embodiments of the disclosed technology, to determine the region where target data TGT_DATA is stored.

[0134] Reference Figure 5 The controller 120 of the storage device 100 is referenced above. Figure 4 Search the described compression mapping table COMP_MAP_TBL for the compression mapping entry corresponding to the target logical address TGT_LA (S510).

[0135] The controller 120 determines whether the search for the compressed mapping entry corresponding to the target logical address TGT_LA was successful (S520).

[0136] When the search for the compressed mapping entry corresponding to the target logical address TGT_LA is successful (S520-Yes), the controller 120 can determine that the target data TGT_DATA corresponding to the target logical address TGT_LA is stored in the compressed memory area COMP_AREA (S530).

[0137] On the other hand, when the search for the compressed mapping entry corresponding to the target logical address TGT_LA is unsuccessful (S520-No), the controller 120 can determine that the target data TGT_DATA corresponding to the target logical address TGT_LA is stored in the non-compressed memory area NON_COMP_AREA (S540).

[0138] Controller 120 can be different from the above reference. Figure 5 The described method searches for the target data TGT_DATA.

[0139] For example, controller 120 may first search the non-compressed memory region NON_COMP_AREA to check whether the target data TGT_DATA corresponding to the target logical address TGT_LA is stored in the non-compressed memory region NON_COMP_AREA, and when the target data TGT_DATA is not stored in the non-compressed memory region NON_COMP_AREA, controller 120 may search the compressed memory region COMP_AREA to check whether the target data TGT_DATA is stored in the compressed memory region COMP_AREA.

[0140] As another example, controller 120 can simultaneously perform the operation of searching for target data TGT_DATA in the non-compressed memory region NON_COMP_AREA and the operation of searching for compressed mapping entries in the compressed memory region COMP_AREA.

[0141] As another example, controller 120 can determine which region to search first, whether it's the compressed memory region COMP_AREA or the uncompressed memory region NON_COMP_AREA, based on a pre-configured compression ratio. For instance, when the pre-configured compression ratio is equal to or greater than a threshold compression ratio, controller 120 can first search for the compression mapping entry corresponding to the target logical address TGT_LA in the compressed memory region COMP_AREA, and when the pre-configured compression ratio is less than the threshold compression ratio, controller 120 can first search for the target data TGT_DATA in the uncompressed memory region NON_COMP_AREA. Conversely, when the pre-configured compression ratio is less than the threshold compression ratio, controller 120 can first search for the compression mapping entry corresponding to the target logical address TGT_LA in the compressed memory region COMP_AREA, and when the pre-configured compression ratio is equal to or greater than the threshold compression ratio, controller 120 can first search for the target data TGT_DATA in the uncompressed memory region NON_COMP_AREA.

[0142] Figure 6 This is a diagram illustrating the operation of a storage device 100 based on some embodiments of the disclosed technology storing a compressed mapping entry COMP_MAP_ENT corresponding to a target logical address TGT_LA in a cache.

[0143] Reference Figure 6 When the search for the compressed mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA is successful, the controller 120 of the storage device 100 can store the compressed mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA in the cache.

[0144] The compression mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA indicates that the target logical address TGT_LA is mapped to the physical address PA. The physical address PA indicates the location in the compressed memory region COMP_AREA where the target data TGT_DATA is stored.

[0145] In some implementations, the reason for storing the compression mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA in a cache is to read the target data TGT_DATA more quickly when the host subsequently requests to read the target data TGT_DATA. When the compression mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA is stored in the cache, the controller 120 can access the cache instead of the memory 110, thereby quickly locating the location of the target data TGT_DATA in the compression memory area COMP_AREA.

[0146] In some embodiments, as will be discussed below, storage device 100 may determine whether to store target data TGT_DATA in cache based on the region where target data TGT_DATA is stored.

[0147] Figure 7 This is a diagram illustrating an example of an operation in which a storage device 100, based on some embodiments of the disclosed technology, determines whether to store target data TGT_DATA in a cache.

[0148] Reference Figure 7 When it is determined that the target data TGT_DATA is stored in the non-compressed memory area NON_COMP_AREA, the controller 120 of the storage device 100 can store the target data TGT_DATA in the cache.

[0149] The controller 120 can directly store the target data TGT_DATA stored in the uncompressed memory area NON_COMP_AREA in the cache CACHE without performing a separate decompression operation.

[0150] Figure 8 This is a diagram illustrating another example of the operation of a storage device 100, based on some embodiments of the disclosed technology, determining whether to store target data TGT_DATA in a cache.

[0151] Reference Figure 8 When it is determined that the target data TGT_DATA is stored in the compressed storage area COMP_AREA, the controller 120 of the storage device 100 may not store the target data TGT_DATA in the cache.

[0152] To store the target data TGT_DATA located in the compressed storage area COMP_AREA in the cache, a decompression operation is performed on the stored target data TGT_DATA. When the controller 120 uses resources to store the target data TGT_DATA in the cache before the host requests to read it, there is a risk that the resources required for the ongoing read operation may become insufficient, potentially leading to degraded read performance.

[0153] Furthermore, when the target data TGT_DATA is stored in the cache, existing data previously stored in the cache may be evicted to make room for the target data TGT_DATA. Therefore, data intended for ongoing read operations may be evicted from the cache, resulting in a lower cache hit rate.

[0154] For example, when the 64-byte target data TGT_DATA is stored in the compressed storage area COMP_AREA, it may be necessary to decompress a 4KB data chunk containing the target data TGT_DATA. In this case, if the result of decompressing the data chunk is stored in the cache, the 4KB of data previously stored in the cache may be evicted.

[0155] In this scenario, further access to the indeterminate 64 bytes of target data TGT_DATA will result in 4KB of data being evicted from the cache. If the evicted data is accessed again later, additional resources will be used to read it, potentially leading to performance degradation.

[0156] To address this issue, when it is determined that the target data TGT_DATA is stored in the compressed storage area COMP_AREA, the storage device 100 can determine whether to store the target data TGT_DATA in the cache based on the compressed size of the target data TGT_DATA.

[0157] Figure 9 This is a flowchart illustrating the operation of a storage device 100 based on some embodiments of the disclosed technology to determine whether to store the target data TGT_DATA in a cache based on the compressed size of the target data TGT_DATA.

[0158] Reference Figure 9The controller 120 of the storage device 100 can determine the compressed size of the target data TGT_DATA in the compressed memory region COMP_AREA (S910). For example, the controller 120 can determine the compressed size of the target data TGT_DATA based on the information included in the compressed mapping entry COMP_MAP_ENT corresponding to the target logical address TGT_LA.

[0159] For example, controller 120 determines whether the compressed size of target data TGT_DATA is less than a preset threshold size (S920).

[0160] When the compressed size of the target data TGT_DATA is less than the threshold size (S920 - Yes), the controller 120 can store the target data TGT_DATA in the cache (S930).

[0161] On the other hand, when the compressed size of the target data TGT_DATA is equal to or greater than the threshold size (S920 - No), the controller 120 may not store the target data TGT_DATA in the cache (S940).

[0162] Figure 10 This is a diagram illustrating a method of operating a storage device 100 based on some embodiments of the disclosed technology.

[0163] Reference Figure 10 The method of operating the storage device 100 may include operation S1010: receiving a speculative memory read command SPEC_RD_CMD from the host, the speculative memory read command SPEC_RD_CMD indicating the possibility that target data TGT_DATA corresponding to the target logical address TGT_LA will be read.

[0164] The method of operating the storage device 100 may include operation S1020: searching for or locating a region in memory 110 where target data TGT_DATA is stored, memory 110 including a compressed memory region COMP_AREA where data is stored in a compressed state and an uncompressed memory region NON_COMP_AREA where data is stored in an uncompressed state (e.g., data is stored at its original size).

[0165] Operation S1020 may further include: searching and locating the compression mapping entry corresponding to the target logical address TGT_LA in the compression mapping table COMP_MAP_TBL, which includes multiple compression mapping entries COMP_MAP_ENT. Each of the multiple compression mapping entries COMP_MAP_ENT can indicate the mapping relationship between the logical address and the physical address in the compressed memory region COMP_AREA.

[0166] For example, operation S1020 may include: when a successful search for a compression mapping entry corresponding to the target logical address TGT_LA in the compression mapping table COMP_MAP_TBL, determining that the target data TGT_DATA is stored in the compression memory region COMP_AREA; and when a failed search for a compression mapping entry corresponding to the target logical address TGT_LA in the compression mapping table COMP_MAP_TBL (e.g., when no compression mapping entry corresponding to the target logical address TGT_LA exists in the compression mapping table COMP_MAP_TBL), determining that the target data TGT_DATA is stored in the non-compression memory region NON_COMP_AREA.

[0167] The method of operating the storage device 100 may include operation S1030: determining whether to store the target data TGT_DATA in a cache CACHE, which is configured to temporarily store data read from the memory 110, based on whether the location where the target data TGT_DATA is stored is a compressed memory region COMP_AREA or a non-compressed memory region NON_COMP_AREA.

[0168] The method of operating the storage device 100 may further include: when the search for the compressed mapping entry corresponding to the target logical address TGT_LA is successful in operation S1020, storing the compressed mapping entry corresponding to the target logical address TGT_LA in the cache CACHE.

[0169] The method of operating the storage device 100 may further include: when it is determined that the target data TGT_DATA is stored in the non-compressed memory area NON_COMP_AREA, storing the target data TGT_DATA in the cache CACHE.

[0170] When it is determined that the target data TGT_DATA is stored in the compressed storage area COMP_AREA, the storage device 100 may not store the target data TGT_DATA in the cache.

[0171] In some embodiments, the method of operating the storage device 100 may further include: when it is determined that the target data TGT_DATA is stored in the compressed storage region COMP_AREA, determining whether to store the target data TGT_DATA in the cache based on the size of the target data TGT_DATA compressed in the compressed storage region COMP_AREA.

[0172] In some implementations, determining whether to store the target data TGT_DATA in the cache based on the compressed size of the target data TGT_DATA may include: determining to store the target data TGT_DATA in the cache when the compressed size of the target data TGT_DATA is less than a threshold size, and determining not to store the target data TGT_DATA in the cache when the compressed size of the target data TGT_DATA is equal to or greater than the threshold size.

[0173] This document describes only some embodiments and examples. Based on the content described and illustrated in this patent application, improvements and changes can be made to the disclosed embodiments and other embodiments.

Claims

1. A data storage device, comprising: A memory device includes: a compressed memory region for storing compressed data; and an uncompressed memory region for storing uncompressed data; and A controller, communicating with the memory device to control the memory device, and: receives a speculative memory read command from a host, the speculative memory read command indicating the possibility that target data corresponding to a target logical address in the memory device will be read; in response to receiving the speculative memory read command, determines whether the location of the target data stored in the memory device is the compressed memory region or the uncompressed memory region; and, based on whether the location of the target data stored in the memory device is the compressed memory region or the uncompressed memory region, determines whether to store the target data from the memory device in a cache.

2. The data storage device according to claim 1, wherein, The controller determines whether a compressed mapping entry corresponding to the target logical address exists in a compressed mapping table that includes multiple compressed mapping entries, and Each of the plurality of compression mapping entries indicates the mapping relationship between logical addresses and physical addresses in the compressed memory region.

3. The data storage device according to claim 2, wherein, The controller: When a compression mapping entry corresponding to the target logical address is successfully found in the compression mapping table, it is determined that the target data is stored in the compression memory area; as well as If no compressed mapping entry corresponding to the target logical address is found in the compressed mapping table, the target data is determined to be stored in the non-compressed memory area.

4. The data storage device according to claim 2, wherein, When it is determined that a compressed mapping entry corresponding to the target logical address exists, the controller stores the compressed mapping entry corresponding to the target logical address in the cache.

5. The data storage device according to claim 1, wherein, When it is determined that the target data is stored in the uncompressed memory area, the controller stores the target data in the cache.

6. The data storage device according to claim 5, wherein, The cache includes a first sub-cache and a second sub-cache. The first sub-cache temporarily stores data from the uncompressed memory region, and the second sub-cache temporarily stores data from the compressed memory region. The controller stores the target data in the first sub-cache.

7. The data storage device according to claim 4, wherein, When the target data is determined to be stored in the compressed memory area, the controller, in response to a read command for the target data received from the host, uses the compressed mapping entry stored in the cache corresponding to the target logical address to store the target data in the cache.

8. The data storage device according to claim 7, wherein, The cache includes a first sub-cache and a second sub-cache. The first sub-cache caches data stored in the uncompressed memory area, and the second sub-cache caches data stored in the compressed memory area. The controller stores the target data in the second sub-cache.

9. The data storage device according to claim 1, wherein, When the target data is determined to be stored in the compressed storage area, the controller determines whether to store the target data in the cache based on the size of the target data compressed in the compressed storage area.

10. The data storage device according to claim 9, wherein, The controller: When the compressed size of the target data is determined to be less than the threshold size, the target data is stored in the cache; as well as When the compressed size of the target data is determined to be equal to or greater than the threshold size, the target data should be prevented from being stored in the cache.

11. A method of operating a data storage device, comprising: Receive a speculative memory read command from the host, the speculative memory read command indicating the probability that target data corresponding to a target logical address will be read; Determine the location where the target data is stored in a memory device, the memory device including a compressed memory region where the data is stored in a compressed state and an uncompressed memory region where the data is stored in an uncompressed state; as well as Based on whether the target data is stored in the compressed memory region or the uncompressed memory region in the memory device, it is determined whether the target data is stored in a cache, the cache storing data read from the memory device.

12. The method according to claim 11, wherein, Determining the location of the target data stored in the memory device includes: determining whether a compression mapping entry corresponding to the target logical address exists in a compression mapping table that includes multiple compression mapping entries, and Each of the plurality of compression mapping entries indicates the mapping relationship between logical addresses and physical addresses in the compressed memory region.

13. The method according to claim 12, wherein, Determining the location of the target data stored in the memory device includes: When a compression mapping entry corresponding to the target logical address is successfully found in the compression mapping table, it is determined that the target data is stored in the compression memory region; and If no compressed mapping entry corresponding to the target logical address is found in the compressed mapping table, the target data is determined to be stored in the non-compressed memory area.

14. The method of claim 12, further comprising: When it is determined that a compressed mapping entry corresponding to the target logical address exists, the compressed mapping entry corresponding to the target logical address is stored in the cache.

15. The method of claim 11, further comprising: When it is determined that the target data is stored in the uncompressed memory area, the target data is stored in the cache.

16. A computing high-speed link device, namely a CXL device, comprising: A memory device, comprising a compressed memory region where data is stored in a compressed state and an uncompressed memory region where data is stored in an uncompressed state; as well as The CXL controller communicates with the memory device and: receives speculative memory read commands from the host via the CXL interface, the speculative memory read commands indicating the probability that target data corresponding to a target logical address will be read; In response to receiving the speculative memory read command, determine whether the location of the target data stored in the memory device is the compressed memory region or the uncompressed memory region; And based on whether the location of the target data stored in the memory device is the compressed memory region or the uncompressed memory region, determine whether to store the target data in a cache, the cache storing data read from the memory device.

17. The CXL device according to claim 16, wherein, The CXL controller determines whether a compressed mapping entry corresponding to the target logical address exists in a compressed mapping table that includes multiple compressed mapping entries, and Each of the plurality of compression mapping entries indicates the mapping relationship between logical addresses and physical addresses in the compressed memory region.

18. The CXL device according to claim 17, wherein, The CXL controller: When a compression mapping entry corresponding to the target logical address is successfully found in the compression mapping table, it is determined that the target data is stored in the compression memory area; as well as If no compressed mapping entry corresponding to the target logical address is found in the compressed mapping table, the target data is determined to be stored in the non-compressed memory area.

19. The CXL device according to claim 17, wherein, When it is determined that a compressed mapping entry corresponding to the target logical address exists, the CXL controller stores the compressed mapping entry corresponding to the target logical address in the cache.

20. The CXL device according to claim 16, wherein, When the target data is determined to be stored in the uncompressed memory region, the CXL controller stores the target data in the cache.

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