Method and device for aggregating input / output (IO) addresses and electronic equipment

Abstract

The invention discloses an IO address aggregation method and device and electronic equipment, and belongs to the technical field of data storage. The method comprises the following steps: determining an IO address candidate set meeting an aggregation validity condition in a plurality of IO address candidate sets as a valid IO address candidate set; based on a gap between adjacent IO addresses in each effective IO address candidate set or based on the gap between the adjacent IO addresses in each effective IO address candidate set and a first span threshold, segmenting the effective IO address candidate sets to obtain a plurality of IO address sets; determining the IO address set meeting a set screening condition in the plurality of IO address sets as a target IO address set; and merging the plurality of IO requests accessing the same target IO address set into an aggregated IO request for processing.

Description

Technical Field

[0001] This application belongs to the field of data storage technology, and specifically relates to a method, apparatus and electronic device for aggregating input and output I / O addresses. Background Technology

[0002] The input / output (I / O) performance of modern electronic devices is a key bottleneck restricting user experience. Analysis of a large amount of user lag data revealed that approximately 22% of user interface lag was caused by I / O requests to load data from memory, with the root cause traceable to I / O efficiency issues. The core of this challenge lies in the complex software stack of electronic applications: during runtime, an application's I / O requests originate from multiple concurrent sources, including the main program, function libraries, and user interface (UI) resources. These requests ultimately manifest as highly discrete and fragmented address access sequences at the physical storage level. When multiple fragmented I / O requests accumulate and are processed together, a perceptible lag or stuttering phenomenon occurs. Summary of the Invention

[0003] The purpose of this application is to provide a method, apparatus, and electronic device for aggregating input / output I / O addresses, which can ensure that users will not experience lag due to I / O read / write operations during application use.

[0004] In a first aspect, embodiments of this application provide a method for aggregating input / output I / O addresses, including: The set of IO address candidates that meets the aggregation validity condition among multiple IO address candidate sets is determined as the valid IO address candidate set; The effective IO address candidate set is divided based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets. The set of IO addresses that meets the set filtering conditions among the plurality of IO address sets is determined as the target IO address set; Multiple I / O requests that access the same target I / O address set are merged into an aggregated I / O request for processing.

[0005] Secondly, embodiments of this application provide an input / output I / O address aggregation device, comprising: The determination module is used to determine the set of IO address candidates that meet the aggregation validity conditions from multiple IO address candidate sets as the valid IO address candidate set; The segmentation module is used to segment the effective IO address candidate set based on the gap between adjacent IO addresses in each effective IO address candidate set or based on the gap between adjacent IO addresses in each effective IO address candidate set and a first span threshold, to obtain multiple IO address sets. The determining module is further configured to determine the set of IO addresses that meets the set filtering conditions among the plurality of IO address sets as the target IO address set; The processing module is used to merge multiple IO requests that access the same target IO address set into an aggregated IO request for processing.

[0006] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0007] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0008] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0009] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0010] In this embodiment, coarse-grained segmentation of IO addresses is achieved by determining the IO address candidate set that meets the aggregation validity condition from multiple IO address candidate sets as the effective IO address candidate set. Furthermore, fine-grained segmentation of IO addresses is achieved by further segmenting the effective IO address candidate sets based on the gaps between adjacent IO addresses in each effective IO address candidate set, or based on the gaps between adjacent IO addresses in each effective IO address candidate set and a first span threshold. Moreover, the IO address set that meets the set filtering condition from the multiple IO address sets is determined as the target IO address set, achieving quality filtering of the IO address set. Multiple IO requests accessing the same target IO address set are merged into an aggregated IO request for processing, replacing multiple fragmented IO requests with a single IO request. This achieves the purpose of amortizing fixed IO overhead, improving system smoothness, and ensuring that users do not experience lag due to IO read / write operations during application usage. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating a method for aggregating input / output I / O addresses provided in some embodiments of this application; Figure 2 This is a schematic flowchart illustrating the method for aggregating input / output I / O addresses provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure of an input / output I / O address aggregation device provided in some embodiments of this application; Figure 4 These are structural block diagrams of electronic devices provided in some embodiments of this application; Figure 5 These are structural block diagrams of electronic devices provided in some embodiments of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] Currently, to address the performance challenges posed by fragmented I / O, prefetching technology has become a standard feature of operating systems. Its logic involves using software prefetching strategies to load data from adjacent or clustered "hotspot areas" on physical addresses into the memory cache in advance. A highly efficient prefetching strategy is key to intelligently merging multiple identified discrete hotspots, thereby replacing multiple fragmented small I / O operations with a single large I / O operation, truly achieving the goal of amortizing fixed I / O overhead and improving system smoothness.

[0015] It is worth noting that in the fields of databases and advanced storage systems, many mature ideas have been developed to address similar performance issues. For example, batch processing and delayed merging transform a large number of random writes into efficient sequential writes; current storage systems all incorporate artificial intelligence (AI) mechanisms for analysis and prediction of subsequent I / O strategies. These advanced, quantitatively-based decision-making mechanisms provide valuable insights for solving the prefetch merging challenge on electronic devices, namely, that prefetch merging decisions should not be fixed or empirical, but rather dynamic and quantifiable.

[0016] The prefetching mechanism used in the operating systems of current electronic devices has a fundamental design flaw in how it executes merging decisions: Due to the hierarchical nature of the I / O path in electronic device systems and the resulting information barriers, the lower-level prefetcher cannot know the application semantics of the upper layer. That is, the prefetcher cannot understand which physically discrete I / O requests are actually for the same application purpose (such as rendering a certain interface). Therefore, the prefetcher may easily miss the valuable opportunity to merge and prefetch these logically related hot blocks.

[0017] Existing prefetchers lack sophisticated analysis mechanisms when deciding whether to merge several physically adjacent hotspots. Their decisions are often based on rigid rules of thumb, without weighing the benefits of saving an I / O request against the cost of additional data reads during the gaps. This crude decision-making can easily lead to serious read amplification problems, where reducing one I / O request introduces several times more invalid data reads, wasting bandwidth, polluting the cache, and sometimes even outweighing the benefits.

[0018] In summary, existing technologies only read the first 64K of data sequentially after the current I / O address, regardless of whether the subsequent 64K will be used. This pre-reading is inflexible. Furthermore, regardless of whether the addresses after the current I / O address will be used, subsequent address usage requires another I / O read / write operation, causing frame drops and stuttering in the application due to I / O read / write operations.

[0019] Therefore, this application provides a method, apparatus, and electronic device for aggregating input / output I / O addresses. Through a multi-level segmentation algorithm of physical address gaps, it achieves adaptive identification of hotspot areas, ensuring that the boundary of the target I / O address set can naturally fit the density changes of I / O access, and ensuring that users will not experience lag due to I / O read / write during application use.

[0020] The method for aggregating input / output I / O addresses provided in this application will be described below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0021] It should be noted that the input / output I / O address aggregation method provided in this application can be executed by electronic devices such as mobile phones, tablets, laptops, PDAs, and in-vehicle electronic devices. Some embodiments of this application use electronic devices as the executing entity to illustrate the input / output I / O address aggregation method provided in this application.

[0022] like Figure 1 As shown, this application embodiment provides a method for aggregating input / output I / O addresses, which may specifically include the following steps 101 to 104: Step 101: Determine the set of IO address candidates that meets the aggregation validity condition from the multiple IO address candidate sets as the valid IO address candidate set.

[0023] Specifically, the candidate I / O address set includes at least one I / O address. If the candidate I / O address set includes at least two I / O addresses, these two I / O addresses are sorted in ascending order (or descending order) by their address values. After determining multiple candidate I / O address sets, it is determined whether each candidate I / O address set satisfies the aggregation validity condition. The candidate I / O address sets that satisfy the aggregation validity condition are determined as valid candidate I / O address sets. By filtering the valid candidate I / O address sets through the aggregation validity condition, coarse-grained segmentation of I / O addresses is achieved.

[0024] In an optional specific embodiment, before step 101 determines the set of IO address candidates that meet the aggregation validity condition from multiple IO address candidate sets as the valid IO address candidate set, the method further includes: Determine the access range of IO addresses, and sort the IO addresses within the access range according to their address values ​​to obtain the sorted IO addresses; Traverse the sorted IO addresses, and determine the gap as a dividing point when the gap between adjacent IO addresses is greater than or equal to a first gap threshold; The sorted IO addresses are divided into multiple IO address candidate sets based on the splitting points.

[0025] Specifically, the system collects historical data from the global address space on which I / O addresses were accessed during specific time periods, and determines the access range of these I / O addresses, i.e., the clustering range of I / O activity. The I / O addresses within this access range are then sorted in ascending or descending order according to their corresponding address values ​​to obtain the sorted I / O addresses (i.e., the sorted I / O address stream). The sorted I / O addresses can be in list form or other formats.

[0026] The sorted I / O addresses are traversed, and the gap between every two adjacent I / O addresses is obtained. This gap is then compared to a first gap threshold (e.g., 80 address spans, 50 address spans, etc., the specific value of which is not specifically limited in this application). If the gap between adjacent I / O addresses is greater than or equal to the first gap threshold, this gap is used as a macroscopic dividing point to coarsely segment the sorted I / O addresses, thus obtaining multiple candidate sets of segmented I / O addresses. The value of the first gap threshold is only an example and can be set as needed.

[0027] It should be noted that there can be one or more split points. For example, if there is one split point, the sorted I / O address stream can be split into two sets of I / O address candidates. If there are two split points, the sorted I / O address stream can be split into three sets of I / O address candidates.

[0028] For example: the first gap threshold is 80 address spans. Suppose that the IO requests collected within a certain time period have the following corresponding IO addresses (already sorted in ascending order): [1000, 1004, 1008, 1012, 1092, 1096, 1100, 1116, 1120, 1300, 1304, ..., 1396, 1500, 1550, 1554]. Among them, [1300, 1304, ..., 1396] are multiple consecutive IO address values ​​with a gap of 4 address spans, and a total span of 96 address spans.

[0029] Since the gap between 1012 and 1092 is 80 address spans, this gap is taken as the macroscopic dividing point. Similarly, since the gap between 1120 and 1300 is 180 address spans, this gap is also taken as the macroscopic dividing point. Furthermore, since the gap between 1396 and 1500 is 104 address spans, this gap is also taken as the macroscopic dividing point. Therefore, the resulting I / O address candidate set is as follows: A=[1000, 1004, 1008, 1012]; B=[1092, 1096, 1100, 1116, 1120]; C = [1300, ..., 1396]; D=[1500, 1550, 1554].

[0030] In one optional specific embodiment, the aggregation validity condition in step 101 includes, but is not limited to, at least one of the following three: The first condition is that the first IO address span between the minimum and maximum IO addresses in the IO address candidate set is greater than or equal to the second span threshold.

[0031] Specifically, for any set of candidate I / O addresses, the minimum and maximum I / O addresses in the set are obtained, and a first I / O address span between the minimum and maximum I / O addresses is calculated. This first I / O address span is compared to a second span threshold (e.g., 4 address spans). If the first I / O address span is less than the second span threshold, the candidate I / O address set is removed. If the first I / O address span is greater than or equal to the second span threshold, the candidate I / O address set is retained. Here, the first I / O address span refers to the address span distance between the maximum and minimum I / O addresses. By evaluating the first I / O address span, a set of I / O addresses with a controllable range within the address set can be intelligently selected for merging and preloading, thereby ensuring that optimization measures truly bring performance improvements rather than introducing additional overhead.

[0032] It should be noted that the value of the second span threshold is only an example and can be set as needed.

[0033] The second condition is that the number of IO addresses in the IO address candidate set is greater than or equal to the number threshold.

[0034] Specifically, for any given set of I / O address candidates, the number of I / O addresses in the candidate set is obtained, and this number is compared with a threshold. If the number of I / O addresses in the candidate set is less than the threshold, the candidate set is removed. If the number of I / O addresses in the candidate set is greater than or equal to the threshold, the candidate set is retained.

[0035] It should be noted that the quantity threshold value is only an example and can be set according to needs. For example, the quantity threshold is set to: no less than 2, and preferably 2.

[0036] The third item: The median of the gap determined based on the gap between every two adjacent IO addresses in the IO address candidate set is less than the median threshold.

[0037] Specifically, for any set of candidate I / O addresses, the gaps between every two adjacent I / O addresses in the set are obtained and sorted to determine the median of the gaps. The median is then compared to a median threshold. If the median is greater than or equal to the median threshold, the candidate I / O address set is removed. If the median is less than the median threshold, the candidate I / O address set is retained. The range of the median threshold is merely an example and can be set as needed. For instance, the median threshold can be set between 16 and 128 address spans, preferably 32 address spans; however, the specific value is not specifically limited in this application.

[0038] It should be noted that the above three judgment processes do not distinguish the order of events. By verifying the quality of the aggregate validity conditions, the valid macro regions, i.e. the set of valid IO address candidates, are determined.

[0039] For example: the second span threshold is 4 address spans, the number threshold is 2, and the median threshold is 32 address spans.

[0040] The candidate set of I / O addresses includes: A = [1000, 1004, 1008, 1012]; B=[1092, 1096, 1100, 1116, 1120]; C = [1300, ..., 1396]; D=[1500, 1550, 1554].

[0041] Since A has a first I / O address span of 12 address spans, contains 4 I / O addresses, and has a median gap of 4 address spans, A satisfies the aggregation validity condition. Since B has a first I / O address span of 28 address spans, contains 5 I / O addresses, and has a median gap of 4 address spans, B satisfies the aggregation validity condition. Since C has a first I / O address span of 96 address spans, contains 25 I / O addresses, and has a median gap of 4 address spans, C satisfies the aggregation validity condition. Since D has a first I / O address span of 54 address spans, contains 3 I / O addresses, and has a median gap of 27 address spans, D satisfies the aggregation validity condition. Therefore, A, B, C, and D are all candidate sets of valid I / O addresses.

[0042] Step 102: Based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, the effective IO address candidate sets are segmented to obtain multiple IO address sets.

[0043] Specifically, the I / O addresses in each valid I / O address candidate set are sorted in ascending order (or descending order) by their address values. The gap between adjacent I / O addresses in this valid I / O address candidate set is obtained. The gap between adjacent I / O addresses refers to the address span distance between two adjacent I / O addresses. The gap between adjacent I / O addresses is a quantitative indicator used to measure the degree of correlation between the access operations of two I / O addresses in storage space. For example, if the address values ​​of two adjacent I / O addresses are 1000 and 1004, then the gap between adjacent I / O addresses is 4 address spans. The first span threshold refers to the limit of the address span between the largest and smallest I / O addresses in a valid I / O address candidate set, such as 32 address spans. The specific value is not specifically limited in this application.

[0044] In one embodiment, for each valid IO address candidate set, the valid IO address candidate set is segmented based on the gap between each adjacent IO address in the valid IO address candidate set to obtain multiple IO address sets corresponding to the valid IO address candidate set. By segmenting each valid IO address candidate set in the above manner, the IO address set corresponding to each valid IO address candidate set is obtained, so as to achieve fine-grained segmentation of IO addresses.

[0045] In one embodiment, for each valid IO address candidate set, the valid IO address candidate set is segmented based on the gap between each adjacent IO address in the valid IO address candidate set and a preset first span threshold to obtain multiple IO address sets corresponding to the valid IO address candidate set. By segmenting each valid IO address candidate set in the above manner, the IO address set corresponding to each valid IO address candidate set is obtained, so as to achieve fine-grained segmentation of IO addresses.

[0046] The above embodiments identify and utilize the gaps between adjacent IO addresses and a first span threshold to aggregate continuous and dense accesses into a set of IO addresses, while separating sparse and scattered accesses, thereby achieving intelligent and efficient IO request merging and preloading.

[0047] In an optional specific embodiment, step 102 divides the effective IO address candidate set based on the gap between adjacent IO addresses in the effective IO address candidate set, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets, specifically including: When the gap between adjacent I / O addresses in the effective I / O address candidate set is greater than or equal to the corresponding second gap threshold, the gap is determined as a dividing point. The second gap threshold is determined based on the median of the gaps in the effective I / O address candidate set, and the median of the gaps is determined based on the gap between every two adjacent I / O addresses in the effective I / O address candidate set. The set of valid IO address candidates is divided based on the dividing point to obtain multiple IO address sets.

[0048] Specifically, the number of valid I / O address candidate sets can be one or more. For any valid I / O address candidate set, the gap between every two adjacent I / O addresses is obtained, and the gap between each adjacent I / O address is compared with a second gap threshold. If the gap between adjacent I / O addresses is greater than or equal to the second gap threshold, then the gap between adjacent I / O addresses is determined as a micro-segmentation point, and the I / O addresses in the valid I / O address candidate set are segmented based on this segmentation point to obtain multiple I / O address sets corresponding to the valid I / O address candidate set. The second gap threshold is determined based on the median of the gaps between every two adjacent I / O addresses in the valid I / O address candidate set and a preset coefficient (e.g., 4). Specifically, the product of the median of the gaps in the valid I / O address candidate set and the preset coefficient is used as the second gap threshold corresponding to that valid I / O address candidate set. The value of the preset coefficient is only an example and can be set as needed.

[0049] In the above embodiments, a large set of valid IO address candidates is divided into a set of IO addresses (i.e., micro-windows) by using a second gap threshold, so as to further refine the IO addresses into a more precise and compact set of IO addresses.

[0050] In an optional specific embodiment, the step of dividing the valid IO address candidate set based on the segmentation point to obtain multiple IO address sets specifically includes: The set of valid I / O address candidates is divided based on the dividing point to obtain multiple subsets of valid I / O address candidates; The subset of valid IO address candidates whose second IO address span between the minimum and maximum IO address is greater than the first span threshold is divided according to the first span threshold to obtain multiple IO address sets.

[0051] Specifically, for any set of valid I / O address candidates, the gap between every two adjacent I / O addresses is obtained, and the gap between each adjacent I / O address is compared with a second gap threshold. If the gap between adjacent I / O addresses is greater than or equal to the second gap threshold, the gap between the adjacent I / O addresses is determined as a micro-segmentation point, and the I / O addresses in the set of valid I / O address candidates are segmented based on the segmentation point to obtain multiple subsets of valid I / O address candidates corresponding to the set of valid I / O address candidates.

[0052] For example: the preset coefficient is 4. The set of valid I / O addresses includes: A = [1000, 1004, 1008, 1012]; B=[1092, 1096, 1100, 1116, 1120]; C = [1300, ..., 1396]; D=[1500, 1550, 1554].

[0053] If the median gap in A is 4 address spans, then the second gap threshold for A is 16 address spans. Since all gaps in A are 4 address spans, A is not segmented.

[0054] The median gap of B is 4 address spans, so the second gap threshold corresponding to B is 16 address spans. Since the gap between 1100 and 1116 is 16 address spans, the gap between 1100 and 1116 is taken as the micro-division point, resulting in B1=[1092, 1096, 1100] and B2=[1116, 1120].

[0055] The median gap in C is 4 address spans, therefore the second gap threshold for C is 16 address spans. Since all gaps in C are 4 address spans, C is not segmented.

[0056] The median gap of D is 27 address spans, therefore the second gap threshold corresponding to D is 108 address spans. Since the gap between 1500 and 1550 is 50 address spans, this gap is used as a micro-level dividing point, resulting in D1=

[1500] and D2=[1550, 1554]. Because D1 contains only one I / O address, which may be noise, it is discarded. Therefore, the subset of valid I / O address candidates is: A=[1000, 1004, 1008, 1012]; B1 = [1092, 1096, 1100]; B2=[1116, 1120]; C = [1300, ..., 1396]; D2=[1550, 1554].

[0057] Then, the second IO address span between the minimum and maximum IO address in each valid IO address candidate subset is calculated, and the second IO address span is compared with the first span threshold. If the second IO address span is greater than the first span threshold, in order to prevent the valid IO address candidate subset from being too large, the valid IO address candidate subset with the second IO address span greater than the first span threshold is forcibly split according to the first span threshold to obtain multiple IO address sets.

[0058] For example: the first span threshold is 32 address spans. The valid I / O address candidate subset is: A=[1000, 1004, 1008, 1012]; B1 = [1092, 1096, 1100]; B2=[1116, 1120]; C = [1300, ..., 1396]; D2=[1550, 1554].

[0059] In this set, the second I / O address span of A is 12 address spans, requiring no mandatory splitting. The second I / O address span of B1 is 8 address spans, requiring no mandatory splitting. The second I / O address span of B2 is 4 address spans, requiring no mandatory splitting. The second I / O address span of C is 96 address spans, requiring mandatory splitting according to the first span threshold of 32 address spans, resulting in C1=[1300, ..., 1332], C2=[1332, ..., 1364], and C3=[1364, ..., 1396]. The second I / O address span of D2 is 4 address spans, requiring no mandatory splitting. Therefore, the I / O address set includes: A=[1000, 1004, 1008, 1012]; B1 = [1092, 1096, 1100]; B2=[1116, 1120]; C1 = [1300, ..., 1332]; C2 = [1332, ..., 1364]; C3 = [1364, ..., 1396]; D2=[1550, 1554].

[0060] In the above embodiments, a large set of valid IO address candidates is divided into a set of IO addresses (i.e., micro-windows) by using a second gap threshold and a first span threshold, so as to further refine the IO addresses into a more precise and compact set of IO addresses.

[0061] Step 103: Determine the set of IO addresses that meets the set filtering conditions from the multiple IO address sets as the target IO address set.

[0062] Specifically, it determines whether each set of I / O addresses meets the set filtering criteria, and determines the set of I / O addresses that meets the criteria as the target I / O address set, thus achieving quality filtering of the I / O address set. The above embodiment, through a multi-level segmentation algorithm of physical address gaps, achieves adaptive identification of hotspot areas, ensuring that the boundaries of the target I / O address set naturally conform to the density changes of I / O access, and guaranteeing that users will not experience lag due to I / O read / write operations during application use.

[0063] In one optional specific embodiment, the set filtering conditions in step 103 include, but are not limited to, the following: The IO address density of the IO address set is greater than or equal to a density threshold, wherein the IO address density is obtained based on the number of IO addresses in the IO address set and a third IO address span between the minimum and maximum IO addresses in the IO address set.

[0064] Specifically, for any set of I / O addresses, obtain the minimum I / O address and the maximum I / O address in the set, and calculate the third I / O address span between the minimum I / O address and the maximum I / O address.

[0065] The system then obtains the number of I / O addresses in the I / O address set. It calculates the number of I / O addresses corresponding to the I / O address set, divides it by the third I / O address span, and uses this value as the I / O address density corresponding to the I / O address set. The I / O address density corresponding to the I / O address set is compared with a density threshold. If the I / O address density is less than the density threshold, the I / O address set does not meet the set filtering conditions and is removed. If the I / O address density is greater than or equal to the second density threshold, the I / O address set is retained. For example, the density threshold can be set between 20% and 100% as needed; in one possible implementation, it is set to 40%.

[0066] The density threshold values ​​shown are for illustrative purposes only and can be set as needed.

[0067] In the above embodiments, if the IO address density of the IO address set is greater than or equal to the density threshold, the IO address set is determined to meet the set filtering conditions, and the IO address set is taken as the final target IO address set whose boundaries can adaptively fit the IO mode, so as to ensure that each output target IO address set has sufficient prefetch value.

[0068] If all I / O address sets meet the set filtering criteria, the output will include data containing metrics such as span and the number of I / O addresses.

[0069] For example: After detection, there are 20 hot addresses around the IO address of 50,000,000 (i.e., the first IO address span between the smallest and largest IO address in the effective IO address candidate set). The effective IO address candidate set of the 20 address spans is then finely segmented to obtain the IO address set. The IO address set that meets the set filtering conditions is determined as the hot IO data set (i.e., the target IO address set).

[0070] By extracting the set of IO hotspot addresses in this solution, the IO address data to be used in the future is read during the application startup process, ensuring that the user will not experience lag due to IO read and write operations while using the application.

[0071] like Figure 2 As shown, the process of determining the target I / O address described above will be explained through a specific embodiment below: Step 201: Determine the access range of IO addresses, and sort the IO addresses within the access range according to their address values ​​to obtain the sorted IO addresses.

[0072] Step 202: Traverse the sorted IO addresses. When the gap between adjacent IO addresses is greater than or equal to the first gap threshold, determine the gap as the split point. Based on the split point, divide the sorted IO addresses into multiple IO address candidate sets.

[0073] Step 203: Determine whether the candidate set of IO addresses meets the aggregation validity condition. If yes, proceed to step 204; otherwise, proceed to step 209.

[0074] Step 204: Determine the set of IO address candidates that meet the aggregation validity conditions as the set of valid IO address candidates.

[0075] Step 205: When the gap between adjacent IO addresses in the valid IO address candidate set is greater than or equal to the corresponding second gap threshold, the gap is determined as the split point. Based on the split point, the valid IO address candidate set is divided to obtain multiple valid IO address candidate subsets.

[0076] Step 206: Divide the subset of valid IO address candidates whose second IO address span between the minimum IO address and the maximum IO address is greater than the first span threshold according to the second span threshold to obtain multiple IO address sets.

[0077] Step 207: Determine whether the I / O address set meets the set filtering conditions. If yes, proceed to step 208; otherwise, proceed to step 209.

[0078] Step 208: Determine the set of I / O addresses that meet the set filtering conditions as the target I / O address set.

[0079] Step 209: Remove the I / O address set that does not meet the set filtering conditions, or remove the I / O address candidate set that does not meet the aggregation validity conditions.

[0080] The above embodiments utilize a multi-level segmentation algorithm based on physical address gap characteristics to achieve adaptive aggregation of hotspot regions (i.e., the target I / O address set), ensuring that their boundaries naturally align with the density variations of I / O access. During operation, if multiple accessed I / O addresses belong to the same target I / O address set, the multiple I / O requests accessing these addresses are merged into a single aggregated I / O request. This single I / O request replaces multiple fragmented I / O requests, significantly optimizing application startup time and reducing stuttering and frame drops caused by accumulated I / O within sliding frames. This effectively addresses performance bottlenecks caused by numerous "fragmented I / Os" initiated by electronic device applications, improving overall system smoothness. Simulation test data based on this embodiment shows that after hotspot address optimization, application startup time is reduced by 16.7%, and stuttering caused by memory I / O during sliding is eliminated.

[0081] Step 104: Merge multiple IO requests that access the same target IO address set into an aggregated IO request for processing.

[0082] Specifically, during use, if multiple IO addresses accessed belong to the same target IO address set, the multiple IO requests accessing multiple IO addresses will be merged into a single aggregated IO request. This single IO request replaces multiple fragmented IO requests, thereby amortizing the fixed overhead of IO and improving system smoothness, ensuring that users will not experience lag due to IO read / write operations during application use.

[0083] In this embodiment, coarse-grained segmentation of IO addresses is achieved by determining the set of IO address candidates that meet the aggregation validity criteria from multiple IO address candidate sets as the effective IO address candidate set. Furthermore, fine-grained segmentation of IO addresses is achieved by further segmenting the effective IO address candidate sets based on the gaps between adjacent IO addresses and a first span threshold. Additionally, the set of IO addresses that meet the set filtering criteria from the multiple IO address sets is determined as the target IO address set, achieving quality filtering of the IO address sets. By merging multiple IO requests accessing multiple IO addresses into a single aggregated IO request—that is, replacing multiple fragmented IO requests with a single IO request—the fixed overhead of IO is amortized, system smoothness is improved, and users are guaranteed not to experience lag due to IO read / write operations during application usage.

[0084] In an optional specific embodiment, step 104 merges multiple IO requests accessing the same target IO address set into an aggregated IO request for processing, specifically including: Multiple I / O requests that access the same set of target I / O addresses are merged into an aggregated I / O request; Based on the aggregated I / O request, the corresponding data is preloaded into volatile memory; If the data corresponding to the aggregated I / O request resides in the volatile memory for more than a first duration, the data corresponding to the aggregated I / O request will be transferred from the volatile memory to non-volatile memory. If the data corresponding to the aggregated I / O request resides in the non-volatile memory for more than a second duration, the data corresponding to the aggregated I / O request will be transferred from the non-volatile memory to the flash memory.

[0085] Specifically, based on the hotspot address statistics algorithm, the top applications used by users within a week occupied a total of 107GB of flash memory space. Of this, only 7GB was read / written via I / O, meaning that hot data in flash memory accounted for only 6.7% of the total data. This portion of hot data in flash memory does not offer any speed or bandwidth advantage compared to the entire storage area. Therefore, a warm data memory buffer (i.e., non-volatile memory) can be added between Double Data Rate (DDR) memory and Universal Flash Storage (UFS). Hotspot I / O data from the target I / O address set can be placed in the warm data memory buffer, which is constructed of non-volatile memory hardware to ensure that data is not lost in the event of an electronic device restart or power failure.

[0086] The specific implementation process can be as follows: Multiple I / O requests accessing the same target I / O address set are merged into a single aggregated I / O request. Based on the aggregated I / O request, the corresponding data is preloaded into volatile memory (e.g., 12GB). If the data resides in volatile memory for longer than a first duration, it is transferred from volatile memory to non-volatile memory (e.g., 32GB). Since a large number of I / O operations on the main thread impact performance, storing the data in non-volatile memory can eliminate stuttering and improve the smoothness of application startup and scrolling. If the data resides in non-volatile memory for longer than a second duration, it is transferred from non-volatile memory to flash memory (e.g., 512GB).

[0087] It should be noted that the first and second durations can be set as needed.

[0088] In the above embodiments, for scenarios with long application startup time and lag during scrolling, since the main thread IO data volume for frame refreshing is large, the solution in this embodiment can merge multiple IO requests accessing the same target IO address set into a single aggregated IO request to eliminate lag caused by IO read and write operations and ensure smooth frame refreshing.

[0089] In summary, the embodiments of this application utilize a multi-level segmentation algorithm based on physical address gap characteristics to intelligently filter out a target I / O address set with a controllable range within the address set. Furthermore, multiple I / O requests accessing the same target I / O address set are merged into a single aggregated I / O request, thereby ensuring that the optimization measures bring performance improvements rather than introducing additional overhead. This not only saves on UFS device hardware costs but also improves system smoothness.

[0090] The input / output I / O address aggregation method provided in this application can be executed by an input / output I / O address aggregation device. This application uses an input / output I / O address aggregation device executing the method as an example to illustrate the input / output I / O address aggregation device provided in this application.

[0091] like Figure 3 As shown in the illustration, this application embodiment also provides an input / output I / O address aggregation device 300, specifically including: The determination module 301 is used to determine the set of IO address candidates that meet the aggregation validity condition from multiple IO address candidate sets as the valid IO address candidate set; The segmentation module 302 is used to segment the effective IO address candidate set based on the gap between adjacent IO addresses in each effective IO address candidate set or based on the gap between adjacent IO addresses in each effective IO address candidate set and a first span threshold, to obtain multiple IO address sets. The determining module 301 is further configured to determine the set of IO addresses that meets the set filtering conditions among the plurality of IO address sets as the target IO address set; The processing module 303 is used to merge multiple IO requests that access the same target IO address set into an aggregated IO request for processing.

[0092] Optionally, the device further includes: The sorting module is used to determine the access range of IO addresses and sort the IO addresses within the access range according to their address values ​​to obtain the sorted IO addresses. The determining module is also used to traverse the sorted IO addresses and determine the gap as a dividing point when the gap between adjacent IO addresses is greater than or equal to a first gap threshold. The segmentation module is further configured to segment the sorted IO addresses into multiple IO address candidate sets based on the segmentation points.

[0093] Optionally, the aggregation validity conditions include: The first IO address span between the minimum IO address and the maximum IO address in the IO address candidate set is greater than or equal to the second span threshold. The number of IO addresses in the IO address candidate set is greater than or equal to the number threshold; The median of the gaps determined based on the gaps between any two adjacent IO addresses in the candidate IO address set is less than the median threshold.

[0094] Optionally, when the segmentation module 302 segments the effective IO address candidate set based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets, it is specifically used for: When the gap between adjacent I / O addresses in the effective I / O address candidate set is greater than or equal to the corresponding second gap threshold, the gap is determined as a dividing point. The second gap threshold is determined based on the median of the gaps in the effective I / O address candidate set, and the median of the gaps is determined based on the gap between every two adjacent I / O addresses in the effective I / O address candidate set. The set of valid IO address candidates is divided based on the dividing point to obtain multiple IO address sets.

[0095] Optionally, when the segmentation module 302 segments the set of valid IO address candidates based on the segmentation point to obtain multiple IO address sets, it is specifically used for: The set of valid I / O address candidates is divided based on the dividing point to obtain multiple subsets of valid I / O address candidates; The subset of valid IO address candidates whose second IO address span between the minimum and maximum IO address is greater than the first span threshold is divided according to the second span threshold to obtain multiple IO address sets.

[0096] Optionally, the set filtering conditions include: The IO address density of the IO address set is greater than or equal to a density threshold, wherein the IO address density is obtained based on the number of IO addresses in the IO address set and a third IO address span between the minimum and maximum IO addresses in the IO address set.

[0097] Optionally, when the processing module 303 merges multiple IO requests accessing the same target IO address set into an aggregated IO request for processing, it is specifically used for: Multiple I / O requests that access the same set of target I / O addresses are merged into an aggregated I / O request; Based on the aggregated I / O request, the corresponding data is preloaded into volatile memory; If the data corresponding to the aggregated I / O request resides in the volatile memory for more than a first duration, the data corresponding to the aggregated I / O request will be transferred from the volatile memory to non-volatile memory. If the data corresponding to the aggregated I / O request resides in the non-volatile memory for more than a second duration, the data corresponding to the aggregated I / O request will be transferred from the non-volatile memory to the flash memory.

[0098] The input / output I / O address aggregation device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the scope of the device.

[0099] The input / output I / O address aggregation device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit it.

[0100] The input / output I / O address aggregation device provided in this application embodiment can achieve Figures 1 to 2 The various processes implemented in the method implementation examples will not be described again here to avoid repetition.

[0101] Optionally, such as Figure 4 As shown, this application embodiment also provides an electronic device 900, including a processor 901 and a memory 902. The memory 902 stores a program or instructions that can run on the processor 901. When the program or instructions are executed by the processor 901, they implement the various steps of the above-described method embodiment for aggregating input / output I / O addresses and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0102] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0103] Figure 5 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0104] The electronic device 1000 includes, but is not limited to, components such as: radio frequency unit 1001, network module 1002, audio output unit 1003, input unit 1004, sensor 1005, display unit 1006, user input unit 1007, interface unit 1008, memory 1009, and processor 1010.

[0105] Those skilled in the art will understand that the electronic device 1000 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1010 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 5 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0106] The processor 1010 is used to determine the set of IO address candidates that meet the aggregation validity condition from multiple IO address candidate sets as the valid IO address candidate set; The effective IO address candidate set is divided based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets. The set of IO addresses that meets the set filtering conditions among the plurality of IO address sets is determined as the target IO address set; Multiple I / O requests that access the same target I / O address set are merged into an aggregated I / O request for processing.

[0107] Optionally, before determining the set of IO address candidates that satisfy the aggregation validity condition from multiple IO address candidate sets as a valid IO address candidate set, the processor 1010 is further configured to: Determine the access range of IO addresses, and sort the IO addresses within the access range according to their address values ​​to obtain the sorted IO addresses; Traverse the sorted IO addresses, and determine the gap as a dividing point when the gap between adjacent IO addresses is greater than or equal to a first gap threshold; The sorted IO addresses are divided into multiple IO address candidate sets based on the splitting points.

[0108] Optionally, the aggregation validity condition includes at least one of the following: The first IO address span between the minimum IO address and the maximum IO address in the IO address candidate set is greater than or equal to the second span threshold. The number of IO addresses in the IO address candidate set is greater than or equal to the number threshold; The median of the gaps determined based on the gaps between any two adjacent IO addresses in the candidate IO address set is less than the median threshold.

[0109] Optionally, when the processor 1010 divides the effective IO address candidate set based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets, it is specifically used for: When the gap between adjacent I / O addresses in the effective I / O address candidate set is greater than or equal to the corresponding second gap threshold, the gap is determined as a dividing point. The second gap threshold is determined based on the median of the gaps in the effective I / O address candidate set, and the median of the gaps is determined based on the gap between every two adjacent I / O addresses in the effective I / O address candidate set. The set of valid IO address candidates is divided based on the dividing point to obtain multiple IO address sets.

[0110] Optionally, when the processor 1010 divides the set of valid I / O address candidates based on the dividing point to obtain multiple I / O address sets, it specifically performs the following: The set of valid I / O address candidates is divided based on the dividing point to obtain multiple subsets of valid I / O address candidates; The subset of valid IO address candidates whose second IO address span between the minimum and maximum IO address is greater than the first span threshold is divided according to the second span threshold to obtain multiple IO address sets.

[0111] Optionally, the set filtering conditions include: The IO address density of the IO address set is greater than or equal to a density threshold, wherein the IO address density is obtained based on the number of IO addresses in the IO address set and a third IO address span between the minimum and maximum IO addresses in the IO address set.

[0112] Optionally, when the processor 1010 merges multiple IO requests accessing the same target IO address set into an aggregated IO request for processing, it specifically performs the following: Multiple I / O requests that access the same set of target I / O addresses are merged into an aggregated I / O request; Based on the aggregated I / O request, the corresponding data is preloaded into volatile memory; If the data corresponding to the aggregated I / O request resides in the volatile memory for more than a first duration, the data corresponding to the aggregated I / O request will be transferred from the volatile memory to non-volatile memory. If the data corresponding to the aggregated I / O request resides in the non-volatile memory for more than a second duration, the data corresponding to the aggregated I / O request will be transferred from the non-volatile memory to the flash memory.

[0113] It should be understood that, in this embodiment, the input unit 1004 may include a graphics processing unit (GPU) 10041 and a microphone 10042. The GPU 10041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1006 may include a display panel 10061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 1007 includes at least one of a touch panel 10071 and other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here.

[0114] The memory 1009 can be used to store software programs and various data. The memory 1009 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1009 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1009 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0115] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor 1010.

[0116] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described method embodiment for aggregating input / output I / O addresses and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0117] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0118] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described method embodiment for aggregating input / output I / O addresses, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0119] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0120] This application provides a computer program product stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-described method embodiment for aggregating input / output I / O addresses, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0122] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0123] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A method for aggregating input / output I / O addresses, characterized in that, include: The set of IO address candidates that meets the aggregation validity condition among multiple IO address candidate sets is determined as the valid IO address candidate set; The effective IO address candidate set is divided based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets. The set of IO addresses that meets the set filtering conditions among the plurality of IO address sets is determined as the target IO address set; Multiple I / O requests that access the same target I / O address set are merged into an aggregated I / O request for processing.

2. The method according to claim 1, characterized in that, Before determining the set of IO address candidates that meet the aggregation validity condition from multiple IO address candidate sets as the valid IO address candidate set, the method further includes: Determine the access range of IO addresses, and sort the IO addresses within the access range according to their address values ​​to obtain the sorted IO addresses; Traverse the sorted IO addresses, and determine the gap as a dividing point when the gap between adjacent IO addresses is greater than or equal to a first gap threshold; The sorted IO addresses are divided into multiple IO address candidate sets based on the splitting points.

3. The method according to claim 1 or 2, characterized in that, The aggregation validity conditions include at least one of the following: The first IO address span between the minimum IO address and the maximum IO address in the IO address candidate set is greater than or equal to the second span threshold. The number of IO addresses in the IO address candidate set is greater than or equal to the number threshold; The median of the gaps determined based on the gaps between any two adjacent IO addresses in the candidate IO address set is less than the median threshold.

4. The method according to claim 1, characterized in that, The effective IO address candidate set is segmented based on the gap between adjacent IO addresses in each of the effective IO address candidate sets, or based on the gap between adjacent IO addresses in each of the effective IO address candidate sets and a first span threshold, to obtain multiple IO address sets, including: When the gap between adjacent I / O addresses in the effective I / O address candidate set is greater than or equal to the corresponding second gap threshold, the gap is determined as a dividing point. The second gap threshold is determined based on the median of the gaps in the effective I / O address candidate set, and the median of the gaps is determined based on the gap between every two adjacent I / O addresses in the effective I / O address candidate set. The set of valid IO address candidates is divided based on the dividing point to obtain multiple IO address sets.

5. The method according to claim 4, characterized in that, The process of segmenting the candidate set of valid I / O addresses based on the segmentation point yields multiple sets of I / O addresses, including: The set of valid I / O address candidates is divided based on the dividing point to obtain multiple subsets of valid I / O address candidates; The subset of valid IO address candidates whose second IO address span between the minimum and maximum IO address is greater than the first span threshold is divided according to the first span threshold to obtain multiple IO address sets.

6. The method according to claim 1, 4, or 5, characterized in that, The set filtering conditions include: The IO address density of the IO address set is greater than or equal to a density threshold, wherein the IO address density is obtained based on the number of IO addresses in the IO address set and a third IO address span between the minimum and maximum IO addresses in the IO address set.

7. The method according to claim 1, characterized in that, The step of merging multiple IO requests accessing the same target IO address set into an aggregated IO request for processing includes: Multiple I / O requests that access the same set of target I / O addresses are merged into an aggregated I / O request; Based on the aggregated I / O request, the corresponding data is preloaded into volatile memory; If the data corresponding to the aggregated I / O request resides in the volatile memory for more than a first duration, the data corresponding to the aggregated I / O request will be transferred from the volatile memory to non-volatile memory. If the data corresponding to the aggregated I / O request resides in the non-volatile memory for more than a second duration, the data corresponding to the aggregated I / O request will be transferred from the non-volatile memory to the flash memory.

8. An input / output I / O address aggregation device, characterized in that, include: The determination module is used to determine the set of IO address candidates that meet the aggregation validity conditions from multiple IO address candidate sets as the valid IO address candidate set; The segmentation module is used to segment the effective IO address candidate set based on the gap between adjacent IO addresses in each effective IO address candidate set or based on the gap between adjacent IO addresses in each effective IO address candidate set and a first span threshold, to obtain multiple IO address sets. The determining module is further configured to determine the set of IO addresses that meets the set filtering conditions among the plurality of IO address sets as the target IO address set; The processing module is used to merge multiple IO requests that access the same target IO address set into an aggregated IO request for processing.

9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that can run on the processor, the program or instructions being executed by the processor to implement the steps of the method for aggregating input / output I / O addresses as described in any one of claims 1-7.

10. A chip, characterized in that, The chip includes a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the steps of the input / output I / O address aggregation method as described in any one of claims 1-7.

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