Concurrent execution of software programs

Abstract

The invention relates to concurrent execution of software programs. Apparatuses, systems, and techniques for task pipeline virtualization for sequential tasks executed by simultaneous sequential kernels. In at least one embodiment, a processor includes one or more circuitry for causing a compiler to indicate one or more portions of one or more software programs to be executed concurrently by one or more processors.

Description

Technical Field

[0001] At least one embodiment relates to generating two or more GPU cores for sequentially executing sequential program tasks without external controller interference. At least one embodiment relates to constructing a "pipeline" structure that allows input data to be computed by two or more sequential cores without being derived from the pipeline. At least one embodiment relates to instructing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors. Background Technology

[0002] Computation of asynchronous (e.g., non-concurrent) kernels in a GPU requires kernel substantialization, processing, exporting output data, instantiating a second kernel, and importing input data. When such tasks are repeatedly executed, latency can occur due to kernel delays caused by the startup and shutdown processes. Asynchronous kernel execution methods can be improved. Attached Figure Description

[0003] Figure 1 An example architecture of a GPU kernel pipeline according to at least one embodiment is shown;

[0004] Figure 2 An example implementation of a task pipeline according to at least one embodiment is shown;

[0005] Figure 3 An example conversion from source code to a task pipeline according to at least one embodiment is shown;

[0006] Figure 4 An example pair of pipeline kernels that provide data to each other via a lock-free buffer memory is shown according to at least one embodiment;

[0007] Figure 5 An example pipeline kernel pair is shown that provides data to each other via a memory buffer using a synchronization completion notification, according to at least one embodiment;

[0008] Figure 6 An example process for the materialization and operation of a kernel pipeline according to at least one embodiment is shown;

[0009] Figure 7 An example execution pipeline operation for performing a kernel pipeline is shown according to at least one embodiment;

[0010] Figure 8 An example data center system according to at least one embodiment is shown;

[0011] Figure 9 A system-on-a-chip (SOC) according to at least one embodiment is shown;

[0012] Figure 10A A parallel processor according to at least one embodiment is shown;

[0013] Figure 10B A processing cluster according to at least one embodiment is shown;

[0014] Figure 10C A graphics multiprocessor according to at least one embodiment is shown;

[0015] Figure 11 An accelerator processor according to at least one embodiment is shown;

[0016] Figure 12A A central processing unit according to at least one embodiment is shown;

[0017] Figure 12B The illustration shows an embodiment according to at least one of the embodiments. Figure 12A The core of the central processing unit;

[0018] Figure 13 Another accelerator processor according to at least one embodiment is shown;

[0019] Figure 14 A neuromorphic processor according to at least one embodiment is shown;

[0020] Figure 15 A supercomputer according to at least one embodiment is shown;

[0021] Figure 16 Another accelerator processor according to at least one embodiment is shown;

[0022] Figure 17 Another processor according to at least one embodiment is shown;

[0023] Figure 18 Another accelerator processor according to at least one embodiment is shown;

[0024] Figure 19 A tensor processing unit according to at least one embodiment is shown;

[0025] Figure 20 A RISC-V compatible processor according to at least one embodiment is shown;

[0026] Figure 21A and Figure 21B A language processing unit according to at least one embodiment is shown;

[0027] Figure 22A software stack of a programming platform according to at least one embodiment is shown;

[0028] Figure 23 Software supported by a programming platform according to at least one embodiment is shown;

[0029] Figure 24 A method for using at least one embodiment is shown. Figure 23 Compiled code executed on the programming platform;

[0030] Figure 25 An example of an autonomous vehicle and its system architecture according to at least one embodiment is shown;

[0031] Figure 26A The inference and / or training logic according to at least one embodiment is illustrated;

[0032] Figure 26B The inference and / or training logic according to at least one embodiment is shown; and

[0033] Figure 26C Training and deployment of a neural network according to at least one embodiment are illustrated. Detailed Implementation

[0034] In at least one embodiment, the systems and methods implemented according to this disclosure are used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors.

[0035] In at least one embodiment, when multiple asynchronous sequential tasks are to be repeatedly executed by kernels on the processor (e.g., a repetitive loop of an image enhancement process performed frame by frame on a video, the process being executed in a specified order), a pipeline can be created to allow these kernels to run entirely under the processor's control, thus eliminating the need for an external controller during execution. In at least one embodiment, source code is provided (e.g., Figure 3 Source code 302), which contains instructions for creating a task pipeline (e.g., Figure 1 The pipeline pipeline 110 contains one or more pipeline object indicator (e.g., pipeline object 304) specifying parameters required for the entire pipeline process. These parameters include individual declarative tasks (e.g., portions of source code and / or input software programs) and / or indicator for such tasks, kernel requirements for the tasks (e.g., processor requirements, memory requirements, and / or other required parameters), input memory size for each task, memory output size for each task, and / or any other necessary parameters. In at least one embodiment, the compiler (e.g., ...) Figure 6The compiler 306 then parses the input parameters to generate instructions for each kernel, each memory buffer between kernels, and any other runtime requirements for pipeline operations, as part of the associated executable generated from the source code. In at least one embodiment, the pipeline can then be processed by a processor (e.g., Figure 3 and / or Figure 7 The processors 220, 320, and / or 702 in the system execute the assigned task indefinitely (e.g., said task is executed concurrently) until the controller issues a shutdown command, suspending processing and shutting down all kernels. In at least one embodiment, the kernel does not need to indicate infinite repetition itself. In at least one embodiment, the compiler modifies the task parameters to ensure that its corresponding kernel infinitely repeats the assigned task. In at least one embodiment, in addition to materialization and shutdown, the controller (e.g., ... Figure 1 The controller 102) will not interfere with the execution of the kernel and / or buffer within the executing pipeline unless execution is shut down. In at least one embodiment, input is provided via an API (e.g., Figure 1 The inputs 114 and / or outputs 116), and the output is also provided via the API. In at least one embodiment, the indicator (e.g., Figure 1 The indicator 118) is used to provide the controller with an indication of the operational metric for the pipeline being executed. In at least one embodiment, a memory buffer within local memory (e.g., GPU VRAM and / or other designated local memory) is used to provide the output of an earlier kernel in the pipeline to the next kernel in the pipeline. In at least one embodiment, when the pipeline goes offline, resources are released from exclusive use, but the pipeline retains exclusive control over its resources and executes indefinitely until then. In at least one embodiment, if no new input is provided, components of the pipeline and / or the entire pipeline may temporarily go into hibernation. In at least one embodiment, in this case, the components come back online to periodically check for new input until the pipeline is completely shut down.

[0036] In at least one embodiment, as described above, this pipeline presents the concept of a fully programmable, processor-native, custom pipeline where different parts of the processor can perform different tasks within the pipeline, but overall, the pipeline exhibits low latency and high throughput. In at least one embodiment, no other prior processor programming models or libraries are designed to implement pipelines with these properties. In at least one embodiment, such pipelines leverage data parallelism within a single task and task parallelism across the entire pipeline by running different tasks in non-overlapping subprocessor assignments, working on the exclusive inputs and / or outputs of the assignments. In at least one embodiment, because such pipelines can operate efficiently on the processor and are unaffected by operating system-level tasks, interrupts, and controller-related interrupts, the pipeline represents a large-scale, highly parallel, and real-time application. In at least one embodiment, such a large-scale, customizable, and timing-accurate pipeline was previously impossible. In at least one embodiment, this pipeline provides a specialized solution for real-time data streaming data processing applications requiring extremely low latency and high throughput (including hard real-time constraints). In at least one embodiment, the pipeline enhances processor optimization and / or utilization by strategically distributing pipeline workloads among processors, excluding controller commands from the pipeline itself, and isolating it from potential associated bottlenecks.

[0037] Various techniques have been described in the preceding and following sections. For ease of explanation, specific configurations and details have been elaborated to provide a comprehensive understanding of the possible ways to implement these techniques. However, it is also apparent that the techniques described below can be practiced in different configurations without specific details. Furthermore, to avoid obscuring the described techniques, well-known features may be omitted or simplified.

[0038] In at least one embodiment, as used in any implementation described herein, unless the context explicitly states otherwise or otherwise specifies otherwise, the term "module" and nominalized verbs refer to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, while "hardware" as used in any implementation described herein may, for example, individually or in any combination, include hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry. In at least one embodiment, a module may be embodied, either wholly or individually, as circuitry forming part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), etc.

[0039] In at least one embodiment, a system such as System 100, System 200, System 300, System 400, System 500, and / or System 600 includes a collection of one or more hardware and / or software computing resources with instructions that, when executed, perform one or more communication processes, such as those described herein. In at least one embodiment, System 100, System 200, System 300, System 400, System 500, and / or System 600 includes one or more software programs, one or more application programs, and / or variations thereof executable on computer hardware. In at least one embodiment, one or more processes of System 100, System 200, System 300, System 400, System 500, and / or System 600 are executed by any suitable processing system or unit such as those described below (e.g., Graphics Processing Unit (GPU), General Purpose GPU (GPGPU), Parallel Processing Unit (PPU), Central Processing Unit (CPU), Data Processing Unit (DPU)) and in any suitable manner (including sequential, parallel, and / or variations thereof). In at least one embodiment, systems 100, 200, 300, 400, 500, and / or 600 use machine learning training frameworks (such as PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein, such that a compiler instructs one or more portions of one or more software programs to be executed concurrently by one or more processors. In at least one embodiment, as an example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that also includes at least a GPU (e.g., an AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using GAN loss).

[0040] Figure 1An example 100 system architecture for a GPU kernel pipeline is illustrated according to at least one embodiment. In at least one embodiment, example 100 includes one or more controllers 102, memory 108, a task pipeline 110, a load pipeline 112, inputs 114, outputs 116, and / or indicators 118. In at least one embodiment, the task pipeline 110 includes one or more task kernels 104A-C (e.g., task kernel 104) and / or one or more buffers 106A and / or 106B (e.g., buffer 106). In at least one embodiment, example 100 executes kernel pipeline procedures (e.g., ... Figure 6 Part or all of the process in 600).

[0041] In at least one embodiment, the processor uses controller 102 to indicate information, such as instructing one or more processors (e.g., CPU, GPU, GPGPU, and / or any other specified processing hardware) to execute one or more control software programs (e.g., GPU drivers and / or other specified control software) and / or to control one or more processors to initiate and / or control the control software itself of one or more task pipelines 110. In at least one embodiment, controller 102 executes task kernel 104, buffer 106, and / or any other constructs and / or specified materializations required to execute task pipeline 110. In at least one embodiment, controller 102 is a processor separate from the processor executing task pipeline 110. In at least one embodiment, controller 102 is software executed separately from task pipeline 110. In at least one embodiment, controller 102 receives indicator 118 as input. In at least one embodiment, controller 102 may dematerialize task pipeline 110, executing a shutdown procedure in response to indicator 118 and / or any other input. In at least one embodiment, once materialized, controller 102 does not directly control task pipeline 110, nor does it directly provide input to task pipeline 110, unless a shutdown operation is performed.

[0042] In at least one embodiment, the processor uses system memory to indicate information, such as information indicating the execution of one or more memory allocations outside of processor internal memory (e.g., GPU VRAM and / or other internal memory specifications). In at least one embodiment, system memory provides input data to the first task core 104 via input 114. In at least one embodiment, memory 108 receives output data from the last task core 104. In at least one embodiment, memory 108 executes one or more application programming interfaces (e.g., APIs) to provide data to one or more task pipelines 110 and / or receive data from one or more task pipelines 110.

[0043] In at least one embodiment, the processor uses task pipeline 110 to indicate information, such as information indicating one or more asynchronous execution kernel families to be executed indefinitely until directly shut down by controller 102, each kernel family separated by a memory buffer to allow direct data provision without external input. In at least one embodiment, the task pipeline executes a series of two or more tasks on input data. In at least one embodiment, the task pipeline is materialized as a processor kernel by controller 102. In at least one embodiment, task pipeline 110 receives input from memory 108 and provides output to memory 108. In at least one embodiment, task pipeline 110 may provide indicator 118 as output to controller 102. In at least one embodiment, task pipeline 110 may be shut down at regular intervals without new input, maintaining the stability of kernel control without using power. In at least one embodiment, in this state, task pipeline 110 may periodically resume operation to check for new input.

[0044] In at least one embodiment, the processor uses task kernels 104A-104C (e.g., task kernel 104) to indicate information, such as information instructing one or more processors (e.g., streaming multiprocessors (SM), threads, and / or any other descriptors of the processing hardware) to execute a computational task. In at least one embodiment, task kernel 104 is materialized as part of task pipeline 110 for performing computational processes. In at least one embodiment, each successive task kernel 104 sequentially performs a task on data provided by the preceding task kernel 104. In at least one embodiment, the task kernel receives input via buffer 106. In at least one embodiment, the first task kernel 104 receives input from memory 108. In at least one embodiment, the last task kernel 104 provides the final computational output to memory 108. In at least one embodiment, if no new data is provided, task kernel 104 may go into hibernation. In at least one embodiment, in this case, task kernel 104 is periodically reactivated to check for new input data. In at least one embodiment, task kernel 104 remains materialized until explicitly shut down by controller 102.

[0045] In at least one embodiment, the processor uses buffers 106A and / or 106B (e.g., buffer 106) to indicate information, such as information indicating one or more portions of internal processor memory (e.g., GPU VRAM and / or any other designation of internal processor memory) used as a buffer between two task cores 104. In at least one embodiment, buffer 106 is materialized by controller 102 within task pipeline 110 along with task cores 104. In at least one embodiment, buffer 106 is either fully asynchronous (e.g., a four-slot lockless buffer, where some data may be lost if writes are faster than reads) or synchronous (e.g., a circular buffer, where data cannot be written while being read, and cannot be read while being written). In at least one embodiment, buffer 106 has a variable size based on indications provided by controller 102.

[0046] In at least one embodiment, the processor uses the load pipeline 112 to indicate information, such as one or more indications for starting the task pipeline 110. In at least one embodiment, the load pipeline 112 includes one or more indications for starting the pipeline 112, one or more indications of the task to be executed by the task kernel 104, and parameters of the task (e.g., SM requirements, input memory requirements, output memory requirements, and / or any other requirements for the materialization of the task kernel 104), one or more indications of buffer characteristics between the tasks (e.g., memory capacity, synchronization, buffer type, and / or any other parameters required for the materialization of buffer 106), and / or any other information required to create the task pipeline 112. In at least one embodiment, the load pipeline is executed via an application programming interface (e.g., an API), such as via pipeline operation 702 (… Figure 8 ).

[0047] In at least one embodiment, the processor uses input 114 and / or output 116 to indicate information, such as information indicating one or more data points to be input to or output from task pipeline 110, respectively. In at least one embodiment, input 114 and / or output 116 may be executed via one or more APIs (e.g., GPUDirect RMA and / or any other API capable of transferring data to internal processor memory). In at least one embodiment, input 114 and / or output 116 are respectively derived from or loaded into memory 108.

[0048] In at least one embodiment, the processor uses indicator 118 to indicate information, such as one or more operating parameters, outputs, and / or any other information required by the controller 102 from the task pipeline 110. In at least one embodiment, indicator 118 is provided to the controller 102 to indicate operating status and / or other information related to the task pipeline 110. In at least one embodiment, indicator 118 may include one or more indications for shutting down the task pipeline 110. In at least one embodiment, the indicator may include data from memory 108.

[0049] In at least one embodiment, system 100 includes one or more processors for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 100 is Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 100 performs... Figure 1-7 The processes shown herein include one or more procedures, such as causing a compiler to instruct one or more portions of a software program to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein. In at least one embodiment, system 100 performs... Figure 8-2 The procedures shown in 6, such as causing the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein.

[0050] Figure 2An example 200 of a task pipeline according to at least one embodiment is illustrated. In at least one embodiment, example 200 includes one or more controllers 202, cores 204A-204B (e.g., core 204), memory 208, task pipeline 210, and / or inputs 214A. In at least one embodiment, task pipeline 210 includes one or more processors 220A-220C (e.g., processor 220), inputs 214B and / or 214C (input 214), outputs 216A-216C (output 216), and / or memory 206A and / or 206B (memory 206). In at least one embodiment, processor 220 includes one or more threads 222A-222C (e.g., thread 222). In at least one embodiment, controller 202, memory 208, task pipeline 210, and / or inputs 214A are combined. Figure 1 The controller 102, memory 108, task pipeline 110, and / or input 114 are described herein, and are fully described without further explanation. In at least one embodiment, Example 200 executes a kernel pipeline procedure (e.g., Figure 6 The process 600) in whole or in part.

[0051] In at least one embodiment, the processor uses kernel 204 to indicate information, such as indicating the definition of one or more tasks (e.g., Figure 1 The information for creating one or more kernels (task 104) as part of task pipeline 210 will be executed by processor 220. In at least one embodiment, kernel 204 will be executed by threads 222 within processor 220, which are provided by controller 202 during the materialization of task pipeline 210.

[0052] In at least one embodiment, the processor uses input 214 and / or output 216 to indicate information, such as information indicating that one or more data points are being written to and / or read from memory 206. In at least one embodiment, input 214 is data provided to processor 220 via memory 206 to perform thread 222 operations. In at least one embodiment, output 216 is written to memory 206 and / or memory 208 via processor 220 after thread 222 processing is complete. In at least one embodiment, input 214 and / or output 216 is one or more data points in software.

[0053] In at least one embodiment, the processor uses memory 206 to indicate information, such as information indicating one or more memory buffers that allow data transfer between processors 220. In at least one embodiment, memory 206 is separate from memory 208. In at least one embodiment, memory 206 is one or more systems that transfer data via shared memory (e.g., GPU VRAM and / or other designations of internal system memory) to allow one task to write to the memory and allow a second task to read from the memory as needed. In at least one embodiment, memory 206 is data storage hardware partitioned for use by two sequential processors 220.

[0054] In at least one embodiment, the processor uses processor 220 to indicate information, such as instructions to execute a specified thread 222 to execute one or more processors (e.g., SM and / or other processor designations) associated with core 204. In at least one embodiment, processor 220 is provided with computational input via input 214. In at least one embodiment, processor 220 provides computational output via output 216. In at least one embodiment, processor 220 remains materialized until task pipeline 210 is completely dissolution. In at least one embodiment, processor 220 executes a specified task of task pipeline 210.

[0055] In at least one embodiment, the processor uses thread 222 to indicate information, such as information indicating one or more software threads to be used by processor 220 to execute associated kernel 204. In at least one embodiment, as part of task pipeline 210, thread 222 uses processing resources to execute a specified task (e.g., task 104).

[0056] In at least one embodiment, system 200 includes one or more processors for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 200 is Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is used to instruct a compiler to direct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 200 performs... Figure 1-7The processes shown herein include one or more procedures, such as causing a compiler to instruct one or more portions of a software program to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein. In at least one embodiment, system 200 performs... Figure 8-2 One or more processes shown in 6, such as causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein.

[0057] Figure 3 Example 300 of source code to a task pipeline is illustrated according to at least one embodiment. In at least one embodiment, example 300 includes one or more source codes 302, pipeline objects 304, compiler 306, pipeline parameters 308 (e.g., processor assignment 308A, buffer instructions 308B, and / or kernel instructions 308C), and / or processor 320. In at least one embodiment, processor 320 is combined with processor 220 ( Figure 2 The description is sufficient to fully define the terms without further elaboration.

[0058] In at least one embodiment, the processor uses source code 302 to indicate information, such as information indicating one or more data points representing code (e.g., CUDA code and / or other low-level code) input to one or more compilers 306 to generate machine code. In at least one embodiment, source code 302 includes one or more references, calls, and / or other indications to one or more pipeline objects 304. In at least one embodiment, source code 302 may include other data points unrelated to the creation of the task pipeline. In at least one embodiment, source code 302 is data stored in memory.

[0059] In at least one embodiment, the processor uses pipeline object 304 to indicate information, such as indications that something will be transformed and / or computed to generate a task pipeline (e.g., Figure 1 The pipeline object (110) contains one or more code-constructed information about the data of the task pipeline. In at least one embodiment, the pipeline object includes one or more parameter descriptions of the task pipeline (e.g., each task in the pipeline, the CUDA tasks executed by each task, the number of SMs for each task, the input memory size for each task, the output memory size for each task, and / or any other parameters required to create the task pipeline). In at least one embodiment, the pipeline object 304 is input to the compiler 306 as part of the source code 302 to be converted into a task pipeline in an executable file generated by the compiler 306 and / or executed by the processor 320.

[0060] In at least one embodiment, the processor uses compiler 306 to indicate information, such as information indicating one or more procedures for compiling source code (e.g., source code 302) into machine-readable executable code. In at least one embodiment, compiler 306 includes methods for converting pipeline object 304 into a process capable of instantiating a task pipeline (e.g., ...). Figure 1 The executable file contains one or more functions of the task pipeline 110. In at least one embodiment, the compiler 306 takes an input pipeline object 304 and creates pipeline parameters 308 to provide to one or more operation processors (e.g., processor 320) for executing the indicated task pipeline.

[0061] In at least one embodiment, the processor uses pipeline parameter 308 to indicate information such as indicating processor assignments for one or more operating kernels, buffered instructions for one or more operating memory buffers, kernel instructions for one or more operating kernels, and / or task pipelines (e.g., Figure 1 Information on any other parameters required for the materialization and execution of the task pipeline 110. In at least one embodiment, pipeline parameters 308 are instructions generated by compiler 306 in one or more machine-readable executable files for materializing the task pipeline and executing tasks as part of said pipeline.

[0062] In at least one embodiment, system 300 includes one or more processors for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 300 is Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 300 performs... Figure 1-7 The processes shown herein include one or more procedures, such as causing a compiler to instruct one or more portions of a software program to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein. In at least one embodiment, system 300 performs... Figure 8-2 The procedures shown in 6, such as causing the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein.

[0063] Figure 4Example 400 of a pair of pipelined kernels according to at least one embodiment is shown, which provide data to each other via a lock-free buffer memory. In at least one embodiment, example 400 includes one or more task kernels 404A and / or 404B, a lock-free buffer 406, task A output 402, task B input 408, and / or new data check 410. In at least one embodiment, task kernels A and / or B are defined in relation to task kernel 104 and are fully defined without further description. In at least one embodiment, example 400 executes kernel pipeline procedures (e.g., Figure 6 The process of 600) is part or all of the process.

[0064] In at least one embodiment, the processor uses a lock-free buffer 406 (e.g., buffer 406) to indicate information, such as information indicating the use of one or more memory buffers of a protocol, wherein a producer task (e.g., task kernel 404A) and a consumer task (task kernel 404B) for the buffer will not read from and / or write to the same memory location at the same time. In at least one embodiment, the lock-free buffer 406 is one or more portions of internal processor memory used to allow task kernel 404A to write to said memory and to provide input data to task kernel 404B on reads. In at least one embodiment, a new data check 410 checks the lock-free buffer 406 at regular intervals to allow task kernel 404B to determine if new input is available. In at least one embodiment, the lock-free buffer 406 can be used as a buffer system when data loss in the output of task kernel 404A is acceptable. In at least one embodiment, for example, some data loss may be acceptable if the output of task kernel 404A is only important when task kernel 404B uses the most recent output.

[0065] In at least one embodiment, the processor uses task A output 402 and / or task B input 408 (e.g., data 408) to indicate information, such as information indicating that one or more data points are output by task kernel 404A to lock-free buffer 406 to allow task kernel 404B to access and use said data as input. In at least one embodiment, data 408 may include one or more signatures (e.g., including one or more data points indicating a unique designation for said data) to allow task kernel 404B to determine whether said data is new. In at least one embodiment, data 408 is read by task kernel 404B to be used as input data. In at least one embodiment, data 408 is overwritten by new data when task kernel 404A generates more output data.

[0066] In at least one embodiment, the processor uses new data check 410 to indicate information, such as information indicating one or more data read operations executed by task kernel 404B to read one or more data segments in unlock buffer 406 to determine whether the data stored in unlock buffer 406 is new data. In at least one embodiment, new data check 410 may check one or more indications of specific descriptors for data in unlock buffer 406, read all data in unlock buffer 406, or use some other combination to determine whether the data in unlock buffer 406 is new data.

[0067] In at least one embodiment, system 400 includes one or more processors for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 400 is Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 400 performs... Figure 1-7 The processes shown herein include one or more procedures, such as causing a compiler to instruct one or more portions of a software program to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein. In at least one embodiment, system 400 performs... Figure 8-2 One or more processes shown in 6, such as causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein.

[0068] Figure 5 Example 500 of a pair of pipelined kernels is shown, representing at least one embodiment. This pair of pipelined kernels provides data to each other via a memory buffer using synchronization completion notifications. In at least one embodiment, example 500 includes one or more task kernels 504A and / or 504B, a lock-free buffer 506, processor hardware 512, task A output 502, task B input 508, event notification 510, and / or kernel queue command 514. In at least one embodiment, task kernels 504A and / or 504B, lock-free buffer 506, task A output 502, and / or task B input 508 are respectively combined with task kernel 104 (… Figure 1 ), lock-free buffer 406 ( Figure 4 Task A output 402 ( Figure 4The description of task B input 408 is sufficient to fully define the task without further description. In at least one embodiment, example 500 executes a kernel pipeline procedure (e.g., Figure 6 The process 600) in whole or in part.

[0069] In at least one embodiment, the processor uses processor hardware 512 to indicate information, such as information indicating one or more hardware communication components for translating output event notification 510 into kernel queue command 514. In at least one embodiment, processor hardware 512 is any communication method between two materialized kernels (e.g., task kernels 504A and / or 504B) to allow task kernel 504A to notify task kernel 504B when new data is available, and / or to allow task kernel 504B to notify task kernel 504A that data saved to the lock-free buffer 506 has been fully read. In at least one embodiment, this communication prevents overwriting unread data, thereby preventing data loss.

[0070] In at least one embodiment, the processor uses event notification 510 and / or kernel queue commands (e.g., a proceed command 514) to indicate information, such as information for a consumer kernel (e.g., task kernel 504B) in a task pipeline, to understand when a producer kernel (e.g., task kernel 504A) has fully provided its output to an unlock-free buffer for input to task kernel 504B. In at least one embodiment, the proceed command 514 allows the producer kernel to avoid overwriting data before the consumer kernel reads previous data, thereby preventing potential data loss. In at least one embodiment, the proceed command is transferred between the two kernels via processor hardware 512.

[0071] In at least one embodiment, system 500 includes one or more processors for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 500 is Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, system 500 performs... Figure 1-7The processes shown herein include one or more procedures, such as causing a compiler to instruct one or more portions of a software program to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein. In at least one embodiment, system 500 performs... Figure 8-2 One or more processes shown in 6, such as causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, and / or otherwise performing the operations described herein.

[0072] Figure 6 Example 600 procedures for the materialization and operation of a kernel pipeline are illustrated according to at least one embodiment. In at least one embodiment, one or more processors initiate procedure 602 (600) when procedure 600 is invoked to perform the materialization and execution of the task kernel pipeline. In at least one embodiment, the received input uses one or more data formats, such that procedure 600 can then iterate to the next feature (e.g., to indicate that a first feature 602 should begin). In at least one embodiment, one or more processors use procedure 600 to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors. In at least one embodiment, procedure 600 begins at step 602.

[0073] In at least one embodiment, process 600 includes, in step 604, loading a task process for each task in the task pipeline to be materialized. For example, in at least one embodiment, if the pipeline is to perform resolution enhancement on one or more images, the first task might be to decompile image code into numeric strings, the second task might be to perform deblurring computation, and the third task might be to recompile back into image code. In at least one embodiment, an integer count of the required tasks and a definition of the computations required for each task are generated.

[0074] In at least one embodiment, process 600 includes step 606: determining whether a kernel 606 has been provided. In at least one embodiment, if kernel parameters (e.g., ...) are provided for each task... Figure 3 If the pipeline parameters (308) are not provided for each task, then process 600 continues to step 610. In at least one embodiment, if no kernel parameters are provided for each task, then process 600 continues to step 608.

[0075] In at least one embodiment, process 600 includes step 608: splitting the input process to be executed by the pipeline into two or more sequential tasks, which will be executed separately by a kernel within the pipeline. In at least one embodiment, such tasks may involve calculating kernel parameters, such as processor requirements, memory input requirements, memory output requirements, and / or other parameters related to the operation of the kernel.

[0076] In at least one embodiment, process 600 includes, in step 610: loading a kernel and a buffer; providing parameters for the buffer and kernel to allow a series of sequential kernels and buffers to be materialized, thereby creating a task pipeline. In at least one embodiment, the pipeline is then brought online to permanently execute a specified task until it is taken offline.

[0077] In at least one embodiment, process 600 includes step 612: performing pipeline tasks, receiving input, performing computations, and permanently providing output until the entire pipeline is offline. In at least one embodiment, the execution of the pipeline may involve temporarily taking itself offline to conserve power when no new input is available for computations to be performed on components within the pipeline and / or the entire pipeline.

[0078] In at least one embodiment, process 600 includes in step 614 determining whether a materialized task pipeline has been indicated to be offline and / or not materialized. In at least one embodiment, if an indication has been issued, process 600 may proceed to step 616. In at least one embodiment, if no such indication has been issued, process 600 may return to step 612.

[0079] In at least one embodiment, process 600 includes step 616: unloading the kernel and buffers, removing instructions for exclusive control, and canceling the materialization of the associated task pipeline. In at least one embodiment, the unloading includes flushing specified memory and / or unrestricting specified processing resources.

[0080] In at least one embodiment, process 600 may end or otherwise terminate at step 618. In at least one embodiment, process 600 may then terminate if process 600 has completed the materialization and execution of the task pipeline, indicates completion of the materialization and execution of the task pipeline, and / or otherwise returns an error.

[0081] In at least one embodiment, a processor uses process 600, comprising one or more steps, to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors and / or otherwise perform the operations described herein. In at least one embodiment, for example, a machine-readable medium storing a set of instructions that, if executed by one or more processors, cause the one or more processors to instruct a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors and / or otherwise perform the operations described herein. In at least one embodiment, process 600 includes… Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is used to instruct a compiler to perform one or more portions of one or more software programs that will be executed concurrently by one or more processors and / or otherwise perform the operations described herein. In at least one embodiment, process 600 is performed by... Figure 1-7 The one or more systems shown herein execute, such as those used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors and / or otherwise perform the operations described herein. In at least one embodiment, process 600 is performed by Figure 8-2 The one or more systems shown in 6 execute, such as those used to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors and / or otherwise perform the operations described herein.

[0082] Figure 7 A pipeline for performing tasks (e.g., according to at least one embodiment) is shown. Figure 1 Example 700 of the materialization and / or execution of the task pipeline 110) performs pipeline operations (“Operation 700”). In at least one embodiment, Operation 700 is one or more computational operations that, if executed, execute an application programming interface (API) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, as described above. Figure 1-7 As stated above.

[0083] In at least one embodiment, performing pipeline operation 702 (“Call 702”) is a function call to be executed by one or more software programs, such as a kernel to be executed by one or more parallel processing units (PPUs) (such as graphics processing units (GPUs)). In at least one embodiment, Call 702 is a call to instructions to cause one or more processors to perform analysis and / or generation of pipeline runtime 712, indicator 714, for pipeline response 704 (“Response 704”). In at least one embodiment, Call 702 is a call to an API to cause one or more processors to generate one or more analyses / assignments 712, 714 for Response 704.

[0084] In at least one embodiment, call 702, when invoked, receives one or more parameters 706, 708, 710 indicating information about kernel tasks, buffer locations, and / or memory locations, thereby providing parameters for the task pipeline to be created. In at least one embodiment, call 702, when invoked, receives one or more parameters 706, 708, 710 indicating information about potential pipeline generation.

[0085] In at least one embodiment, call 702 receives parameters 706, 708, and 710 as input, including kernel 706, buffer location 708, and / or memory location 710. In at least one embodiment, the parameters are described in conjunction with the corresponding components in the previous figures (e.g., kernel instruction 308C, respectively). Figure 3 ), Location of memory 206 ( Figure 2 ) and / or the location of memory 108 ( Figure 1 In at least one embodiment, the components in the figure can be fully defined without further description.

[0086] In at least one embodiment, response 704 generates parameters 712, 714, including one or more pipeline runtimes 712, as output. In at least one embodiment, pipeline runtime 712 is one or more running task pipelines (e.g., Figure 1 The task pipeline 110) and / or indications of operation or failure of running one or more task pipelines. In at least one embodiment, if a function call is to execute call 702, then pipeline runtime 712 is data output in response to the function call. In at least one embodiment, the generation of pipeline runtime 712 takes into account kernel 706, buffer location 708, memory location 710, and / or other parameters required for the materialization of the task pipeline.

[0087] In at least one embodiment, response 704 generates parameters 712, 714 as output, including one or more indicators 714. In at least one embodiment, indicator 714 is one or more indications of successful pipeline materialization, indicators of pipeline runtime metrics, pipeline output, indicators of failed pipeline materialization, and / or other indicators required to indicate the pipeline state as a result of the attempt to materialize the pipeline. In at least one embodiment, the generation of indicator 714 takes into account kernel 706, buffer location 708, memory location 710, and / or other parameters required for the materialization of the task pipeline. In at least one embodiment, indicator 714 is data to be output by the API (if the API causes call 702 to be executed). In at least one embodiment, indicator 714 indicates whether operation 700 was executed successfully or failed. In at least one embodiment, response 704 generates additional parameters as output besides pipeline runtime 712 and / or indicator 714.

[0088] In at least one embodiment, the processor uses operation 700, comprising one or more steps, to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors on two or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, as an example, a machine-readable medium stores a set of instructions that, if executed by one or more processors, cause the one or more processors to instruct the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors on two or more processors, and / or otherwise perform the operations described herein. In at least one embodiment, operation 700 includes... Figure 1-7 The system shown is included Figure 1-7 The system shown and / or otherwise includes Figure 1-7 The system shown is used to instruct a compiler to direct one or more portions of one or more software programs to be executed concurrently on two or more processors by one or more processors, and / or to perform other operations described herein. In at least one embodiment, operation 700 is performed by... Figure 8-2 The one or more systems shown in 6 execute, such as those used to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently on two or more processors by one or more processors, and / or otherwise perform the operations described herein.

[0089] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, those skilled in the art will understand that the inventive concept can be practiced without one or more of these specific details.

[0090] Data Center

[0091] Figure 8 An example data center 800 in which at least one embodiment can be used is illustrated. The data center 800 may include one or more rooms having racks 802 and auxiliary equipment for housing one or more racks 802 and one or more substrates 804. Racks 802 may include one or more substrates 804. Racks 802 may include housings for housing and supporting individual substrates 804. Operational aspects of racks 802 may be adjustable at the rack level (corresponding to a group of substrates 804) or at the substrate level (corresponding to individual substrates 804), among other options. Racks 802 or substrates 804 may have specific selected maximum operating parameters, such as, but not limited to, power consumption, operating frequency, etc. The data center 800 may be supported by various cooling systems, such as, but not limited to, cooling towers, cooling loops, pumps, and other support systems. The cooling system may include sensors and controllers for monitoring and managing the cooling characteristics of racks 802. The substrates 804 within racks 802 may draw operating power from one or more power distribution units (PDUs; not shown). PDUs can be arranged within racks 802, for example, between racks 802 that include substrates 804, or within racks 802 that also house substrates 804.

[0092] Rack 802 and substrate 804 may include subsystems, modules, add-in cards, and other semiconductor components. Substrate 804 may include one or more computing units 806, each computing unit 806 may include one or more processors 808, one or more memories 810, and an interface controller 812. Computing unit 806 may include any number of processors, such as, but not limited to, a central processing unit (“CPU”), a graphics processing unit (“GPU”), or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), including any processors described herein, such as, but not limited to, those described herein. Figure 9-21B The processor in the computing unit 806 may include one or more memory storage devices 810 (e.g., dynamic read-only memory, solid-state storage devices, or disk drives), as well as network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules, etc. One or more computing units 806 may be a server having one or more of the aforementioned computing resources.

[0093] Computing unit 806 may include individual computing unit groups housed in one or more racks (not shown), or in numerous racks within data centers in different geographical locations (also not shown). Individual computing unit groups may include grouped computing, networking, memory, or storage resources that can be configured or allocated to support one or more workloads. Several computing units (e.g., including CPUs and / or other processors) may be grouped within one or more racks to provide computing resources to support one or more workloads. Resource coordinator 814 may configure or otherwise control one or more computing units 806 or groups of computing units. Resource coordinator 814 may include a Software Design Infrastructure (“SDI”) management entity for data center 800. Resource coordinator 814 may include hardware, software, or some combination thereof.

[0094] Data center 800 may include any one or any combination of the framework layer 820, software layer 830, and application layer 840. For example... Figure 8 As shown, framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. Framework layer 820 may include a framework for supporting software 832 of software layer 830 and / or one or more applications 842 of application layer 840. Software 832 or application 842 may respectively include web-based service software or applications, such as, but not limited to, software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. Framework layer 820 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark. TM (Hereinafter referred to as "Spark"), which can utilize the distributed file system 828 for large-scale data processing (e.g., "big data"). The job scheduler 822 may include Spark drivers, which facilitate the scheduling of workloads supported by various layers of the data center 800. The configuration manager 824 may be able to configure different layers, such as, but not limited to, the software layer 830 and the framework layer 820 (which includes Spark and the distributed file system 828 for supporting large-scale data processing). The resource manager 826 may be able to manage clustered or grouped compute units 806 mapped to or allocated to support the distributed file system 828 and the job scheduler 822. The resource manager 826 may coordinate with the resource coordinator 814 to manage these mapped or allocated compute resources.

[0095] Software 832 may be included in software layer 830, and may include software used by at least a portion of computing units 806, one or more computing units 806, groups of computing units 806, and / or the distributed file system 828 of framework layer 820. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

[0096] Application 842 may be included in application layer 840 and may include one or more types of applications used by at least the portions of computing unit 806, one or more computing units 806, groups of computing units 806, and / or the distributed file system 828 of framework layer 820. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0097] Any of the Configuration Manager 824, Resource Manager 826, and Resource Coordinator 814 can implement any number and type of self-modification actions based on any amount and type of data obtained in any technically feasible manner. Self-modification actions can alleviate the burden on data center operators of Data Center 800 to make potentially erroneous configuration decisions and may prevent underutilized and / or poorly performing portions of the data center.

[0098] Data center 800 may include tools, services, software, or other resources for training one or more machine learning models according to one or more embodiments described herein, or for using one or more machine learning models to predict or infer information. For example, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above regarding data center 800. The trained machine learning model corresponding to one or more neural networks can be used with the resources described above regarding data center 800 to infer or predict information using weight parameters calculated through one or more training techniques described herein.

[0099] Data Center 800 can use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware (e.g., Figure 9-21BThe embodiments described herein can be used to perform some or all of the processes and techniques described elsewhere, such as, but not limited to, training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above can be configured as a service to allow a user to train or perform information inference, such as, but not limited to, image recognition, speech recognition, or other artificial intelligence services.

[0100] In at least one embodiment, processor 808 may include one or more processors and / or one or more circuits for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein. In at least one embodiment, processor 808 is configured by software 832 to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein. Data center 800 may use logic, CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware (e.g., Figure 9-21B (The embodiments in the document) can be used to perform any of the operations described above or elsewhere in this document.

[0101] processor

[0102] The following figure illustrates, without limitation, example processors and processing systems that can be used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform some or all of the processes, operations, and / or techniques described elsewhere herein. The example processors and processing systems can be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. Processors and processing systems can include logic, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an XPU (i.e., any computing architecture best suited to the needs of the application), or other hardware (e.g., Figure 9-21BThe embodiments described herein (in the text) are used to perform any of the operations described above, below, or elsewhere herein. The processors and / or processing systems described herein may include one or more circuits that can be used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. As used herein, one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. Figure 26A and Figure 26B Logic 2615, as described elsewhere herein, is illustrated and can be used in one or more devices to perform, for example (but not limited to), the operations discussed herein according to at least one embodiment. Logic can refer to, for example, any combination of software logic, hardware logic, and / or firmware logic for providing the functions and / or operations described herein, wherein the logic can be collectively or individually embodied as circuitry forming part of a larger system, such as an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system-on-a-chip (SoC), or one or more processors (e.g., a CPU, a GPU).

[0103] Figure 9 A processor according to at least one embodiment is illustrated, which is a system-on-a-chip (SOC) 900 (may be referred to as a system-on-a-chip, superchip, or other names). The SOC 900 may include processor complexes 910 and 940. The SOC 900 may include any number of processor complexes 910 and / or processor complexes 940, which may include any number of processors described herein in any combination, such as, but not limited to, processors described herein in any combination. Figure 9-21B The processor in the system. For example, processor 910 may include a central processing unit (CPU), and processor 940 may include a graphics processor. Alternatively, processor 910 may include a graphics processor, and processor 940 may include a graphics processor. The SOC 900 may include any number of display controllers 992, any number of multimedia engines 994, any number of I / O interfaces 970, any number of memory controllers 980, and any number of fabrics 960 in any combination. For ease of explanation, this document uses reference numbers identifying objects and bracket numbers identifying instances (if necessary) to denote multiple instances of similar objects. The SOC 900 may include a processor from Broadcom Corporation, Palo Alto, California.

[0104] Processor complex 910 may include a CPU, processor complex 940 may include a GPU, and SOC 900 may be a processing unit integrating processor complex 910 and processor complex 940 onto a single chip. Certain tasks may be assigned to processor complex 910, while other tasks may be assigned to processor complex 940. Processor complex 910 may be configured to execute main control software associated with SOC 900, such as, but not limited to, an operating system. Processor complex 910 may be the main processor of SOC 900, controlling and coordinating the operation of other processors. Processor complex 910 may issue commands that control the operation of processor complex 940 to perform some or all of the operations described herein. Processor complex 910 may be configured to execute host-executable code derived from CUDA or other source code (e.g., HIP source code), while processor complex 940 may be configured to execute device-executable code derived from CUDA or other source code to perform any of the operations described herein.

[0105] The processor complex 910 may include cores 920(1)-920(4) and cache (e.g., L3 cache) 930 for storing information for performing the operations described herein. The processor complex 910 may include any number of cores 920 in any combination and any number and type of cache. The cores 920 may be configured to execute instructions of a specific instruction set architecture (“ISA”) to perform some or all of the operations described herein. Each core 920 may include a CPU core. Cores 920(1)-920(4) may be referred to as compute units or arithmetic units. The SOC 900 may include any number of processor complexes 910, architecture 960, I / O interface 970, and memory controller 980.

[0106] Each core 920 may include a fetch / decode unit 922, an integer execution engine 924, a floating-point execution engine 926, and an L2 cache 928. The fetch / decode unit 922 may fetch instructions to perform some or all of the operations described herein (e.g., but not limited to APIs compiled into instructions) and decode those instructions, generate micro-operations, and dispatch individual micro-instructions to the integer execution engine 924 and / or the floating-point execution engine 926. The fetch / decode unit 922 may concurrently dispatch one micro-instruction to the integer execution engine 924 and another micro-instruction to the floating-point execution engine 926. The integer execution engine 924 may perform integer and memory operations. The floating-point engine 926 may perform floating-point and vector operations. The fetch / decode unit 922 may dispatch micro-instructions to one or more execution engines, which may replace both the integer execution engine 924 and the floating-point execution engine 926.

[0107] Each core 920(i) (where i is an integer representing a specific instance of core 920) can access the L2 cache 928(i) included in core 920(i). Each core 920 included in core complex 910(j) (where j is an integer representing a specific instance of core complex 910) can be connected to other cores 920 included in core complex 910(j) via the L3 cache 930(j) included in core complex 910(j). The cores 920 included in core complex 910(j) (where j is an integer representing a specific instance of core complex 910) can access all L3 caches 930(j) included in core complex 910(j). The L3 cache 930 can include any number of slices.

[0108] Processor complex 940 may be a graphics complex that can be configured to perform computational operations (e.g., the computational operations described herein) in a highly parallel manner. Processor complex 940 may be configured to perform graphics pipeline operations, such as, but not limited to, drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. Processor complex 940 may be configured to perform graphics-independent operations, such as, but not limited to, neural network training and / or simulation. Processor complex 940 may be configured to perform both graphics-related and graphics-independent operations.

[0109] The processor complex 940 may include any number of compute units 950(1)-950(N) (where N is any integer greater than 1) and an L2 cache 942. The compute units 950 may share the L2 cache 942, which may store information that will be used to perform some or all of the operations described herein. The L2 cache 942 may be partitioned. The processor complex 940 may include any number of compute units 950 and any number (including zero) and type of cache. The processor complex 940 may include any number of dedicated graphics hardware.

[0110] Each compute unit 950 may include any number of SIMD units 952(1)-952(N) (where N is any integer greater than 1) and shared memory 954. Each SIMD unit 952 may implement a SIMD architecture and may be configured to perform some or all of the operations described herein in parallel. Each compute unit 950 may execute any number of thread blocks, but each thread block may execute on a single compute unit 950, although in some embodiments, the thread block may execute on multiple compute units. A thread block may include any number of execution threads. A workgroup may be a thread block. Each SIMD unit 952 may execute a set of threads. A set of threads (e.g., 16 threads), also referred to as a warp, subgroup, or wavefront (e.g., used by AMD and Intel), may belong to a single thread block and be configured to process different datasets based on a single instruction set. Prediction may be used to disable one or more threads in a warp, subgroup, or wavefront. A lane may be a thread. A work item can be a thread, such as (but not limited to) an OpenCL thread. Different thread bundles, subgroups, or wavefronts within a thread block can be synchronized together and communicate via shared memory 954. Each compute unit 950 can include one or more thread block clusters, where thread block clusters can implement programmable control over locality at a larger granularity than a single thread block of a single streaming multiprocessor (SM). Thread block clusters (also referred to as “clusters”) can support multiple thread blocks running concurrently across streaming multiprocessors, thereby synchronously and cooperatively acquiring, exchanging, or otherwise using data. In at least one embodiment, a streaming multiprocessor (“SM”) can refer to a streaming microprocessor, a streaming processor (“SP”), a streaming processing unit (“SPU”), a compute unit (“CU”), an execution unit (“EU”), and / or a slice, where a slice in this context can refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0111] Structure 960 may be a system interconnect that facilitates data and control transfers across processor complex 910, processor complex 940, I / O interface 970, memory controller 980, display controller 992, and multimedia engine 994, for example, to perform some or all of the operations described herein. SOC 900 may include any number and type of system interconnects other than or replacing structure 960, facilitating data and control transfers across any number and type of directly or indirectly linked components within or outside SOC 900. I / O interface 970 may represent any number and type of I / O interfaces (e.g., PCI, PCI extensions (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). Various types of peripheral devices may be coupled to I / O interface 970. Peripherals that may be coupled to I / O interface 970 may include keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0112] Display controller 992 can display images on one or more display devices, such as, but not limited to, liquid crystal displays (“LCD”) devices. Multimedia engine 994 can include any number and type of circuitry related to multimedia, such as, but not limited to, video decoders, video encoders, image signal processors, etc. Memory controller 980 can facilitate data transfer between SOC 900 and unified system memory 990. Processor complex 910 and processor complex 940 can share unified system memory 990. Unified system memory 990 can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as, but not limited to, synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Unified system memory 990 can include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, or HDM3.

[0113] The SOC 900 can implement a memory subsystem comprising any number and type of memory controllers 980 and memory devices (e.g., shared memory 954), which may be dedicated to a single component or shared among multiple components to perform any of the operations described herein. The SOC 900 can implement a cache subsystem comprising one or more cache memories (e.g., L2 cache 928, L3 cache 930, and L2 cache 942), each cache memory which may be dedicated to any number of components (e.g., core 920, core complex 910, SIMD unit 952, compute unit 950, and processor complex 940) or shared among any number of components (e.g., core 920, core complex 910, SIMD unit 952, compute unit 950, and processor complex 940).

[0114] In at least one embodiment, the SOC 900 may include one or more circuits for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein. One or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein.

[0115] Figure 10A A parallel processor 1000 according to at least one embodiment is illustrated. The parallel processor 1000 can be implemented using one or more circuits and can be referred to as a programmable processor (e.g., CPU and / or GPU), logic, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other hardware (e.g., Figure 9-21B (The embodiments in this document) are used to perform any of the operations described above or elsewhere herein.

[0116] Parallel processor 1000 may include parallel processing unit 1002 for performing any of the operations described above or elsewhere herein. Parallel processing unit 1002 may include I / O unit 1004 that enables communication with other devices, including other instances of parallel processing unit 1002. I / O unit 1004 may be directly connected to other devices. I / O unit 1004 may be connected to other devices via the use of a hub or switch interface, such as, but not limited to, memory hub 1005. The connection between memory hub 1005 and I / O unit 1004 may form a communication link 1013. I / O unit 1004 may be connected to host interface 1006 and memory crossbar switch 1016, wherein host interface 1006 receives commands directed to perform processing operations, and memory crossbar switch 1016 receives commands directed to perform memory operations.

[0117] When host interface 1006 receives a command buffer via I / O unit 1004, host interface 1006 can route the work operations that execute these commands to front-end 1008. Front-end 1008 can be coupled to scheduler 1010 (which may be referred to as sequencer), which is configured to distribute commands or other work items to processing cluster array 1012. Scheduler 1010 can ensure that processing cluster array 1012 is correctly configured and in an active state before tasks are distributed to the cluster of processing cluster array 1012. Scheduler 1010 can be implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 1010 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 1012. Host software can validate workloads scheduled on processing cluster array 1012 via one of multiple graphics processing paths. The workload can then be automatically distributed to the processing array cluster 1012 by the scheduler 1010 logic within the microcontroller, which includes the scheduler 1010.

[0118] Processing cluster array 1012 can perform any of the operations described above or elsewhere herein, and may include up to “N” processing clusters (e.g., clusters 1014A, 1014B through 1014N), where “N” represents a positive integer (which may be a different integer “N” than used in other diagrams). Each cluster 1014A-1014N in processing cluster array 1012 can execute a large number of concurrent threads. Scheduler 1010 may use various scheduling and / or work distribution algorithms to distribute work to clusters 1014A-1014N in processing cluster array 1012, which may vary depending on the workload generated by each type of program or computation. Scheduling may be dynamically handled by scheduler 1010 or may be assisted by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1012. Different clusters 1014A-1014N of processing cluster array 1012 may be assigned to process different types of programs or perform different types of computations.

[0119] The processing cluster array 1012 can be configured to perform various types of parallel processing operations, such as, but not limited to, any of the operations described above or elsewhere herein. The processing cluster array 1012 can be configured to perform general-purpose parallel computing operations. For example, the processing cluster array 1012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0120] Processing cluster array 1012 can be configured to perform parallel graphics processing operations. Processing cluster array 1012 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Processing cluster array 1012 can be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 1002 can transfer data from system memory via I / O unit 1004 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1022) during processing and then written back to system memory.

[0121] When the parallel processing unit 1002 is used to perform graphics processing, the scheduler 1010 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1014A-1014N of the processing cluster array 1012. Each part of the processing cluster array 1012 can be configured to perform different types of processing. For example, a first part can be configured to perform vertex shading and topology generation, a second part can be configured to perform tessellation and geometry shading, and a third part can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more clusters 1014A-1014N can be stored in a buffer to allow intermediate data to be transferred between clusters 1014A-1014N for further processing.

[0122] Processing cluster array 1012 can receive processing tasks to be executed via scheduler 1010, which receives commands defining the processing tasks from front end 1008. Processing tasks may include indexes of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., which program to execute). Scheduler 1010 can be configured to retrieve the index corresponding to the task, or can receive the index from front end 1008. Front end 1008 can be configured to ensure that processing cluster array 1012 is configured to be active before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0123] Each instance of one or more instances of parallel processing unit 1002 may be coupled to parallel processor memory 1022 to perform any of the operations described above or elsewhere herein. Parallel processor memory 1022 may be accessed via memory crossbar switch 1016, which may receive memory requests from processing cluster array 1012 and I / O unit 1004. Memory crossbar switch 1016 may access parallel processor memory 1022 via memory interface 1018. Memory interface 1018 may include multiple partition units (e.g., partition units 1020A, 1020B through 1020N), each partition unit may be coupled to a portion (e.g., a memory cell) of parallel processor memory 1022. The number of partition units 1020A-1020N can be configured to be equal to the number of memory units, such that the first partition unit 1020A has a corresponding first memory unit 1024A, the second partition unit 1020B has a corresponding memory unit 1024B, and the Nth partition unit 1020N has a corresponding Nth memory unit 1024N. The number of partition units 1020A-1020N may not be equal to the number of memory units.

[0124] Memory cells 1024A-1024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as, but not limited to, synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory. Memory cells 1024A-1024N may also include 3D stacked memory, including but not limited to high-bandwidth memory (HBM), HBM2e, or HDM3. Render targets (e.g., but not limited to framebuffers or texture maps) may be stored in memory cells 1024A-1024N, allowing partitioning cells 1020A-1020N to write portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 1022. A local instance of the parallel processor memory 1022 may not be included to support a unified memory design that combines system memory with local cache memory.

[0125] Any cluster 1014A-1014N in the processing cluster array 1012 can process data to be written to any memory cell 1024A-1024N within the parallel processor memory 1022. The memory crossbar switch 1016 can be configured to transfer the output of each cluster 1014A-1014N to any partition cell 1020A-1020N, ​​or to another cluster 1014A-1014N on which additional processing operations can be performed. Each cluster 1014A-1014N can communicate with the memory interface 1018 via the memory crossbar switch 1016 to read from or write to various external memory devices. The memory crossbar switch 1016 can be connected to the memory interface 1018 to communicate with the I / O unit 1004, or to a local instance of the parallel processor memory 1022, enabling processing units within different processing clusters 1014A-1014N to communicate with system memory or other memory local to the non-parallel processing unit 1002. The memory crossbar switch 1016 can use virtual channels to separate traffic flows between clusters 1014A-1014N and partition units 1020A-1020N.

[0126] Multiple instances of the parallel processing unit 1002 can be mounted on a single add-in card, or multiple add-in cards can be interconnected. Even if different instances of the parallel processing unit 1002 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, these different instances can be configured to interoperate. For example, some instances of the parallel processing unit 1002 may include higher-precision floating-point units relative to other instances. Systems including one or more instances of the parallel processing unit 1002 or the parallel processor 1000 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0127] Figure 10A It also includes a block diagram of a partitioning unit 1020 according to at least one embodiment. The partitioning unit 1020 is... Figure 10AAn example of one of the partition units 1020A-1020N in the parallel processor memory. Partition unit 1020 may include L2 cache 1021, frame buffer interface 1025, and ROP 1026 (raster operation unit). L2 cache 1021 may be a read / write cache configured to perform load and store operations received from memory crossbar switch 1016 and ROP 1026. Read misses and urgent write-back requests may be output from L2 cache 1021 to frame buffer interface 1025 for processing. Updates may also be sent to the frame buffer via frame buffer interface 1025 for processing. Frame buffer interface 1025 may interface with one of the memory cells in the parallel processor memory, such as, but not limited to, Figure 10A The memory cells 1024A-1024N are located in the parallel processor memory 1022 (for example, within the parallel processor memory 1022).

[0128] ROP 1026 can be a processing unit that performs raster operations, such as, but not limited to, stenciling, z-testing, blending, etc. ROP 1026 can then output processed graphics data stored in graphics memory. ROP 1026 may include compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic that utilizes one or more compression algorithms. The type of compression performed by ROP 1026 can vary based on the statistical characteristics of the data to be compressed. For example, incremental color compression is performed on depth and color data on a per-tile basis.

[0129] ROP 1026 can be included in each processing cluster (e.g., Figure 10A The data is stored within clusters 1014A-1014N, not within partition units 1020. Read and write requests for pixel data (not pixel fragment data) can be transferred via memory crossbar switch 1016. Processed graphics data can be displayed on a monitor and routed for further processing by the processor, or routed to... Figure 10A One of the processing entities within the 1000 parallel processors in the system is further processed.

[0130] In at least one embodiment, the parallel processor 1000 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described above or elsewhere herein.

[0131] Figure 10B A block diagram including a processing cluster 1014 within a parallel processing unit according to at least one embodiment. The processing cluster may be... Figure 10A An instance of one of the processing clusters 1014A-1014N is provided, which can be used to perform any of the operations described above or elsewhere herein. Processing cluster 1014 can be configured to execute many threads in parallel, where a “thread” refers to an instance of a specific program executed on a specific input dataset. Single Instruction Multiple Data (SIMD) instruction issuing techniques can be used to support the parallel execution of a large number of threads without providing multiple independent instruction units. Single Instruction Multiple Thread (SIMT) techniques can be used to support the parallel execution of a large number of typically synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0132] The operation of cluster 1014 can be controlled via pipeline manager 1032, which distributes processing tasks to SIMT parallel processors. Pipeline manager 1032 can... Figure 10A The scheduler 1010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1034 and / or texture unit 1036. The graphics multiprocessor 1034 may be an example instance of a SIMT parallel processor. However, the processing cluster 1014 may include various types of SIMT parallel processors with different architectures. The processing cluster 1014 may include one or more instances of the graphics multiprocessor 1034. The graphics multiprocessor 1034 can process data and can use the data cross switch 1040 to distribute the processed data to one of several possible destinations, including other shader units. The pipeline manager 1032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 1040.

[0133] Each graphics multiprocessor 1034 within the processing cluster 1014 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.) for performing computations for any of the operations described above or elsewhere herein. The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions complete. The functional execution logic can support a wide range of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. Different operations can be performed using the same functional unit hardware, and arbitrary combinations of functional units are possible.

[0134] Instructions transmitted to the processing cluster 1014 can form threads, which may also be called thread bundles, subgroups, waves, or wavefronts. A group of threads executing across a set of parallel processing engines can be called a thread group. Thread groups can execute a common program on different input data. Each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1034. The number of threads in a thread group can be less than the number of processing engines within the graphics multiprocessor 1034. When the number of threads in a thread group is less than the number of processing engines, one or more processing engines may be idle during the processing cycle of that thread group. The number of threads in a thread group can also be more than the number of processing engines within the graphics multiprocessor 1034. When the number of threads in a thread group is more than the number of processing engines within the graphics multiprocessor 1034, processing can be performed in consecutive clock cycles. Multiple thread groups can execute concurrently on the graphics multiprocessor 1034.

[0135] The graphics multiprocessor 1034 includes an internal cache memory for performing load and store operations, such as, but not limited to, any of the operations described above or elsewhere herein. The graphics multiprocessor 1034 may forgo the internal cache and instead use a cache memory within the processing cluster 1014 (e.g., L1 cache 1048). Each graphics multiprocessor 1034 may also access partition units that can be shared across all processing clusters 1014 (e.g., ...). Figure 10A The L2 cache within partition units 1020A-1020N is used for transferring data between threads. The graphics multiprocessor 1034 can also access off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 1002 can be used as global memory. The processing cluster 1014 may include multiple instances of the graphics multiprocessor 1034 and can share common instructions and data, which can be stored in the L1 cache 1048.

[0136] Each processing cluster 1014 may include an MMU 1045 (Memory Management Unit), which can be configured to map virtual addresses to physical addresses. One or more instances of the MMU 1045 may reside in... Figure 10AThe MMU 1045 is located within the memory interface 1018. It may include a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles, and optional cache line indexes. The MMU 1045 may include address translation lookup buffers (TLBs) or caches that may reside within the graphics multiprocessor 1034 or L1 1048 cache or processing cluster 1014. Physical addresses can be processed to distribute surface data access locally, allowing for efficient request interleaving between partition units. The cache line indexes can be used to determine whether a request for a cache line is a hit or a miss.

[0137] Processing cluster 1014 can be configured such that each graphics multiprocessor 1034 is coupled to a texture unit 1036 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data can be read from an internal texture L1 cache (not shown) or an L1 cache within the graphics multiprocessor 1034, and can be retrieved as needed from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 1034 can output processed tasks to a data crossbar switch 1040 to provide the processed tasks to another processing cluster 1014 for further processing, or store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1016. Pre-ROP 1042 (pre-raster operation unit) can be configured to receive data from the graphics multiprocessor 1034 and direct the data to ROP units, which can be associated with partitioning units (e.g., ...) described herein. Figure 10A The PreROP 1042 unit is located together with partition units 1020A-1020N. The PreROP 1042 unit can perform color blending optimization, organize pixel color data, and perform address translation.

[0138] In at least one embodiment, the processing cluster 1014 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. One or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0139] Figure 10CA graphics multiprocessor 1034 according to at least one embodiment is illustrated, for example, to perform any of the operations described above or elsewhere herein. The graphics multiprocessor 1034 may be coupled to a pipeline manager 1032 of a processing cluster 1014. The graphics multiprocessor 1034 may include an execution pipeline including, but not limited to, an instruction cache 1052 (e.g., which may store instructions, such as, but not limited to, compiled API instructions), instruction units 1054, address mapping units 1056, register files 1058, one or more general-purpose graphics processing unit (GPGPU) cores 1062, and one or more load / store units 1066, one or more of which may perform load / store operations to load / store instructions corresponding to the execution operations. The GPGPU cores 1062 and load / store units 1066 may be coupled to cache memory 1072 and shared memory 1070 via a memory and cache interconnect 1068. The GPGPU cores 1062 may be part of a SoC, such as, but not limited to, [other components]. Figure 9 It is part of the integrated circuit 900.

[0140] Instruction cache 1052 can receive a stream of instructions to be executed (e.g., perform any of the operations described above or elsewhere herein) from pipeline manager 1032. Instructions can be cached in instruction cache 1052 and dispatched for execution by instruction unit 1054. Instruction unit 1054 can dispatch instructions into thread groups (e.g., thread bundles, subgroups, wavefronts, or waves), with each thread in the thread group assigned to a different execution unit within GPGPU core 1062. Instructions can access any of the local, shared, or global address spaces by specifying an address within a unified address space. Address mapping unit 1056 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 1066.

[0141] Register file 1058 provides a set of registers for the functional units of graphics multiprocessor 1034. Register file 1058 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 1034 (e.g., GPGPU core 1062, load / store unit 1066). Register file 1058 can be partitioned among the functional units, such that each functional unit is allocated a dedicated portion of register file 1058. Register file 1058 can be partitioned among different thread bundles (which may be referred to as wavefronts, subgroups, and / or waves or threads) executed by graphics multiprocessor 1034.

[0142] Each GPGPU core 1062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1034. The architectures of the GPGPU cores 1062 may be similar or different. A first part of the GPGPU core 1062 may include a single-precision FPU and an integer ALU, while a second part of the GPGPU core may include a double-precision FPU. The FPU may implement IEEE 754-2008 standard floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 1034 may also include one or more fixed-function or special-function units for performing specific functions, such as, but not limited to, copying rectangles or pixel blending operations. One or more of the GPGPU cores 1062 may also include fixed-function or special-function logic.

[0143] The GPGPU core 1062 may include SIMD logic capable of executing a single instruction on multiple sets of data. The GPGPU core 1062 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core may be generated by the shader compiler at compile time, or may be automatically generated when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of a program can be configured for a SIMT execution model that can be executed via a single SIMD instruction. For example, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0144] The memory and cache interconnect 1068 may include an interconnect network that connects each functional unit of the graphics multiprocessor 1034 to the register file 1058 and shared memory 1070. The memory and cache interconnect 1068 may be a cross-switch interconnect that allows the load / store unit 1066 to perform load and store operations between the shared memory 1070 and the register file 1058. The register file 1058 may operate at the same frequency as the GPGPU core 1062, thus data transfer between the GPGPU core 1062 and the register file 1058 can have very low latency. The shared memory 1070 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 1034. The cache memory 1072 can be used as a data cache, for example, for caching texture data transferred between functional units and texture units 1036. The shared memory 1070 can also be used as a program-managed cache. In addition to automatically caching the data stored in the cache memory 1072, threads executing on the GPGPU core 1062 can also programmatically store data in shared memory.

[0145] The parallel processor or GPGPU described herein can be communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects, such as, but not limited to, PCIe or NVLink). A System-on-a-Chip (SoC) may include the parallel processor or GPGPU described herein, which executes on the SoC. The GPU may be integrated as a core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. Regardless of the GPU's connection method, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU can then use dedicated circuitry / logic to efficiently process these commands / instructions to perform any of the operations described above or elsewhere herein.

[0146] In at least one embodiment, the graphics multiprocessor 1034 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0147] Figure 11A processor 1100 according to at least one embodiment is illustrated. The processor 1100 may include a hybrid architecture processor (e.g., Lunar Lake or Meteor Lake) from Intel Corporation, Santa Clara, California, or other processors sharing at least some of the components described herein. The processor 1100 may include one or more central processing units (CPU 1102), one or more graphics processing units (GPU 1106), and / or one or more neural processing units (NPU 1108), which may be, for example, dedicated AI accelerators for offloading artificial intelligence (AI) workloads from the CPU 1102 and GPU 1106. The processor 1100 may use instructions that, if executed, cause the processor 1100 and / or any of its components to perform some or all of the processes and techniques described elsewhere herein. The processor 1100 may include any number of memory and cache units 1110 for facilitating processing between different components. The memory and cache 1110 on processor 1100 may include one or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination. Regarding processor 1100 and any components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) inside or outside the processor. The results of APIs may be stored in storage devices inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory. One or more APIs described herein may include calls.

[0148] Processor 1100 may include a computing engine as CPU 1102, and may include any number of cores, such as, but not limited to, up to 16 cores / 22 threads. The cores in CPU 1102 may include P-cores (performance), E-cores (high efficiency), and LP-E cores (low-power, high-efficiency). Performance cores can be used for low-latency, single-threaded, computationally intensive workloads, while high-efficiency cores can be used for multi-threaded, less computationally intensive workloads. Low-power, high-efficiency cores can be used for scalable multi-threaded execution and offloading background tasks. P-cores can be used for single-threaded and limited-threaded execution, while E-cores and LP-E cores are used for multi-threaded throughput and power efficiency.

[0149] The GPU 1106 can include any number of graphics engines, such as, but not limited to, those with 8 Xe cores (up to 128 execution units or EUs). Arc TM Graphics engine (Xe LPG). For example... Figure 11 As shown, GPU 1106 may include a vector engine 1110 and a matrix engine 1112, which, for example, can run FP, INT, and matrix operation tasks simultaneously, individually, or in batches. GPU 1106 may include a load / store unit 1114, as well as other memories, such as, but not limited to, an instruction cache (I$) 1116 and an L1 cache / subsystem local memory (SLM) 1118, which may, for example, store instructions for performing any of the operations described above or elsewhere herein.

[0150] The NPU 1104 may include one or more AI Boost integrates a Neural Processing Unit (NPU). The NPU 1104 can be enumerated as an integrated PCIe device to the host processor. The NPU 1104 may include one or more (e.g., two) Neural Computation Engine (NCE) tiles 1130. Each tile may be configured with any combination of, but not limited to, the following: (e.g., 2000) Multiply-Accumulate (MAC) engines 1134, a post-processing engine (not shown), an AEP processor (not shown), and memory per tile (2MB dedicated SRAM), such as... Figure 11 As shown. For general computing needs, the neural computing engine 1130 may include a streaming hybrid architecture vector engine (SHAVE) 1128 for high-performance parallel computing, which may include a DMA (Direct Memory Access) engine 1124 for transporting data between system memory DRAM (Dynamic Random Access Memory) 1126 and a software-managed cache. The built-in device MMU (Memory Management Unit) 1122, plus the IOMMU (Input-Output Memory Management Unit) (not shown), can support multiple concurrent hardware contexts and provide secure isolation between execution contexts according to the MCDM (Microsoft Compute Driver Model) architecture. The processor 1100 may also include a media unit (not shown), which may be included on or separate from the XCD or other components of the processor to enable video playback and video processing of compressed or uncompressed data, such as using HEVC, AV1, VP9, ​​and AVC hardware-accelerated decoding support and HEVC, VP9, ​​and AVC hardware-accelerated encoding support.

[0151] Thread bootstrap ( The Thread Director (which includes firmware built into the processor) can prioritize and manage the distribution of workloads, sending tasks to optimized cores. For example, the Thread Director can tie P cores, E cores, and / or LP-E cores (as described above) together with task scheduling capabilities and the ability to send less demanding tasks to E cores or LP-E cores. Deep learning acceleration ( DLBoost (not shown) can provide built-in AI acceleration for training and inference workloads and may include support for VNNI (for CPU) and DP4a (for GPU) instruction sets. This instruction set can be used with OpenVINO. TM The toolkit and oneAPI are optimized to accelerate INT8 inference. For example, the software stack described elsewhere in this document can be used to leverage OpenVINO. TM The toolkit enables AI inference. The processor 1100 can be configured to execute applications, such as, but not limited to, CUDA programs.

[0152] In at least one embodiment, processor 1100 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0153] Processor 1100 may alternatively include a processor based on Qualcomm's AIEngine Direct architecture from Santa Clara, California, or other processors sharing at least some of the components described herein. It may include any number of NPUs, GPUs, CPUs, and other associated components, such as, but not limited to, an NPU 1104 as a Hexagon NPU, a GPU 1106 as an Adreno GPU, a CPU 1102 as a Kryo or Qualcomm Oryon CPU, and a Qualcomm Sensing Hub (not shown) and a memory subsystem 1110. Hexagon NPU 1104 may include power rails, micro-tile inference units, hardware acceleration units, tensor units, scalar units, and vector units (all not shown), which may have dedicated or shared memory (e.g., cache or memory, such as HBM3) for storing, for example, instructions for performing any of the operations described above or elsewhere herein. The Adreno GPU 1106 can provide graphics and parallel processing for AI, in formats including but not limited to 32-bit floating-point (FP32), 16-bit floating-point (FP16), and 8-bit integer (INT8). The Kryo or Qualcomm Oryon CPU 1102 can execute AI workloads and handle the contextualization of ubiquitous generative AI applications. The CPU 1102 may also include an instruction fetch unit, a renaming and deprecation unit, a memory management unit, a vector execution unit, an integer execution unit, and a load and store unit for processing and instruction management. Regarding the processor 1100 and any of its components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by the instruction fetch unit, decoded by the processor decoder or equivalent, scheduled (e.g., sequentially or out of order) for execution by the scheduler or equivalent, executed by execution logic or equivalent, reordered, and then deprecated by the renaming and deprecation unit. The API (and / or compiled instructions including the API) can be stored in any storage device, either inside or outside the processor (e.g., in cache and / or memory). An arbitrary number of CPU cores 1102 can be included in an arbitrary number of CPU clusters, which can be coupled to memory and / or cache, such as, but not limited to, a shared L2 cache. Memory can be separate or shared; for example, the CPU clusters of CPU cores 1102 can be coupled to a memory subsystem 1110, which can include structures capable of reading and writing to memory (e.g., DRAM), system-level caches, and an arbitrary number of memory management units.The Qualcomm sensing hub (not shown) includes a miniature NPU, power rails, and conventional sensors (such as gyroscopes, accelerometers, or even barometers) that support voice and data streaming. The memory subsystem 1110 may include memory and cache on the processor 1100, which may include L1 or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination, for example, for storing information and / or instructions for performing any of the operations described above or elsewhere herein. All or part of the memory and / or cache in the memory subsystem 1110 may be shared or used individually by any component or combination of components on the processor 1100 (e.g., GPU 1106, NPU 1104, and CPU 1102).

[0154] The Qualcomm AI Engine 1100 can be programmed and controlled using a software stack to perform some or all of the operations described herein, including, for example... The Neural Processing SDK is available for inference on Android, Linux, and Windows. Developer libraries and services support the latest programming languages, virtual platforms, and compilers. At lower levels of the software stack, system software includes a basic real-time operating system (RTOS), system interfaces, and drivers. The software stack supports various operating systems, including Android, Windows, Linux, and QNX, as well as deployment and monitoring infrastructures such as Prometheus, Kubernetes, and Docker. OpenCL and DirectML are supported for direct cross-platform access to the GPU. For the CPU, LLVM compiler infrastructure optimizations enable accelerated and efficient AI inference. Regarding the Qualcomm AI Engine 1100 and any of its components described above or elsewhere herein, one or more APIs described herein can, for example, be compiled into instructions that can be fetched by instruction fetching logic or equivalents, decoded by processor decoders or equivalents, scheduled (e.g., sequentially or out of order) for execution by a scheduler or equivalent, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) can be stored in any storage device, either inside or outside the processor (e.g., in cache and / or memory). The results of the API can be stored in storage devices, either inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory.

[0155] In at least one embodiment, processor 1100 or Qualcomm AI Engine 1100 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. One or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0156] Figure 12A A processor 1200 according to at least one embodiment is illustrated. The processor 1200 may include a Scalable family processor from Intel Corporation, Santa Clara, California, or other processors sharing at least some of the components described herein. The processor 1200 may include one or more cores 1212(1)-1212(N) capable of performing the operations described elsewhere herein, where N is any integer greater than 1. Cores 1212(1)-1212(N) may be interconnected using ring and / or mesh interconnects. Utilizing a mesh interconnect architecture, arrays of vertical and horizontal communication paths may allow traversal from one core to another 1212(1)-1212(N) via the shortest path (jumping to the correct row along the vertical path and to the correct column along the horizontal path). For the mesh interconnect, a die may accommodate cores 1212(1)-1212(N) and may include a Converging Mesh Stop Point (CMS) grid that may be associated with cores 1212(1)-1212(N) (e.g., 1:1). Each core can be associated with a low-level cache (LLC) slice 1214(1)-1214(N), or cores 1212(1)-1212(N) can share a cache, such as a low-level cache. LLC 1214(1)-1214(N) can be inclusive or non-inclusive (having blocks not present in the high-level cache) by merging blocks from a higher-level cache (e.g., L2 cache). Each core and LLC slice can include a caching and home agent (CHA) (not shown), which can maintain cache consistency by providing resource scalability via mesh interconnect. Super Path Interconnect ( UPI 1216 provides cache coherency capabilities. UPI 1216 can provide coherent interconnects for scalable systems and allows multiple processors to share a single shared address space via links, such as, but not limited to, two or three UPI links per processor.

[0157] Processor 1200 may also include system agent 1210, which may house and / or perform various functions, such as, but not limited to, memory management, display functions, and / or input / output (I / O) functions. For example, processor 1200 may include one or more integrated memory controllers (IMCs) 1208. IMCs 1208 may control and manage memory, such as, but not limited to, different memory types, such as DDR RAM, such as DDR4, or other memory described elsewhere herein. System agent 1210 may include a display controller (not shown) for supporting one or more displays. System agent 1210 may also integrate PCIe 1204 (e.g., up to 20 PCIe lanes), which may, for example, be connected to an external dedicated graphics connector via a DMI bus (e.g., Intel's DMI 3.0 bus) 1206. System agent 1210 may include an image processing unit (IPU) (not shown) that integrates an on-die image signal processor (ISP). Structure 1202 provides scalability for connecting to other nodes (e.g., processors, such as processor 1200) and can, for example, be connected to Cornelis Networks (…). It can be used together with elements of a scalable system framework that provides performance for high-performance computing (HPC) workloads and the ability to scale to tens of thousands of nodes.

[0158] Figure 12B Components within a core 1212 according to at least one embodiment are illustrated. The core 1212 may include a front-end 1218, a back-end or execution engine 1232, and a memory subsystem 1242. The front-end 1218 can provide operations (e.g., operations described elsewhere herein) to the execution engine 1232 by decoding instructions stored in memory. For example, the front-end 1218 may include micro-operation (μOps) cache paths and / or traditional paths, and a branch prediction unit 1220 capable of determining path instructions. A traditional path of instructions might involve fetching variable-length (e.g., x86) instructions from an L1 instruction cache, queuing these instructions into an instruction queue 1224, and decoding the instructions into μOps that can be provided to an allocation queue 1228 using a decoder 1226. Alternatively, the μOps cache path may include a cache that includes decoded μOps (μOps 1230) that can be sent to the allocation queue 1228. The allocation queue 1228 may act as an interface between the front-end 1218 and the execution engine 1232, and may provide instructions to the execution engine 1232. For example, one or more APIs described herein can be compiled into instructions that can be stored, processed, and executed by the front-end 1218 and the execution engine 1232, and stored in the memory subsystem 1242.

[0159] Execution engine 1232 can receive micro-operations into reordering buffer 1234, which can register, rename, and deregister μOPs. μOPs can be sent from the reordering buffer to scheduler 1236, which can be connected to one or more different execution units 1238. Execution units 1238 can perform operations such as basic arithmetic logic unit (ALU) operations, multiplication, division, and / or more complex operations, such as, but not limited to, various vector operations. Scheduler 1236 can manage the queuing of μOPs for one or more execution units 1238 based on, for example, the operations that need to be performed.

[0160] The memory subsystem 1242 can handle load and store requests as well as sorting operations. For example, μOPs may be associated with memory accesses (e.g., load and store), and these μOPs can be sent through dedicated scheduler ports that can perform these memory operations. For example, store and load operations can be sent to load and store buffers 1244. The memory subsystem 1242 may also include shared or separate L1 data and instruction caches 1246, and an L2 cache 1248 that can be used and shared by the L1 data and instruction caches 1246. (As described above regarding...) Figure 12A Each core 1212 can be connected to a slice of a level 3 cache (e.g., LLC1214), which can be shared by all cores 1212.

[0161] In at least one embodiment, processor 1200 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0162] Figure 13An AI accelerator 1300 according to at least one embodiment is illustrated. Processor 1300 may include a processor with an AI accelerator architecture manufactured by Intel Corporation, Santa Clara, California, or other processors sharing at least some of the components described herein. AI accelerator 1300 may use instructions that, if executed by AI accelerator 1300, cause AI accelerator 1300 to perform some or all of the processes and techniques described elsewhere herein. For example, with respect to AI accelerator 1300 and any components described above or elsewhere herein, one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) by scheduler or equivalents for execution, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device internal or external to the processor (e.g., in cache and / or memory). The results of the API can be stored in internal or external storage devices, including registers, DRAM, flash memory, SRAM, cache, or other memory. The AI ​​accelerator 1300 may include one or more compute dies, which may include homogeneous or heterogeneous processors. The compute dies may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), or a combination of both.

[0163] In at least one embodiment, the computational die may include a computational engine for performing AI computations. In at least one embodiment, the computational die of the AI ​​accelerator 1300 may be split into any number (e.g., four) clusters, which may be referred to as DCORE (Deep Learning Core) 1306, and include any number of matrix multiplication engines (MME) 1308, tensor processor cores (TPC) 1310, and L2 cache 1314 in any combination. The MME 1308 may perform operations using matrix multiplication, such as fully connected layers, convolutions, and batch general matrix multiplication (GEMM). The MME 1308 may be equipped with a multiplication-accumulation unit (MAC) (not shown), which may perform general matrix multiplication (GEMM) operations, such as, but not limited to, AxB multiplication, which involves generating a tensor C [NxM] from two input tensors A [NxK] and B [KxN]. The MME 1308 may be programmed with array dimensions, positions, data types, and various operands. The MME 1308 can retrieve tensors A and B from memory and pull them into its streaming buffer for parallel matrix multiplication by the MAC. After completion, the MME 1308 can push tensor C back to memory. The TPC1310 may include any number of scalar units for performing scalar operations, any number of vector units for performing vector operations, any number of register files or local memory units (e.g., vector local memory), and load and store components for instructions, which may be coupled to memory or caches (e.g., HBM, L3 cache, and / or L2 cache) (all not shown). The TPC can support different types of parallel processing, such as Very Long Instruction Word (VLIW) Single Instruction Multiple Data (SIMD) data types such as, but not limited to, FP32, BF16, FP16, and FP8 (both E4M3 and E5M2), UINT32, INT32, UINT16, INT16, UINT8, and INT8 data types. Any number of computational dies can be interconnected. Interconnections within a compute die can be achieved via an intermediary bridge, which is transparent to the software.

[0164] The memory on the AI ​​accelerator 1300 may include one or more levels of cache (e.g., L1, L2, L3, and / or last-level cache) and high-bandwidth memory (e.g., HBM2e or HBM3) in any combination. The memory and / or cache system may be unified or separate. The compute die of the AI ​​accelerator 1300 may include on-chip memory comprising one or more levels (e.g., two levels) of cache. On-chip SRAM or other memory described elsewhere herein may be used as a unified last-level cache (L3) or split into multiple slices of L2 cache accessible to the MME 1308 and TPC 1310 groups. The use of on-chip memory as an L2 or L3 cache is entirely software-configurable, and the software can dynamically determine its optimal cache allocation based on I / O tensors. AI accelerator 1300 may include one or more memory management units (MMUs) 1322 for managing memory, such as allowing the AI ​​accelerator 1300 memory subsystem to run in virtual space when accessing VRAM.

[0165] AI accelerator 1300 may include a communication port (e.g., a PCIe Gen5 x16 port) 1302 for communicating with a host and scheduling and synchronization unit 1304. AI accelerator 1300 may include a media unit 1316, which may include any number or combination of media decoder engines (DECs) 1320 and rotation engines (ROTs) 1318. AI accelerator 1300 may include a network unit 1324, which may include any number or combination of network ports 1326 and an accompanying RDMA engine 1328, L2 cache, and memory (e.g., HBM2e or HBM3) stack. AI accelerator 1300 may include a programmable control path entity (not shown) for managing the parallel and efficient execution of the various engines. The control path may include a submission queue (SQ) that can be issued by the runtime system, a completion queue (CQ) that can be used for job completion reporting, a programmable scheduling mechanism that can be used for task scheduling, a programmable hardware synchronization mechanism or "synchronization manager (SM)" that can be used for hardware synchronization, and a programmable interrupt service mechanism or "interrupt manager (INTR)" that can pass asynchronous events to drivers.

[0166] AI Accelerator 1300 may include media decoding units supporting video formats such as, but not limited to, HEVC, Progressive H.264, SVC base layer, MVC, VP9, ​​JPEG, and Progressive JPEG. AI Accelerator 1300 may support post-processing of the decoded media stream, such as, but not limited to, image downsizing (image resizing), vertical and horizontal scaling at different scaling ratios, image enlargement, image cropping, bilinear scaling, and Lancos scaling. AI Accelerator 1300 may implement two post-processing channels per decoder unit, one for scalar (up and down) and the other solely for outputting the original image. AI Accelerator 1300 may include a hardware rotation engine that performs the following transformations on the input image: 2D rotation, 3D rotation, projection, image warping and de-warping, resampling of the input data at user-defined coordinates, and rescaling.

[0167] The RDMA 1328 based on converged Ethernet on the AI ​​accelerator 1300 enables scaling from a single node (i.e., from a single AI accelerator 1300 to hundreds or thousands of nodes or AI accelerators 1300). The network subsystem 1324 may include... The accelerator 1300 includes an In-Gigabit Ethernet Communication Library (IGCL), a master controller coordinating data movement, and a programmable scheduling mechanism that enables smooth engine activation while maintaining task dependencies. The accelerator network subsystem may include a Gigabit Ethernet NIC port 1326, a Layer 2 MAC (not shown), and an RDMA engine 1328. The AI ​​accelerator 1300 may include an aggregation engine for performing summation activities. All engines in the processor 1300 can run in parallel; for example, the MME 1308, TPC 1310, and NIC 1326 can all operate simultaneously. Dependencies may exist between operations running on different engines; for example, the output of one engine may be used as the input of another engine, and / or the MME, TPC, and NIC may be scheduled to run in parallel. When one engine completes its execution, another engine can be scheduled to begin working on the next operation (executed immediately after its input is ready).

[0168] The AI ​​accelerator 1300 can be operated and controlled using a software layer 1328, which may include low-level components such as, but not limited to, a graph compiler, an automatic kernel fusionist and pre-compiled kernel libraries, and integration with the AI ​​ecosystem such as, but not limited to, PyTorch, DeepSpeed, Hugging Face, vLLM, Ray, etc., or as described elsewhere in this document regarding software and programming platforms. The software layer 1328 may include implementations of algorithms such as, but not limited to, paged attention, flash attention, etc. The software layer 1328 may generate optimized binary code that implements a given model topology, such as, but not limited to, performing operator fusion, data layout management, parallelization, pipeline and memory management, and graph-level optimization.

[0169] In at least one embodiment, the AI ​​accelerator 1300 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0170] This paper describes a neuromorphic computing system employing a multi-core architecture, where each core houses computing elements including neurons, synapses with on-chip learning capabilities, and local memory for storing synaptic weights and routing tables. Figure 14This is a simplified block diagram 1400 illustrating at least a portion of an example of such a neuromorphic computing device 1405 according to at least one embodiment. The neuromorphic computing device 1405 may include a neuromorphic processor from Intel Corporation, Santa Clara, California, or other processors that include at least a portion of the components described herein. As shown in this example, the device 1405 may be equipped with a network 1410 consisting of multiple neural network cores interconnected by a network on the device, thereby potentially defining multiple distinct connections between the cores. For example, the device 1405 may provide a network 1410 of spiking neural network cores, each core communicating via short packet pulse messages sent from one core to another through network channels. Each core (e.g., 1415) may have processing and memory resources, as well as logic, for implementing a number of primitive nonlinear time computation elements, such as, but not limited to, multiple (e.g., more than 1000) distinct artificial neurons (referred to herein as “neurons”). For example, each core may be able to implement multiple neurons concurrently, such that a collection of neuromorphic cores can be used to implement many, many neurons using the device. With respect to neuromorphic computing device 1405 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) inside or outside the processor. The results of the APIs may be stored in storage devices inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0171] continue Figure 14 For example, neuromorphic computing device 1405 may also include processor 1420 and system memory 1425 for implementing one or more components to manage and provide the functionality of the device. For instance, a system manager 1430 may be provided to manage the global attributes and operations of the device (e.g., attributes affecting core network 1410, multiple cores in network 1410, interconnection of device 1405 with other devices, managing access to global system memory 1425, and other potential examples). In one example, system manager 1430 may manage the definition and configuration of specific routing tables for individual routers in network 1410, orchestration of network definitions and attributes to be applied to the network (e.g., weights, attenuation rates, etc.), core synchronization and time multiplexing management, routing input to the appropriate core, and other potential functions.

[0172] As another example, the neuromorphic computing device 1405 may also include a programming interface 1435 through which a user or system can specify the neural network definition to be applied (e.g., via routing tables and individual neuron attributes), implemented by the neuromorphic core grid 1410. A software-based programming tool may be provided with or separately from the neuromorphic computing device 1405, through which a user can provide a definition for a specific neural network to be implemented using the neuromorphic core network 1410. The programming interface 1435 can receive input from a programmer, then generate the corresponding routing table and populate the specified parameters into the local memory of each neuromorphic core (e.g., 1415) to implement the corresponding custom artificial neural network implemented by the neuromorphic core.

[0173] In certain circumstances, neuromorphic computing device 1405 can advantageously engage and interoperate with other devices, including general-purpose computing devices, to enable specific applications and use cases. Therefore, external interface logic 1440 may be provided in certain situations to communicate with one or more other devices (e.g., via one or more defined communication protocols). External interface 1440 may be used to accept input data from another device or an external memory controller used as an input data source. External interface 1440 may additionally or alternatively be used to allow the results or outputs of computations performed using the neural network implemented using neuromorphic computing device 1405 to be provided to another device (e.g., another general-purpose processor implementing machine learning algorithms) to enable additional applications and enhancements, among other examples.

[0174] like Figure 14 The diagram illustrates a network 1410 interconnected by a network on the device, showing a portion of a network structure interconnecting multiple neuromorphic cores (e.g., 1415a-d). For example, several neuromorphic cores (e.g., 1415a-d) can be provided in a mesh, each core interconnected via a network including multiple routers (e.g., 1450). In one implementation, each neuromorphic core (e.g., 1415a-d) can be connected to a single router (e.g., 1450) in the routers, and the router can be connected to at least one other router (e.g., [other router]). Figure 14(As shown at 1410 in the diagram). As an example, in one particular implementation, four neuromorphic cores (e.g., 1415a-d) can be connected to a single router (e.g., 1450), and each router 1450 can be connected to two or more other routers to form a multi-core mesh, thereby allowing each neuromorphic core to interconnect with every other neuromorphic core in the device. Furthermore, since each neuromorphic core can be configured to implement multiple different neurons, the router network of the device can similarly implement connections or artificial synapses (or simply "synapses") defined between any two of the potentially many (e.g., 30,000+) neurons defined using the neuromorphic core network provided in the neuromorphic computing device.

[0175] Figure 14 A block diagram of the internal components of an example implementation of a neuromorphic core 1415 is shown. In one example, a single neuromorphic core may implement a number of neurons (e.g., 1024) that share the architectural resources of the neuromorphic core in a time-division multiplexing manner. In one example, each neuromorphic core 1415 may include a processor block 1455 capable of executing arithmetic functions and routing related to the implementation of the digitally implemented artificial neurons, such as, but not limited to, those explained herein. Each neuromorphic core 1415 may also provide local memory in which routing tables of the neural network can be stored and accessed, accumulated potentials of each cell body of each neuron implemented using the core can be tracked, parameters of each neuron implemented by the core can be recorded, and other data and usage can be recorded. Components or architectural resources of the neuromorphic core 1415 may also include: an input interface 1465 for receiving input spike messages generated by other neurons on other neuromorphic cores; and an output interface 1470 for sending spike messages to other neuromorphic cores via a mesh network 1410. In some instances, the routing logic of the neuromorphic core 1415 can be implemented at least partially using the output interface 1470. Furthermore, in some cases, the core (e.g., 1415) can implement multiple neurons within an example SNN, and some of these neurons can be interconnected. In this case, spiking messages sent between neurons hosted on a particular core can forgo communication via the routing structure of the neuromorphic computing device and can be managed locally within that particular neuromorphic core.

[0176] Each neuromorphic core may also include logic for implementing artificial dendrites 1480 and artificial cell bodies 1485 (hereinafter referred to as “dendrites” and “cell bodies”, respectively) for each neuron 1475. Dendrite 1480 may be a hardware-implemented process for receiving impulses from the network. Cell body 1485 may be a hardware-implemented process for receiving the current time-accumulated neurotransmitter mass of each dendrite and evolving the potential states of each dendrite and cell body to generate outgoing impulse messages at appropriate times. Dendrite 1480 may be defined for each connection receiving input from another source (e.g., another neuron). In one implementation, the dendritic process 1480 may receive and process the impulse message as it arrives serially from the network in a time-division multiplexed manner. With the reception of impulses, neuronal activation (tracked using cell body 1485 (and local memory 1460)) may increase. When the activation of a neuron exceeds a threshold set for neuron 1475, the neuron generates a spike message, which is propagated via output interface 1470 to a fixed set of fan-out neurons. The network distributes the spike message to all destination neurons, which in turn can update their activation in a transient, time-dependent manner in response. This can lead to some of the destination neurons also exceeding their corresponding thresholds and triggering further spike messages, just as in real biological neural networks.

[0177] As described above, neuromorphic computing devices can reliably implement spiking-based neural computation models. Such models are also known as spiking neural networks (SNNs). In addition to neuronal and synaptic states, SNNs incorporate temporal concepts. For example, in SNNs, communication occurs via event-driven action potentials or spiking, which convey no explicit information other than the spiking time and the implicit source and destination neuron pairs corresponding to the spiking transmission. The computation of the result of a dynamic nonlinear integral as a weighted spiking input occurs in each neuron. In some implementations, recurrent and dynamic feedback can be incorporated into the SNN computation model. Furthermore, various network connectivity models can be employed to model a wide range of real-world networks or relationships, including fully connected (all-to-all) networks, feedforward trees, fully random projections, "small-world" networks, and other examples. Isomorphic two-dimensional networks at the neuromorphic core (e.g., but not limited to...) Figure 14 The network shown in the example can advantageously support all these network models. Since all cores of the device can be connected, some or all of the neurons defined in a core can also be fully connected via a certain number of router hops. The device can also include fully configurable routing tables for defining a wide variety of neural networks by allowing neurons in each core to distribute their spurs to any number of cores in the grid to achieve a completely arbitrary connection graph.

[0178] In improved implementations of systems capable of supporting SNNs, for example, but not limited to... Figure 9 The example illustrates a very large-scale integrated circuit (VLSI) hardware device that can provide high-speed, reliable circuitry to implement SNNs (Spiritual Neural Networks) to model the information processing algorithms used by the brain, but in a more programmable way. For instance, while a biological brain can only perform a specific set of defined behaviors (a consequence of years of development), a neuromorphic processor device can provide the ability to rapidly reprogram all neural parameters. Therefore, a single neuromorphic processor can be used to implement a wider range of behaviors than a single slice of biological brain tissue. This distinction can be achieved by employing neuromorphic processors with neuromorphic designs that are radically different from those found in natural neural circuitry.

[0179] As an example, a neuromorphic processor can implement a spontaneous neural network (SNN) by leveraging time-multiplexed computation in both a spiking communication network and the neuronal mechanism of the device. Therefore, the same physical circuitry of the processor device can be shared by many neurons to achieve higher neuron density. Through time multiplexing, the network can connect N cores with a total wiring length of O(N), whereas the length of discrete point-to-point wiring would be extended to O(N). 2 This significantly reduces wiring resources to accommodate planar and non-plastic VLSI routing techniques, among other examples. In the neuromorphic core, time multiplexing can be implemented through dense memory allocation, for example, using static random access memory (SRAM) with a shared bus, address decoding logic, and other multiplexed logic elements. The state of each neuron can be stored in the processor's memory, where data describing the state of each neuron includes the state of the collective synapse of each neuron, all currents and voltages on its membrane, and other example information (e.g., but not limited to configuration and other information).

[0180] Neuromorphic processors can be implemented in a “digital” manner, unlike other processors that employ more “analog” or “isomorphic” neuromorphic approaches. For example, a digital implementation can use digital adder and multiplier circuitry to integrate synaptic currents, in contrast to an analog isomorphic neuromorphic approach that accumulates charge on capacitors in a manner similar to how neurons accumulate synaptic charge on their lipid membranes. For instance, the accumulated synaptic charge for each neuron can be stored in the local memory of the corresponding core. Furthermore, at the architectural level of an example digital neuromorphic processor, reliable and deterministic operation can be achieved through time synchronization across the core network, ensuring that any two executions of the design, given the same initial conditions and configuration, will produce the same results. Asynchronicity can be reserved at the circuit level to allow individual cores to operate as quickly and freely as possible while maintaining determinism at the system level. Therefore, in neural computing, the concept of time as a time variable can be abstracted away from the “wall clock” time used by the hardware to perform computations. Thus, in some implementations, a time synchronization mechanism can be provided that globally synchronizes the neuromorphic cores at discrete time intervals. The synchronization mechanism allows the system to complete neural computations at the fastest speed allowed by the circuitry, and there is a difference between the runtime and the biological time for modeling neuromorphic systems.

[0181] In operation, the neuromorphic mesh device can start in an idle state when all neuromorphic cores are inactive. As each core asynchronously loops through its neurons, it generates impulse messages, which are routed by the mesh interconnect to the appropriate destination core containing all destination neurons. The implementation of multiple neurons on a single neuromorphic core can be time-multiplexed, and time steps can be defined, where all impulses involving multiple neurons can be processed and considered using the shared resources of the respective cores. When each core completes its service to its neurons within the corresponding time step, in some implementations, the core can communicate with neighboring cores using synchronization messages (e.g., using a handshake) to refresh the mesh of all transmitted impulse messages, allowing the core to safely determine that all impulses have been serviced within a given time step. At this point, all cores can be considered synchronized, allowing them to advance their time steps and return to their initial state to begin the next time step.

[0182] Given this context, as described above, a device (e.g., 1405) can be provided to realize an interconnected neuromorphic core network 1410, wherein core 1415 can realize multiple artificial neurons capable of interconnecting to realize an SNN. Each neuromorphic core (e.g., 1415) can provide two loosely coupled asynchronous processes: an input dendrite process (e.g., 1480) that receives impulses from network 1410 and applies them to the appropriate destination dendritic compartment at an appropriate future time; and an output cell body process (e.g., 1485) that receives the current-time accumulated neurotransmitter mass of each dendritic compartment and evolves the membrane potential state of each dendrite and cell body to generate an outgoing impulse message at an appropriate time (e.g., when the threshold potential of the cell body is reached). It should be noted that, from a biological perspective, the names of dendrites and cell bodies used herein are only approximate to the function of these features and should not be interpreted too literally.

[0183] In at least one embodiment, the neuromorphic computing device 1405 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0184] Figure 15 This is a block diagram of an embodiment of a multi-node network capable of enabling remote memory computing according to any embodiment. System 1500 may represent the node network described herein, for example, the node network may be used to perform some or all of the operations described herein. System 1500 may represent a data center. System 1500 may represent a server farm. System 1500 may represent a data cloud or processing cloud. System 1500 may represent a supercomputer. System 1500 may include tens, hundreds or thousands of nodes. The nodes of System 1500 may include processors, such as, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), or any combination of processors described herein, such as, but not limited to, processors described herein. Figure 9-21BOther processors in the system. For any processor in System 1500 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device (e.g., cache and / or memory) inside or outside the processor. The results of APIs may be stored in storage devices inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents. System 1500 may include more than nine thousand nodes, each node comprising two Intel Xeon Max processors, six Intel Max series GPUs, and a unified memory architecture, such as, but not limited to, the architecture used in Intel's Aurora supercomputer in Santa Clara, California, or other supercomputers that share at least some of the components described herein.

[0185] One or more clients 1502 send requests to system 1500 via network 1504. Network 1504 represents one or more local area networks, wide area networks, or a combination of both. Clients 1502 can be human or machine clients that generate requests for operations to be performed by system 1500. System 1500 executes the application or data computation task requested by client 1502.

[0186] System 1500 may include one or more racks, which represent structural and interconnect resources for housing and interconnecting multiple computing nodes. Rack 1510 may include multiple nodes 1530. Rack 1510 may carry multiple blade assemblies 1520. Carrying can refer to providing power, structural or mechanical support, and interconnection. Blade 1520 may refer to computing resources on a printed circuit board (PCB), where the PCB houses the hardware components of one or more nodes 1530. Blade 1520 may or may not include a chassis, housing, or other “box” besides those provided by rack 1510. Blade 1520 may include a housing with exposed connectors for connection to rack 1510. System 1500 may or may not include rack 1510, and each blade 1520 may include a chassis or housing that may be stacked or otherwise closely proximate with other blades, allowing nodes 1530 to interconnect. The System 1500 can include 10,624 compute blades, comprising 63,744 Intel Max series GPUs and 21,248 Intel Xeon Max CPUs across 166 racks.

[0187] System 1500 may include architecture 1570, which represents one or more interconnectors of nodes 1530. Architecture 1570 may include multiple switches 1572 or routers or other hardware for routing signaling between nodes 1530. Furthermore, architecture 1570 may couple system 1500 to network 1504 for access by client 1502. In addition to routing devices, architecture 1570 may also be considered to include cables or ports or other hardware devices for coupling nodes 1530 together. Architecture 1570 may have one or more associated protocols for managing signaling routing through system 1500. One or more protocols are at least partially dependent on the hardware devices used in system 1500.

[0188] As shown in the figure, rack 1510 may include N blades 1520. In addition to rack 1510, system 1500 may also include rack 1550. As shown in the figure, rack 1550 may include M blades 1560. M is not necessarily the same as N; therefore, it is understood that various different hardware device components can be used and coupled together into system 1500 via structure 1570. Blades 1560 may be the same as or similar to blades 1520. Nodes 1530 may be any type of node described herein and are not necessarily of the same type. System 1500 is not limited to homogeneous or non-homogeneous structures.

[0189] The nodes in blade 1520(0) are shown in detail. However, other nodes in system 1500 may be the same or similar. At least some nodes 1530 may be compute nodes, having processor 1532 and memory 1540. A compute node is a node having processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. At least some nodes 1530 may include storage server nodes, which have servers as processing resources 1532 and memory 1540. A storage server is a node having more storage resources than a compute node, and instead of having processors for performing tasks, a storage server includes processing resources for managing access to storage nodes within the storage server.

[0190] Node 1530 may include interface controller 1534, which may represent logic for controlling node 1530's access to structure 1570. The logic may include hardware resources for interconnecting to physical interconnect hardware. The logic may include software or firmware logic for managing the interconnect. Interface controller 1534 may be or include a host structure interface, which may be a structure interface according to any embodiment described herein.

[0191] Node 1530 may include a memory subsystem 1540. Memory 1540 may include a memory computation resource (comp) 1542, which represents the ability of memory 1540 to perform one or more memory computations. System 1500 supports remote memory operations, such as, but not limited to, those described elsewhere herein. Therefore, node 1530 may request a remote node to perform a memory computation, wherein the data used for the computation remains local to the executing node and is not sent via structure 1570 or from memory to the structure interface. In response to the execution of the memory computation, the executing node may provide the result to the requesting node.

[0192] Processor 1532 may include one or more individual processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. A processing unit may be a main processor, such as, but not limited to, a CPU (Central Processing Unit), a peripheral processor (such as, but not limited to, a GPU (Graphics Processing Unit)), or a combination thereof. Memory 1540 may be or include memory devices and a memory controller.

[0193] The term "memory device" can refer to different types of memory. Memory devices generally refer to volatile memory technology. Volatile memory is memory whose state (and the data stored within it) is uncertain if the device's power is interrupted. Non-volatile memory is memory whose state is deterministic even if the device's power is interrupted. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. An example of dynamically volatile memory includes DRAM (Dynamic Random Access Memory) or variations thereof, such as, but not limited to, Synchronous DRAM (SDRAM). The memory subsystem described in this article is compatible with a variety of memory technologies, such as, but not limited to, DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electron Device Engineering Committee) on June 27, 2007, currently version 21), DDR4 (DDR version 4, initial specification released by JEDEC in September 2012), DDR4E (DDR version 4, extended version, currently under discussion by JEDEC), LPDDR3 (Low Power DDR version 3, JESD209-3B, released by JEDEC in August 2013), and LPDDR4 (Low Power Double Data Rate (LPDDR) version 4). JESD209-4 (originally released by JEDEC in August 2014), WIO2 (Wide I / O2), JESD229-2 (originally released by JEDEC in August 2014), HBM (High Bandwidth DRAM), JESD235 (originally released by JEDEC in October 2013), DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC) or combinations of other memory technologies, as well as technologies derived from or extended based on such specifications.

[0194] In addition to or as an alternative to volatile memory, in one embodiment, a reference to a memory device may refer to a non-volatile memory device whose state remains deterministic even when power is interrupted. In one embodiment, a non-volatile memory device is a block-addressable memory device, such as, but not limited to, NAND or NOR technology. Therefore, the memory device may also include future-generation non-volatile devices, such as, but not limited to, three-dimensional cross-point (3DXP) memory devices, other byte-addressable non-volatile memory devices, or memory devices using chalcogenide phase change materials (e.g., chalcogenide glasses). In one embodiment, the memory device may be or include multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase change memory (PCM) or switched phase change memory (PCMS), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) incorporating memristor technology, or spin-transfer torque (STT)-MRAM, or any combination of the foregoing, or other memories.

[0195] In at least one embodiment, system 1500 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0196] Figure 16An accelerated processing unit 1600 according to at least one embodiment is illustrated. The accelerated processing unit 1600 may include a processor based on the CDNA architecture of AMD Inc., Santa Clara, California, or other processors sharing at least some of the components described herein. The accelerated processing unit 1600 may include one or more accelerator complex dies (XCDs) 1604 for performing the operations described elsewhere in this document, such as, but not limited to, graphics processing and / or parallel processing and instruction-level parallel computing, including support for multiple precisions (INT8, FP8, BF16, FP16, TF32, FP32, and FP64) and sparse matrix data (i.e., sparsity). In some cases, the XCD may be referred to as a graphics computing die (GCD). The accelerated processing unit 1600 may include one or more complex computing dies (CCDs) 1606 for performing the operations described elsewhere in this document, such as, but not limited to, operations performed by a host processor. In some cases, the CCD may be referred to as a core complex or CCX, such as, but not limited to, the CCX used in AMD Ryzen processors. XCDs and CCDs can share any type of cache or memory (e.g., one or more memory cells 1602), or a cache or memory can be allocated to each XCD or CCD or group of XCDs or CCDs. For example, AMD Infinity Fabric within the package connects XCDs and CCDs to a shared AMD Infinity Cache 1608, and in some embodiments, to high-bandwidth memory (e.g., HMB3). Accelerated processing unit 1600 may include an AMD MI300a processor comprising three CPU die (or CCD) and six accelerator die (XCD) on top of four input-output dies (IODs) that may be layered on a single silicon die (e.g., via AMD Infinity Fabric) and linked together to eight high-bandwidth DRAM stacks in a ring to form a superchip. For systems using only accelerators, the AMD MI300x processor replaces the CCD with two or more XCDs.

[0197] Accelerated processing unit 1600 may include one or more input / output (I / O) interfaces. For example, XCD 1604 and CCD 1606 may coexist on one or more input-output dies (IODs) 1610, which may include one or more I / O interfaces. IOD 1610 may include any number and type of I / O interfaces (e.g., PCI, PCI expansion (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). Various types of peripheral devices may be coupled to I / O interfaces 1670. The I / O interfaces of IOD 1610 may also be used to connect one or more accelerated processing units 1600, for example, in a server architecture.

[0198] Accelerated processing unit 1600 may include one or more memory units 1602 for storing instructions and other information for performing the operations described in other parts of this document. Memory units 1602 may include any volatile memory, such as, but not limited to, the memory types described in other parts of this document, and may include, for example, high-bandwidth memory (e.g., HMB3) or high-bandwidth DRAM. The memory associated with accelerated processing unit 1600 (e.g., memory unit 1602) may include system memory, which can be used for, for example, commands, instructions, and constants, as well as input and output. Memory unit 1602 may also include device memory, which can be used for storage and, for example, for commands, instructions, and constants, as well as input and output, as a return buffer, and for private data. Memory unit 1602 may be linked to one or more IODs 1610. In at least one embodiment, L1 cache 1620 initiates a memory hierarchy including a shared L2 cache 1628 (e.g., within an XCD). AMD Infinity Cache TM It is the last-level cache (LLC) located on the active I / O die (IOD). The CCD 1606 and XCD1604 can have independent or shared memory. AMD Infinity architecture and AMD Infinity Fabric TM The technology enables consistent, high-throughput unification of GPU and CPU chip technologies (such as XCD, CCD, and / or CCX) with memory (such as stacked HBM3 memory) in a single device and across multiple device platforms.

[0199] like Figure 16As shown, the XCD 1604 may include a set of shared global resources 1630, which may include a hardware scheduler 1632 and an asynchronous compute engine (ACE) 1624. The ACE 1624 sends tasks (e.g., compute shader workgroups) to compute units (CUs or cores) 1634. Each of the ACEs 1624 (e.g., four) may be associated with a CU 1634 (e.g., 40 CUs), and some CUs 1634 may be disabled for yield management. CUs 1634 may have dedicated caches or shared caches (e.g., L2 caches) 1628 for consolidating all memory traffic on a single die. CU1634 may include threaded and parallel processor cores, including instruction fetching and scheduling using a scheduler (S) 1612, a matrix core unit (MCU) 1616, and a shader core (SC) 1618 (e.g., execution units for scalar, vector, and matrix data types), and a load / store pipeline with an L1 cache 1620 and a local data share (LDS) 1614. The local data share may include, for example, sticky-note RAM with built-in arithmetic capabilities, allowing data sharing between threads in a workgroup. An instruction cache 1640 (e.g., for storing and providing instructions for performing the operations described in other sections of this document) may be connected to one or more CUs and may be shared between two CUs. The matrix core 1616 can handle various data types, such as, but not limited to, INT8, FP8, FP16, BF16, and TF32 data types. Accelerated processing unit 1600 may include computation units 1634, which may be arranged in an array format, such as as a data parallel processor (DPP) array. The hyper-threaded dispatch processor 1642 can communicate with the compute unit 1634, and the command processor 1644 can read commands written by the host to memory-mapped registers in the system memory address space (not shown). When a command is completed, the command processor 1644 can send a hardware-generated interrupt to the host processor (e.g., a CCD). The memory controller 1636 can also directly access all device memories and system memory regions specified by the host. To satisfy read and write requests, the memory controller 1636 can perform the functions of a direct memory access (DMA) controller, including calculating the memory address offset based on the format of the requested data in memory. For example, one or more APIs described herein can be compiled into instructions that can be stored in the instruction cache 1640, then fetched by the instruction fetch logic in the processor 1640, decoded by the processor decoder or equivalent, scheduled (e.g., sequentially or out of order) by the scheduler or equivalent for execution, executed by the execution logic or equivalent, reordered, and then retired by the retirement logic or equivalent.The API (and / or compiled instructions including the API) can be stored in any storage device, either inside or outside the processor 1600 (e.g., in a cache and / or memory). The results of the API can be stored in storage devices, either inside or outside the processor 1600, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0200] Applications may include programs running on the main processor (e.g., a CCD) and programs running on one or more XCDs (referred to as kernels). Programs can be controlled by host commands that set internal base addresses and other configuration registers, specify data fields on which the accelerator processing unit 1600 can run, invalidate and flush caches on the accelerator processing unit 1600, and cause the accelerator processing unit 1600 to begin executing a program. A kernel can be referred to as a program executed by the accelerator processing unit 1600. Kernels can execute independently on each work item or as a group of work items, referred to as a wavefront, which can execute kernels on all (e.g., 64) work items in a single pass. The computation unit 1634 may include: a scalar arithmetic logic unit (ALU) that can operate on a single value for each wavefront (shared by all work items); a vector ALU that can operate on a unique value for each work item; a local data share 1614 that allows work items within a workgroup to communicate and share data; a scalar memory (not shown) that can transfer data between the scalar general-purpose registers (SGPRs) and memory via cache; and a vector memory that can transfer data between the vector general-purpose registers (VGPRs) and memory, including sampling of texture maps. Kernel control flow can be manipulated using scalar ALU instructions, which may include if / else statements, branches, and loops. Scalar ALU (SALU) and memory instructions can operate on the entire wavefront and operate on one or more SGPRs. Vector memory and ALU instructions can operate on all work items in the wavefront simultaneously.

[0201] In at least one embodiment, the acceleration processing unit 1600 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0202] Figure 17Processor 1700 is shown, including, but not limited to, a Zen architecture-based processor (e.g., Zen1, 2, 3, 4, 5, or other architectures) from AMD Inc. of Santa Clara, California, or other processors that share at least some of the components described herein. Processor 1700 includes one or more CPU dies 1702(1)-1702(N), where N is any integer greater than 1. CPU die 1702 may include any number of processor cores 1716 (e.g., for performing any operations described elsewhere herein) and any number of cache memories (e.g., for storing instructions and other information to perform any operations described elsewhere herein). For example, L2 cache unit 1718 may be coupled to processor core 1716, and processor core 1716 may share and / or be individually coupled to L2 cache unit 1718. Processor core 1716 can be coupled to L3 cache 1722 and / or a shared L3 cache, which can be the lowest level cache (LLC) 1722 used to access data and other information used by processor core 1716. One or more processor cores 1716 and one or more L2 cache units 1718 can be included in a core complex (CCX) 1720, which can include (e.g., 32MB) a shared cache (e.g., L3 cache 1722). Core complex 1720 can be manufactured onto a die (CCD or CPU die) 1702. For example, up to 12 core complexes 1720 can be configured into a processor along with 8 CPU dies 1702, providing up to 96 processor cores 1716 for the processor. For example, a "Zen 4c" core complex 1720 can include up to 8 cores 1716 and a shared 16MB L3 cache 1722. Two core complexes from these core complexes 1720 can be combined onto a single CPU die 1702, resulting in 16 cores per die and a total of 32MB of L3 cache per die 1722. Up to eight CPU dies 1702 can be combined with I / O units 1704 to provide up to 128 processor cores 1716 for the CPU. Up to four "Zen 4c" dies mentioned above can be combined to provide up to 64 processor cores 1716 for the CPU.

[0203] Processor 1700 may include various configurations for input / output operations, which will be further described herein. I / O unit 1704 may include one or more memory controllers 1706 capable of managing the memory usage of processor 1700 (e.g., DDR5 memory). I / O unit 1704 may include one or more SATA disk controllers for managing storage device 1712, and one or more Compute Express Links (CXL) for providing CPU-to-device and CPU-to-memory connectivity, which can be flexibly assigned to specific functions during server design. TM 1.1+ Memory controller 1714. I / O unit 1704 may include PCIe controller 1708 for connecting peripherals and other components connected to processor 1700. I / O unit 1704 may also include USB port 1710 for connecting to other components separate from processor 1700. CPU die 1702 may support any number of connections to I / O unit 1704, for example, one or two connections. As shown, I / O unit 1704 may include components further described herein, and I / O unit 1704 may be an I / O die accommodating several different components. Memory controller 1706, PCIe controller 1708, USB port 1710, SATA controller 1712 and / or CXL controller 1714 may be individually integrated into any location within processor 1700, or integrated in any group or combination.

[0204] Processor 1700 may include an Infinity Fabric 1724 interconnect (which may be similar to or based on a PCIe architecture) that provides connectivity between the CPU (e.g., CPU die 1702(1)-1702(N)), graphics processor 1726, inference engine 1732, and other components in a multi-chip architecture (e.g., security processor 1728 and I / O unit 1704). One or more AMD Infinity Fabrics TM Interconnect 1710 can be connected to CPU dies 1702(1)-1702(N) and used as a connection between CPUs. One or more Infinity Fabric connections 1710 can connect each CPU die 1702 to the I / O unit 1710.

[0205] In at least one embodiment, processor 1700 may include a central processing unit (CPU) and other related hardware and software described above and further herein. Processor 1700 may also include a graphics processor 1726. Graphics processor 1726 may be used for image generation and processing, as well as other computations and operations described further herein. Graphics processor 1726 may be based on AMD's RDNA 3 or 3.5 architecture, located in Santa Clara, California. Graphics processor 1726 may include a graphics computing die (GCD) and a memory cache die (MCD). GCD may include any number of computing units (CUs) for graphics or other processing, such as operations performed by an arithmetic logic unit (ALU) described further herein. Graphics processor 1726 may include an L2 cache available for use by the computing units. MCD (not shown) may include any number of memory cells and may include a cache (e.g., an L3 cache) and a memory interface for coupling to memory (e.g., memory 1742(1)-(N), where N is an integer). Components within the graphics processor 1726 can be connected using various methods, such as using Infinity Fabric 1724 interconnects, either internally or externally to the graphics processor 1726.

[0206] Inference engine 1732 can provide neural processing capabilities to processor 1700 for computational processes used in neural networks, deep learning, and other AI-related operations described further herein. Processor 1700 may include: a security processor 1728 for managing the security of processor 1700; a display controller 1730 for controlling the display; a system management unit 1734 for managing and operating some or all components on processor 1700; a multimedia engine 1736 for audio and video operations; a fusion controller hub 1738 for managing USB, SATA, and PCIe connections to the processor; and a sensor fusion hub 1740 for managing sensors (e.g., accelerometers). Processor 1700 may also include memory 1742(1)-(N), where N is any integer. Memory may include different memory types, such as LPDDR5 and / or DDR5, or other memory described elsewhere herein.

[0207] To perform the operations further described herein, processor 1700 may include an execution pipeline including a front end that may include a cache for storing instructions (e.g., an L1 cache) (not shown). A branch predictor may modify the instruction stream. Instructions may be decoded by a decoder, dispatched to a back end for execution, and renamed. For example, the instruction fetch and decode pipeline may be dispatched to integer or floating-point execution operations, which may be scheduled by a scheduler and passed to vectors and / or general-purpose registers. Floating-point multipliers and / or addition operations may be processed, and an arithmetic logic unit (ALU) may also be used to perform computations, such as arithmetic and logical operations. The output of the computation unit may be coupled to a load / store queue that may be connected to a cache, such as an L1 cache and / or an L2 cache.

[0208] With respect to the processor 1700 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may be compiled, for example, into instructions or equivalents (e.g., AVX-512 instructions based on a SIMD model). These instructions or equivalents may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. The APIs (and / or compiled instructions including the APIs) may be stored in any storage device, either internal or external to the processor (e.g., in caches and / or memory). The results of the APIs may then be stored in storage devices, either internal or external to the processor, including registers, DRAM, flash memory, SRAM, caches, or other memory equivalents.

[0209] In at least one embodiment, processor 1700 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0210] Figure 18 An example of a processing core 1800 is shown, which may implement an Arm architecture (e.g., v9.0-A) or other processors that share at least some of the components described herein. Neoverse TMThe V2 core 1800 can be implemented within a DynamIQ shared unit (DSU) cluster via a DSU-110 interconnect 1854 for connecting one or more cores, for example, for parallel processing. Neoverse TM The V2 core can be implemented as a single core in a DSU cluster configured for direct interconnection, with or without L3 cache, listener filter, or listener control unit (SCU) logic (not shown). Neoverse TMThe V2 core may include a CPU bridge 1852 for connecting core 1800 to the DSU-110 interconnect. This bridge may also connect core 1800 to an external memory system and the remainder of the on-chip system. The L1 instruction memory system 1802 may fetch instructions from instruction cache 1804 and deliver instructions (e.g., one or more compileable APIs described herein) to instruction decoding unit 1810, for example, to perform some or all of the operations described above or elsewhere herein. The L1 instruction memory system 1802 may include L1 instruction cache 1804 (e.g., with 64-byte cache lines), L1 instruction translation back buffer (TLB) 1806 (e.g., natively supporting 4KB, 16KB, 64KB, and 2MB page sizes), and macro operation cache (MOP) 1808 (e.g., a 1536-entry, 4-way skewed associated L0 MOP cache), which may include decoded and optimized instructions for higher performance. Instruction decoding unit 1810 may decode AArch64 instructions into its internal format. The register renaming unit 1812 can perform register renaming to facilitate out-of-order execution and dispatch decoded instructions to various issue queues. The instruction issuing unit 1814 can control when decoded instructions are dispatched to the execution pipeline, and it can include an issue queue for storing instructions to be dispatched to the execution pipeline. The integer execution pipeline 1816 can be included in the execution pipeline and includes an integer execution unit 1818 that can perform arithmetic and logical data processing operations. The vector execution unit 1820 can be included in the execution pipeline and can execute advanced SIMD and floating-point arithmetic (FPU) 1822, execute Scalable Vector Extension (SVE) and Scalable Vector Extension 2 (SVE2) instructions 1824, and can also selectively execute cryptographic instructions 1826. The advanced SIMD can include a media and signal processing architecture that primarily adds instructions for audio, video, 3D graphics, image, and speech processing. The floating-point architecture provides support for single-precision and double-precision floating-point operations. The L1 data memory system 1830 executes load and store instructions, as well as service memory coherence requests. The L1 data memory system 1830 may include an L1 data cache 1832 and a fully associative L1 data TLB 1834, natively supporting 4KB, 16KB, and 64KB page sizes and 2MB and 512MB block sizes. The memory management unit (MMU) 1828 provides fine-grained memory system control through a set of virtual-to-physical address mappings and memory attributes, which are stored in a translation table and saved to the TLB 1834 after address translation. The L2 memory system 1836 may include an L2 cache 1838 and can be connected to the DSU-110 1854 via an asynchronous CPU bridge 1852. TMThe V2 core 1800 supports a range of debugging, testing, and tracing options, including the tracing unit 1842, the tracing buffer 1840, and the embedded logic analyzer (ELA) 1848. Neoverse TM The V2 core 1800 implements the Statistical Analysis Extension (SPE) 1844, which provides a statistical view of the performance characteristics of executed instructions. Software writers can leverage these views to optimize code for better performance. The Performance Monitoring Unit (PMU) 1846 provides a performance monitor that can be configured to collect statistics on the operation of each core and memory system. This information can be used for debugging and code analysis. The General Purpose Interrupt Controller (GIC) CPU interface 1850, when integrated with external allocator components, serves as a resource for supporting and managing interrupts in a cluster system. In a cluster, each Neoverse... TM There can be a CPU bridge 1852 between the V2 core 1800 and the DSU-110 1854. The CPU bridge 1852 can control the buffering and synchronization between the core 1800 and the DSU-110 1854. The CPU bridge 1852 can be asynchronous to allow each core 1800 to use a different frequency, power, and area implementation point. The CPU bridge 1852 can operate synchronously without affecting other interfaces, such as, but not limited to, asynchronous debug and tracing interfaces.

[0211] In at least one embodiment, core 1800 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0212] Figure 19 One or more chips including one or more tensor processing units (TPUs) 1900 are shown according to at least one embodiment. Figure 19 The TPU 1900 may include an application-specific integrated circuit (ASIC), for example, for performing some or all of the operations described above or elsewhere herein, such as, but not limited to, machine learning workloads that accelerate the execution of matrix operations. The TPU 1900 may be an ASIC from Alphabet Corporation, Mountain View, California. The cloud TPU includes a cloud service that enables the TPU to be used as a scalable resource for processing tasks, such as, but not limited to, machine learning workloads that can run on frameworks such as, but not limited to, TensorFlow, PyTorch, and JAX.

[0213] Chip 1900 may include any number of TPUs, which may include a tensor core 1906. Tensor core 1906 may include one or more core sequencers 1908, vector processing units (VPUs) 1910, matrix multiplication units (MXUs) 1912(A)-1914(N) (where N is any integer greater than 1), and transpose permutation units 1916. Core sequencer 1908 may fetch instructions (e.g., VLIW (Very Long Instruction Word)) from the instruction memory (Imem) of core 1906, perform scalar operations using scalar data memory (Smem) and scalar registers (Sregs) (not shown), and forward vector instructions to the vector processing units (VPUs) 1910. For example, an instruction may initiate eight operations: two scalar operations, two vector ALU operations, vector loading and storing, and queuing data into the matrix multiplication and transpose units and a pair of slots for queuing data from them. The VPU1910 can perform vector operations using a large on-chip vector memory (Vmem) and vector registers (Vregs). The VPU1910 can stream data to or from the MXU via a decoupled FIFO. The VPU1910 can collect and distribute data to the Vmem using both data-level parallelism (2D matrix and vector function units) and instruction-level parallelism (8 operations per instruction). Large two-dimensional matrix multiplication units (MXUs) 1912(A)–1912(N) can, for example, use a systolic array to reduce area and power consumption, and use a large, software-controlled on-chip memory instead of a cache. The transpose-reduction-permute unit 1916 can perform (e.g., 128x128) matrix transpose, reduction, and permute on the VPU1910 channels. A high-bandwidth memory 1904 can be used for on-chip applications. One or more chips 1900 can be connected together for computation. For example, one or more chips 1900 can be connected to form a torus, such as a 2D torus. Chip 1900 may also include any number (e.g., 4) of inter-core interconnect (ICI) links 1918, which can enable direct connections between chips to form a supercomputer.

[0214] For any processor in chip 1900 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device external to or internal to the processor (e.g., in cache and / or memory). The results of the APIs may then be stored in storage devices internal to or external to the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0215] In at least one embodiment, chip 1900 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configurable to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0216] Figure 20A vector processor according to at least one embodiment is illustrated. The vector processor 2000 may support the RISC-V standard. The vector processor 2000 may include one or more cores 2010 (e.g., scalar units) and one or more vector processing units (VPUs) 2042 (e.g., vector units), which may, for example, perform some or all of the operations described above or elsewhere herein. The core 2010 may include an Andes Custom Extension (ACE) 2016, which can be used to deliver custom instructions to the processor 2000. The core 2010 may include a 1-cycle multiplier and a 1-cycle instruction / data local memory (ILM / DLM) for improving parallelism by allowing simultaneous instruction fetching and data access. A memory management unit (MMU) 2024 manages system memory and cache, and provides branch execution, instruction pair issuance, L1 instruction / data cache, and local memory storage. The core 2010 may include a physical memory protection and programmable physical memory attribute unit (PMP / PPMA) 2022. Core 2010 may include a digital signal processor (DSP) 2028 and a floating-point unit (FPU) 2026, as well as a load-memory unit (LSU) 2032 for interaction with memory hierarchies (D$2034 and I$2030). Core 2010 may include a branch prediction unit 2018 and a multiplier unit 2020.

[0217] The vector processing unit (VPU) 2042 may include one or more vector function units (FU) 2046(A)-2046(N) (these vector function units may be linked together for parallel processing), a separate memory path for loading / storing RISC-V vectors (RVV) via ACE-RVV 2048 and AndesStreaming port (ASP) 2044, and a vector load / store unit (VLSU) 2050.

[0218] The vector processor 2000 may include bus interfaces, such as, but not limited to, a cacheable L2 cache port 2056, a non-cacheable MMIO port 2054, an input-output coherence port (IOCP) 2058 for a cacheless bus master, a local memory access port for ILM / DLM 2012 and high-bandwidth vector memory (HVM) 2036 access, and a shared peripheral port (SPP) 2052 for external peripherals. Other memory ports include an LM slave port AXI 2002 and an HVM subordinate port AXI 2004.

[0219] For any processor of the processor 2000 and any components described above or elsewhere herein, one or more APIs or equivalents described herein may, for example, be compiled into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. The API (and / or compiled instructions including the API) may be stored in any storage device external to or internal to the processor (e.g., in cache and / or memory). The results of the API may then be stored in storage devices internal to or external to the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0220] In at least one embodiment, the vector processor 2000 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0221] Figure 21A A schematic diagram of an example multi-core tiled processor microarchitecture is shown. Figure 21A Multi-core tiled processors in a system can include language processing processors. For example... Figure 21A As shown, each “tile” in the processor architecture is a processing element bundled together using an on-chip network (NoC) that can be used to perform some or all of the operations described above or elsewhere in this document. For example, each tile may have an instruction dispatch 2104 and integer (INT) units 2106 and floating-point (FP) units 2108, a load-memory unit (LSU) 2112 for engaging with the memory hierarchy (data cache (D$) 2110 and instruction cache (I$) 2114), and a network (NET) interface 2116 for communicating with other tiles in the architecture. Some tiles in processor 2100 may include a memory controller 2102 for managing and controlling memory, as further described herein. Processor 2100 may have a functionally sliced ​​architecture. Processor 2100 may reside on an application-specific integrated circuit (ASIC). Figure 21AThe layout of an ASIC can be represented. Processor 2100 may include a coprocessor designed to execute instructions for a predictive model. A predictive model refers to any model configured to make predictions based on input data. The predictive model can use a classifier for classification predictions. The predictive model can be a machine learning model, such as, but not limited to, a tensor flow model, and processor 2100 is a tensor flow processor.

[0222] The processor 2100 can employ different microarchitectures, which will Figure 21B Each tile in the process represents a separate functional unit. Conversely, the functional tiles of processor 2100 can be aggregated into multiple functional processing units (hereinafter referred to as "slices") 2104, each corresponding to a specific functional type (e.g., FP / INT, NET, MEM). For example, as... Figure 21B As shown, each slice may correspond to a row of functional tiles extending in a north-south direction. Furthermore, the processor may include communication channels for carrying data between tiles in different slices, each communication channel extending horizontally in an east-west direction. Each communication channel may be connected to each slice 2104 of the processor 2100.

[0223] The slices 2104 of processor 2100 may each correspond to different functions and may include arithmetic logic slices (e.g., FP / INT), channel switching slices (e.g., NET), and memory slices (e.g., MEM). Arithmetic logic units can perform one or more arithmetic and / or logical operations on data received via a communication channel to generate output data. Examples of arithmetic logic units may be matrix multiplication units and vector multiplication units. Memory slices include memory units that store data. Memory slices can provide data to other slices via communication channels. Memory slices can also receive data from other slices via communication channels. Channel switching slices can configurably route data from one communication channel to any other communication channel. For example, data from a first channel can be provided to a second channel via a channel switching slice. In some embodiments, a channel switching slice can be implemented as a crossbar switch. Each slice 2104 also includes its own instruction queue (not shown) for storing instructions and an instruction control unit (ICU) for controlling instruction execution. Instructions in a given instruction queue can only be executed by a tile in its associated functional slice and not by other slices of the processor.

[0224] By arranging the tiles of processor 2100 into different functional slices 2104, the on-chip instruction and control flow of processor 2100 can be separated from the data flow. For example, according to some embodiments, Figure 21B One of the arrows illustrates the instruction flow within the processor architecture. According to at least one embodiment, Figure 21BAnother arrow in the diagram illustrates the data flow within the processor architecture. As shown, instruction and control flow can flow across the tiles of processor 2100 in a first direction (e.g., north-south along the length of a functional slice, as indicated by the first arrow), while data flow can flow across the tiles of processor 2100 in a second direction (e.g., east-west across a functional slice, as indicated by the second arrow), which is perpendicular to the first direction.

[0225] Different functional slices of the processor can correspond to MEM (Memory), VXM (Vector Execution Module), MXM (Matrix Execution Module), NIM (Numerical Interpretation Module), and SXM (Exchange and Permutation Module). Each slice can include N tiles, all of which can be controlled by the same Instruction Control Unit (ICU) (not shown). Each slice can operate completely independently and can only be coordinated using barrier-like synchronization primitives or by the compiler leveraging tractable determinism. Each tile of the processor can correspond to an execution unit organized as ×M SIMD tiles. For example, each tile of the processor's on-chip memory can be organized to atomically store L-element vectors. Thus, a MEM slice with N tiles can work together to store or process large vectors (e.g., with a total of N×M elements).

[0226] Tiles within the same slice can execute instructions in an "interleaved" manner, where instructions can be issued tile-by-tile within the slice over N cycle periods. Functional slices can be physically arranged on the chip to allow efficient data flow for pipelined execution over hundreds of cycles for common patterns. The data flow can perform a single "u-turn" (direction change) corresponding to a single matrix operation before being written back to memory; in some embodiments, a particular data flow can change direction multiple times before writing the resulting data back to memory (due to multiple matrix and vector operations).

[0227] To achieve good single-threaded performance, conventional multi-core processor designs (e.g., ...) Figure 21A As shown, a significant portion of silicon area typically needs to be dedicated to exposing and utilizing instruction-level parallelism (ILP). This often involves register renaming schemes and large instruction windows where instructions lack explicit understanding of the hardware on which they will execute, while maintaining the illusion that programs execute sequentially. In contrast, when using processors with a function slice architecture (e.g., TSP), the TSP compiler generates an explicit plan of how the processor will execute microprograms. The compiler can specify when each operation will execute, which function slices will perform the work, and which STREAM registers will hold operands. The compiler can maintain a high-fidelity (cycle-accurate) model of the TSP's hardware state so that microprograms can coordinate data flow.

[0228] Processor 2100 (e.g., TSP) can use a web-hosted compiler that takes a model (e.g., an ML model, such as, but not limited to, a TensorFlow model) as input and issues a proprietary stream of instructions for the processor TSP hardware. The compiler is responsible for coordinating the program's control and data flow and specifying any instruction-level parallelism by explicitly bundling instructions that can and should be executed concurrently so that they can be dispatched together. The primary hardware architecture is the architecture-visible streaming register file (STREAM), described in more detail below, which acts as a conduit for operands to flow from MEM slices (e.g., SRAM) to functional slices (and vice versa).

[0229] The processor's MEM cells can be used for: (1) storage of model parameters, microprograms, and the data on which they operate; and (2) the on-chip network (NoC) for transferring data operands from the MEM to functional slices and returning computation results to the MEM. In some embodiments, the on-chip memory may consume approximately 75% of the processor chip area. In some embodiments, the on-chip memory of the MEM tiles may include SRAM instead of DRAM due to the processor's bandwidth requirements. The processor's on-chip memory capacity can be determined by: (i) the number of ML models that can reside on the chip simultaneously, (ii) the size of any given model, and (iii) partitioning of large models to fit a multi-chip system. In some embodiments, the processor's MEM system may provide multiple memory slices organized into two distinct hemispheres (referred to as "MEM WEST" and "MEMEAST," respectively).

[0230] The memory slices in each hemisphere can be mirrored such that the slices are physically numbered {0,...L} in the eastern hemisphere 410 and {L,...0} in the western hemisphere 405, such that memory slice 0 in each hemisphere corresponds to the slice of the VXM slice 415 closest to the hemisphere, where each hemisphere comprises L slices. The direction of data transfer towards the chip center can be referred to as inward, while data transfer towards the outer edge of the chip (easternmost or westernmost) can be referred to as outward. Although the processor's memory hemispheres can be referred to as east and west, it is understood that other names may be used to refer to different memory hemispheres in other embodiments.

[0231] In some embodiments, streaming register files (referred to as STREAMS) transfer operands and results between the SRAM of a processor's MEM slice and the functional slice. In some embodiments, multiple MEM slices (e.g., 2 to 10 adjacent MEM slices) can be physically organized into sets. Each slice set can be located between a pair of STREAMS register files, allowing each slice to read from or write to the STREAMS registers in either direction. By placing STREAMS register files between MEM slice sets, the number of cycles required to transfer data operands across hemispheres can be reduced (e.g., reduced by a factor corresponding to the number of slices per set). The number of slices per set can be configured based on the distance of data transfer within a single clock cycle.

[0232] for Figure 21A Any processor and any components described above or elsewhere herein, one or more APIs or equivalents described herein may be compiled, for example, into instructions or equivalents that may be fetched by instruction fetching logic or equivalents, decoded by processor decoder or equivalents, scheduled (e.g., sequentially or out of order) for execution by scheduler or equivalents, executed by execution logic or equivalents, reordered, and then retired by retirement logic or equivalents. APIs (and / or compiled instructions including APIs) may be stored in any storage device inside or outside the processor (e.g., in cache and / or memory). The results of the APIs may then be stored in storage devices inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory equivalents.

[0233] In at least one embodiment, processor 2100 may include one or more circuits configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere. The one or more circuits may be software-configured to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any operations described herein above or elsewhere.

[0234] Software Structure

[0235] The following figures illustrate, in a non-limiting manner, examples of software structures for implementing at least one embodiment.

[0236] Figure 22A software stack of a programming platform according to at least one embodiment is illustrated. The programming platform may include a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. The programming platform may be CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL... TM Developed by the Khronos Group), SYCL, or Intel OneAPI.

[0237] The software stack 2200 of the programming platform can provide an execution environment for the application 2201. The application 2201 can include any computer software that can be launched on the software stack 2200. The application 2201 can include artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0238] Application 2201 and software stack 2200 run on hardware 2208. Hardware 2208 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting programming platforms. Software stack 2200 may be vendor-specific and compatible only with vendor-specific devices, such as CUDA, ROCm, OneAPI, OpenCL, or other implementations. Hardware 2208 may include a host connected to one or more devices that can be accessed via application programming interface (“API”) calls to perform computational tasks. In at least one embodiment, the devices within hardware 2208 may include GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory, while the host within hardware 2208 may include CPUs (but may also include computing devices) and their memory. For any hardware 2208 described above or elsewhere herein, the one or more APIs described herein may, for example, be compiled into instructions that may be fetched by instruction fetching logic, decoded by a processor decoder, scheduled (e.g., sequentially or out of order) for execution by a scheduler, executed by execution logic, reordered, and then retired by retirement logic. APIs (and / or compiled instructions including APIs) can be stored in any storage device, either inside or outside the processor (e.g., in cache and / or memory). The results of an API can be stored in storage devices, either inside or outside the processor, including registers, DRAM, flash memory, SRAM, cache, or other memory. One or more APIs described herein may include calls. One or more APIs described herein may include a library or part of a library to perform the function described by the call. One or more APIs described herein may include calls and a library or part of a library to perform the function described by the call.

[0239] The software stack 2200 of the programming platform may include multiple libraries 2203, a runtime 2205, optional drivers / interfaces 2207, and device kernel drivers 2208. Each library 2203 may include data and programming code that can be used by computer programs and utilized during software development. Library 2203 may include pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. Library 2203 may include functionality optimized for execution on one or more types of devices. Library 2203 may include functionality for performing mathematical, deep learning, and / or other types of operations on the device. Library 2203 may be associated with corresponding APIs 2202, which may include one or more APIs for exposing the functionality implemented in library 2203. A processor (e.g., CPU, GPU) may execute, call, or otherwise use one or more APIs to determine kernel priority. For example, a first kernel (e.g., a parent kernel) may launch a second kernel (e.g., a child kernel), and the processor may use the second kernel to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. The processor can execute APIs or call APIs from memory to support dynamic stream priorities (e.g., updating priorities when performing operations using streams). For example, when the processor executes the API, it allows the programmer to copy stream priorities from one stream to one or more other streams.

[0240] Software stack 2200 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to set the stream's priority at any time after the stream is created. Software stack 2200 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to obtain the stream's current priority, where the priority is one of several attributes of the stream. Software stack 2200 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to obtain the stream's current priority as a single attribute. Software stack 2200 may include APIs that support dynamic stream prioritization (e.g., updating priority while performing operations on the stream), allowing programmers to start the kernel to perform operations on the stream at a set priority, which may be different from the stream priority. Software stack 2200 may include an API for indicating whether an object (e.g., a thread synchronization object, such as, but not limited to, a barrier) tracks whether all data movement operations of a set of threads running on the GPU have a specified state after a specified time period, wherein the specified state may be a state indicating that data has been moved and is ready for use, and is specified using expected parity values ​​as input to the API.

[0241] Software stack 2200 may include one or more APIs for updating the kernel. The processor may execute APIs or call APIs from memory to update existing APIs, thereby supporting a context-independent kernel. This allows programmers to add kernel nodes to a graph without a graph context, so that the graph context can be dynamically associated with the kernel at runtime. Software stack 2200 may include one or more APIs that allow programmers to obtain kernel identifiers and graph contexts as separate parameters from kernel nodes, thereby enabling parameter retrieval from both the kernel and the context-independent kernel. Software stack 2200 may include one or more APIs that use parallel processors (e.g., but not limited to one or more graphics processing units) to initiate task graphs (e.g., task graphs) and execute one or more task graphs (e.g., including one or more programs).

[0242] Software stack 2200 may include one or more APIs for associating one or more instructions with one or more memory sorting operations (e.g., but not limited to fence or memory barrier operations). Instructions may be associated with one or more domains, causing memory sorting operations to execute in association with one or more specific domains without interfering with instructions in other domains. APIs may indicate that a thread has reached (e.g., reached a thread synchronization barrier) or completed a certain phase of work associated with an asynchronous data movement operation on the GPU. Software stack 2200 may include one or more APIs that allow programmers to manually indicate an expected transaction count when a thread completes a certain phase of work; this transaction count can be used to update an object used to track whether all data movement operations for a set of threads have been completed.

[0243] Application 2201 can be written as source code and then compiled into executable code, as described below. Figure 23 and Figure 24 As discussed in more detail, the executable code of application 2201 can run, at least partially, within the execution environment provided by software stack 2200. During the execution of application 2201, code that needs to run on the device (rather than the host) may be encountered. In this case, runtime 2205 can be invoked to load and launch the required code on the device. Runtime 2205 can include any technically feasible runtime system capable of supporting the execution of application 2201.

[0244] Runtime 2205 can be implemented as one or more runtime libraries associated with a corresponding API (shown as API 2204). One or more such runtime libraries may include functions for memory management, execution control, device management, error handling, and / or synchronization, etc. Memory management functions may include functions for allocating, dealing with, and copying device memory, as well as functions for transferring data between host memory and device memory. Execution control functions may include functions for launching functions on the device (sometimes referred to as the "kernel" when the function is a global function that can be called from the host) and setting attribute values ​​in buffers maintained by the runtime libraries so that a given function can be executed on the device.

[0245] Runtime libraries and corresponding APIs 2204 can be implemented in any technically feasible manner. One (or any number) of APIs can expose a set of low-level functions for fine-grained control of the device, while another (or any number) of APIs can expose a set of high-level functions for such functions. High-level runtime APIs can be built on top of low-level APIs. One or more runtime APIs can be language-specific APIs, which can be layered on top of language-independent runtime APIs.

[0246] Optional drivers or interfaces 2207 can be implemented, for example, for CUDA and ROCm implementations, which will be described further below. Optional drivers / interfaces 2207 can be associated with optional driver or interface APIs, such as, but not limited to, CUDA and / or ROCm APIs.

[0247] One or more processors disclosed in the “processing system” may execute, access, or otherwise use the software stack 2200. For example, the system-on-a-chip 900, parallel processor 1000, graphics multiprocessor 1034, processor 1100, processor 1200, accelerator 1300, neuromorphic processor 1405, supercomputer 1500, acceleration processing unit 1600, processor 1700, processor 1800, tensor processing unit 1900, processor 2000, and language processing unit 2100 may execute, use, call, or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 2200.

[0248] Device kernel driver 2208 can be configured to facilitate communication with the underlying device. Device kernel driver 2208 can provide low-level functionality for APIs (such as, but not limited to, API 2204) and / or other software. Device kernel driver 2208 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. For CUDA or other implementations (such as, but not limited to, ROCm, OneAPI, or OpenCL), device kernel driver 2208 can compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code for a specific target device at runtime (and cache the compiled binary code), which is sometimes referred to as “finalized” code. Doing so allows the finalized code to run on a target device that may not have existed when the source code was initially compiled into PTX code. Alternatively, the device source code can be compiled into binary code offline without device kernel driver 2208 compiling the IR code at runtime.

[0249] Processors described elsewhere in this document (e.g., but not limited to) Figure 9-21B The processor (in the document) may include one or more circuits that cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be configured by software (e.g., software stack 2200) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0250] According to at least one embodiment, Figure 22 The software stack 2200 can execute in a CUDA implementation. The CUDA software stack 2200, on which the application 2201 can be launched, may include CUDA libraries 2203, CUDA runtime 2205, CUDA driver 2207, and device kernel driver 2208. The CUDA software stack 2200 can execute on hardware (e.g., a graphics multiprocessor 1134, which may include a CUDA-enabled GPU developed by NVIDIA Corporation, Santa Clara, California).

[0251] Application 2201, CUDA runtime 2205, and device kernel driver 2208 can perform the functions described above and elsewhere in this document. CUDA driver 2207 may include a library (libcuda.so) that implements CUDA driver API 2206. Similar to CUDA runtime API 2204 implemented by the CUDA runtime library (cudart), CUDA driver API 2206 exposes functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. CUDA driver API 2206 differs from CUDA runtime API 2204 in that CUDA runtime API 2204 simplifies device code management by providing implicit initialization, context (similar to processes), and module (similar to dynamically loaded libraries) management. Compared to the high-level CUDA runtime API 2204, CUDA driver API 2206 can serve as a low-level API, providing finer-grained device control, especially in terms of context and module loading. CUDA Driver API 2206 can expose context management functions not exposed in CUDA Runtime API 2204. CUDA Driver API 2206 can also be language-agnostic, supporting technologies such as OpenCL in addition to CUDA Runtime API 2204. Furthermore, development libraries, including CUDA Runtime 2205, can be considered separate from driver components, including user-mode CUDA Driver 2207 and kernel-mode device driver 2208 (sometimes referred to as the "display" driver).

[0252] CUDA library 2203 may include mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (such as, but not limited to, application 2201) may utilize. CUDA library 2203 may include mathematical libraries, such as, but not limited to, the cuBLAS library (an implementation of the basic linear algebra subroutine (“BLAS”) for performing linear algebra operations), the cuFFT library (for computing the Fast Fourier Transform (“FFT”)), and the cuRAND library (for generating random numbers), etc. CUDA library 2203 may include deep learning libraries, such as, but not limited to, the cuDNN primitive library for deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0253] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to Figure) Figure 9-21BThe processor (in the document) may include one or more circuits that cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be configured by software (e.g., software stack 2200) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0254] According to at least one embodiment, Figure 22 The software stack 2200 can execute in the ROCm implementation. An application 2201 can be launched on the ROCm software stack 2200, which includes a language runtime 2203, a system runtime 2205, a thunk 2207, and a ROCm kernel driver 2208. The ROCm software stack 2200 executes on hardware 2209, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0255] Application 2201 is executable and can be combined with the above. Figure 22 Similar functionality to that discussed. Furthermore, the language runtime 2203 and system runtime 2205 can execute functions related to the above. Figure 22 The runtime discussed is similar in functionality to 2205. The difference between the language runtime 2203 and the system runtime 2205 is that the system runtime 2205 is a language-independent runtime that implements the ROCr System Runtime API 2204 and uses the Heterogeneous System Architecture (“HSA”) runtime API. The HSA runtime API may include a streamlined user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control via kernel architecture dispatch, error handling, system and agent information, and runtime initialization and shutdown. Unlike the system runtime 2205, the language runtime 2203 may be an implementation of the language-specific runtime API 2202, which sits in a layer above the ROCr System Runtime API 2204. The language runtime API may include the Heterogeneous Computing Portable Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. HIP is an extension of the C++ programming language, offering a functionally similar version to the CUDA mechanism. Furthermore, the HIP runtime API can include features related to the above. Figure 22The discussion covers functions similar to those in the CUDA runtime API, such as, but not limited to, memory management, execution control, device management, error handling, and synchronization.

[0256] The Thunk(ROCt)2207 can be interface 2206, which is used to interact with the underlying ROCm driver 2208. The ROCm driver 2208 can be the ROCk driver, a combination of the AMD GPU driver and the HSA core driver (amdkfd). The AMD GPU driver can be a device core driver developed by AMD for GPUs, performing functions similar to those described above. Figure 22 The device kernel driver discussed is similar to the 2209. An HSA kernel driver can be a driver that allows different types of processors to share system resources more efficiently through hardware features.

[0257] Various libraries (not shown) may be included in the ROCm software stack 2200 on top of the language runtime 2203, and provide integration with the above. Figure 22 The discussion focuses on CUDA library 2203 and similar functionality. Various libraries can include mathematical libraries, deep learning libraries, and / or other libraries, such as, but not limited to, the hipBLAS library which implements functionality similar to CUDA cuBLAS, the rocFFT library for computing FFTs similar to CUDA cuFFT, etc.

[0258] Processors described elsewhere in this document (e.g., but not limited to) Figure 9-21B The processor (in the document) may include one or more circuits that cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be configured by software (e.g., software stack 2200) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0259] According to at least one embodiment, Figure 22 The software stack 2200 can execute in an OpenCL implementation. The OpenCL software stack 2200, on which the application 2201 can be launched, may include the OpenCL framework 2203, the OpenCL runtime 2205, and a driver 2208. The OpenCL software stack 2200 can execute on non-vendor-specific hardware 2209. Because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with the hardware of those vendors.

[0260] Application 2201, OpenCL runtime 2205, device kernel driver 2208, and hardware 2209 can execute in combination with the above. Figure 22 Other implementations of the discussed application 2201, runtime 2205, device kernel driver 2208, and hardware 2209 offer similar functionality. Application 2201 may also include an OpenCL kernel (not shown), whose code will execute on the device.

[0261] OpenCL can define a "platform" that allows a host to control devices connected to it. The OpenCL framework provides platform-level APIs and runtime APIs, shown as Platform API 2202 and Runtime API 2204, respectively. Runtime API 2204 uses contexts to manage kernel execution on devices. Each identified device can be associated with a corresponding context, which Runtime API 2204 uses to manage the device's command queue, program objects, kernel objects, shared memory objects, and so on. Platform API 2202 exposes functions that allow the use of device contexts to select and initialize devices, submit work to devices via command queues, and enable data transfer with devices. In addition, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions.

[0262] The OpenCL framework 2203 may also include a compiler (not shown). Source code can be compiled offline before application execution or online during application execution. Unlike CUDA and ROCm, OpenCL applications can be compiled online by a compiler, which represents any number of compilers that can be used to compile source code and / or IR code (e.g., but not limited to Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, OpenCL applications can be compiled offline before execution.

[0263] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to) Figure 9-21B The processor (in the document) may include one or more circuits that cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be configured by software (e.g., software stack 2200) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0264] According to at least one embodiment, the software may be supported by a programming platform configured to support various programming models, middleware and / or libraries, and frameworks that the application may rely on. The application may be an AI / ML application implemented using, for example, a deep learning framework (e.g., but not limited to, MXNet, PyTorch, or TensorFlow), which may rely on libraries such as, but not limited to, cuDNN, the NVIDIA Collective Communication Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0265] The programming platform can be a combination of the above. Figure 22 The platform described is one of CUDA, ROCm, or OpenCL. The programming platform can support various programming models, which can be abstractions of the underlying computing system that allow the expression of algorithms and data structures. Programming models can expose features of the underlying hardware to improve performance. Programming models may include CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++AMP”), Open Multiprocessing (“OpenMP”), Open Accelerators (“OpenACC”), and / or Vulcan Compute.

[0266] Libraries and / or middleware can provide abstract implementations of programming models. Such libraries may include data and programming code that computer programs can use and leverage during software development. Such middleware may include software that provides services to applications beyond those offered by the programming platform. Libraries and / or middleware may include cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Furthermore, libraries and / or middleware may include the NCCL and ROCm communication collection library (“RCCL”) libraries that provide communication routines for GPUs, the MIOpen library for accelerating deep learning, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0267] Application frameworks may depend on libraries and / or middleware. Each application framework can be a software framework that provides a standard structure for implementing application software. Returning to the AI / ML example discussed above, AI / ML applications can be implemented using frameworks such as, but not limited to, deep learning frameworks like Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet.

[0268] In at least one embodiment, the processor described elsewhere herein (e.g., but not limited to) Figure 9-21BThe processor (in the document) may include one or more circuits that cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein. The one or more circuits may be configured by software (such as the programming platform described herein) to cause the compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors, or otherwise perform any of the operations described above or elsewhere herein.

[0269] Figure 23 The method for using at least one embodiment in the above is shown. Figure 22 The compiled code is executed on one of the programming platforms shown. Compiler 2301 is configured to receive source code 2300, compile source code 2300, and output executable file 2310. Compiler 2301 can be configured to convert source code 2300 into host executable code 2307 for execution on a host and device executable code 2308 for execution on a device. Source code 2300 can be compiled offline before executing the application or online during application execution. Source code 2300 can include code in any programming language supported by compiler 2301, such as, but not limited to, C++, C, Fortran, etc. Source code 2300 can be included in a single source file containing both host code and device code, indicating the location of the device code. The single source file can be a .cu file including CUDA code, or a .hip.cpp file including HIP code, or a file in other formats including both host code and device code. Alternatively, source code 3200 can include multiple source code files instead of a single source file, with host code and device code separated into these files. Compiler 2301 includes or can access one or more libraries to identify API call sequences to execute a single fused API, wherein the single fused API is a combination of two or more APIs. In at least one embodiment, compiler 2301 may be an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files, or other compilers.

[0270] Compiler 2301 can be configured to compile source code 2300 into host executable code 2307 for execution on a host and device executable code 2308 for execution on a device. The operations performed by compiler 2301 include parsing source code 2300 into an abstract system tree (AST), performing optimizations, and generating executable code. When source code 2300 comprises a single source file, compiler 2301 can separate the device code from the host code in that single source file, compile the device code and host code into device executable code 2308 and host executable code 2307 respectively, and link the device executable code 2308 and host executable code 2307 together to form a single file.

[0271] Compiler 2301 may include compiler front-end 2302, host compiler 2305, device compiler 2306, and linker 2309. Compiler front-end 2302 may be configured to separate device code 2304 from host code 2303 in source code 2300. In at least one embodiment, device code 2304 may be compiled by device compiler 2306 into device executable code 2308, which may include binary code or IR code as described above. Separately, host code 2303 may be compiled by host compiler 2305 into host executable code 2307. For other compilers such as NVCC (e.g., but not limited to oneAPI, ROCm, and OpenCL compilers), host compiler 2305 may be a general-purpose C / C++ compiler that outputs native object code, while device compiler 2306 may be a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. For HCC, both host compiler 2305 and device compiler 2306 may be LLVM based compilers that output object binary code.

[0272] After compiling source code 2300 into host executable code 2307 and device executable code 2308, linker 2309 can link host executable code 2307 and device executable code 2308 together to form executable file 2310. The host's native object code and the device's PTX or binary code can be linked together in an executable and linkable format (“ELF”) file, a container format for storing object code. Host executable code 2307 and device executable code 2308 can take any suitable format, such as, but not limited to, binary code and / or IR code. In at least one embodiment, for CUDA, host executable code 2307 may include native object code, while device executable code 2308 may include code in a PTX intermediate representation. In at least one embodiment, for ROCm, both host executable code 2307 and device executable code 2308 can include object binary code. Other implementations (e.g., but not limited to oneAPI, OpenCL) are considered and can be performed similarly to the CUDA and ROCm implementations described above.

[0273] Source code 2300 can be transformed before compilation. The source code is passed through a transformation tool (not shown), which transforms source code 2300 into transformed source code. Compiler 2301 can be used to compile the transformed source code into host executable code 2307 and device executable code 2308, a process similar to compiler 2301 compiling source code 2300 into host executable code 2307 and device executable code 2308, as described above. Figure 23 The discussion.

[0274] The transformations performed by the transformation tools can be used to port Source Code 2300 to environments different from the environment it was originally intended to run in. The transformation tools may include a HIP converter, which is used to "hipify" CUDA code intended for the CUDA platform into HIP code that can be compiled and executed on the ROCm platform. The transformation of Source Code 2300 may include parsing Source Code 2300 and translating calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as described below. Figure 24 Let's discuss this in more detail. Returning to the example of HIP-enhanced CUDA code, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. The automatic conversion performed by conversion tool 2301 may sometimes be incomplete, requiring additional manual intervention to fully port the source code 2300.

[0275] One or more techniques described herein can leverage other methods of converting one type of code into another to achieve interoperability between different device architectures. In at least one embodiment, an application for one platform (e.g., a CUDA application) can be compiled into code for implementation on another platform (e.g., an AMD processor, an Intel processor, or another processor). For example, source code 2300 may include source code for one platform (e.g., CUDA). Compiler 2301 can compile source code 2300 into an executable file 2310 that can be used by another platform (e.g., AMD or Intel). Programming toolkits can allow applications for one platform (e.g., CUDA) to be compiled (e.g., natively compiled) against another platform (e.g., AMD or Intel). For example, a GPGPU programming toolkit can allow CUDA applications to be natively compiled against AMD GPUs. Programs (e.g., CUDA programs) or their build systems do not require modification or conversion into other languages ​​before being compiled into code for another platform. The compiler can accept the same command-line options and programming cognates (e.g., CUDA cognates) as another compiler (e.g., nvcc for CUDA), serving as a direct replacement for the installation of emulation toolkits (e.g., the NVIDIA CUDA Toolkit), so existing build tools and scripts (e.g., cmake) will work without further modification. In at least one embodiment, an nvcc-cognate CUDA can be compiled for AMD GPUs (including PTX asm) using an nvcc-compatible compiler. Implementations of the CUDA runtime and driver APIs for AMD GPUs can be used. Libraries (e.g., open-source wrapper libraries) can provide APIs by delegating to the corresponding ROCm libraries, such as the "CUDA-X" API. Example implementations include SCALE from Spectral Compute in London, UK. SCALE does not provide a new method for writing GPGPU software, but rather allows programs written in the popular CUDA language to be directly compiled for AMD GPUs. Additional implementations could include the Clang compiler, which provides language front-ends and tooling infrastructure for languages ​​in the C family of languages ​​(C, C++, Objective C / C++, OpenCL, CUDA, and RenderScript).In at least one embodiment, the compiler described herein (e.g., but not limited to compiler 2301, compiler 2305, and / or compiler 2306) may include one or more circuits for compiling code (e.g., CUDA, HIP, OpenCL, OneAPI, or others) such that the compiler instructs one or more portions of one or more software programs to be executed concurrently by one or more processors or otherwise performs any of the operations described above or elsewhere herein.

[0276] Figure 24 A system 2400 is shown, configured to compile and execute CUDA source code 2410 using different types of processing units according to at least one embodiment. The system 2400 includes CUDA source code 2410, CUDA compiler 2450, host executable code 2470(1), host executable code 2470(2), CUDA device executable code 2484, CPU 2490, CUDA-enabled GPU 2494, GPU 2492, CUDA to HIP conversion tool 2420, HIP source code 2430, HIP compiler driver 2440, HCC 2460, and HCC device executable code 2482.

[0277] CUDA source code 2410 can be a collection of human-readable code in the CUDA programming language. The CUDA programming language can be an extension of the C++ programming language, including mechanisms for defining device code and distinguishing between device code and host code. Device code can include source code that, after compilation, can be executed in parallel on a device. A device can be a processor optimized for parallel instruction processing, such as, but not limited to, a CUDA-enabled GPU 2490, GPU 2492, or other GPGPUs. Host code is source code that, after compilation, can be executed on a host machine. A host machine is a processor optimized for sequential instruction processing, such as, but not limited to, a CPU 2490.

[0278] CUDA source code 2410 may include any number (including zero) of global functions 2412, any number (including zero) of device functions 2414, any number (including zero) of host functions 2416, and any number (including zero) of host / device functions 2418. Global functions 2412, device functions 2414, host functions 2416, and host / device functions 2418 can be mixed within CUDA source code 2410. Each global function 2412 can be executed on the device and called from the host. Therefore, one or more global functions 2412 can act as entry points for the device. Each global function 2412 can be a kernel. In a technique called dynamic parallelism, one or more global functions 2412 can define a kernel that can be executed on the device and called from the device. During execution, the kernel can be executed in parallel N times by N different threads on the device (where N is any positive integer).

[0279] Each device function 2414 can be executed on a device and can only be called from that device. Each host function 2416 can be executed on a host and can only be called from that host. Each host / device function 2416 can define a host version of a function that can be executed on a host and called only from that host, and a device version of a function that can be executed on a device and called only from that device.

[0280] CUDA source code 2410 can also include any number of calls to any number of functions, which can be defined through CUDA runtime API 2402. CUDA runtime API 2402 can include any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. CUDA source code 2410 can also include any number of calls to any number of functions, which can be specified in any number of other CUDA APIs. CUDA APIs can be any API designed for use by CUDA code. CUDA APIs can include CUDA runtime API 2402, CUDA driver APIs, APIs for any number of CUDA libraries, etc., including any APIs described elsewhere in this document. Compared to CUDA runtime API 2402, CUDA driver APIs can be lower-level APIs but can provide more fine-grained control over devices. Examples of CUDA libraries include cuBLAS, cuFFT, cURAND, cuDNN, etc.

[0281] CUDA compiler 2450 can compile input CUDA code (e.g., CUDA source code 2410) to generate host executable code 2470(1) and CUDA device executable code 2484. CUDA compiler 2450 can be, but is not limited to, NVCC. Host executable code 2470(1) can be a compiled version of the host code included in the input source code, which can be executed on CPU 2490. CPU 2490 can be any processor optimized for sequential instruction processing.

[0282] CUDA device executable code 2484 may be a compiled version of the device code included in the input source code, which can be executed on a CUDA-enabled GPU 2494. CUDA device executable code 2484 may include binary code. CUDA device executable code 2484 may include IR code (e.g., but not limited to PTX code), which is further compiled at runtime by the device driver into binary code for a specific target device (e.g., a CUDA-enabled GPU 2494). CUDA-enabled GPU 2494 may include any processor optimized for parallel instruction processing and supporting CUDA. CUDA-enabled GPU 2494 may be developed by NVIDIA Corporation, located in Santa Clara, California.

[0283] The CUDA to HIP conversion tool 2420 can be configured to convert CUDA source code 2410 into functionally similar HIP source code 2430. The HIP source code 2430 may include a collection of human-readable code written in the HIP programming language. The HIP code may include human-readable code written in the HIP programming language. The HIP programming language may include extensions to the C++ programming language that include functionally similar versions of the CUDA mechanisms for defining device code and distinguishing it from host code. The HIP programming language may include a subset of the functionality of the CUDA programming language. For example, the HIP programming language may include mechanisms for defining global functions 2412, but such HIP programming languages ​​may lack support for dynamic parallelism, so the global function 2412 defined in the HIP code may only be called from the host.

[0284] HIP source code 2430 may include any number (including zero) of global functions 2412, any number (including zero) of device functions 2414, any number (including zero) of host functions 2416, and any number (including zero) of host / device functions 2418. HIP source code 2430 may also include any number of calls to any number of functions specified in HIP runtime API 2432. HIP runtime API 2432 may include functionally similar versions of a subset of functions contained in CUDA runtime API 2402. HIP source code 2430 may also include any number of calls to any number of functions specified in any number of other HIP APIs. HIP APIs may be any API designed for use by HIP code and / or ROCm. HIP APIs may include HIP runtime API 2432, HIP driver APIs, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0285] The CUDA to HIP conversion tool 2420 can convert each kernel call in CUDA code from CUDA syntax to HIP syntax, and can convert any number of other CUDA calls in CUDA code into any number of other functionally similar HIP calls. CUDA calls can include calls to functions specified in the CUDA API, and HIP calls can include calls to functions specified in the HIP API. The CUDA to HIP conversion tool 2420 can convert any number of calls to functions specified in the CUDA runtime API 2402 into any number of calls to functions specified in the HIP runtime API 2432.

[0286] The CUDA to HIP conversion tool 2420 may include a tool called hipify-perl, which performs a text-based conversion process. The CUDA to HIP conversion tool 2420 may also include a tool called hipify-clang, which, compared to hipify-perl, performs a more complex and robust conversion process, including parsing the CUDA code using clang (a compiler front-end) and then converting the resulting symbols. Converting CUDA code to HIP code may include modifications beyond those performed by the CUDA to HIP conversion tool 2420 (e.g., manual editing).

[0287] HIP compiler driver 2440 may include a front-end that identifies target device 2446 and then configures a compiler compatible with target device 2446 to compile HIP source code 2430. Target device 2446 may include a processor optimized for parallel instruction processing. HIP compiler driver 2440 may identify target device 2446 in any technically feasible manner.

[0288] If the target device 2446 is CUDA compatible (e.g., a CUDA-enabled GPU 2494), the HIP compiler driver 2440 can generate HIP / NVCC compilation commands 2442. The HIP / NVCC compilation commands 2442 can configure the CUDA compiler 2450 to compile HIP source code 2430 using a HIP-to-CUDA translation header and the CUDA runtime library. In response to the HIP / NVCC compilation commands 2442, the CUDA compiler 2450 can generate host executable code 2470(1) and CUDA device executable code 2484.

[0289] If the target device 2446 is incompatible with CUDA, the HIP compiler driver 2440 can generate HIP / HCC compilation command 2444. HIP / HCC compilation command 2444 can configure HCC 2460 to compile HIP source code 2430 using the HCC header and HIP / HCC runtime library. In response to HIP / HCC compilation command 2444, HCC 2460 can generate host executable code 2470(2) and HCC device executable code 2482. HCC device executable code 2482 can be a compiled version of the device code included in HIP source code 2430, which can be executed on GPU 2492. GPU 2492 can be any processor optimized for parallel instruction processing, incompatible with CUDA, and compatible with HCC. GPU 2492 can be developed by AMD Inc., located in Santa Clara, California. GPU 2492 can include GPU 2492 that does not support CUDA.

[0290] For illustrative purposes only, Figure 24Three different flows, which can be implemented in at least one embodiment, are described for compiling CUDA source code 2410 for execution on CPU 2490 and various devices. A direct CUDA stream can compile CUDA source code 2410 for execution on CPU 2490 and CUDA-enabled GPU 2494 without converting CUDA source code 2410 to HIP source code 2430. An indirect CUDA stream can convert CUDA source code 2410 to HIP source code 2430 and then compile HIP source code 2430 for execution on CPU 2490 and CUDA-enabled GPU 2494. A CUDA / HCC stream can convert CUDA source code 2410 to HIP source code 2430 and then compile HIP source code 2430 for execution on CPU 2490 and GPU 2492.

[0291] The achievable direct CUDA stream is represented by dashed lines and a series of bubbles labeled A1-A3. As shown in bubble A1, CUDA compiler 2450 can receive CUDA source code 2410 and CUDA compilation command 2448, which configures CUDA compiler 2450 to compile CUDA source code 2410. The CUDA source code 2410 available for direct CUDA stream can be written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In response to CUDA compilation command 2448, CUDA compiler 2450 can generate host executable code 2470(1) and CUDA device executable code 2484 (shown in bubble A2). As shown in bubble A3, host executable code 2470(1) and CUDA device executable code 2484 can be executed on CPU 2490 and CUDA-enabled GPU 2494, respectively. CUDA device executable code 2484 may include binary code. CUDA device executable code 2484 may include PTX code and may be further compiled at runtime into binary code for a specific target device.

[0292] The achievable indirect CUDA streams are represented by dashed lines and a series of bubbles labeled B1-B6. As shown in bubble B1, the CUDA-to-HIP conversion tool 2420 can receive CUDA source code 2410. As shown in bubble B2, the CUDA-to-HIP conversion tool 2420 can convert CUDA source code 2410 into HIP source code 2430. As shown in bubble B3, the HIP compiler driver 2440 can receive HIP source code 2430 and determine that the target device 2446 supports CUDA.

[0293] As indicated by bubble B4, the HIP compiler driver 2440 can generate HIP / NVCC compilation command 2442 and transfer HIP / NVCC compilation command 2442 and HIP source code 2430 to CUDA compiler 2450. HIP / NVCC compilation command 2442 can configure CUDA compiler 2450 to compile HIP source code 2430 using HIP to CUDA translation header and CUDA runtime library. HIP to CUDA translation header can convert any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. CUDA compiler 2450 can combine HIP to CUDA translation header and CUDA runtime library corresponding to CUDA runtime API 2402 to generate host executable code 2470(1) and CUDA device executable code 2484. In response to HIP / NVCC compilation command 2442, CUDA compiler 2450 can generate host executable code 2470(1) and CUDA device executable code 2484 (represented by bubble B5). As shown in bubble B6, host executable code 2470(1) and CUDA device executable code 2484 can be executed on CPU 2490 and CUDA-enabled GPU 2494, respectively. CUDA device executable code 2484 may include binary code. CUDA device executable code 2484 may include PTX code and can be further compiled at runtime into binary code for a specific target device.

[0294] The implementable CUDA / HCC streams are represented by solid lines and a series of bubbles labeled C1-C6. As shown in bubble C1, the CUDA-to-HIP conversion tool 2420 can receive CUDA source code 2410. As shown in bubble C2, the CUDA-to-HIP conversion tool 2420 can convert CUDA source code 2410 into HIP source code 2430. As shown in bubble C3, the HIP compiler driver 2440 can receive HIP source code 2430 and can determine that the target device 2446 does not support CUDA.

[0295] HIP compiler driver 2440 can generate HIP / HCC compilation command 2444 and transfer HIP / HCC compilation command 2444 and HIP source code 2430 to HCC 2460 (shown as bubble C4). HIP / HCC compilation command 2444 can configure HCC 2460 to compile HIP source code 2430 using HCC header files and HIP / HCC runtime library. HIP / HCC runtime library can correspond to HIP runtime API 2432. HCC header can include any number and type of HIP and HCC interoperability mechanisms. In response to HIP / HCC compilation command 2444, HCC 2460 can generate host executable code 2470(2) and HCC device executable code 2482 (shown as bubble C5). As shown in the bubble labeled C6, host executable code 2470(2) and HCC device executable code 2482 can be executed on CPU 2490 and GPU 2492, respectively.

[0296] After converting CUDA source code 2410 to HIP source code 2430, executable code for a CUDA-enabled GPU 2494 or GPU 2492 can then be generated using HIP compiler driver 2440 without re-executing the CUDA to HIP conversion tool 2420. CUDA to HIP conversion tool 2420 can convert CUDA source code 2410 to HIP source code 2430 and then store the HIP source code 2430 in memory. HIP compiler driver 2440 can then configure HCC 2460 to generate host executable code 2470(2) and HCC device executable code 2482 based on the HIP source code 2430. In at least one embodiment, HIP compiler driver 2440 subsequently configures CUDA compiler 2450 to generate host executable code 2470(1) and CUDA device executable code 2484 based on the stored HIP source code 2430.

[0297] According to at least one embodiment, the example kernel may be derived from... Figure 24 The CUDA to HIP conversion tool 2420 in the CUDA source code 2410 performs the conversion. The CUDA source code 2410 divides the overall problem that a given kernel is designed to solve into relatively coarse subproblems, which can be solved independently using thread blocks. Each thread block contains any number of threads. Each subproblem can be divided into relatively fine pieces, which can be solved collaboratively in parallel by threads within the thread block. Threads within a thread block can cooperate by sharing data via shared memory and synchronizing execution to coordinate memory access.

[0298] CUDA source code 2410 can organize thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional thread block grid. Each thread block contains any number of threads, and the grid contains any number of thread blocks.

[0299] A kernel can be a function defined in device code using the "__global__" declaration specifier. The dimensions of the raster of kernels and their associated streams that execute a given kernel call can be specified using the CUDA kernel startup syntax. The CUDA kernel startup syntax is specified as "KernelName <<<GridSize,BlockSize,SharedMemorySize,Stream> >>

[0300] (KernelArguments);". The execution configuration syntax can include a "<<<...>>>" structure between the kernel name ("KernelName") and the parenthesized list of kernel parameters ("KernelArguments"). The CUDA kernel boot syntax can include the CUDA boot function syntax, instead of the execution configuration syntax.

[0301] "GridSize" can be of type dim3 and specifies the dimensions and size of the grid. The dim3 type can be a CUDA-defined structure containing unsigned integers x, y, and z. If z is not specified, it defaults to 1. If y is not specified, it defaults to 1. The number of thread blocks in the grid can be equal to the product of GridSize.x, GridSize.y, and GridSize.z. "BlockSize" can be of type dim3 and specifies the dimensions and size of each thread block. The number of threads per thread block can be equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. Each thread executing the kernel can be assigned a unique thread ID, which can be accessed in the kernel via built-in variables such as "threadIdx".

[0302] Regarding the CUDA kernel startup syntax, "SharedMemorySize" is an optional argument that, in addition to statically allocated memory, can specify the number of bytes in shared memory dynamically allocated per thread block for a given kernel call. The default value for SharedMemorySize is zero. Regarding the CUDA kernel startup syntax, "Stream" is also an optional argument that specifies the associated stream; the default value is zero to specify the default stream. A stream can be a sequence of commands executed sequentially (which may be emitted by different host threads). Different streams can execute commands out of order or concurrently.

[0303] CUDA source code 2410 may include the kernel definition and main function of the example kernel "MatAdd". The main function may be host code that executes on the host machine and includes a kernel call that causes the MatAdd kernel to execute on the device. The MatAdd kernel can add two NxN matrices A and B, where N is a positive integer, and store the result in matrix C. The main function can define the threadsPerBlock variable as 16x16 and the numBlocks variable as N / 16 x N / 16. The main function can then specify the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);”. According to the CUDA kernel startup syntax, the kernel MatAdd can be executed using a thread block grid of dimensions N / 16 x N / 16, where each thread block is 16x16. Each thread block can contain 256 threads, and a grid with enough thread blocks can be created so that there is one thread per matrix element, and each thread in such a grid can execute the kernel MatAdd to perform a pairwise addition.

[0304] When converting CUDA source code 2410 to HIP source code 2430, the CUDA-to-HIP conversion tool 2420 can convert each kernel call in CUDA source code 2410 from CUDA kernel startup syntax to HIP kernel startup syntax, and can convert any number of other CUDA calls in source code 2410 into any number of other functionally similar HIP calls. The HIP kernel startup syntax can be specified as "hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);". Each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel startup syntax as it does in the CUDA kernel startup syntax (described earlier in this document). The arguments SharedMemorySize and Stream can be required in the HIP kernel startup syntax, but optional in the CUDA kernel startup syntax.

[0305] A portion of the HIP source code 2430 can be identical to a portion of the CUDA source code 2410 shown, except for the kernel call that causes the kernel MatAdd to execute on the device. The kernel MatAdd can be defined in the HIP source code 2430 using the same "__global__" declaration specifier as used in the CUDA source code 2410. The kernel call in the HIP source code 2430 can be "hipLaunchKernelGGL(MatAdd,numBlocks,threadsPerBlock,0,0,A,B,C);", while the corresponding kernel call in the CUDA source code 2410 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);

[0306] Other implementations are conceivable, and these can be implemented similarly to the CUDA and HIP implementations described above, such as oneAPI, OpenCL, and other programming platforms. Code can be converted in any direction. For example, CUDA can be converted to HIP, and CUDA can be converted to OpenCL. SnuCL-Tr and CUCL can be used to convert OpenCL to CUDA or CUDA to OpenCL, respectively. Compiled code or intermediate representations (such as CUDA PTX code) can also be converted to run on other processor platforms (such as AMD or Intel). For example, conversion tools (such as ZLUDA) can be used to convert PTX code to run on Intel or AMD processors.

[0307] The techniques described herein can utilize the oneAPI programming model. The oneAPI programming model can refer to a programming model used to interact with various computing accelerator architectures. OneAPI can refer to an application programming interface (API) designed to interact with various computing accelerator architectures. The oneAPI programming model can use the DPC++ programming language. The DPC++ programming language can refer to a high-level language used for data-parallel programming productivity. The DPC++ programming language can be at least partially based on the C and / or C++ programming languages. The oneAPI programming model can be, but is not limited to, a programming model developed by Intel Corporation of Santa Clara, California.

[0308] OneAPI and / or the oneAPI programming model can be used to interact with a variety of accelerators, GPUs, processors, and / or their variant architectures. OneAPI may include a set of libraries that implement various functions. OneAPI may include at least the oneAPIDPC++ library, the oneAPI math kernel library, the oneAPI data analysis library, the oneAPI deep neural network library, the oneAPI collection communication library, the oneAPI thread building block library, the oneAPI video processing library, and / or their variants.

[0309] The oneAPIDPC++ library (also known as oneDPL) can be a library that implements algorithms and functions to accelerate DPC++ kernel programming. oneDPL can implement one or more Standard Template Library (STL) functions. OneDPL can implement one or more parallel STL functions. OneDPL can provide a set of library classes and functions, such as, but not limited to, parallel algorithms, iterators, function object classes, range-based APIs, and / or variations thereof. OneDPL can implement one or more classes and / or functions from the C++ Standard Library. OneDPL can implement one or more random number generator functions.

[0310] The oneAPI math kernel library (also known as oneMKL) can be a library that implements various optimized and parallelized routines for various mathematical functions and / or operations. OneMKL can implement one or more Basic Linear Algebra Subroutines (BLAS) and / or Linear Algebra Packages (LAPACK) dense linear algebra routines. OneMKL can implement one or more sparse BLAS linear algebra routines. OneMKL can implement one or more random number generators (RNGs). OneMKL can implement one or more vector math (VM) routines for performing mathematical operations on vectors. OneMKL can implement one or more Fast Fourier Transform (FFT) functions.

[0311] The OneAPI data analysis library (also known as oneDAL) can include libraries for implementing various data analysis applications and distributed computing. OneDAL can implement various algorithms for data analysis preprocessing, transformation, analysis, modeling, validation, and decision-making, including batch, online, and distributed computing processing modes. OneDAL can implement various C++ and / or Java APIs as well as various connectors for connecting to one or more data sources. OneDAL can implement the DPC++ API extension to the traditional C++ interface and support GPU usage for various algorithms.

[0312] The OneAPI Deep Neural Network Library (also known as oneDNN) can include libraries that implement various deep learning functions. OneDNN can implement various neural networks, machine learning and deep learning functions, algorithms and / or variations thereof.

[0313] The OneAPI collection communication library (also known as oneCCL) can include libraries that implement a variety of applications for deep learning and machine learning workloads. OneCCL can be built on lower-level communication middleware, such as, but not limited to, message passing interfaces (MPI) and libfabrics. OneCCL can support a set of deep learning-specific optimizations, such as, but not limited to, priority ordering, persistence operations, out-of-order execution, and / or variations thereof. OneCCL can implement a variety of CPU and GPU functionalities.

[0314] The OneAPI Thread Building Blocks library (also known as oneTBB) can include libraries that implement various parallel processes for a wide range of applications. OneTBB can be used for task-based shared parallel programming on a host machine. OneTBB can implement general-purpose parallel algorithms. OneTBB can implement concurrent containers. OneTBB can implement scalable memory allocators. OneTBB can implement work-stealing task schedulers. OneTBB can implement low-level synchronization primitives. OneTBB can be compiler-independent and can be used on a variety of processors, such as, but not limited to, GPUs, PPUs, CPUs, and / or variants thereof.

[0315] The OneAPI video processing library (also known as oneVPL) can include libraries for accelerating video processing in one or more applications. OneVPL can implement a variety of video decoding, encoding, and processing functions. OneVPL can implement various functions for media pipelines on CPUs, GPUs, and other accelerators. OneVPL can implement device discovery and selection in media-centric and video analytics workloads. OneVPL can implement API primitives for zero-copy buffer sharing.

[0316] The oneAPI programming model can use the DPC++ programming language. The DPC++ programming language can include a version of a programming language that is functionally similar to the CUDA mechanism to define device code and distinguish it from host code. The DPC++ programming language can include a subset of the functionality of the CUDA programming language. One or more CUDA programming model operations can be performed using the oneAPI programming model utilizing the DPC++ programming language.

[0317] Any application programming interface (API) described herein can be compiled by a compiler, interpreter, or other software tool into one or more instructions, operations, or other signals. Compilation may include generating one or more machine-executable instructions, operations, or other signals from source code. An API compiled into one or more instructions, operations, or other signals, when executed, may enable one or more processors (e.g., but not limited to...) Figure 9-21BThe processor described herein or any other logic circuit further described herein performs one or more computational operations.

[0318] In at least one embodiment, the transformation tools described elsewhere herein (e.g., but not limited to) may include one or more circuitry for transforming CUDA code such that the compiler instructs one or more portions of one or more software programs to be executed concurrently by one or more processors with HIP, oneAPI, OpenCL, or any other language used to perform any of the operations described above or elsewhere herein. The one or more circuitry may be software-configurable to transform CUDA code such that the compiler instructs one or more portions of one or more software programs to be executed concurrently by one or more processors with HIP, oneAPI, OpenCL, or any other language used to perform any of the operations described above or elsewhere herein.

[0319] Autonomous vehicles

[0320] Figure 25 An example of an autonomous vehicle 2500 according to at least one embodiment is shown. The autonomous vehicle 2500 (referred to herein alternatively as "vehicle 2500") can be a passenger vehicle, such as, but not limited to, a sedan, truck, bus, and / or other type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 2500 can be a semi-trailer tractor for transporting goods. Vehicle 2500 can be an aircraft, robotic vehicle, or other type of vehicle.

[0321] Autonomous vehicles can be described according to their automation levels, which are defined by the National Highway Traffic Safety Administration (NHTSA) (a division of the U.S. Department of Transportation) and the Society of Automotive Engineers (SAE) in their "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 2500 can achieve functionality at one or more levels of autonomy, from Level 1 to Level 5. For example, in at least one embodiment, depending on the embodiment, vehicle 2500 can achieve conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0322] Vehicle 2500 may include components such as, but not limited to, chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle parts. Vehicle 2500 may include a propulsion system 2550, such as, but not limited to, an internal combustion engine, a hybrid power plant, an all-electric motor, and / or other propulsion system types. Propulsion system 2550 may be connected to the drivetrain of vehicle 2500 (which may include a transmission) to propel vehicle 2500. Propulsion system 2550 may be controlled based on signals received from throttle / accelerator 2552.

[0323] A steering system 2554 (which may include a steering wheel) is used to maneuver the vehicle 2500 (e.g., to travel along a desired path or route) while the propulsion system 2550 is in operation (e.g., when the vehicle 2500 is in motion). The steering system 2554 may receive signals from a steering actuator 2556. The steering wheel is optional for fully automated (Level 5) functionality. A brake sensor system 2546 may be used to operate the vehicle brakes in response to signals received from brake actuator 2548 and / or brake sensors.

[0324] Controller 2536 may include one or more system-on-a-chip (“SoC”) and / or graphics processing units (“GPUs”) that can provide signals (e.g., signals representing commands) to one or more components and / or systems of vehicle 2500. For example, controller 2536 may send signals to operate vehicle brakes via brake actuator 2548, steering system 2554 via steering actuator 2556, and propulsion system 2550 via throttle / accelerator 2552. Controller 2536 may include one or more onboard (e.g., integrated) computing devices for processing sensor signals and outputting operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 2500. Controller 2536 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. A single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0325] The controller 2536 may provide signals for controlling one or more components and / or systems of the vehicle 2500 in response to sensor data (e.g., sensor inputs) received from one or more sensors. Sensor data can be received from, for example, a Global Navigation Satellite System (“GNSS”) sensor 2558 (e.g., a Global Positioning System sensor), a RADAR (radar) sensor 2560, an ultrasonic sensor 2562, a LIDAR (light radar) sensor 2564, an Inertial Measurement Unit (“IMU”) sensor 2566 (e.g., an accelerometer, a gyroscope, one or more magnetic compasses, a magnetometer, etc.), a microphone 2596, a stereo camera 2568, a wide-angle camera 2570 (e.g., a fisheye camera), an infrared camera 2572, a surround-view camera 2574 (e.g., a 360-degree camera), a long-range camera 2598, a medium-range camera 2576, a speed sensor 2544 (e.g., for measuring the speed of vehicle 2500), a vibration sensor 2542, a steering sensor 2540, a braking sensor (e.g., as part of a braking sensor system 2546), and / or other types of sensors.

[0326] One or more controllers 2536 may receive input (e.g., represented by input data) from the instrument panel 2532 of the vehicle 2500 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 2534, an audible annunciator, a speaker, and / or via other components of the vehicle 2500. Output may include, but is not limited to, vehicle speed, rate, time, map data (e.g., a high-resolution map (not shown), location data (e.g., the location of the vehicle 2500, such as, but not limited to, its location on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the status of objects perceived by the controllers 2536. For example, the HMI display 2534 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.) and / or information about driving actions that the vehicle has performed, is performing, or will perform (e.g., changing lanes now, exiting from exit 34B in two miles, etc.).

[0327] Figure 25 Each component, feature, and system of the vehicle 2500 can be connected via bus 2502. Bus 2502 may include a CAN data interface (also referred to herein as the "CAN bus"). CAN can be a network within the vehicle 2500 used to assist in the control of various features and functions of the vehicle 2500, such as, but not limited to, the activation of brakes, acceleration, braking, steering, windshield wipers, etc. Bus 2502 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). Bus 2502 can be read to locate steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. Bus 2502 can be an ASIL B compliant CAN bus.

[0328] In addition to CAN, or as an alternative to CAN, FlexRay and / or Ethernet protocols may be used. Bus 2502 may consist of any number of buses, which may include zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. Two or more buses may be used to perform different functions and / or for redundancy. For example, a first bus may be used for collision avoidance functions, and a second bus may be used for actuation control. Each bus in bus 2502 may communicate with any component of vehicle 2500, and two or more buses of bus 2502 may communicate with corresponding components. Any number of System-on-Chip (“SoC”) 2504 (e.g., but not limited to SoC 2504(A) and SoC 2504(B)), each controller 2536, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 2500) and may be connected to a common bus, such as a CAN bus.

[0329] According to at least one embodiment, for Figure 25 The autonomous vehicle 2500 can place any number of cameras at any chosen camera locations and within any field of view. The cameras and corresponding fields of view are an exemplary embodiment and are not intended to be limiting. For example, additional and / or alternative cameras may be included, and / or the cameras may be located at different locations within the vehicle 2500.

[0330] The camera type may include a digital camera suitable for components and / or systems in vehicle 2500. The camera may operate under Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. According to embodiments, the camera type may support any image capture rate, such as, but not limited to, 60 frames per second (fps), 1220 fps, 240 fps, etc. The camera may be able to use a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-to-clear-to-clear (“RCCC”) color filter array, a red-to-clear-to-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. Transparent pixel cameras (e.g., but not limited to cameras with RCCC, RCCB, and / or RBGC color filter arrays) may be used to enhance sensitivity.

[0331] One or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, a multi-function monochrome camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. One or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0332] One or more cameras can be mounted in mounting assemblies, such as, but not limited to, custom-designed (3D-printed) assemblies, to eliminate stray light and reflections inside the vehicle 2500 (e.g., dashboard reflections in the windshield mirror) that could interfere with the camera's image data capture capabilities. Regarding rearview mirror mounting assemblies, these assemblies can be custom-3D printed to match the shape of the camera mounting plate to the rearview mirror. The camera can be integrated into the rearview mirror. For side-view cameras, the cameras can also be integrated into the four pillars in each corner of the cab.

[0333] A field of view including a portion of the environment in front of the vehicle 2500 (e.g., a front-facing camera) can be used for surround view to help identify the path and obstacles ahead, and, with the assistance of one or more controllers 2536 and / or control SoCs, provide information crucial for generating an occupancy grid and / or determining a preferred vehicle path. The front-facing camera can be used to perform many ADAS functions similar to LiDAR, including emergency braking, pedestrian detection, and collision avoidance. The front-facing camera can also be used in ADAS functions and systems, including Lane Departure Warning (“LDW”), Automatic Cruise Control (“ACC”), and / or other functions such as, but not limited to, traffic sign recognition.

[0334] Various front-mounted cameras can be used, including, for example, monocular camera platforms including CMOS (“complementary metal-oxide-semiconductor”) color imagers. A wide-angle camera 2570 can be used to perceive objects entering the field of view from the periphery (e.g., pedestrians, crossing vehicles, or bicycles). Any number (including zero) of wide-angle cameras 2570 can be mounted on vehicle 2500. Any number of remote cameras 2598 (e.g., long-view stereo camera pairs) can be used for depth-based object detection, particularly for objects on which neural networks have not yet been trained. The remote cameras 2598 can also be used for object detection and classification, as well as basic object tracking.

[0335] It may also include any number of front-mounted stereo cameras 2568. One or more stereo cameras 2568 may include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. Such a unit can be used to generate a 3D map of the environment of the vehicle 2500, including distance estimates for all points in the image. One or more stereo cameras 2568 may include a compact stereo vision sensor that may include two camera lenses (one on each side) and an image processing chip that measures the distance from the vehicle 2500 to a target object and uses the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. Other types of stereo cameras 2568 may be used in addition to, or as an alternative to, the stereo cameras described herein.

[0336] Cameras (e.g., side-view cameras) that include portions of the environment along the sides of vehicle 2500 can be used in the surround view to provide information for creating and updating occupancy grids and generating side collision warnings. For example, surround view cameras 2574 (e.g., four surround view cameras) can be mounted on vehicle 2500. Surround view cameras 2574 can include any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or similar cameras. For example, four fisheye cameras can be mounted at the front, rear, and sides of vehicle 2500, respectively. Vehicle 2500 can use three surround view cameras 2574 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., front-facing cameras) as a fourth surround view camera.

[0337] A field of view including a portion of the environment behind vehicle 2500 (e.g., a rear-view camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. A wide variety of cameras can be used, including but not limited to cameras that are also suitable as front-facing cameras (e.g., long-range camera 2598 and / or mid-range camera 2576, stereo camera 2568, infrared camera 2572, etc.), as described herein.

[0338] Vehicle 2500 may include any number of SoC 2504 or other processors described elsewhere in this document, such as, but not limited to, those described elsewhere. Figure 9-21BThe processor and / or components shown and described. Each SoC 2504 may include a central processing unit (“CPU”) 2506, a graphics processing unit (“GPU”) 2508, a processor 2510, a cache 2512, an accelerator 2514, a data storage 2516, and / or other components and features not shown. The SoC 2504 can be used to control the vehicle 2500 in various platforms and systems. For example, the SoC 2504 may be combined with a high-definition (“HD”) map 2522 in a system (e.g., the system of the vehicle 2500), which may obtain map refreshes and / or updates from one or more servers (not shown) via a network interface 2524.

[0339] The CPU 2506 may include a CPU cluster or CPU complex (referred to herein as “CCPLEX”). The CPU 2506 may include multiple cores and / or a secondary (“L2”) cache. For example, the CPU 2506 may include eight cores in a consistent multiprocessor configuration. The CPU 2506 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). The CPU 2506 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of CPU 2506 clusters to be active at any given time.

[0340] One or more of the CPU 2506 can implement power management capabilities, including one or more of the following features: individual hardware blocks can automatically clock-gated when idle to save dynamic power; clock gating can be applied to cores when each core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Wait for Event (“WFE”) instructions; each core can independently perform power gating; each core cluster can independently clock-gated when all cores can perform clock or power gating; and / or each core cluster can independently power-gated when all cores can perform power gating. The CPU 2506 can also implement enhanced algorithms for managing power states, where allowed power states and expected wake-up times can be specified, and the hardware / microcode determines which optimal power state the core, cluster, and CCPLEX enter. Processing cores can enter a simplified power state sequence via software support, offloading work to the microcode.

[0341] The GPU 2508 may include an integrated GPU (referred to herein as an "iGPU"). The GPU 2508 may be programmable and capable of efficiently handling parallel workloads. The GPU 2508 may use an enhanced tensor instruction set. The GPU 2508 may include one or more streaming microprocessors, each of which may include a Level 1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512KB). The GPU 2508 may include at least eight streaming microprocessors. The GPU 2508 may use a computation application programming interface (API). The GPU 2508 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model). A streaming microprocessor may be referred to as a streaming multiprocessor (“SM”), a streaming processor (“SP”), a streaming processing unit (“SPU”), a compute unit (“CU”), an execution unit (“EU”), and / or a slice, wherein, in this context, a slice may refer to a portion of the processing resources within a processing unit (e.g., 16 cores, a ray tracing unit, a thread bootstrap, or a scheduler).

[0342] One or more of the GPU 2508 can be power-optimized for optimal performance in automotive and embedded use cases. For example, the GPU 2508 can be fabricated on FinFET (“FinFET”) circuitry. Each streaming microprocessor can include multiple mixed-precision processing cores partitioned into blocks. For example, 64 PF32 cores and 32 FP64 cores can be partitioned into four processing blocks. Each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix operations, a level-zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, dispatch units, and / or a 64KB register file. Streaming microprocessors can include independent parallel integer and floating-point data paths for efficiently performing workloads involving mixed computations and addressing computations. Streaming microprocessors can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. Streaming microprocessors may include a combination of L1 data cache and shared memory units to improve performance while simplifying programming.

[0343] One or more GPU 2508s may include high-bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, used in some examples to provide a peak memory bandwidth of approximately 900GB / s. In addition to HBM memory, or as an alternative to HBM memory, synchronous graphics random access memory (“SGRAM”) may be used, such as, but not limited to, graphics double data rate type 5 synchronous random access memory (“GDDR5”).

[0344] The GPU 2508 may include unified memory technology. Address translation service (“ATS”) supports page tables that allow the GPU 2508 to directly access the CPU 2506. When a GPU memory management unit (“MMU”) misses an address, it can send an address translation request to the CPU 2506. In response, one or more CPUs in the CPU 2506 can look up the virtual-to-physical mapping of the address in their page tables and transfer the translation back to the GPU 2508. Unified memory technology can provide a single, unified virtual address space for the memory of both the CPU 2506 and the GPU 2508, thereby simplifying GPU 2508 programming and application porting to the GPU 2508.

[0345] The GPU 2508 may include any number of access counters that can track the frequency of the GPU 2508's access to the memory of other processors. These access counters help ensure that memory pages are moved to the physical memory of the processor that accesses those pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0346] One or more SoCs 2504 may include any number of caches 2512, including the caches described herein. For example, cache 2512 may include a Level 3 (“L3”) cache available for use by both CPU 2506 and GPU 2508 (e.g., connected to both CPU 2506 and GPU 2508). Cache 2512 may include a write-back cache that can track the state of rows, for example, but not limited to, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). According to embodiments, the L3 cache may include 4 MB or more of memory, although a smaller cache size may be used.

[0347] One or more SoCs 2504 may include one or more accelerators 2514 (e.g., hardware accelerators, software accelerators, or a combination thereof). SoC 2504 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. Large on-chip memory (e.g., 4MB SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. The hardware acceleration cluster can be used to supplement GPU 2508 and offload some tasks from GPU 2508 (e.g., freeing up more cycles of GPU 2508 to perform other tasks). Accelerators 2514 can be used for targeted workloads (e.g., perceptrons, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are sufficiently stable to be easily accelerated. CNNs may include region-based or regional convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., for object detection) or other types of CNNs.

[0348] Accelerator 2514 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). A DLA may include one or more tensor processing units (“TPUs”) that can be configured to provide an additional trillion operations per second for deep learning applications and inference, such as those described in this paper (e.g., Figure 19 The TPU described in the text is a TPU that can be configured and optimized for performing image processing functions, such as CNNs, RCNNs, etc. The DLA can be further optimized for a specific set of neural network types, floating-point operations, and inference. The DLA is designed to provide higher performance per millimeter than typical general-purpose GPUs and often significantly outperforms CPUs. The TPU can perform several functions, including single-instance convolutional functions, support for features and weights of data types such as INT8, INT16, and FP16, and post-processor functions. The DLA can quickly and efficiently execute neural networks (especially CNNs) on processed or unprocessed data to achieve a variety of functions, including, for example: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection and recognition using data from microphones; CNNs for face recognition and driver identification using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0349] The DLA can perform any function of the GPU 2508, and by using the inference accelerator, designers can direct any function to either the DLA or the GPU 2508. For example, designers can focus CNN and floating-point processing on the DLA, while leaving other functions to the GPU 2508 and / or the accelerator 2514.

[0350] Accelerator 2514 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. The PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 2538, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA can provide a balance between performance and flexibility. For example, each PVA may include any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0351] The RISC core can interact with image sensors (e.g., the image sensor of any camera described herein), image signal processors, etc. Each RISC core may include memory of any size. The RISC core can use any of a variety of protocols, depending on the implementation. The RISC core can execute a real-time operating system (“RTOS”). The RISC core can be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or memory devices. For example, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0352] DMA enables PVA components to access system memory independently of the CPU 2506. DMA supports any number of features for providing optimizations to the PVA, including support for multidimensional addressing and / or circular addressing. DMA supports addressing in up to six or more dimensions, which can include block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0353] The vector processor can be a programmable processor designed to efficiently and flexibly execute computer vision algorithms and provide signal processing capabilities. The PVA may include a PVA core and two vector processing subsystem partitions. The PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. The vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). The VPU core may include a digital signal processor, such as, but not limited to, a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. The combination of SIMD and VLIW can improve throughput and speed.

[0354] Each vector processor may include an instruction cache and may be coupled to dedicated memory. Therefore, each vector processor can be configured to execute independently of other vector processors. The vector processors included in a particular PVA can be configured to employ data parallelism. For example, multiple vector processors included in a single PVA can execute general computer vision algorithms, but for different regions of an image. The vector processors included in a particular PVA can execute different computer vision algorithms on a single image simultaneously, or even execute different algorithms on consecutive images or multiple parts of an image. Furthermore, a hardware-accelerated cluster can include any number of PVAs, and each PVA can include any number of vector processors. PVAs may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0355] Accelerator 2514 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for accelerator 2514. The on-chip memory may include at least 4 MB of SRAM, for example, comprising eight field-configurable memory blocks accessible by both the PVA and DLA. Each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. Any type of memory can be used. The PVA and DLA can access the memory via a backbone that provides high-speed memory access for both the PVA and DLA. The backbone may include an on-chip computer vision network that connects the PVA and DLA to the memory (e.g., using the APB).

[0356] The on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. This interface can provide separate stages and channels for transmitting control signals / addresses / data, as well as burst communication for continuous data transmission. The interface may conform to the International Organization for Standardization (ISO) 26262 or the International Electrotechnical Commission (IEC) 61508 standard, although other standards and protocols may also be used.

[0357] One or more of the SoC 2504 may include a real-time ray tracing hardware accelerator. The real-time ray tracing hardware accelerator can be used to quickly and efficiently determine the location and extent of objects (e.g., within a world model), generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR (sonar) system simulation, for general wave propagation simulation, for comparison with LiDAR data to achieve localization and / or other functions, and / or other uses.

[0358] Accelerator 2514 has broad applications in the field of autonomous driving. PVA can be used in critical processing stages in ADAS and autonomous vehicles. PVA's capabilities are well-suited for algorithmic domains requiring predictable processing, low power consumption, and low latency. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets requiring predictable runtime, low latency, and low power. In Vehicle 2500, PVA can be designed to run classic computer vision algorithms because they are highly efficient in object detection and integer mathematical operations. For example, PVA is used to perform computer stereo vision. In some examples, algorithms based on semi-global matching can be used, but this is not intended to be limiting. Level 3–5 autonomous driving applications use motion estimation / stereo matching (e.g., motion reconstruction of structures, pedestrian recognition, lane detection, etc.) in operation. PVA can perform computer stereo vision functions on input from two monocular cameras. PVA can be used to perform dense optical flow. For example, PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. PVA is used for in-depth time-of-flight processing, for example, to provide processed time-of-flight data by processing raw time-of-flight data.

[0359] DLA can be used to run any type of network to enhance control and driving safety, including, for example, neural networks that output confidence measurements for each object detection. Confidence can be represented or interpreted as a probability, or provide a relative “weight” for each detection compared to other detections. Confidence measurements enable the system to further decide which detections should be considered true positives rather than false positives. The system can set a confidence threshold and only consider detections exceeding the threshold as true positives. When using an Automatic Emergency Braking (“AEB”) system, false positives can cause the vehicle to automatically perform emergency braking, which is clearly undesirable. High-confidence detections can be considered triggers for AEB. DLA can run a neural network to regress the confidence values. The neural network can take at least a subset of parameters as its input, such as, but not limited to, bounding box dimensions, obtained ground plane estimates (e.g., from another subsystem), the output of IMU sensor 2566 related to the vehicle 2500 orientation, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., LiDAR sensor 2564 or RADAR sensor 2560), and so on.

[0360] One or more of the SoC 2504 may include a data storage 2516 (e.g., memory). The data storage 2516 may be on-chip memory of the SoC 2504, which can store neural networks to be executed on the GPU 2508 and / or DLA. The data storage 2516 is large enough to store multiple neural network instances for redundancy and security. The data storage 2516 may include L2 or L3 cache.

[0361] One or more of the SoC 2504 may include any number of processors 2510 (e.g., embedded processors). Processors 2510 may include boot and power management processors, which may be dedicated processors and subsystems for handling boot power and management functions, as well as related security enforcement. The boot and power management processor may be part of the SoC 2504 boot sequence and may provide runtime power management services. The boot power and management processor may provide clock and voltage programming, system low-power state transition assistance, SoC 2504 thermal and temperature sensor management, and / or SoC 2504 power state management. Each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to the temperature, and the SoC 2504 may use the ring oscillator to detect the temperature of the CPU 2506, GPU 2508, and / or accelerator 2514. If the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place the SoC 2504 into a low-power state, and / or place the vehicle 2500 into a driver-safe parking mode (e.g., safely parking the vehicle 2500).

[0362] The processor 2510 may also include a set of embedded processors that can be used as an audio processing engine. This audio processing engine can be an audio subsystem capable of providing comprehensive hardware support for multi-channel audio through multiple interfaces, as well as a wide range of flexible audio I / O interfaces. The audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0363] The processor 2510 may also include an always-on processor engine that provides the hardware features required to support low-power sensor management and wake-up use cases. The always-on processor engine may include a processor core, tightly coupled RAM, peripheral support (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0364] Processor 2510 may also include a security cluster engine, which may include a dedicated processor subsystem for handling security management for automotive applications. The security cluster engine may include two or more processor cores, tightly coupled RAM, peripheral support (e.g., timers, interrupt controllers, etc.), and / or routing logic. In secure mode, the two or more cores may operate in lockstep mode and act as a single core, with comparison logic to detect any differences between their operations. Processor 2510 may also include a real-time camera engine, which may include a dedicated processor subsystem for handling real-time camera management. Processor 2510 may also include a high dynamic range signal processor, which may include an image signal processor, a hardware engine that is part of the camera processing pipeline.

[0365] Processor 2510 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) for implementing video post-processing functions required by a video playback application to generate a final image for the player window. The video image...

Claims

1. A processor, comprising: One or more circuits, said one or more circuits for causing a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors.

2. The processor of claim 1, wherein the one or more portions of the one or more software programs are executed using information generated by another or more portions of the one or more software programs.

3. The processor of claim 1, wherein the compiler is configured to indicate the one or more portions of the one or more software programs based at least in part on the input memory requirements and output memory requirements of the one or more software programs.

4. The processor of claim 1, wherein the compiler is configured to allocate one or more portions of memory for use by the one or more software programs.

5. The processor of claim 1, wherein the one or more portions of the one or more software programs are modified by the compiler to be executed concurrently by the one or more processors.

6. The processor of claim 1, wherein the one or more portions of the one or more software programs are configured to generate information that will be asynchronously provided to one or more other portions of the one or more software programs.

7. The processor of claim 1, wherein the one or more processors are configured to execute the one or more portions of the one or more software programs.

8. A system comprising: One or more processors, said one or more processors being used to cause a compiler to instruct one or more portions of one or more software programs to be executed concurrently by one or more processors.

9. The system of claim 8, wherein the one or more portions of the one or more software programs will perform using information generated by another one or more portions of the one or more software programs.

10. The system of claim 8, wherein the compiler is configured to indicate the one or more portions of the one or more software programs based at least in part on the input memory requirements and output memory requirements of the one or more software programs.

11. The system of claim 8, wherein the compiler is configured to allocate one or more portions of memory for use by the one or more software programs.

12. The system of claim 8, wherein the one or more portions of the one or more software programs are modified by the compiler to be executed concurrently by the one or more processors.

13. The system of claim 8, wherein the one or more portions of the one or more software programs are used to generate information that will be asynchronously provided to one or more other portions of the one or more software programs.

14. The system of claim 8, wherein the one or more processors are configured to execute the one or more portions of the one or more software programs.

15. A method comprising: This instructs the compiler to specify one or more parts of a software program that will be executed concurrently by one or more processors.

16. The method of claim 15, further comprising: The one or more portions of the one or more software programs are executed using information generated by another one or more portions of the one or more software programs.

17. The method of claim 15, further comprising: The compiler indicates the one or more portions of the one or more software programs based at least in part on the input memory requirements and output memory requirements of the one or more software programs.

18. The method of claim 15, further comprising: The compiler causes one or more portions of memory to be allocated for use by the one or more software programs.

19. The method of claim 15, wherein the one or more portions of the one or more software programs are modified by the compiler to be executed concurrently by the one or more processors.

20. The method of claim 15, further comprising: Information generated by one or more parts of the one or more software programs will be asynchronously provided to one or more other parts of the one or more software programs.

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