Distributed attention calculation system

Abstract

The invention provides a distributed attention computing system, and relates to the technical field of high-performance computing. The device comprises a division unit and a scheduling unit, the division unit is used for performing task division on an input sequence request according to a pre-established mapping relation between a logic block and a physical core of a wafer-level chip to obtain a task distribution queue containing calculation tasks; and the scheduling unit is used for performing dynamic scheduling calculation based on physical core distance perception on the first calculation task and the second calculation task to obtain a task scheduling sequence, and executing the task scheduling sequence. According to the system provided by the embodiment of the invention, the calculation task is mapped to the adjacent physical core position of the wafer-level chip, and then dynamic scheduling calculation based on physical core distance perception is carried out, so that the efficiency of distributed attention calculation is improved in a manner of avoiding long-delay communication.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing technology, and more specifically to a distributed attention computing system. Background Technology

[0002] The input sequence can be a context window of a large language model composed of lexical units. As large language models develop towards longer context windows (millions to tens of millions of tokens), the computational and communication bottlenecks of the task become increasingly prominent.

[0003] To overcome this bottleneck, system-on-wafer (SoC) integration technology has emerged as an emerging direction. Wafer-level chips can integrate 850,000 / 900,000 AI cores, equipped with 40GB of on-chip SRAM and 22PB / s on-chip bandwidth (7000 times higher than GPUs); existing packaging technologies can achieve integration of millions of cores. Meanwhile, distributed attention algorithms continue to evolve: Ring-Attention overlaps computation and communication through ring-like communication, but the communication complexity increases linearly with the number of GPUs; Mesh-Attention uses two-dimensional tile partitioning instead of one-dimensional rings, theoretically reducing the communication complexity from O(n) to O(n). With a 256 GPU configuration, communication volume is reduced by 79%. Current mainstream LLM inference systems (such as vLLM and SGLang) and DNN compilers (such as Ladder) are optimized for GPU / TPU shared memory architectures, while compilers such as T10, which are designed for distributed on-chip memory, assume that on-chip cross switches provide constant latency.

[0004] Despite the progress made by each of these technologies, fundamental mismatches exist. For example, when Ring-Attention is combined with wafer-level chips, ring communication on a 2D mesh NoC results in long-distance communication spanning thousands of hops (with latency differences reaching 1000 times). With a 128 GPU configuration, communication latency accounts for as much as 91.5%, resulting in performance lower than a single GPU. When Mesh-Attention is combined with GPU clusters, the mapping of logical tiles to physical GPUs ignores topological locations, and Q / KV communication within a tile may span multiple nodes. With 256 GPUs, only a 2.9x speedup is achieved, failing to fully utilize O(log n) speedup. Theoretical advantages: General-purpose DNN compilers (such as Ladder) assume uniform memory access and cannot handle the non-uniform latency of wafer-level chips. Coarse data partitioning leads to memory constraint violations, resulting in a speedup of 100 times compared to a single A100 on WSE-2. The root cause is that there is a topological abstraction layer between the logical 2D tile of Mesh-Attention and the physical 2D mesh of the wafer-level chip, causing the communication path to be misaligned with physical proximity. This prevents the use of the ultra-high bandwidth (22PB / s) of the wafer level to support fine-grained communication, creating a performance gap due to advanced hardware but mismatched software. Summary of the Invention

[0005] To address the problems in the prior art, embodiments of the present invention provide a distributed attention computing system that can at least partially solve the problems existing in the prior art.

[0006] On one hand, this invention proposes a distributed attention computing system, including a partitioning unit and a scheduling unit; wherein: The partitioning unit is used to partition the input sequence request into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, thereby obtaining a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The scheduling unit is used to perform dynamic scheduling calculations based on physical core distance perception on the first computing task and the second computing task respectively, to obtain a task scheduling sequence, and to execute the task scheduling sequence.

[0007] The distributed attention computing system further includes a construction unit: The construction unit is used to map the logical blocks to the physical core according to the pre-determined block parameters and preset mapping function to obtain the mapping relationship.

[0008] The preset mapping function includes a first mapping function based on a physical layout strategy; correspondingly, the construction unit is specifically used for: The physical core is divided according to the block parameters to obtain multiple sub-physical blocks; Based on the logical block identifier, the number of the plurality of sub-physical blocks, and the size of each sub-physical block, the logical block corresponding to the logical block identifier is allocated to the target sub-physical block, and a computing task is mapped to each target sub-physical block; wherein, the number of computing tasks mapped to the target sub-physical block is equal to the block parameter; The query vector group members are arranged continuously according to the logical block identifier to obtain a first arrangement sequence. The key value vector group members are arranged continuously at equal intervals according to the logical block identifier to obtain a second arrangement sequence. The interval length of the arrangement is the first block parameter corresponding to the query vector. The query vector group members are the key value vectors corresponding to each query vector group, and the key value vector group members are the query vectors corresponding to each key value vector group. Determine a first starting position in a first target sub-physical block for mapping query vector groups, and sequentially map each member of the query vector group in the first permutation sequence to a subsequent column in the same row as the first starting position; determine a second starting position in a second target sub-physical block for mapping key-value vector groups, and sequentially map each member of the key-value vector group in the second permutation sequence to a subsequent row in the same column as the second starting position.

[0009] Wherein, the preset mapping function includes a second mapping function based on a mathematical mapping function; correspondingly, the construction unit is specifically used for: The logical block identifier is decomposed to obtain the index within the query vector group in the first value range and the index within the key value vector group in the second value range; Wherein, the upper limit of the first value range is the first block parameter, and the upper limit of the second value range is the second block parameter; Based on the index within the query vector group and the index within the key-value vector group, the block parameters are mapped to the target physical location of the physical core using the following mapping expression:

[0010] Where i is the index within the query vector group, and j is the index within the key-value vector group. To preset the row step size parameter, For preset column loop parameters, The row number of the physical core; Preset column step size parameter, For preset row loop parameters, The number of columns in the physical core.

[0011] The scheduling unit includes a profit calculation subunit, an update subunit, and an acquisition subunit; wherein: The profit calculation subunit is used to perform profit calculation based on physical core distance perception on the first task distribution queue and the second task distribution queue to obtain a first profit calculation result corresponding to the query vector group and a second profit calculation result corresponding to the key value vector. The update subunit is used to perform communication and calculation overlap calculation of the key value vector group if it is determined that the first profit calculation result is less than the second profit calculation result, and update the calculation tasks in the first task distribution queue and the second task distribution queue according to the calculation result; The acquisition subunit is used to execute the computation tasks of the third parameter group until completion if it is determined that the computation tasks in the first task distribution queue and the second task distribution queue are empty, thereby obtaining the task scheduling sequence.

[0012] The profit calculation subunit is further used for: Traverse the physical core distance to perform candidate communication operations on the query vector group and key value vector group, and obtain the query vector group distance length value and the number of unlocked first computing tasks corresponding to the query vector group for each traversal, as well as the key value vector group distance length value and the number of unlocked second computing tasks corresponding to the key value vector group. Obtain the first distance correction calculation cost corresponding to the distance length value of the query vector group, and the second distance correction calculation cost corresponding to the distance length value of the key value vector group; Calculate the ratio of the number of unlocked first computational tasks to the first distance correction computational cost in each traversal, and use the maximum value of the ratio as the first profit calculation result; and calculate the ratio of the number of unlocked second computational tasks to the second distance correction computational cost in each traversal, and use the maximum value of the ratio as the second profit calculation result.

[0013] Specifically, the profit calculation subunit is also used for: Candidate communication operations are performed on the query vector group and the key-value vector group based on a pre-established first pre-configured path; wherein the first pre-configured path corresponds to the first communication primitive.

[0014] The distributed attention computing system is also used for: During the execution of the calculation task of the output matrix group, communication operations are performed on the output matrix group based on a pre-established second pre-configured path; wherein, the second pre-configured path corresponds to the second communication primitive.

[0015] In another aspect, embodiments of the present invention provide a distributed attention computation method, comprising: The input sequence request is divided into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, resulting in a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The first computing task and the second computing task are respectively subjected to dynamic scheduling calculation based on physical core distance perception to obtain a task scheduling sequence, and the task scheduling sequence is executed.

[0016] According to one aspect of this disclosure, a wafer-level chip is provided, the wafer-level chip including the distributed attention computing system described above.

[0017] According to one aspect of this disclosure, a board is provided, the board comprising the wafer-level chip as described above.

[0018] According to one aspect of this disclosure, an electronic device is provided, the electronic device including the board as described above.

[0019] The distributed attention computing system provided in this embodiment of the invention includes a partitioning unit and a scheduling unit. The partitioning unit is used to partition input sequence requests into tasks based on a pre-established mapping relationship between logical blocks and physical cores of a wafer-level chip, resulting in a task distribution queue containing computing tasks. The task distribution queue includes a first task distribution queue corresponding to a query vector and a second task distribution queue corresponding to a key-value vector. A first computing task in the first task distribution queue is mapped to a continuously variable physical core horizontal coordinate, and a second computing task in the second task distribution queue is mapped to a continuously variable physical core vertical coordinate. The scheduling unit is used to perform dynamic scheduling calculations based on physical core distance awareness on the first and second computing tasks respectively, obtaining a task scheduling sequence, and executing the task scheduling sequence. By mapping computing tasks to adjacent physical core locations of the wafer-level chip, dynamic scheduling calculations based on physical core distance awareness are performed, thereby improving the efficiency of distributed attention computing by avoiding long-latency communication. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a distributed attention computing system provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram illustrating the architecture of a distributed attention computing system provided in another embodiment of the present invention.

[0022] Figure 3 This is a flowchart illustrating a distributed attention computation method provided in an embodiment of the present invention.

[0023] Figure 4 This is a flowchart illustrating a distributed attention computation method provided in another embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0025] Explanation of relevant terms: WSE NoC (Wafer Scale Engine Network-on-Chip) is a wafer-level engine network on-chip.

[0026] GPU (Graphics Processing Unit) / Graphics card.

[0027] vLLM (Virtual Large Language Model serving system) is a system that provides services for virtual large language models.

[0028] SGLang (Structured Generation Language) is a structured generation language.

[0029] DNN Compiler (Deep Neural Network Compiler) is a compiler for deep neural networks.

[0030] Q: Query vector.

[0031] KV: Key-value vector.

[0032] O: Output matrix.

[0033] Logical Tiles: In Mesh-Attention (Distributed Attention Computation), logical tiles can be understood as computational tiles, which are subtask regions allocated to each GPU (physical core) after the attention computation is divided into two-dimensional blocks.

[0034] Input sequence request: This is a computational task that inputs into Mesh-Attention for computation. It consists of multiple tokens. A token is a discrete symbol generated after text is tokenized. It can be a word, a subword (such as the BPE segmentation result), or a character. In multimodal scenarios, it can also be a non-text element such as an image region. In this embodiment of the invention, the token can be understood as the smallest semantic unit for processing text.

[0035] Figure 1This is a schematic diagram of the structure of a distributed attention computing system provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the distributed attention computing system provided in this embodiment of the invention includes a partitioning unit 1 and a scheduling unit 2, wherein: The partitioning unit 1 is used to partition the input sequence request into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, thereby obtaining a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The scheduling unit 2 is used to perform dynamic scheduling calculations based on physical core distance awareness on the first computing task and the second computing task respectively, to obtain a task scheduling sequence, and to execute the task scheduling sequence. The distributed attention computing system of the present invention can run on a wafer-level computing chip, which contains a computing core array connected by a two-dimensional mesh network of P_rows × P_cols.

[0036] like Figure 2 As shown, the task divider is used to automatically determine the optimal two-dimensional block shape (a×b) based on the Q, K, and V tensor dimensions calculated by attention and the core grid size of the chip, where a×b ≤ P_rows × P_cols.

[0037] The hardware sensor for PLMR is described below: P (parallel scale): Records the grid size of the physical core (e.g., P_rows × P_cols).

[0038] L (Delay): By using micro-benchmark testing, the single-hop transmission delay α and software routing overhead β are calibrated to establish a quantitative relationship between communication distance (number of hops) and delay.

[0039] M (memory): Gets the available local memory capacity Mem_core for each core.

[0040] R (routes): Get the maximum number of simultaneous routes supported by each core (Routes_max).

[0041] The mapping optimizer is explained below: Based on the number and topology of the physical cores of the wafer-level chip, the block parameters of the logic blocks are determined, namely the optimal block parameters (a,b), and then the mapping relationship between the logic blocks and the physical cores is established.

[0042] Mesh-Attention's a×b logical tiles are directly mapped to the physical cores of the wafer-level chip. Based on the physical hop count satisfying the "local Q-KV property" (each physical core calculates the Q-KV pairs of its neighboring physical cores, eliminating cross-mesh diagonal communication), the specific method is as follows: The total amount of data that each physical core needs to communicate can be calculated using the following formula:

[0043] in, The total amount of data that each physical core needs to communicate. The block parameters are defined as follows: 'a' is the first block parameter corresponding to the query vector, and 'b' is the second block parameter corresponding to the key-value vector. d represents the sequence length composed of the smallest semantic units, and d represents the feature dimension of each smallest semantic unit; the physical topology can be made close to a square grid (a≈b), and the communication links should be configured evenly to avoid uneven bandwidth in the row / column direction.

[0044] The specific explanation is as follows: b = n / a, ; Ignore constant terms , minimize communication volume = ; According to the arithmetic-geometric inequality: ; If and only if ,Right now , When the time is equal, the communication volume is at its lowest. The lowest communication volume at that time.

[0045] Technical effects: Mesh-Attention significantly reduces communication volume and communication overhead, resulting in a substantial reduction in communication latency. It also increases the overlap between computation and communication, thereby significantly improving computational utilization and system throughput.

[0046] The Q-sequence dimension and the KV-sequence dimension constitute a logical n_q × n_kv computational grid. Based on the P parameter, the logical computational grid is divided into a × b computational tasks (tiles), where the selection of a and b must satisfy a × b ≤ P_rows × P_cols, and minimize communication overhead. Approaching optimal (optimal at a≈) (nearby), since n = a × b and a ≈ According to Once b is obtained, the block parameters are thus determined.

[0047] To maximize the communication efficiency of wafer-level mesh topology, this invention provides a topology-aware mapping strategy for computational tiles to physical cores for mesh-attention workloads: a computational tile of logical size a×b (where a corresponds to the Q-group dimension and b corresponds to the KV-group dimension) is mapped to a physically continuous and shape-adapted core sub-mesh a′×b′, where each Q-group in the Q-group dimension (query vector group) corresponds to b KV (query vector group members), and each KV-group in the KV-group dimension (key value vector group) corresponds to a Q (key value vector group members).

[0048] In this design, a′ and b′ are dynamically adjusted based on the actual physical coordinates of the cores on the wafer to minimize the Manhattan distance and communication hop count between cores within a tile. This mapping fully leverages the characteristics of highly localized communication within Q-groups in Mesh-Attention (where logically continuous cores a need to interact frequently) and the regular sparse pattern of communication within KV-groups (where logically discrete but spatially predictable cores b exchange data periodically). By aligning logical proximity with physical proximity, members of the same Q-group or KV-group occupy adjacent or short-hop-reachable positions within the mesh NoC as much as possible. This design effectively reduces communication latency for all-reduce and gather-scatter operations within a group, alleviates link contention and congestion caused by long-distance routing, and thus achieves high-bandwidth, low-latency on-chip data exchange under limited routing resources (e.g., <32 paths per core).

[0049] The specific mapping method is as follows: Logical computation grid: For simplicity, assume that the number of Q and KV blocks are equal, i.e., n_q = n_kv, and the total number of logical cores n = a × b).

[0050] Logical Tile: Each GPU / core is responsible for an a × b logical computation task. The logical core ID is denoted as g (0 ≤ g < n).

[0051] Physical core mesh: A two-dimensional mesh with dimensions P_rows × P_cols. The physical core coordinates are (px, py).

[0052] The goal is to find a mapping function F that maps g to (px, py), and its inverse function (for routing).

[0053] Method 1 is implemented based on the first mapping function of the physical layout strategy, and is explained in detail below: (1) Define sub-physical blocks: Divide the entire physical core grid P_rows × P_cols into several physical blocks of size B_r × B_c. The choice of B_r and B_c should be proportional to the a × b of the logical tile, usually B_r ≈ a, B_c ≈ b. For example, if a=4, b=4, you can choose B_r=4, B_c=4 or B_r=8, B_c=2 (adjust according to the network shape).

[0054] (2) Allocation of logical cores to physical blocks: Number the n logical cores (i.e., n logical tiles) in row priority or column priority order. The logical block identifier can be specifically the logical block number numbered in row priority or column priority order.

[0055] These logical cores are cyclically distributed across various sub-physical blocks. Specifically, a logical core g is allocated to a sub-physical block (floor(g / (B_r×B_c)) mod (total_blocks)). This ensures that the logical cores are evenly distributed across the physical space, which is beneficial for load balancing. Here, total_blocks represents the number of sub-physical blocks, and B_r×B_c represents the size of each sub-physical block. The value of the logical core g is represented by the logical block number. Each logical block number is traversed, and calculations are performed according to (floor(g / (B_r×B_c)) mod (total_blocks)). Each calculation completes the mapping calculation task to a target sub-physical block.

[0056] (3) Mapping within a sub-physical block: Taking a selected sub-physical block as an example, it is necessary to map a×b computation tasks belonging to the same logical tile. These a×b computation tasks correspond to a Q group members and b KV group members.

[0057] Within a physical block, the method of this invention does not simply place logical core IDs consecutively, but rather according to the Q-group and KV-group definitions of Mesh-Attention to ensure intra-group proximity. For a logical tile g, its Q-group members are consecutive in logical ID: {g, g+1, ..., g+a-1}, i.e., the first permutation sequence. Its KV-group members are equally spaced in logical ID: {g, g+a, g+2a, ..., g+(b-1) ×a}, i.e., the second permutation sequence.

[0058] (4) Physical Layout Strategy: Within a B_r × B_c sub-physical block (the first target sub-physical block), prioritize ensuring that Q group members are consecutive in physical rows and KV group members are consecutive in physical columns. For example, place the logical core g (the main core of the Tile) at a certain starting position (sx, sy) within this sub-physical block, i.e., the first starting position. Place the other a-1 cores of the same Q group sequentially in the subsequent columns of the same physical row (sx, sy+1), (sx, sy+2), ... If the row cannot accommodate them, move them to the next row. The goal is to make these a cores physically form a compact 1D or 2D local region (sub-row or small rectangle).

[0059] For a KV group, the logical cores g, g+a, g+2a, ... are physically placed within another B_r × B_c sub-physical block (the second target sub-physical block). Priority is given to ensuring that KV group members are consecutive in physical columns and Q group members are consecutive in physical rows. For example, the logical core g (the main core of the Tile) is placed at a starting position (sx′, sy′) within this sub-physical block, i.e., the second starting position. The other b-1 cores from the same KV group are placed sequentially in subsequent rows of the same physical column (sx′+1, sy′), (sx′+2, sy′), ... If a column cannot accommodate them, they are moved to the next column. The goal is to make these b cores physically form a compact 1D or 2D local region (sub-column or small rectangle).

[0060] The first target sub-physical block and the second target sub-physical block of the present invention can both be arbitrarily selected. The first starting position in the first target sub-physical block and the second starting position in the second target sub-physical block can also be arbitrarily selected in the present invention. The key point is to ensure that the query vector and key value vector after this sub-physical block are continuous in physical location.

[0061] Method 2 is implemented based on the second mapping function of the mathematical mapping function, as detailed below: If the physical mesh is large and regular enough, a direct mathematical mapping function can be defined. For example, a bijective linear transformation can be used.

[0062] Let the logical core ID g be decomposed into g = i × b + j, where 0 ≤ i < a, 0 ≤ j < b (i can be regarded as the index within the Q group, and j can be regarded as the index within the KV group).

[0063] The block parameters are mapped to the target physical location of the physical core using the following mapping expression:

[0064] Where i is the index within the query vector group, and j is the index within the key-value vector group. To preset the row step size parameter, For preset column loop parameters, The row number of the physical core; Preset column step size parameter, For preset row loop parameters, The number of columns in the physical core.

[0065] in, and This is used to control the "span" of cores within the same group in physical space. For the sake of proximity, it should be set as small as possible (e.g., 1).

[0066] and This is used to control how different core groups are interleaved to avoid hotspots. For example, by setting... = b, which maps a complete key-value group (fixed j, different i) to different rows in the same column, achieving key-value group proximity. Similarly, by setting =a can map a complete Q group (fixed i, different j) to different columns in the same row, achieving Q group proximity.

[0067] The PLMR sensing communication library is explained as follows: Hardware optimizations for the three core communication modes required by Mesh-Attention: Q / KV Group Intra-Group All-Gather (First Communication Primitive) Optimization: This approach abandons the traditional, long-distance, multi-hop All-Gather implementation. Leveraging the high bandwidth and low latency of wafer-level mesh networks, it establishes one or a few statically configured, fast data paths across the entire physical scope of each communication group (Q group or KV group), i.e., the first pre-configured path. This consumes routing resources (R), but through the aforementioned proximity mapping, the required path length and number can be minimized, ensuring it remains within the Routes_max limit. Data is transmitted along this first pre-configured path in a "pipeline" or "broadcast tree" manner, rather than hop-by-hop store-and-forward, thereby significantly reducing critical path latency.

[0068] Q-group Reduce-Scatter (Second Communication Primitive) Optimization: Similarly, for the Reduce-Scatter operation of output O, design an aggregation tree based on a pre-configured path, i.e., the second pre-configured path, to aggregate some results along the tree, reducing intermediate hops and software routing overhead.

[0069] The task distribution queue containing computational tasks is explained as follows: The first task distribution queue can be denoted as Ready_Q_Blocks, and the second task distribution queue can be denoted as Ready_KV_Blocks. Taking mapping 32×32 logical tiles to a 32×32 sub-mesh at physical core coordinates (100-131, 200-231) as an example, the number of rows corresponding to Ready_Q_Blocks is 100-131, and each row includes 32 KVs. Similarly, the number of columns corresponding to Ready_KV_Blocks is 200-231, and each column includes 32 Qs.

[0070] like Figure 3 As shown, the initialization phase includes acquiring hardware PLMR parameters, including α, β, Mem_core, and Routes_max. Referring to the explanation of L (latency) above, the number of hops can be determined based on the values ​​of α and β. Then, based on the hop counts contained in Dist_Q and Dist_KV, Cost_Q and Cost_KV can be calculated. Mem_core ensures that the total number of Q blocks, KV blocks, and some O blocks temporarily stored on each core does not exceed Mem_core. Routes_max ensures that the routing resources consumed on each core do not exceed Routes_max. The initialization phase also includes acquiring the first task distribution queue and the second task distribution queue based on the pre-established mapping relationship between logical blocks and the physical cores of the wafer-level chip.

[0071] The calculation of profit based on distance perception is explained below: This includes acquiring candidate communication operations, querying physical distance, calculating distance correction computation costs, calculating the number of unlocked computational blocks, and calculating computational profits.

[0072] For acquiring candidate communication operations, namely RecvQ (pxi points to pxj) and RecvKV (pym points to pyn), taking the mapping of a 32×32 logical tile to a 32×32 sub-mesh of physical core coordinates (100-131, 200-231) as an example, the first candidate communication operation pxi pointing to pxj is: pxi=100, pxj=101, and pym pointing to pyn is pym=200, pyn=201.

[0073] For querying physical distance, i.e., Dist_Q=hops(pxi, pxj) and Dist_KV=hops(pym, pyn), referring to the above cases where pxi=100, pxj=101, pym=200, and pyn=201, Dist_Q=1 hop and Dist_KV=1 hop.

[0074] The distance correction calculation cost is calculated as Cost_Q = lookup_table(Dist_Q, BH); Cost_KV = lookup_table(Dist_KV, BH); BH is the communication bandwidth. The first distance correction calculation cost Cost_Q and the second distance correction calculation cost Cost_KV can be obtained by looking up the table.

[0075] The number of computational blocks to be unlocked, i.e. the number of first computational tasks to be unlocked, n_Q = |unlocked Q-related blocks|, is equivalent to the computation time of Q computational blocks. The computation time of a single Q is known. n_KV = |unlocked KV-related blocks|, is equivalent to the computation time of KV computational blocks. The computation time of a single KV is known.

[0076] Calculate n_Q / Cost_Q and n_KV / Cost_KV for this traversal (T=1).

[0077] Then, the next candidate communication operation is executed, i.e., the candidate communication operation pxi points to pxj as: pxi=100, pxj=102, pym points to pyn as pym=200, pyn=202. At this time, Dist_Q=2 hops, Dist_KV=2 hops, and then Cost_Q and Cost_KV are calculated, as well as the number of computational blocks unlocked by these two hops n_Q and n_KV. The n_Q / Cost_Q and n_KV / Cost_KV of this traversal (T=2) are calculated.

[0078] This process continues until pxi=100, pxj=131, pym=200, pyn=231, then repeats pxi=101, pxj=102, pym=201, pyn=202…pxi=101, pxj=131, pym=201, pyn=231, until the last iteration reaches pxi=130, pxj=131, pym=230, pyn=231. At this point, the maximum value among all the calculated n_Q / Cost_Q is taken as the first profit calculation result Prfit_Q, and the maximum value among n_KV / Cost_KV is taken as the second profit calculation result Prfit_KV.

[0079] If Prfit_Q is less than or equal to Prfit_KV, then the communication and computation overlap calculation of the KV group is performed. If Prfit_Q is greater than Prfit_KV and all Rec Q / KV operations are not completed, then the above steps for distance-aware profit calculation are continued. The details will not be repeated here.

[0080] The communication and computation overlap calculations for KV groups are explained below: Execute the RecvKV operation on the communication path corresponding to Prfit_Q being less than or equal to Prfit_KV. This communication path has the advantages of both short distance and a large number of unlocked computational tasks. Then, calculate the physical distance Dist_KVhops of this RecvKV operation and trigger overlapping computation based on this physical distance. After the computation is completed, update the computational tasks in the first and second task distribution queues. The update includes deleting completed computational tasks and adding new computational tasks.

[0081] If all Rec Q / KV operations have been completed, but not all Send O operations have been completed, then the output portion is executed. Specifically, this includes checking if a complete row has been calculated. If yes, then the Send O operation is executed using the second pre-configured path. If no, then the overlapping calculation O operation continues, and the output status is updated according to the overlapping calculation result. After updating the output status, the step of determining whether all Send O operations have been completed is executed again.

[0082] It should be noted that if a complete row is calculated, it means that one group Q has completed the O operation calculation. If no complete row is calculated, it means that no group Q has completed the O operation calculation yet, that is, there are still other members of group Q (columns of group Q) that have not completed the O operation calculation.

[0083] If all Send O operations are completed, it indicates that dynamic scheduling calculations have yielded a task scheduling sequence. This task scheduling sequence is understood to be the most profitable task scheduling sequence based on physical core distance perception. Executing this task scheduling sequence at the wafer-level chip level can significantly improve communication efficiency.

[0084] like Figure 4 As shown, the distributed attention computing system provided in the embodiments of the present invention will be further described as follows: 1. Input stage: When the system starts, it receives the following input parameters: (1) Model parameters: including the configuration information of the LLM model, such as the number of attention heads (e.g., 32), the dimension of hidden layers (e.g., 4096), the number of layers, etc. (2) Sequence length: the minimum number of semantic units to be processed (Token Count), for example, 1M.

[0085] 2. Hardware parameter acquisition and modeling: The system automatically detects or reads the hardware specifications of the wafer-level chip and establishes a PLMR model: Core Count: Identifies the total number of available computing cores (e.g., approximately 850,000). Total Memory: Obtains the aggregate on-chip memory capacity (e.g., 40GB SRAM). Bandwidth: Measures the total memory bandwidth of the on-chip network (NoC) (e.g., 22PB / s). Number of Routes: Determines the maximum number of concurrent routing paths supported by each core (e.g., 32). Latency Parameters: Calibrates single-hop transmission delay α (e.g., 1 cycle) and software routing overhead β (e.g., 10 cycles) using micro-benchmarks.

[0086] 3. Task allocation and optimization: Based on input and hardware parameters, logical tasks are partitioned: The number of logical blocks is determined by the sequence length and hardware parallelism capabilities. For example, for a 1M sequence, it might be divided into n=1024 logical blocks, each performing a 1024B computation task. The specific task partitioning method is not limited; for instance, it can be based on the order in which the smallest semantic units appear in the text of the input sequence request, sequentially selecting units with a minimum number of 1024B to form the computation tasks assigned to each logical block. An example is provided below: The input sequence request = {u1, u2, ... ue} represents a sequence consisting of e smallest semantic units. If the total capacity of the m smallest semantic units u1, u2, ... um is 1024B, then they are allocated to logic block 1 for computation; if the total capacity of the nm smallest semantic units um+1, u m+2, ... un is 1024B, then they are allocated to logic block 2 for computation, and so on.

[0087] Optimal a×b selection: The values ​​of a and b are selected using optimization algorithms (such as traversal search or formula-based derivation) to minimize a×b=n and theoretical communication volume. Typically, a=32 and b=32 are chosen (because 32×32=1024), at which point the communication complexity is close to optimal. Theoretical communication volume calculation: The theoretical communication volume of the selected scheme is calculated and compared with benchmark schemes (such as Ring-Attention). For example, the calculated communication volume of this invention is approximately 1.26GB, a reduction of approximately 85% compared to Ring-Attention's 8.4GB. Performance prediction: Based on theoretical communication volume, computational cost, and hardware bandwidth, the speedup ratio and maximum core utilization (MFU) are predicted.

[0088] 4. The mapping from logic to physics: Mapping abstract logical computation tasks to concrete physical cores: Mapping algorithm execution: Run the mapping optimizer to map each logical a×b computation tile to a physically contiguous and compact core subgrid region. For example, map a 32×32 logical tile to a 32×32 subgrid at physical core coordinates (100-131, 200-231). Proximity guarantee: Ensure that after mapping, cores logically belonging to the same Q group (requiring frequent intra-row communication) are physically located in the same or adjacent rows; cores belonging to the same KV group (requiring frequent intra-column communication) are physically located in the same or adjacent columns. The goal is to maximize the physical proximity of cores within a group and minimize the number of communication hops.

[0089] 5. Communication optimization configuration: Based on the mapping results, configure hardware-level communication paths: Q-group path configuration: Configure a horizontal broadcast path on the corresponding physical row for each logical Q-group (32 groups in total). Utilize the chip's static routing function to pre-program these paths into the hardware routing table. KV-group path configuration: Configure a vertical broadcast path on the corresponding physical column for each logical KV-group (32 groups in total). Resource constraint check: Ensure that the total number of configured routing paths does not exceed the Routes_max limit for each core (e.g., 32 paths).

[0090] 6. Scheduling Generation and Optimization: Generate a micro-scheduled instruction sequence to guide the overlapping execution of computation and communication: Performance profiling integration: Incorporating distance-latency cost data measured during the hardware modeling phase (e.g., 5 compute blocks need to be hidden for 1-hop communication, and 50 compute blocks need to be hidden for 16-hop communication). Distance-aware greedy algorithm execution: The scheduler evaluates all ready communication operations (Recv Q and Recv KV), calculating the "profit" of each operation (number of compute blocks unlocked / distance cost of the operation). Scheduling sequence generation: Prioritizes scheduling high-profit, short-distance operations and schedules the corresponding compute blocks to execute during their communication to hide communication latency. Finally, a detailed, step-by-step instruction sequence is output.

[0091] 7. Hardware execution: The runtime system loads the configuration and scheduling sequence generated in the above steps: Configuration loading: The mapping table, routing configuration, and scheduling sequence are distributed to all cores. Computation execution: Each core, according to the scheduling sequence, alternately executes communication operations (sending and receiving data via pre-configured short paths) and computation operations (performing the computation of attention blocks). Pipeline overlap: Thanks to fine-grained scheduling, communication and computation highly overlap, maintaining high hardware utilization.

[0092] 8. Performance Monitoring: The system collects performance data during and after operation: Real-time metrics: monitoring the computational utilization of each core, communication latency, cache hit rate, etc. Performance analysis: analyzing whether the actual performance meets expectations and identifying potential bottlenecks (such as specific long-distance communication or memory bottlenecks). Feedback optimization: the collected performance data can be used in subsequent iterations to optimize task partitioning, mapping, or scheduling strategies, forming a closed-loop optimization system.

[0093] The distributed attention computing system provided in this embodiment of the invention includes a partitioning unit and a scheduling unit. The partitioning unit is used to partition input sequence requests into tasks based on a pre-established mapping relationship between logical blocks and physical cores of a wafer-level chip, resulting in a task distribution queue containing computing tasks. The task distribution queue includes a first task distribution queue corresponding to Q and a second task distribution queue corresponding to KV. A first computing task in the first task distribution queue is mapped to a continuously variable physical core horizontal coordinate, and a second computing task in the second task distribution queue is mapped to a continuously variable physical core vertical coordinate. The scheduling unit is used to perform dynamic scheduling calculations based on physical core distance awareness on the first and second computing tasks respectively, obtaining a task scheduling sequence, and executing the task scheduling sequence. By mapping computing tasks to adjacent physical core locations of the wafer-level chip, and then performing dynamic scheduling calculations based on physical core distance awareness, the efficiency of distributed attention computing is improved by avoiding long-latency communication.

[0094] In the above optional embodiments, the distributed attention computing system further includes a construction unit: The construction unit is used to map the logical blocks to the physical core according to the pre-determined block parameters and preset mapping function to obtain the mapping relationship. This can be referred to the above embodiments for further explanation and will not be repeated here.

[0095] In the above optional embodiments, the preset mapping function includes a first mapping function based on a physical layout strategy; correspondingly, the construction unit is specifically used for: The physical core is divided according to the block parameters to obtain multiple sub-physical blocks; the above embodiments can be referred to for explanation, and will not be repeated here.

[0096] Based on the logical block identifier, the number of the plurality of sub-physical blocks, and the size of each sub-physical block, the logical block corresponding to the logical block identifier is allocated to the target sub-physical block, and a computing task is mapped to each target sub-physical block; wherein, the number of computing tasks mapped to the target sub-physical block is equal to the block parameter; the above embodiments can be referred to for explanation, and will not be repeated here.

[0097] The query vector group members are arranged continuously according to the logical block identifier to obtain a first arrangement sequence. The key value vector group members are arranged continuously at equal intervals according to the logical block identifier to obtain a second arrangement sequence. The interval length of the arrangement is the first block parameter corresponding to the query vector. The query vector group members are the key value vectors corresponding to each query vector group, and the key value vector group members are the query vectors corresponding to each key value vector group. The above embodiments can be referred to for explanation, and will not be repeated here.

[0098] A first starting position is determined in the first target sub-physical block used for mapping query vector groups, and each member of the query vector group in the first permutation sequence is sequentially mapped to a subsequent column in the same row as the first starting position; a second starting position is determined in the second target sub-physical block used for mapping key-value vector groups, and each member of the key-value vector group in the second permutation sequence is sequentially mapped to a subsequent row in the same column as the second starting position. This can be referred to the above embodiment for explanation, and will not be repeated here.

[0099] In the above optional embodiments, the preset mapping function includes a second mapping function based on a mathematical mapping function; correspondingly, the construction unit is specifically used for: The logical block identifier is decomposed to obtain the index within the query vector group in the first value range and the index within the key-value vector group in the second value range; the above embodiment can be referred to for explanation, and will not be repeated here.

[0100] Wherein, the upper limit of the first value range is the first block parameter, and the upper limit of the second value range is the second block parameter; please refer to the above embodiment for explanation, and will not be repeated here.

[0101] Based on the index within the query vector group and the index within the key-value vector group, the block parameters are mapped to the target physical location of the physical core using the following mapping expression:

[0102] Where i is the index within the query vector group, and j is the index within the key-value vector group. To preset the row step size parameter, For preset column loop parameters, The row number of the physical core; Preset column step size parameter, For preset row loop parameters, This refers to the number of columns in the physical core. Refer to the above embodiments for further details; no further repetition is necessary.

[0103] In the above optional embodiments, the scheduling unit includes a profit calculation subunit, an update subunit, and an acquisition subunit; wherein: The profit calculation subunit is used to perform profit calculation based on physical core distance perception on the first task distribution queue and the second task distribution queue to obtain a first profit calculation result corresponding to the query vector group and a second profit calculation result corresponding to the key value vector; the above embodiments can be referred to for explanation, and will not be repeated here.

[0104] The update subunit is used to perform communication and calculation overlap calculation of the key value vector group if it is determined that the first profit calculation result is less than the second profit calculation result, and update the calculation tasks in the first task distribution queue and the second task distribution queue according to the calculation result; the above embodiments can be referred to for description, and will not be repeated here.

[0105] The acquisition subunit is used to execute the computation tasks of the third parameter group until completion if it is determined that the computation tasks in the first task distribution queue and the second task distribution queue are empty, thereby obtaining the task scheduling sequence. This can be referred to the above embodiments for further explanation and will not be repeated here.

[0106] In the above optional embodiments, the profit calculation subunit is further configured to: The physical core distance is traversed to perform candidate communication operations on the query vector group and the key value vector group, and the distance length value of the query vector group corresponding to the query vector group and the number of unlocked first computing tasks are obtained for each traversal, as well as the distance length value of the key value vector group corresponding to the key value vector group and the number of unlocked second computing tasks; the above embodiments can be referred to for explanation, and will not be repeated here.

[0107] Obtain the first distance correction calculation cost corresponding to the distance length value of the query vector group, and the second distance correction calculation cost corresponding to the distance length value of the key value vector group; the above embodiments can be referred to for explanation, and will not be repeated here.

[0108] Calculate the ratio of the number of unlocked first computational tasks to the first distance correction computational cost in each traversal, and use the maximum value of the ratio as the first profit calculation result. Similarly, calculate the ratio of the number of unlocked second computational tasks to the second distance correction computational cost in each traversal, and use the maximum value of the ratio as the second profit calculation result. Refer to the above embodiments for further explanation; elaboration will not be repeated here.

[0109] In the above optional embodiments, the profit calculation subunit is further specifically used for: Candidate communication operations are performed on the query vector group and the key-value vector group based on a pre-established first pre-configured path; wherein the first pre-configured path corresponds to the first communication primitive. This can be referred to the above embodiments for further explanation, and will not be repeated here.

[0110] In the above optional embodiments, the distributed attention computing system is further used for: During the calculation of the output matrix group, communication operations are performed on the output matrix group based on a pre-established second pre-configured path; wherein the second pre-configured path corresponds to a second communication primitive. This can be referred to the above embodiments for further explanation, and will not be repeated here.

[0111] This invention provides a distributed attention computation method, comprising: The input sequence request is divided into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, resulting in a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The first computing task and the second computing task are respectively subjected to dynamic scheduling calculation based on physical core distance perception to obtain a task scheduling sequence, and the task scheduling sequence is executed.

[0112] The embodiments of the distributed attention computing method provided in this invention can be used to execute the processing flow of the above system embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above system embodiments.

[0113] This disclosure also proposes a wafer-level chip, which includes the distributed attention computing system described above.

[0114] This disclosure also proposes a board that includes a wafer-level chip as described above.

[0115] This disclosure also proposes an electronic device, which includes the board described above.

[0116] Compared with existing technologies, the distributed attention computing system provided in this invention includes a partitioning unit and a scheduling unit. The partitioning unit is used to partition input sequence requests into tasks based on a pre-established mapping relationship between logical blocks and physical cores of a wafer-level chip, resulting in a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to a query vector and a second task distribution queue corresponding to a key-value vector. A first computational task in the first task distribution queue is mapped to a continuously variable physical core horizontal coordinate, and a second computational task in the second task distribution queue is mapped to a continuously variable physical core vertical coordinate. The scheduling unit performs dynamic scheduling calculations based on physical core distance awareness on the first and second computational tasks respectively, obtaining a task scheduling sequence, and executes the task scheduling sequence. By mapping computational tasks to adjacent physical core locations on the wafer-level chip, and then performing dynamic scheduling calculations based on physical core distance awareness, the efficiency of distributed attention computing is improved by avoiding long-latency communication.

[0117] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0118] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A distributed attention computing system, characterized in that, It includes a partitioning unit and a scheduling unit; wherein: The partitioning unit is used to partition the input sequence request into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, thereby obtaining a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The scheduling unit is used to perform dynamic scheduling calculations based on physical core distance perception on the first computing task and the second computing task respectively, to obtain a task scheduling sequence, and to execute the task scheduling sequence.

2. The distributed attention computing system according to claim 1, characterized in that, The distributed attention computing system also includes a construction unit: The construction unit is used to map the logical blocks to the physical core according to the pre-determined block parameters and preset mapping function to obtain the mapping relationship.

3. The distributed attention computing system according to claim 2, characterized in that, The preset mapping function includes a first mapping function based on a physical layout strategy; correspondingly, the construction unit is specifically used for: The physical core is divided according to the block parameters to obtain multiple sub-physical blocks; Based on the logical block identifier, the number of the plurality of sub-physical blocks, and the size of each sub-physical block, the logical block corresponding to the logical block identifier is allocated to the target sub-physical block, and a computing task is mapped to each target sub-physical block; wherein, the number of computing tasks mapped to the target sub-physical block is equal to the block parameter; The query vector group members are arranged continuously according to the logical block identifier to obtain a first arrangement sequence. The key value vector group members are arranged continuously at equal intervals according to the logical block identifier to obtain a second arrangement sequence. The interval length of the arrangement is the first block parameter corresponding to the query vector. The query vector group members are the key value vectors corresponding to each query vector group, and the key value vector group members are the query vectors corresponding to each key value vector group. Determine a first starting position in a first target sub-physical block for mapping query vector groups, and sequentially map each member of the query vector group in the first permutation sequence to a subsequent column in the same row as the first starting position; determine a second starting position in a second target sub-physical block for mapping key-value vector groups, and sequentially map each member of the key-value vector group in the second permutation sequence to a subsequent row in the same column as the second starting position.

4. The distributed attention computing system according to claim 2, characterized in that, The preset mapping function includes a second mapping function based on a mathematical mapping function; correspondingly, the construction unit is specifically used for: The logical block identifier is decomposed to obtain the index within the query vector group in the first value range and the index within the key value vector group in the second value range; Wherein, the upper limit of the first value range is the first block parameter, and the upper limit of the second value range is the second block parameter; Based on the index within the query vector group and the index within the key-value vector group, the block parameters are mapped to the target physical location of the physical core using the following mapping expression: Where i is the index within the query vector group, and j is the index within the key-value vector group. To preset the row step size parameter, For preset column loop parameters, The row number of the physical core; Preset column step size parameter, For preset row loop parameters, The number of columns in the physical core.

5. The distributed attention computing system according to any one of claims 1 to 4, characterized in that, The scheduling unit includes a profit calculation subunit, an update subunit, and an acquisition subunit; wherein: The profit calculation subunit is used to perform profit calculation based on physical core distance perception on the first task distribution queue and the second task distribution queue to obtain a first profit calculation result corresponding to the query vector group and a second profit calculation result corresponding to the key value vector. The update subunit is used to perform communication and calculation overlap calculation of the key value vector group if it is determined that the first profit calculation result is less than the second profit calculation result, and update the calculation tasks in the first task distribution queue and the second task distribution queue according to the calculation result; The acquisition subunit is used to execute the computation tasks of the third parameter group until completion if it is determined that the computation tasks in the first task distribution queue and the second task distribution queue are empty, thereby obtaining the task scheduling sequence.

6. The distributed attention computing system according to claim 5, characterized in that, The profit calculation subunit is also used for: Traverse the physical core distance to perform candidate communication operations on the query vector group and key value vector group, and obtain the query vector group distance length value and the number of unlocked first computing tasks corresponding to the query vector group for each traversal, as well as the key value vector group distance length value and the number of unlocked second computing tasks corresponding to the key value vector group. Obtain the first distance correction calculation cost corresponding to the distance length value of the query vector group, and the second distance correction calculation cost corresponding to the distance length value of the key value vector group; Calculate the ratio of the number of unlocked first computational tasks to the first distance correction computational cost in each traversal, and use the maximum value of the ratio as the first profit calculation result; and calculate the ratio of the number of unlocked second computational tasks to the second distance correction computational cost in each traversal, and use the maximum value of the ratio as the second profit calculation result.

7. The distributed attention computing system according to claim 6, characterized in that, The profit calculation subunit is also specifically used for: Candidate communication operations are performed on the query vector group and the key-value vector group based on a pre-established first pre-configured path; wherein the first pre-configured path corresponds to the first communication primitive.

8. The distributed attention computing system according to claim 5, characterized in that, The distributed attention computing system is also used for: During the execution of the calculation task of the output matrix group, communication operations are performed on the output matrix group based on a pre-established second pre-configured path; wherein, the second pre-configured path corresponds to the second communication primitive.

9. A distributed attention computation method, characterized in that, include: The input sequence request is divided into tasks according to the pre-established mapping relationship between logical blocks and physical cores of wafer-level chips, resulting in a task distribution queue containing computational tasks. The task distribution queue includes a first task distribution queue corresponding to the query vector and a second task distribution queue corresponding to the key value vector. The first computational task in the first task distribution queue is mapped to the horizontal coordinate of the physical core with continuous values, and the second computational task in the second task distribution queue is mapped to the vertical coordinate of the physical core with continuous values. The first computing task and the second computing task are respectively subjected to dynamic scheduling calculation based on physical core distance perception to obtain a task scheduling sequence, and the task scheduling sequence is executed.

10. A wafer-level chip, characterized in that, The distributed attention computing system included in any one of claims 1 to 8.

11. A circuit board, characterized in that, Includes the wafer-level chip as described in claim 10.

12. An electronic device, characterized in that, Includes the board as described in claim 11.

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