Matrix parallel computing method for solving minimum cut set of fault tree

Abstract

The invention discloses a matrix parallel computing method for solving a minimum cut set of a fault tree, and relates to the field of fault tree analysis. The matrix parallel computing method for solving the minimum cut set of the fault tree aims at solving the problems that in the prior art, the computing process is serialized, the parallel efficiency is low, a data structure is not matched with a GPU architecture, and the minimum cut set of the large-scale fault tree cannot be efficiently solved. According to the method, structured coding is carried out on a fault tree, and gate events and input relations are constructed into a structure description matrix; vectorizing the basic event and representing a candidate cut set of the intermediate event in a binary matrix form; under a GPU parallel architecture, row merging is performed on an OR gate, broadcast type combination is performed on an AND gate, parallel cut set simplification is performed, and meanwhile, a blocking and cache multiplexing strategy is introduced to improve the calculation throughput rate and reduce memory occupation. And carrying out loop iteration until the top event matrix is stable, and outputting a minimum cut set. The method is suitable for safety and reliability analysis of a large complex engineering system.

Description

Technical Field

[0001] This involves the field of fault tree analysis, and in particular, matrix-based parallel computation for finding the minimum cut set of a fault tree. Background Technology

[0002] Fault Tree Analysis (FTA) is a top-down system safety analysis method that identifies system weaknesses and assesses failure risks by modeling and reasoning the logical relationships between unwanted events (top events) and potential causes (basic events) in a system. Since its inception at Bell Labs in the 1960s, this method has been widely applied in high-reliability industries such as aerospace, nuclear energy, power, rail transportation, automotive electronics, and chemical safety.

[0003] In fault tree analysis, solving for the minimum cut set (MCS) is the most crucial step. A minimum cut set represents a minimal set of basic events; the top event occurs when all these events occur simultaneously. Accurately and efficiently solving for the minimum cut set is essential not only for the accuracy of system failure mode identification and quantitative reliability assessment but also for the scientific validity of system safety design and maintenance strategies.

[0004] For finding the minimum cut set, scholars and engineering software developers both domestically and internationally have proposed various algorithms and improved methods. For example: (1) MOCUS algorithm (Method of Obtaining Cut Sets): This method generates cut sets step by step through top-down logical expansion and is one of the earliest and most classic algorithms. Its advantage is that it is simple to implement, but in large-scale fault trees, it is necessary to perform logical simplification frequently, which leads to an exponential increase in computational complexity.

[0005] (2) Fussell-Vesely algorithm: It solves the intermediate event cut set step by step by the idea of ​​logical simplification, which improves the computational efficiency to some extent, but it is still unfolded in a recursive form, making it difficult to make full use of the parallel capabilities of modern computing platforms.

[0006] (3) Algorithms based on Boolean algebra and ZBDD (Zero-suppressed Binary Decision Diagram): This type of method uses the decision graph data structure for logical compression, which can effectively reduce redundant calculations. A typical example is the BDD solver module in the SCRAM tool. However, BDD-type methods can consume huge memory resources in large-scale engineering systems due to node explosion, and there are difficulties in parallelization implementation.

[0007] (4) Heuristic and intelligent algorithms: In recent years, some studies have attempted to introduce cut set search, branch deduction or Monte Carlo simulation to improve minimum cut set search. However, these methods generally rely on random search mechanisms, which make it difficult to guarantee the integrity and determinism of the results, and the computational efficiency decreases rapidly with the problem size.

[0008] With the rapid increase in the scale and complexity of modern engineering systems, traditional minimum cut set solutions face significant challenges: On the one hand, the system has a deep hierarchy, many logic gates, and complex combinations, which leads to an exponential increase in the number of cut sets. Traditional recursive or serial algorithms are time-consuming and consume a lot of memory. On the other hand, the data structures of existing algorithms (such as linked lists and tree structures) are not suitable for modern parallel architectures such as GPUs, and cannot fully utilize the high throughput and multi-threaded concurrency characteristics of graphics processors. In addition, current mainstream methods focus more on algorithm-level improvements, but lack systematic reconstruction from the perspective of data structures and computational mapping mechanisms, and have failed to achieve the transformation from symbolic logic solution to numerical matrix solution.

[0009] In summary, existing technologies suffer from drawbacks such as serialized computation processes, low parallel efficiency, data structures that are not compatible with GPU architectures, and the inability to efficiently solve for the minimum cut set of large-scale fault trees. Summary of the Invention

[0010] To address the shortcomings of existing technologies, such as serialized computation processes, low parallel efficiency, data structures incompatible with GPU architecture, and inability to efficiently solve for the minimum cut set of large-scale fault trees, the technical solution provided by this invention is as follows: A matrix-based parallel computation method for solving the minimum cut set of a fault tree includes: The input fault tree model is structured and encoded to establish a structural description matrix that represents the relationship between gate events and input events and the gate type attributes. The fault tree logic structure is uniformly represented in matrix form to form a computable input step. The steps are: to vectorize the basic events and generate corresponding one-hot vectors, and to combine the intermediate events and their candidate cut sets into a candidate matrix in binary form to form a set of data inputs for logical operations; The steps to determine intermediate events in the current computation round where all inputs have candidate matrices based on the structure description matrix, and to generate a list of target events to ensure the correctness of the computation order; When the intermediate event is an OR gate, the process involves performing row-dimensional merging and parallel deduplication on the candidate matrix of the input event to generate a union candidate matrix, and then outputting the result as the input of the upper-level event. When the intermediate event is an AND gate, the input candidate matrix is ​​expanded in row dimension and component-wise combination and normalization are performed on the parallel processing unit to generate a Cartesian combination matrix. The combination result is output for subsequent simplification steps. The process involves performing parallel cut set comparison on the generated candidate matrix to remove redundant cut sets with inclusion relations and retain the minimum cut set, and then using the simplified matrix as the input for the next round. Based on the size of the candidate matrix and the computational bandwidth, a blockization and cache reuse strategy is dynamically implemented to reduce memory consumption and improve computational throughput, and the optimization results are used for continuous iterative computation. The process involves iteratively performing steps to determine intermediate events, logical combinations, and parallel simplifications until the top event candidate matrix stabilizes and the minimum cut set is output as the final solution.

[0011] Furthermore, in a preferred embodiment, the structured coding process employs a partitioned structure description matrix to represent the input relationships between gate events and the input relationships between gate events and basic events in partitions, and sets gate type identifiers in additional columns to distinguish between AND gates and OR gates.

[0012] Furthermore, in a preferred embodiment, during the vectorization representation process, the number of basic events in the system is used as the vector dimension, each event or event combination is represented as a binary vector, and multiple cut set vectors are stacked row by row to form a candidate matrix.

[0013] Furthermore, in a preferred embodiment, the candidate matrix of multiple input events of the AND gate is expanded along the row dimension and a component-wise addition operation is performed on a parallel processing unit, and the binary property is maintained by performing normalization on the elements greater than one in the addition result.

[0014] Furthermore, in a preferred embodiment, an inclusion relationship judgment mechanism is used to perform parallel comparison of all row vectors of the candidate matrix, and the containing row vector is deleted when it is detected that a row vector completely contains another row vector.

[0015] Furthermore, in a preferred embodiment, computational blocks are dynamically divided according to the size of the candidate matrix and the bandwidth of the computing hardware, and cache space is reused in the cyclic computation.

[0016] Based on the same inventive concept, the present invention also provides a matrix-based parallel computing device for solving the minimum cut set of a fault tree, comprising: The input fault tree model is structured and encoded to establish a structural description matrix that represents the relationship between gate events and input events and the gate type attributes. The fault tree logic structure is uniformly represented in matrix form to form a module that can compile input. The module represents basic events in vector form and generates corresponding one-hot vectors. It combines intermediate events and their candidate cut sets into a candidate matrix in binary form to form a data input set for logical operations. Based on the structure description matrix, determine the intermediate events in the current calculation round where all inputs have candidate matrices, and generate a list of target events to ensure the correctness of the calculation order; When the intermediate event is an OR gate, the module performs row-dimensional merging and parallel deduplication on the candidate matrix of the input event to generate a union candidate matrix, and outputs the result as the input of the upper-level event. When the intermediate event is an AND gate, the input candidate matrix is ​​expanded in row dimension and component-wise combination and normalization are performed on the parallel processing unit to generate a Cartesian combination matrix. The combination result is output to the module for subsequent simplification. The module performs parallelized cut set comparison on the generated candidate matrix to remove redundant cut sets with inclusion relations and retain the minimum cut set, and uses the simplified matrix as the input for the next round. Based on the size of the candidate matrix and the computational bandwidth, a module dynamically implements blockization and cache reuse strategies to reduce memory consumption and improve computational throughput, and uses the optimization results for continuous iterative computation. The module iteratively executes intermediate events determination, logical combination, and parallel simplification operations until the top event candidate matrix stabilizes and outputs the minimum cut set as the final solution.

[0017] Based on the same inventive concept, the present invention also provides a computer storage medium for storing a computer program, wherein when the computer program is read by a computer, the computer executes the method described thereon.

[0018] Based on the same inventive concept, the present invention also provides a computer, including a processor and a storage medium, wherein when the processor reads a computer program stored in the storage medium, the computer executes the method described thereon.

[0019] Based on the same inventive concept, the present invention also provides a computer program product, which, when executed, implements the method described.

[0020] Compared with the prior art, the advantages of the technical solution provided by the present invention are as follows: This scheme achieves the transformation from symbolic logic to numerical computation by representing the logical solution process of fault trees in a matrix format. This design allows gate events, input events, and their logical relationships to be stored and processed in a unified matrix and vector form, avoiding the memory access irregularities caused by linked list and tree structures in traditional algorithms. Compared to recursive algorithms such as MOCUS and Fussell-Vesely, this matrix structure is naturally adapted to parallel hardware architectures such as GPUs, significantly improving the parallelizability of computation and memory access efficiency, thereby enabling efficient modeling and computation of large-scale fault trees.

[0021] This scheme employs a broadcast-style parallel combination strategy in the AND gate computation stage. It expands the input candidate matrix by row dimension to achieve full Cartesian combinations, and then generates all candidate combinations at once on the GPU core through component-wise addition. This approach fully leverages the multi-threaded architecture of the GPU, significantly improving computational throughput compared to the traditional CPU-based method of iterative computation. With the same input size, the scheme can complete combination computation in an order of magnitude shorter time, solving the problem of exponential computational expansion in the AND gate operation stage and achieving scalability under complex logical structures.

[0022] This scheme introduces a parallelized cutset comparison mechanism during the simplification phase, mapping the inclusion relationship judgment between all candidate cutsets to matrix comparison operations, and implementing multi-comparison parallel execution on the GPU. This approach eliminates the simplification process's reliance on recursive or nested loop judgments, avoiding the time bottleneck caused by the explosion of the number of cutsets in traditional algorithms. Compared with structural compression methods such as ZBDD, this scheme maintains logical accuracy while ensuring determinism and real-time performance, guaranteeing the efficiency and completeness of the minimum cutset extraction process.

[0023] This scheme optimizes intermediate matrix results during parallel computation through block-based and cache reuse strategies. It dynamically adjusts block sizes based on candidate matrix size and device bandwidth, effectively reducing GPU memory usage in large-scale solutions. This adaptive memory management mechanism offers significant advantages over the full loading of traditional BDD storage methods, ensuring the algorithm's runnability and stability on general-purpose GPU hardware without sacrificing computational accuracy, thus achieving a balance between high performance and resource constraints.

[0024] This scheme employs a cyclical iterative approach to solve the fault tree layer by layer, progressively generating and simplifying cut sets from the bottom-level basic events to the top events. This maintains the traceability of the computational logic and ensures the completeness of the input at each level. This structured iterative strategy simplifies the control flow of traditional recursive algorithms, resulting in excellent parallel decomposition and verifiability. Compared to traditional algorithms that rely on symbolic resolution, this scheme not only improves computational speed and scalability but also provides a unified numerical interface for subsequent coupling with probability calculation and reliability assessment modules.

[0025] It is applicable to the safety and reliability analysis of large and complex engineering systems, and is used to efficiently solve the minimum cut set of fault trees on parallel computing platforms such as GPUs. Attached Figure Description

[0026] Figure 1 The overall flowchart of the representation method; Figure 2 This represents the way the fault tree structure is encoded as an adjacency matrix; Figure 3 This represents the result of a broadcast-style parallel AND gate operation. Detailed Implementation

[0027] To make the advantages and benefits of the technical solution provided by the present invention clearer, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, specifically: Implementation Method 1: This implementation method provides a matrix-based parallel computing method for solving the minimum cut set of a fault tree, including: The input fault tree model is structured and encoded to establish a structural description matrix that represents the relationship between gate events and input events and the gate type attributes. The fault tree logic structure is uniformly represented in matrix form to form a computable input step. The steps are: to vectorize the basic events and generate corresponding one-hot vectors, and to combine the intermediate events and their candidate cut sets into a candidate matrix in binary form to form a set of data inputs for logical operations; The steps to determine intermediate events in the current computation round where all inputs have candidate matrices based on the structure description matrix, and to generate a list of target events to ensure the correctness of the computation order; When the intermediate event is an OR gate, the process involves performing row-dimensional merging and parallel deduplication on the candidate matrix of the input event to generate a union candidate matrix, and then outputting the result as the input of the upper-level event. When the intermediate event is an AND gate, the input candidate matrix is ​​expanded in row dimension and component-wise combination and normalization are performed on the parallel processing unit to generate a Cartesian combination matrix. The combination result is output for subsequent simplification steps. The process involves performing parallel cut set comparison on the generated candidate matrix to remove redundant cut sets with inclusion relations and retain the minimum cut set, and then using the simplified matrix as the input for the next round. Based on the size of the candidate matrix and the computational bandwidth, a blockization and cache reuse strategy is dynamically implemented to reduce memory consumption and improve computational throughput, and the optimization results are used for continuous iterative computation. The process involves iteratively performing steps to determine intermediate events, logical combinations, and parallel simplifications until the top event candidate matrix stabilizes and the minimum cut set is output as the final solution.

[0028] The structured coding process uses a partitioned structure to describe the matrix, which represents the input relationship between gate events and the input relationship between gate events and basic events in partitions, and sets gate type identifiers in additional columns to distinguish between AND gates and OR gates.

[0029] In the vectorization process, the number of basic events in the system is used as the vector dimension. Each event or combination of events is represented as a binary vector, and multiple cut set vectors are stacked row by row to form a candidate matrix.

[0030] The candidate matrix of multiple input events of the AND gate is expanded along the row dimension and the component-wise addition operation is performed on the parallel processing unit. The binary property is preserved by normalizing the elements greater than one in the addition result.

[0031] An inclusion relationship judgment mechanism is used to compare all row vectors of the candidate matrix in parallel. When a row vector is found to completely contain another row vector, the containing one is deleted.

[0032] The computation blocks are dynamically divided based on the size of the candidate matrix and the bandwidth of the computing hardware, and the cache space is reused in the loop computation.

[0033] Implementation Method Two: This implementation method provides a further detailed description of the technical solution provided in Implementation Method One. Specifically: First, the input fault tree model is formally encoded to establish a structural description matrix representing the relationship between gate events and input events, as well as gate type attributes. In this process, all gate events and basic events in the fault tree are uniformly numbered, and a correspondence matrix is ​​established based on the logical structure. Rows in the matrix represent output events, and columns represent input events, with numerical values ​​indicating the input-output relationship in the corresponding cells. When a gate event has multiple input events, its corresponding column is marked as having a connection relationship. Additionally, gate type information is recorded in the matrix's supplementary columns, for example, 0 for an OR gate and 1 for an AND gate. This approach maps complex hierarchical logical structures into a matrix structure with numerical patterns, avoiding the discontinuous data access problems caused by pointers or linked lists in traditional methods, and providing a unified input data foundation for subsequent vectorized and parallelized operations.

[0034] Next, the basic events in the fault tree are vectorized, and intermediate events and their candidate cut sets are represented as binary matrices. In this step, the total number of basic events in the system is used as the vector dimension, and each basic event is represented as a one-hot vector that takes a value of 1 only in the corresponding dimension. For example, in a system containing five basic events, the vector for a fault in main coolant pump A is [1,0,0,0,0], and the vector for a fault in main coolant pump B is [0,1,0,0,0]. Each cut set is represented as a binary 0-1 vector; for example, a vector containing faults in both main coolant pump A and main coolant pump B is [1,1,0,0,0]. When an intermediate event consists of multiple candidate cut sets, the binary vectors of all its candidate cut sets are stacked row-wise to form a candidate matrix. For example, when the intermediate event "insufficient main coolant flow" is triggered by either event E1 or E2, its candidate matrix is ​​formed by directly concatenating the two row vectors mentioned above. This vectorization process allows each event combination to be expressed in binary matrix form, laying the foundation for converting logical operations into linear algebraic calculations.

[0035] Then, based on the fault tree's structural description matrix, the intermediate events for each round of solution are determined. The algorithm scans the matrix from bottom to top, identifying intermediate events for which all inputs have candidate matrices as the target for this round of solution. This hierarchical decision-making method ensures the correct logical order of event solution and complete data input. For example, in a nuclear reactor core overheating fault tree, the events selected in the initial round include "insufficient main coolant flow" and "emergency shutdown system failure," both of which are basic events as input events. As the calculation progresses, the output of the previous round becomes the input for the next round, ensuring that the intermediate event "shutdown failure and abnormal power" has complete input, thus allowing for the next stage of calculation.

[0036] When the logic type of the intermediate event is an OR gate, a row-wise merging operation is performed on the candidate matrices of the input events to generate a union candidate matrix. Specifically, the algorithm directly concatenates the input candidate matrices along the row dimension and removes duplicate rows through parallel deduplication operations, ensuring that each row in the output matrix represents a unique candidate cut set. In practice, when there are many input events, the multi-threaded architecture of the GPU can be used to process the concatenation and deduplication operations of multiple candidate matrices simultaneously, significantly reducing redundant computations. In this way, the traditional symbolic logic "OR" operation is transformed into a matrix-level row concatenation and deduplication process, achieving unification between the logic and data layers.

[0037] When the intermediate event is an AND gate, a broadcast-style parallel combination operation is performed. The algorithm expands the candidate matrices of multiple input events along the row dimensions, allowing each candidate matrix to be combined with all row vectors of other input matrices simultaneously on the parallel processing unit. In specific execution, any two input candidate matrices E1 and E2 are expanded to align their dimensions and then subjected to component-wise addition to generate new candidate matrices. When the result at a certain position is greater than 1, it is normalized to 1 to preserve binary characteristics. Taking "emergency shutdown system failure and abnormal reactor power" as an example, through parallel broadcast operations, the system simultaneously expands and combines the matrices representing M4 and E3 on the GPU core, generating all possible failure modes {E3, E4} and {E3, E5}. This process no longer relies on pairwise loop traversal but completes all Cartesian combinations at once through the GPU's parallel mechanism, significantly improving computational throughput.

[0038] After obtaining the candidate matrices, a parallelized cutset simplification operation is performed to remove redundant cutsets and retain the minimum cutsets. This simplification process is achieved by determining the inclusion relationship between matrices. The algorithm compares all candidate row vectors simultaneously in a multi-threaded manner on the GPU. When a row is detected to completely contain another row, it is determined to be a redundant set and removed. For example, when the candidate matrix contains three rows {E1}, {E1,E2}, and {E4,E5}, the algorithm identifies {E1,E2} as a superset and automatically deletes it, ultimately retaining only the two minimum cutsets {E1} and {E4,E5}. This parallelized simplification operation avoids the time overhead of nested loops in traditional methods, allowing the cutset extraction process to be completed in a short time.

[0039] To address the memory and GPU usage issues caused by large-scale candidate matrices during parallel computing, a block-based and cache reuse strategy is introduced. The algorithm dynamically divides computation into blocks based on the size of the candidate matrix and GPU bandwidth, loading only a portion of the data for computation at a time, and reusing cache space in subsequent batches to reduce memory management overhead. When the input matrix is ​​large, a dynamic balance between performance and resource consumption is achieved by adjusting the block size and batch size, ensuring stable execution of high-intensity computational tasks on general-purpose hardware platforms.

[0040] Finally, the intermediate event filtering, logical operations, and simplification steps are repeated, progressing layer by layer to the top event. When the candidate matrix of the top event no longer changes after two consecutive iterations, it indicates that all possible cut sets have been generated and simplified. At this point, the output matrix is ​​the minimum cut set of the fault tree, and the algorithm terminates. The output result is expressed in a standardized binary matrix form, facilitating direct integration with the system reliability calculation model.

[0041] Through the above steps, the logical structure of the fault tree is completely mapped into a numerical matrix system, and all logic gate operations are replaced by parallel computable matrix operations. The output of each step serves as the input for the next step, realizing a progressive logic from data modeling to cutset solving. Compared with traditional recursive algorithms, this method not only significantly improves the efficiency of solving large-scale fault trees, but also has obvious advantages in terms of structured approach, parallelization, and scalability, enabling fast solving of minimum cutsets for complex systems on high-performance computing platforms such as GPUs.

[0042] Implementation Method 3: Combination Figure 1-3 This embodiment describes the technical solution provided above in further detail through specific examples. Specifically: A matrix-based parallel computation method for solving the minimum cut set of a fault tree includes the following steps: Step 1: Formalize the fault tree and construct a structural description adjacency matrix or equivalent tensor to characterize the relationship between gate events and inputs and the gate type. Taking the fault tree analysis of a nuclear reactor "core overheating" accident as an example, this matrix accurately records which subordinate events (M4 and E3) and through what logical relationship (such as "AND gate") each event (such as intermediate event M3: "emergency shutdown system failure and abnormal reactor power") was triggered by. Step 2: Represent the basic events as independent vectors, and the cut sets as binary vectors; represent the candidate cut sets corresponding to intermediate events as candidate vector sets and arrange them into an event matrix by rows. In a system containing 5 basic events, the basic event E1 ("Main coolant pump A failure") is represented as the vector [1, 0, 0, 0, 0]. The candidate matrix for the intermediate event M2 (caused by E1 or E2) consists of two row vectors [1,0,0,0,0] and [0,1,0,0,0]. This representation transforms the symbolic logic problem into a linear algebra problem; Step 3: Identify the intermediate events to be solved in each round. For example, in the initial round, only M2 and M4, whose inputs are both basic events, satisfy the calculation conditions. After the candidate matrices of M2 and M4 are generated, the next round will identify M3, with M4 as input, as satisfying the calculation conditions. In this way, the algorithm progresses upwards layer by layer until the top event. Step 4: Merge the candidate matrices of multiple input events of the OR gate in the row direction to obtain the union candidate. For example, to calculate the candidate matrix of OR gate M2, merge the candidate matrix of E1 [[1,0,0,0,0]] and the candidate matrix of E2 [[0,1,0,0,0]] in the row dimension to obtain the final candidate matrix of M2; Step 5: Broadcast-parallel combination of candidate matrices of multiple input events of the AND gate to generate Cartesian combination candidates, and perform component-wise normalization on the combination result to maintain binary properties. Taking intermediate event M3: "Emergency shutdown system failure and abnormal reactor power" as an example, this is a typical AND gate scenario, which requires two completely independent events to occur simultaneously: M4: Emergency shutdown system (shutdown rod) failure. Based on previous calculations, the candidate matrix for M4 contains two independent failure modes: {E4: Control rod drive mechanism jamming} and {E5: Emergency shutdown signal logic processing unit failure}. Its candidate matrix is: [[0, 0, 0, 1, 0], [0, 0, 0, 0, 1]]. E3: A failure of the reactor power regulation system leads to an abnormal increase in power. This is a basic event with a candidate matrix of [[0, 0, 1, 0, 0]].

[0043] To compute the candidate cut sets of M3, this invention employs a broadcast-style parallel combination operation. The algorithm adds the candidate matrices of M4 and E3 element-wise on the computational core. The parallel architecture of the GPU naturally broadcasts (copies) the row vectors of the E3 candidate matrix and combines them with each row of the M4 candidate matrix, instantly completing the following computation: [0, 0, 0, 1, 0] (from M4) + [0, 0, 1, 0, 0] (from E3) yields [0, 0, 1, 1, 0], generating a new candidate cut set {E3, E4}.

[0044] [0, 0, 0, 0, 1] (from M4) + [0, 0, 1, 0, 0] (from E3) yields [0, 0, 1, 0, 1], generating a new candidate cut set {E3, E5}.

[0045] Finally, the candidate matrix of M3 [[0, 0, 1, 1, 0], [0, 0, 1, 0, 1]] is generated.

[0046] Step 6: Perform parallelized inter-cutset comparisons on the candidate sets obtained in Steps 4 and 5 to remove redundant candidates and retain the minimum cutset. Assuming that when analyzing a more complex intermediate event (e.g., "overall failure of the security system"), this implementation obtains a temporary candidate matrix through prior matrix merging and combination, containing the following three candidate cutsets: Line 1: {E1}(vector: [1,0,0,0,0]) "Main coolant pump A stopped due to power failure".

[0047] Line 2: {E1, E4} (vector: [1,0,0,1,0]) "Pump A power supply failure" and "Control rod drive mechanism jammed".

[0048] Line 3: {E4, E5} (vector: [0,0,0,1,1]) "Control rod jammed" and "Station stop signal failed".

[0049] The algorithm utilizes a broadcast mechanism to perform parallelized cut-set comparisons on the matrix. The computational core compares all row vector pairs simultaneously. Therefore, row 2, representing {E1, E4}, will be identified as a superset and eliminated from the candidate matrix in parallel. After simplification, the remaining matrix will contain only {E1} and {E4, E5}.

[0050] Step 7: Repeat steps 3 to 6 until the candidate set corresponding to the top event is stable, and output the retained candidates as the minimum cut set; To further understand the present invention, the matrix-based parallel computing method for solving the minimum cut set of a fault tree provided by the present invention will be described in detail below with reference to the embodiments. The scope of protection of the present invention is not limited by the following embodiments.

[0051] Example 1 This embodiment uses a fault tree of a typical nuclear reactor core overheating accident scenario as an example. Its fault tree logic structure is as follows: Figure 2 As shown, a matrix-based parallel computing method for solving the minimum cut set of a fault tree is presented, and the overall process is as follows: Figure 1 As shown, it includes the following steps: Step 1: With Figure 2 Taking a fault tree as an example, this embodiment first formally encodes the fault tree, transforming the graphical gate-event-basic-event relationship into a matrix representation. Specifically, gate events and basic events are uniformly numbered, and a partitioned structure matrix is ​​constructed. The first partition is used to represent the input relationship between gate events, and the second partition is used to represent the input relationship between gate events and basic events. Gate type identifiers are set in the additional columns of the matrix to distinguish logical attributes such as AND gates and OR gates.

[0052] In this scenario, this implementation assigns specific physical meaning to the events in the fault tree: Top event M1: Represents the eventual undesirable accident, namely "reactor core overheating".

[0053] Intermediate event M2: Represents a major failure mode that leads to core overheating, namely, "severe insufficiency of main coolant flow".

[0054] Intermediate event M3: Represents another parallel failure mode, "emergency shutdown system failure and abnormal reactor power".

[0055] Intermediate event M4: As a sub-event of M3, it represents "emergency shutdown system (shutdown bar) failure".

[0056] Basic events E1-E5: These represent the non-decomposable root causes that led to system failure.

[0057] E1: Main coolant pump A has stopped due to a power failure. E2: "Main coolant pump B has stopped due to mechanical failure." E3: "A malfunction in the reactor power regulation system caused an abnormal increase in power." E4: "Control rod drive mechanism jamming prevents some stop rods from being inserted." E5: "Emergency shutdown signal logic processing unit failure" The specific encoding process is as follows: all gate events (M1-M4) and basic events (E1-E5) are uniformly numbered, and a partitioned structure matrix is ​​constructed. This matrix clearly records the input source and logical type of each gate event. The first partition of the matrix represents the input relationship between gate events (e.g., the input of M1 is M2 and M3), and the second partition represents the input relationship between a gate event and a specific physical fault (basic event) (e.g., the input of M2 is E1 and E2). In the additional columns of the matrix, this implementation sets gate type identifiers; for example, "0" represents an OR gate, and "1" represents an AND gate.

[0058] For example, for Figure 2 The fault tree shown represents an intermediate event M3, which signifies "emergency shutdown system failure and abnormal reactor power." This event is an AND gate, and its occurrence requires the simultaneous fulfillment of its two input events: "emergency shutdown system (shutdown rod) failure" (M4) and "reactor power regulation system failure leading to abnormal power increase" (E3). Therefore, in the structure matrix describing this fault tree, the row corresponding to M3 will be marked with 1 in the columns corresponding to M4 and E3, indicating that these two events are its inputs; simultaneously, the value of its gate type identifier column will be set to 1 to define its AND logical relationship.

[0059] Step 2: After completing the structured modeling of the fault tree, this embodiment further vectorizes the basic events (i.e., specific physical faults) and candidate cut sets (i.e. fault combinations that may lead to higher-level events) to facilitate numerical processing by the computer.

[0060] Specifically, since there are 5 basic events (E1 to E5) in this scenario's system, each event or combination of events will be represented as a vector of length 5. Each dimension of the vector corresponds one-to-one with a specific basic physical fault.

[0061] One-hot vector representation of basic events: Each independent physical fault is represented as a one-hot vector. For example, basic event E1 ("Main coolant pump A stops due to power failure") is represented as vector [1, 0, 0, 0, 0], where the first bit is 1, indicating that the event has occurred. Similarly, E4 ("Control rod drive mechanism jams") is represented as [0, 0, 0, 1, 0].

[0062] Candidate matrix representation of intermediate events: For an intermediate event, since it may correspond to multiple candidate cut sets, this implementation arranges the vectors of all these cut sets in rows to form a "candidate matrix". Taking intermediate event M2 ("severely insufficient main coolant flow") as an example, it is caused by the occurrence of E1 or E2. Therefore, the candidate cut set of M2 contains two independent cut sets {E1} and {E2}, and its corresponding candidate matrix is: The first line represents the mode caused by "Main coolant pump A failure", and the second line represents the mode caused by "Main coolant pump B failure".

[0063] By using this vector and matrix representation, this implementation transforms complex logical relationships into a regular numerical data structure, laying the data foundation for efficient parallel computation of logic gates in steps 4 and 5.

[0064] Step 3: After representing the basic events and candidate sets, this embodiment proceeds with the calculation step by step according to the hierarchical structure of the fault tree. Specifically, in each iteration, the algorithm first determines the intermediate events that are currently "solvingable". The input condition for this intermediate event is that all its lower-level input events have completed the corresponding candidate sets, thus ensuring that its candidate set can be fully generated in this round of computation.

[0065] by Figure 2 Taking the "core overheating" fault tree as an example, the algorithm execution flow is as follows: In the first round of calculations, the algorithm first scans all intermediate events and finds that the inputs for M2 ("Severely insufficient main coolant flow") and M4 ("Emergency shutdown system failure") are {E1, E2} and {E4, E5}, respectively. Since these inputs are all basic events (whose failure modes are known and initial), M2 and M4 are identified as the solution targets for the first round.

[0066] Second Round of Calculation: After completing the first round of calculations and obtaining the candidate matrices for M2 and M4, the algorithm begins a new round of scanning. At this point, it discovers that in the input {M4, E3} of the intermediate event M3 ("stack shutdown failure and abnormal power"), the candidate matrix of M4 has just been calculated, and the failure mode of E3, as a basic event, is also known. Thus, all inputs to M3 are now clear, making M3 the target for the second round of calculation.

[0067] Final round of calculation: After the candidate matrices for M3 are calculated, the algorithm finds that the candidate matrices for the input {M2, M3} of the top event M1 ("reactor core overheating") are also all calculated. Therefore, in the final round of calculation, the algorithm will solve for the top event M1, ultimately obtaining all minimal cut sets for the entire "core overheating" accident. In summary, the results obtained in this step... Figure 2 The event solver queue for the example shown is {{M2,M4},{M3},{M1}}.

[0068] Therefore, based on the structural description matrix established in step 1, and combined with the connection relationship between gate events and input events, a bottom-up approach can be adopted to select intermediate events that have not yet been calculated but have complete input, and use them as the target events for this round of computation. This strategy ensures the correctness of the computation order and provides complete input for subsequent AND and OR gate operations, avoiding duplicate or invalid computations.

[0069] Step 4: When the determined intermediate event is an OR gate, this embodiment generates a union candidate by performing row-level merging on the candidate matrices of the input events. Specifically, the semantics of an OR gate is "any input event occurring will cause the output event to occur," therefore, the candidate set of this gate is equivalent to the union of all input candidate sets. In the implementation process, the input candidate matrices are directly concatenated along the row dimension, and duplicate rows are removed to obtain the candidate matrix of the target intermediate event.

[0070] This implementation takes the intermediate event M2 ("Severely insufficient main coolant flow") in the first round of calculation as an example, which is a typical OR gate. According to the fault tree definition, the occurrence of E1 ("Main coolant pump A failure") or E2 ("Main coolant pump B failure") will independently and sufficiently lead to the occurrence of M2 ("Severely insufficient main coolant flow"). According to the vectorization definition in step 2, the candidate matrices of the two input events of M2 are: E1's candidate matrix (containing only the fault mode itself): The candidate matrix of E2 (also containing only itself): To compute the candidate matrix of M2, the algorithm directly concatenates the two input matrices along the row dimension to form a new matrix: The resulting matrix after merging is the candidate matrix for M2. The two rows of this matrix represent the two independent and simplest failure modes that can lead to "insufficient main coolant flow": the first row is {E1} (pump A failure only), and the second row is {E2} (pump B failure only).

[0071] In practice, if the candidate sets of multiple input events intersect (i.e., they share the same failure mode), row-level merging will result in duplicate rows. In this case, the algorithm performs an efficient parallel deduplication operation to ensure that each row in the final candidate matrix represents a unique candidate cut set. In this way, the algorithm transforms the logical "union" operation into a matrix concatenation and deduplication operation that can be efficiently executed on a parallel computing architecture.

[0072] Step 5: When the determined intermediate event is an AND gate, the AND gate operation is implemented in parallel using the following broadcast method: For the two input candidate matrices E1∈{0,1}^(dimension p1×n) and E2∈{0,1}^(dimension p2×n), the row dimensions are expanded to E1′∈{0,1}^(dimension p1×1×n) and E2′∈{0,1}^(dimension 1×p2×n), respectively. Component-wise addition of E1′ and E2′ is performed on the parallel processing unit, triggering a parallel broadcast operation to obtain T∈{0,1}^(dimension p1×p2×n). Then, the first two dimensions of T are flattened into a (p1·p2)×n candidate matrix. If any position in the result is greater than 1, it is changed to 1. The result is as follows: Figure 3 As shown; when there are more than two OR gate inputs, the above operations are applied in pairs in sequence, and the result of the previous round is used as the input of the next round.

[0073] This implementation takes intermediate event M3 ("emergency shutdown system failure and abnormal reactor power") in the second round of calculation as an example. It is an AND gate, and its calculation process is as follows: Based on the aforementioned steps, this embodiment has known the candidate matrices of the two input events of M3: M4 and E3 After dimensional expansion: M4' and E3' Next, we will use the wide-range characteristics to efficiently complete this operation, which means directly adding M4' and E3'. This process is equivalent to performing the following operations simultaneously: (1) Combine the first row of M4 (representing fault {E4}) with the row of E3 (representing fault {E3}): [0,0,0,1,0] + [0,0,1,0,0] = [0,0,1,1,0], generating a new cut set {E3, E4}.

[0074] (2) Combine the second row of M4 (representing fault {E5}) with the row of E3 (representing fault {E3}): [0,0,0,0,1] + [0,0,1,0,0] = [0,0,1,0,1], generating a new cut set {E3, E5}.

[0075] Stacking all the combined results row by row yields the final candidate matrix of M3: As the size of the input candidate set grows, the Cartesian product can cause the dimensionality of the candidate matrix to expand rapidly, leading to significant computational overhead and high memory consumption. To address this issue, this embodiment proposes an optimization strategy based on block / batch processing and cache reuse, as described in claim 4. Specifically, the input candidate matrix is ​​divided into several smaller computational blocks according to the row dimension. Only a portion of these blocks is loaded into the computational unit for combination operations at a time. After the result is generated and stored, the next portion is processed, thus avoiding the allocation of excessive memory at once. Simultaneously, a cache reuse strategy is employed for intermediate results, meaning the memory space required for the same computational block is reused in different batches instead of being frequently allocated and released, thereby reducing memory management overhead and improving overall throughput. During operation, this embodiment can also dynamically adjust the block size and batch number based on the size of the candidate matrix and the computational hardware bandwidth to achieve a balance between memory consumption and computational efficiency. Through these optimization mechanisms, stable operation with limited hardware resources is ensured even during large-scale candidate generation, and the scalability of parallel combination is significantly improved.

[0076] Step 6: After obtaining the candidate matrix, this embodiment needs to remove redundant cutsets, i.e., cutset simplification. Specifically, all candidates are compared pairwise in parallel. If a candidate cutset of a row contains another row (i.e., it has more or the same basic events than the other row), then that row is a superset and should be removed. In this way, only rows that do not cover any other candidates are retained. After this round of processing, the candidate set consists only of minimal cutsets.

[0077] Let's assume a hypothetical scenario: after calculating a certain intermediate event, this implementation method yields a candidate matrix containing the following three types of cut sets: Cut set A (row 1): {E1} (“Main coolant pump A failure”), vector is [1, 0, 0, 0, 0] Cut set B (row 2): {E1, E2} (“Pump A and Pump B fail simultaneously”), vector [1, 1, 0, 0, 0] Cut set C (line 3): {E4, E5} (“Control rod jammed and stop signal failed”), vector [0, 0, 0, 1,1] The algorithm performs "containment" checks on each row vector in the matrix in parallel with all other row vectors.

[0078] When comparing cutsets A and B, the algorithm uses vector operations to find that the vector [1, 0, 0, 0, 0] of cutset A is contained within the vector [1, 1, 0, 0, 0] of cutset B. According to the definition of a minimal cutset, the fault combination represented by cutset B should be removed. This is because, from a physical perspective, a single "pump A fault" (cutset A) is sufficient to cause a problem. After this round of parallel simplification, the second row representing pattern B will be removed from the candidate matrix. Ultimately, the candidate matrix for this event will only retain those rows that cannot be "contained" by any other row, i.e., the true minimal cutsets. These two lines correspond to the two fundamental failure modes of the event: {E1} and {E4, E5}. In this way, the algorithm ensures that, as it progresses through the events at the top level, it only processes and transmits the most concise and essential failure mode information.

[0079] Step 7: After generating and simplifying the candidate set, this embodiment continues to iterate upwards according to the hierarchical structure of the fault tree. The output candidates from each round of calculation will be used as input for higher-level events, and steps 3 to 6 will be repeated. This process continues upwards layer by layer until the candidate set of the top event no longer changes, indicating that all possible cut sets have been completely generated and simplified. The candidate set obtained at this point is the minimum cut set set of the fault tree, and it is output as the final result.

[0080] In the embodiment of "reactor core overheating", the complete process of this cyclical recursion is as follows: (1) Startup and First Iteration: The algorithm starts and executes step 3, confirming that intermediate events M2 and M4 have all input conditions. Subsequently, the algorithm executes steps 4 (row-level merging) and 6 (simplification) in parallel on these two OR gates, calculating their respective minimal cut sets: The minimal cut set of M2 ("Main coolant flow is severely insufficient") is: {E1}, {E2}: The minimal cut set of M4 (“Emergency shutdown system failure”) is: {E4}, {E5}: (2) Second iteration: Based on the results of the previous iteration, the algorithm executes step 3 again and finds that all inputs (M4 and E3) of the intermediate event M3 have candidate matrices. Therefore, the algorithm uses the candidate matrices of M4 and E3 as inputs and executes steps 5 (broadcast parallel combination) and 6 (simplification) on the AND gate M3 to obtain its minimal cut set set: The minimum cut sets of M3 ("shutdown failure and power anomaly") are: {E3, E4}, {E3, E5}. (3) Final iteration and termination: At this point, the minimum cut sets of all inputs (M2 and M3) of the top event M1 have been calculated. In the final iteration, the algorithm uses the minimum cut set matrices of M2 and M3 as inputs to execute steps 4 and 6 on the OR gate M1. When the candidate set of the top event M1 has been calculated and no longer changes (i.e., one calculation is completed in the bottom-up calculation process), the loop terminates.

[0081] (4) Final Output: The final output of the algorithm is the minimum cut set matrix of the top event M1 ("reactor core overheating"). This matrix precisely reveals all the most fundamental and irreducible combinations of failure modes that led to this nuclear accident. In this embodiment, the final result is: Its physical meaning is Cut set 1 (first row): {E1} (i.e., "Main coolant pump A failure" occurs alone) Cut set 2 (second line): {E2} (i.e., "Main coolant pump B failure" occurs alone) Cut set 3 (third row): {E3, E4} (i.e., "power anomaly" and "control rod jamming" occur simultaneously) Cut set 4 (fourth row): {E3, E5} (i.e., "power anomaly" and "shutdown signal failure" occur simultaneously) This final binary matrix is ​​the direct output of the algorithm of this invention. It accurately describes the four fundamental risk scenarios that lead to "core overheating" in a fully structured form that can be directly used for subsequent quantitative calculations (such as probability calculations). These scenarios are the minimum cut sets, providing a direct and efficient basis for decision-making in system reliability and safety analysis.

[0082] The above description of several specific embodiments further details the technical solution provided by the present invention in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, combinations of embodiments, and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A matrix-based parallel computing method for solving the minimum cut set of a fault tree, characterized in that, include: The input fault tree model is structured and encoded to establish a structural description matrix that represents the relationship between gate events and input events and the gate type attributes. The fault tree logic structure is uniformly represented in matrix form to form a computable input step. The steps are: to vectorize the basic events and generate corresponding one-hot vectors, and to combine the intermediate events and their candidate cut sets into a candidate matrix in binary form to form a set of data inputs for logical operations; The steps to determine intermediate events in the current computation round where all inputs have candidate matrices based on the structure description matrix, and to generate a list of target events to ensure the correctness of the computation order; When the intermediate event is an OR gate, the process involves performing row-dimensional merging and parallel deduplication on the candidate matrix of the input event to generate a union candidate matrix, and then outputting the result as the input of the upper-level event. When the intermediate event is an AND gate, the input candidate matrix is ​​expanded in row dimension and component-wise combination and normalization are performed on the parallel processing unit to generate a Cartesian combination matrix. The combination result is output for subsequent simplification steps. The process involves performing parallel cut set comparison on the generated candidate matrix to remove redundant cut sets with inclusion relations and retain the minimum cut set, and then using the simplified matrix as the input for the next round. Based on the size of the candidate matrix and the computational bandwidth, a blockization and cache reuse strategy is dynamically implemented to reduce memory consumption and improve computational throughput, and the optimization results are used for continuous iterative computation. The process involves iteratively performing steps to determine intermediate events, logical combinations, and parallel simplifications until the top event candidate matrix stabilizes and the minimum cut set is output as the final solution.

2. The matrix-based parallel computing method for solving the minimum cut set of a fault tree according to claim 1, characterized in that, The structured coding process uses a partitioned structure to describe the matrix, which represents the input relationship between gate events and the input relationship between gate events and basic events in partitions, and sets gate type identifiers in additional columns to distinguish between AND gates and OR gates.

3. The matrix-based parallel computing method for solving the minimum cut set of a fault tree according to claim 1, characterized in that, In the vectorization process, the number of basic events in the system is used as the vector dimension. Each event or combination of events is represented as a binary vector, and multiple cut set vectors are stacked row by row to form a candidate matrix.

4. The matrix-based parallel computing method for solving the minimum cut set of a fault tree according to claim 1, characterized in that, The candidate matrix of multiple input events of the AND gate is expanded along the row dimension and the component-wise addition operation is performed on the parallel processing unit. The binary property is preserved by normalizing the elements greater than one in the addition result.

5. A matrix-based parallel computing method for solving the minimum cut set of a fault tree according to claim 1, characterized in that, An inclusion relationship judgment mechanism is used to compare all row vectors of the candidate matrix in parallel. When a row vector is found to completely contain another row vector, the containing one is deleted.

6. A matrix-based parallel computing method for solving the minimum cut set of a fault tree according to claim 1, characterized in that, The computation blocks are dynamically divided based on the size of the candidate matrix and the bandwidth of the computing hardware, and the cache space is reused in the loop computation.

7. A matrix-based parallel computing device for solving the minimum cut set of a fault tree, characterized in that, include: The input fault tree model is structured and encoded to establish a structural description matrix that represents the relationship between gate events and input events and the gate type attributes. The fault tree logic structure is uniformly represented in matrix form to form a module that can compile input. The module represents basic events in vector form and generates corresponding one-hot vectors. It combines intermediate events and their candidate cut sets into a candidate matrix in binary form to form a data input set for logical operations. Based on the structure description matrix, determine the intermediate events in the current calculation round where all inputs have candidate matrices, and generate a list of target events to ensure the correctness of the calculation order; When the intermediate event is an OR gate, the module performs row-dimensional merging and parallel deduplication on the candidate matrix of the input event to generate a union candidate matrix, and outputs the result as the input of the upper-level event. When the intermediate event is an AND gate, the input candidate matrix is ​​expanded in row dimension and component-wise combination and normalization are performed on the parallel processing unit to generate a Cartesian combination matrix. The combination result is output to the module for subsequent simplification. The module performs parallelized cut set comparison on the generated candidate matrix to remove redundant cut sets with inclusion relations and retain the minimum cut set, and uses the simplified matrix as the input for the next round. Based on the size of the candidate matrix and the computational bandwidth, a module dynamically implements blockization and cache reuse strategies to reduce memory consumption and improve computational throughput, and uses the optimization results for continuous iterative computation. The module iteratively executes intermediate events determination, logical combination, and parallel simplification operations until the top event candidate matrix stabilizes and outputs the minimum cut set as the final solution.

8. A computer storage medium for storing computer programs, characterized in that, When the computer program is read by the computer, the computer executes the method of claim 1.

9. A computer, comprising a processor and a storage medium, characterized in that, When the processor reads the computer program stored in the storage medium, the computer executes the method of claim 1.

10. A computer program product, as a computer program, is characterized by: When the computer program is executed, it implements the method of claim 1.

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