High throughput prediction method and device supporting parallel prediction of multiple dynamic branches

Abstract

The invention relates to a high throughput prediction method and device supporting parallel prediction of multiple dynamic branches, and the method comprises the steps: obtaining the branch information of a first branch instruction and at least one second branch instruction in a target prediction period, and the execution sequence of the second branch instruction is behind the first branch instruction; when the first branch instruction is predicted, selecting a historical context snapshot; determining a prediction result of the first branch instruction according to the historical context snapshot and the branch information of the first branch instruction; and when the second branch instruction is predicted, determining a prediction result of the second branch instruction according to the historical context snapshot used when the first branch instruction is predicted and the branch information of the second branch instruction. The method herein enables prediction and training of subsequent branches to be performed on a historical reference consistent with the first branch, thereby supporting processor implementation of higher throughput parallel prediction and consistent training updates.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, and in particular to a high-throughput prediction method and apparatus that supports parallel prediction of multiple dynamic branches. Background Technology

[0002] In modern high-performance processors, multi-stage pipelined architectures, superscalar execution, and speculative execution are commonly employed to improve instruction-level parallelism and overall processing performance. Branch prediction is a crucial component of speculative execution. It predicts whether a branch will occur and its corresponding target address before the actual execution of a branch instruction, allowing for advance instruction fetching and execution of instructions along the predicted path. If the prediction is incorrect, the processor needs to recover the relevant pipeline stages and re-fetch instructions; if the prediction is correct, pipeline stalls caused by waiting for branch execution results can be avoided, thus improving front-end bandwidth utilization and overall execution efficiency. With the increasing front-end fetching capabilities of processors, branch prediction throughput has gradually become a significant factor influencing processor performance.

[0003] Therefore, improving the throughput of branch prediction is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] To address the problems existing in the prior art, embodiments of this specification provide a high-throughput prediction method and apparatus that supports parallel prediction of multiple dynamic branches. In the prediction phase, this method selects and reuses the same historical context reference for multiple branches, enabling multiple branches that are related in the program execution order to generate prediction results in parallel under the same historical benchmark. In the training phase, the method maintains the consistency between the prediction and the historical reference used for training, thereby improving the prediction throughput in the branch prediction phase.

[0005] The specific technical solutions of the embodiments in this specification are as follows: On the one hand, embodiments of this specification provide a high-throughput prediction method that supports parallel prediction of multiple dynamic branches, the method comprising: Obtain branch information for the first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction; When predicting the first branch instruction, a snapshot of the historical context selected during the prediction phase is obtained; The prediction result of the first branch instruction is determined based on the historical context snapshot and the branch information of the first branch instruction; When predicting the second branch instruction, the prediction result of the second branch instruction is determined based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

[0006] Furthermore, the prediction times of both the first branch instruction and the second branch instruction are within the target prediction period.

[0007] Furthermore, the first branch instruction and the second branch instruction may be contiguous or non-contiguous in the instruction address space.

[0008] Furthermore, the prediction of the second branch instruction does not depend on the historical context information updated based on the prediction result or execution result of the first branch instruction.

[0009] Furthermore, the method also includes: After the first or second branch instruction is completed, the prediction structure is trained and updated based on the actual execution results of the branch instruction. The training update is based on a historical reference state that is consistent with the historical context snapshot used in the corresponding branch instruction prediction phase.

[0010] Furthermore, the method also includes: After the branch instruction is executed, the actual branch behavior information of the first branch and / or the second branch instruction is updated to the historical context information according to the preset historical maintenance rules.

[0011] Furthermore, the history maintenance rules include any one or a combination of the following: The selection rules for whether to include branch instructions in the history; Rules for compressing, sampling, or filtering historical information; The actual rules for updating historical information.

[0012] Furthermore, the branch information includes program count information.

[0013] On the other hand, embodiments of this specification also provide a high-throughput prediction apparatus that supports parallel prediction of multiple dynamic branches, the apparatus comprising: The branch information acquisition unit is used to acquire branch information of a first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction. The historical context snapshot acquisition unit is used to select a historical context snapshot during the prediction phase when predicting the first branch instruction. The prediction unit is configured to determine the prediction result of the first branch instruction based on the historical context snapshot and the branch information of the first branch instruction; and when predicting the second branch instruction, to determine the prediction result of the second branch instruction based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

[0014] On the other hand, embodiments of this specification also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0015] On the other hand, embodiments of this specification also provide a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0016] Compared with the prior art, the examples in this specification have the following beneficial effects: By selecting and reusing the same historical context reference for multiple branches during the prediction phase, multiple branches can generate prediction results in parallel within the same prediction period, thereby improving the prediction throughput during the branch prediction phase. It provides a multi-branch prediction organization method based on the same historical benchmark, which is a prediction organization mechanism that does not depend on constructing the evolved historical state for different branches. In some implementations, this method can be applied to various control flow scenarios where branch instructions are continuous or discontinuous in the address space, thereby enhancing the applicability of multi-branch prediction technology under complex control flow conditions. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The diagram shown is a flowchart illustrating a high-throughput prediction method that supports parallel prediction of multiple dynamic branches in an embodiment of this specification. Figure 2 The diagram shown illustrates the parallel prediction implementation mechanism in the embodiments of this specification. Figure 3 The diagram shown illustrates the implementation mechanism of multi-branch parallel predictive arbitration and instruction fetch control in the embodiments of this specification. Figure 4The diagram shown illustrates the implementation mechanism of the updated prediction structure in the embodiments of this specification. Figure 5 The diagram shown illustrates the implementation mechanism of the historical context record queue in the embodiments of this specification. Figure 6 The diagram shown is a structural schematic of a high-throughput prediction device that supports parallel prediction of multiple dynamic branches according to an embodiment of this specification. Figure 7 The diagram shown is a structural schematic of the computer device in an embodiment of this specification.

[0019] [Explanation of Figure Markers]: 601. Branch Information Acquisition Unit; 602. Historical Context Snapshot Acquisition Unit; 603. Prediction Unit; 702. Computer equipment; 704. Processing equipment; 706. Storage resources; 708. Drive system; 710. Input / Output Module; 712. Input devices; 714. Output devices; 716. Presentation equipment; 718. Graphical User Interface; 720. Network interface; 722. Communication link; 724. Communication bus. Detailed Implementation

[0020] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this specification, and not all embodiments. Based on the embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this specification.

[0021] It should be noted that the terms "first," "second," etc., in the description, claims, and accompanying drawings of the embodiments herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0022] It should be noted that the acquisition, storage, use, and processing of data in the technical solutions of the embodiments of this specification all comply with the relevant provisions of national laws and regulations.

[0023] It should be noted that in the embodiments of this specification, certain software, components, models, and other existing solutions in the industry may be mentioned. These should be considered as exemplary, and their purpose is only to illustrate the feasibility of implementing the technical solution of this application, but does not mean that the applicant has already used or necessarily used such a solution. Similarly, the descriptions of prediction algorithms, table organization forms, and hardware structures are also exemplary.

[0024] The inventors discovered in their research that existing single-branch dynamic prediction schemes typically focus on predicting a single branch. When the processor front-end pipeline has high fetch bandwidth and multiple branches exist in the instruction stream, it becomes difficult to generate prediction results for multiple dynamic branches simultaneously within a single prediction cycle in some scenarios, potentially leading to limited throughput during the fetch stage. Existing multi-branch prediction schemes based on fetch blocks usually rely on the address continuity of instructions within the fetch block. However, their multi-branch prediction capability is limited by the fetch block boundaries in some implementations, primarily covering the situation within the fetch block. When branch instruction behavior crosses the fetch block boundaries—that is, when the branch behavior causes the program execution process to exhibit contextual continuity but address discontinuity—it is usually difficult to effectively support parallel prediction of multiple dynamic branches, and bandwidth may be limited by factors such as the fetch block size.

[0025] To address the problems existing in the prior art, embodiments of this specification provide a high-throughput prediction method and apparatus that supports parallel prediction of multiple dynamic branches. When predicting multiple branches in parallel, when constructing a prediction request for a subsequent branch (e.g., the second branch), the same historical context snapshot of the preceding branch (e.g., the first branch) is reused. This allows the prediction and training of subsequent branches to be performed on a historical basis consistent with that of the first branch, thereby supporting higher-throughput parallel prediction and consistent training updates. In some embodiments of this application, the multiple branches may be contiguous or discontinuous in the instruction address space. Figure 1 The diagram illustrates a high-throughput prediction method supporting parallel prediction of multiple dynamic branches, as described in an embodiment of this specification. The diagram depicts the process of predicting multiple branch instructions within a prediction cycle. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the method can be executed sequentially or in parallel according to the embodiment or the accompanying drawings. Specifically, as shown... Figure 1 As shown, the method may include: Step 101: Obtain the branch information of the first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction; Step 102: When predicting the first branch instruction, obtain a snapshot of the historical context selected in the prediction phase; Step 103: Determine the prediction result of the first branch instruction based on the historical context snapshot and the branch information of the first branch instruction; Step 104: When predicting the second branch instruction, determine the prediction result of the second branch instruction based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

[0026] In the embodiments described in this specification, the execution order of the second branch instruction is after the first branch instruction. The two branch instructions are related in terms of program execution order, and the second branch is located after the first branch; however, they may be contiguous or non-contiguous in the address space. The relative positions of the first branch instruction and the second branch instruction in the instruction address space do not constitute a limitation on the present invention. Branch information includes program count information, used to identify the address location and related characteristics of the branch instruction.

[0027] In the embodiments of this specification, the above method can be applied to various scenarios where branch instructions are continuous or discontinuous in the instruction address space, including but not limited to multi-branch prediction scenarios spanning instruction fetch blocks or prediction blocks.

[0028] In the embodiments described in this specification, the prediction of the second branch instruction does not depend on the historical context information updated based on the prediction result or execution result of the first branch instruction.

[0029] like Figure 2 The diagram illustrates the parallel prediction implementation mechanism in this embodiment. When predicting the first branch instruction, a historical context snapshot HS is selected. This embodiment uses the selected historical context snapshot HS as the historical baseline state. The historical context snapshot HS represents the historical reference state selected during the prediction phase, and may include, for example, the state information of the Global History Register (GHR), providing a unified historical reference baseline for subsequent predictions. Based on the historical context snapshot HS and the program count information (PC1 or other derived information) of the first branch instruction, the prediction structure is accessed to generate the prediction result. The prediction structure can be any dynamic prediction structure, such as a structure based on entries, labels, or statistical models.

[0030] In the embodiments described in this specification, the prediction of the second branch instruction does not use the historical state updated based on the prediction result of the first branch instruction. Instead, it directly reuses the same historical context snapshot HS as the first branch instruction. Using this historical context snapshot HS and the program count information (PC2) of the second branch instruction, the prediction structure is accessed to obtain the prediction result of the second branch instruction. This reuse mechanism allows the prediction of the first branch instruction and the second branch instruction to be based on the same historical benchmark, enabling the first branch and the second branch to generate prediction results in parallel within the same prediction cycle.

[0031] During the prediction process, the prediction times of both the first and second branch instructions are within the target prediction period. Alternatively, the prediction times of the first and second branch instructions can be set to be the same as needed to achieve parallel prediction. The prediction unit is configured to record and manage the context information of prediction requests. Each prediction request's corresponding record entry includes the branch identifier, prediction result, and the identifier of the historical context snapshot used. When the second branch instruction reuses the historical snapshot of the first branch instruction, the record entry explicitly indicates that both share the same historical benchmark.

[0032] It should be noted that the embodiments in this specification use two branches sharing the same historical context snapshot for prediction as an example for illustration, but this technical concept is also applicable to three or more branches: each subsequent branch is located after the first branch in the program execution order, and can generate prediction results in parallel under the same historical reference. For example, if each subsequent branch is located after the first branch in the program execution order, and can generate prediction results in parallel within the same prediction period under the same historical reference; the subsequent branches can be located on different control flow paths, and this specification does not impose any restrictions on the examples.

[0033] Through the aforementioned historical context snapshot reuse mechanism, the embodiments of this specification enable parallel prediction of multiple branch instructions on the same historical baseline, thereby improving the throughput of multi-branch prediction. In some implementations, this scheme can be applied to scenarios that cross prediction block / fetch block boundaries, and the branches can be contiguous or discontinuous in the address space; subsequent branches only need to have a sequential relationship with the first branch in terms of program execution order.

[0034] In the embodiments of this specification, the purpose of branch prediction is to predict branch behavior / subsequent program execution path before the actual result of the branch instruction is obtained. For example, the branch prediction process is as follows: Step 1: Obtain branch instruction information; In this step, when a branch instruction enters the prediction phase (usually in the fetch or decode phase), the processor obtains the program counter (PC) value of that branch instruction and the history context snapshot (HS) selected for the prediction phase. The prediction phase can be set by the operator as needed. For example, when predicting the first branch instruction, the current history context snapshot can be obtained to perform parallel prediction of the first and second branch instructions.

[0035] Step 2: Generate a prediction request; For example, the PC and HS (typically the contents of the Global History Register GHR) of branch instructions can be used to generate an index for accessing the prediction structure through hashing, folding, or combination. In some implementations, the PC and historical context snapshot may only be one element in the generation of the prediction request, and may include other elements such as random numbers or branch type identifiers depending on specific implementation requirements.

[0036] Step 3: Access the predicted structure; For example, the address table / pattern table / counter in the prediction structure can be accessed to generate prediction results; the prediction structure is not limited to the form of PHT (Pattern History Table) or specific counters.

[0037] Step 4: Obtain the prediction results; In this step, the prediction result is determined based on the information output by the prediction structure. In some implementations, the prediction result may be necessary information indicating the subsequent execution path of the program, such as whether a jump occurs, the target address, or the instruction fetch address.

[0038] In the embodiments described in this specification, the History Context Snapshot (HS) may include historical information of several branches; for example, in one implementation, the GHR may record the jump results of several branch instructions.

[0039] The program counter (PC) information refers to the address (or partial address) of the current branch instruction. In some implementations, the PC may participate in the prediction process in ways such as hashing / folding / truncating / concatenating / combining.

[0040] It should be noted that the above process is merely exemplary. In actual implementation, historical context snapshots can be implemented using different forms of historical information representation, including but not limited to global history, path history, folded history, segmented history, or combinations thereof. The specific encoding method, bit width, or organizational structure of historical information does not constitute a limitation of the embodiments in this specification. As long as multiple branches share the same historical context benchmark during the prediction and training phases, the technical ideas of the embodiments in this specification can be realized.

[0041] The historical context snapshot can be generated and referenced through explicit storage, logical identification, index association, or other equivalent methods. The historical context snapshot is not required to exist as an independent physical copy; as long as the reference to the same historical context benchmark can be guaranteed during the prediction and training phases, it should fall within the protection scope of the embodiments in this specification.

[0042] In some implementations, recording branch history information does not require updating for every branch instruction. The historical context can be selectively updated based on a preset recording strategy, such as recording only branches that meet specific conditions, recording only branches of certain types, or sampling, filtering, or compressing historical information based on the predictor design requirements.

[0043] In this case, the historical context snapshot represents the historical reference state selected during the prediction phase, and is not required to correspond to the historical state formed by the most recent branch instruction in the program execution sequence. As long as multiple branches share the same selected historical context snapshot as a historical benchmark during the prediction and training phases, even if the historical context does not contain historical information of some branches, it should still be regarded as an equivalent implementation of the technical solution of the embodiments in this specification.

[0044] The branches described in the embodiments of this specification are not limited to specific types of branch instructions, and may also include unconditional jumps, indirect jumps, return instructions, and other instructions that may cause changes in program control flow. In the context of this application, "branch" refers to any instruction that changes control flow. Schemes that use the same historical context snapshot for parallel prediction and training for different types of branches should be considered equivalent implementations of the embodiments of this specification.

[0045] The embodiments in this specification do not limit the specific branch prediction algorithm or hardware structure used to access and generate predictions from historical context snapshots. Different prediction algorithms, prediction structures, or implementation methods, as long as they enable multiple branches to share the same historical context snapshot for prediction and training, should be considered equivalent substitutes for the technical solutions in the embodiments of this specification.

[0046] In the embodiments of this specification, after multiple branch prediction results are generated in parallel within the same prediction period, the branch prediction results can be processed according to preset rules to determine the validity and priority of the prediction results. For example, multiple prediction results can be selected or arbitrated based on front-end instruction fetching bandwidth, control flow redirection rules, or other implementation requirements.

[0047] According to one embodiment of this specification, such as Figure 3 The diagram shown illustrates the implementation mechanism of multi-branch parallel prediction arbitration and instruction fetch control in the embodiments of this specification. Instruction fetch path coordination and redirection control can be performed based on multiple prediction results obtained in parallel. When multiple prediction results simultaneously indicate changes in control flow, the front end arbitrates according to preset rules to determine the redirection order and instruction fetch bandwidth allocation strategy, thereby improving instruction fetch efficiency and avoiding limited prediction throughput.

[0048] Specifically, if multiple prediction results of multiple second branch instructions simultaneously indicate changes in control flow, then the multiple prediction results are arbitrated according to preset rules.

[0049] For example, the arbitration process can be implemented by selection logic, such as a multiplexer, a priority encoder, or other equivalent structure, which arbitrates the results of parallel predictions of multiple branches to produce a prediction of the execution path of the subsequent program.

[0050] For example, arbitrating the multiple prediction results according to preset rules further includes: Based on the prediction result of the previous branch instruction corresponding to the multiple prediction results, determine the failed prediction results among the multiple prediction results.

[0051] In the embodiments of this specification, the validity of subsequent prediction results located on different control flow paths can be marked based on the prediction results of the preceding branch; the validity marking rules can be configured according to implementation needs. For example, the branch instructions to which the multiple prediction results belong are located on different branch paths of the preceding branch instruction.

[0052] Reference Figure 3The prediction period N predicts branches 3, 4, and 5. Branch 3 can be considered as the first branch instruction, and branches 4 and 5 can be considered as the second branch instructions, respectively. Branches 4 and 5 are located on branch paths 3' and 3' of branch 3, respectively. For example, if the prediction result of branch 3 is execution path 3, the prediction result of branch 4 can be marked as invalid.

[0053] This can be understood as follows: if the prediction result of a current branch instruction indicates that a certain branch path will not be executed, the prediction results of subsequent branch instructions on that branch path are marked as invalid. This mechanism helps maintain the validity of prediction results and reduces the propagation of invalid predictions based on unselected paths.

[0054] In the embodiments of this specification, after the branch instruction is executed, the historical context information can be updated according to the actual execution result of the branch instruction and the preset historical maintenance rules. The historical maintenance rules may include rules for selecting whether to record the branch instruction in history, rules for compressing, sampling or filtering historical information, and actual rules for updating historical information, etc. The selection rules for whether to historically record branch instructions are used to determine whether the actual execution result of the branch instruction updates the historical context information. Among the rules for compression, sampling, or filtering of historical information, compression refers to compressing a long branch history sequence into a shorter bit vector. For example, a hash function (such as XOR hash) can be used to merge multiple historical bits into a shorter index, so that a large amount of historical information can be represented with fewer bits. Sampling refers to selecting only a portion of the historical history (e.g., taking one bit every few bits) when updating the historical context information, which aims to reduce the dimensionality of the history while retaining most of the information. Sampling can be regular (e.g., fixed intervals) or random. Filtering refers to ignoring branch results marked as unimportant when updating the historical context. For example, only considering the results of conditional branches and ignoring unconditional branches, or only considering specific types of branches. The purpose of filtering is to remove noise and retain only the information useful for prediction. The actual rules for updating historical information refer to how the predictor modifies the historical context information recorded internally based on the result of the branch instruction execution after it is determined in the pipeline execution stage. For example, it may shift the existing bit sequence in GHR one bit to the left or right, or insert the actual branch result into the vacated position after the shift (usually LSB, least significant bit).

[0055] It should be noted that the method of maintaining historical context information is independent of the historical context reference selection rules adopted in the prediction phase, and does not affect the parallel generation of prediction results by multiple branches based on the same historical context reference in the prediction phase.

[0056] According to one embodiment of this specification, after a branch instruction enters the execution phase and produces an actual execution result, the execution result is fed back to the prediction unit for training updates. For the second branch instruction that reuses a historical context snapshot during the prediction phase, its training update process is also based on that historical context snapshot. The prediction structure is updated using the global history register corresponding to the same historical context snapshot as the prediction phase and the program count information of the second branch instruction. This ensures that the prediction phase and the training phase maintain consistency in the historical reference system, avoiding semantic offset problems caused by differences in the historical benchmarks used for prediction and training.

[0057] Specifically, the methods described in the embodiments of this specification further include: After the first branch instruction or the second branch instruction is executed, the prediction structure is updated based on the actual execution result of the branch instruction and the historical context snapshot.

[0058] like Figure 4 The diagram illustrates the implementation mechanism of updating the prediction structure in an embodiment of this specification. In this embodiment, after the first branch instruction is executed, the execution unit feeds back the actual execution result of the first branch instruction to the prediction unit. The actual execution result may include necessary information required for specific implementation, such as the actual jump direction of the branch instruction, the target address, and program counter information. After receiving the execution result of the first branch instruction, the prediction unit extracts necessary information such as the historical context snapshot (HS) used when generating the prediction request for the first branch instruction during the prediction phase. Based on the global historical register status information in the historical context snapshot (HS) and necessary information such as the program counter of the first branch instruction, the prediction unit generates a training request and accesses the prediction expectation information recorded / stored by the prediction structure. According to the actual execution result of the first branch instruction, the prediction expectation information recorded / stored by the prediction unit / prediction result is updated. For example, in some implementations, if the actual execution result matches the prediction expectation expressed by the prediction information, the prediction information is maintained or the prediction unit's perception of the credibility of the prediction expectation is maintained / enhanced according to specific implementation requirements; if they are inconsistent, the prediction information is modified or the prediction unit's perception of the credibility of the prediction expectation is weakened according to specific implementation requirements.

[0059] After the second branch instruction completes execution, the execution unit also feeds back the actual execution result of the second branch instruction to the prediction unit. Since the second branch instruction reuses the same historical context snapshot (HS) as the first branch instruction during the prediction phase, the prediction unit extracts the same historical context snapshot HS as one of the training baseline elements during the training update phase. The prediction unit uses the global history register status information in the historical context snapshot HS and necessary information such as the program counter of the second branch instruction, as required by specific implementation needs, to generate a training / access request. This request can locate the prediction information associated with the second branch instruction in the prediction structure. Based on the actual execution result of the second branch instruction, the prediction unit trains and updates the corresponding prediction information; for example, it may maintain / modify the prediction information or maintain / enhance / weaken the prediction unit's perception of the credibility of the prediction expectation expressed by the prediction information according to specific implementation requirements, in order to improve the accuracy and stability of subsequent predictions.

[0060] During training updates, the prediction unit maintains consistency with the training phase in terms of historical reference. For the second branch instruction, although it follows the first branch instruction in the program execution order, it uses the same historical context snapshot (HS) as the first branch instruction during the prediction phase, and therefore, it is also updated based on this historical context snapshot (HS) during the training phase. This consistency mechanism avoids semantic offset issues caused by using different historical benchmarks for prediction and training, enabling the prediction structure to accurately learn the behavioral patterns of branch instructions.

[0061] The prediction unit also maintains a context record queue, recording the branch identifier, prediction result, and historical context snapshot identifier used for each prediction request. When the execution result of a branch instruction is returned, the prediction unit queries the context record queue to accurately locate the historical context snapshot used by that branch instruction during the prediction phase, ensuring that the correct historical baseline is used during the training and update process. The record structure can be a queue, a table, or other indexed structure.

[0062] By updating the prediction structure based on actual execution results and historical context snapshots, this method achieves historical alignment between the prediction and training phases, improves the accuracy and consistency of multi-branch parallel prediction, and effectively supports the high-throughput branch prediction requirements of the processor front end.

[0063] According to one embodiment of this specification, since multiple prediction results may be generated within the same prediction period, this embodiment of the specification sets up context information for recording and managing prediction requests. Specifically: Generate historical context information for the first branch instruction based on the actual branch behavior information of the first branch instruction and the historical context snapshot; and / or The historical context information of the second branch instruction is generated based on the actual branch behavior information of the second branch instruction and the historical context snapshot.

[0064] In the embodiments of this specification, the actual branch behavior information includes, but is not limited to, program count information. In the embodiments of this specification, the actual branch behavior information of the branch instruction is used as the label of the branch instruction. This can be understood as adding a label to the historical context snapshot used in the prediction stage to obtain historical context information.

[0065] Therefore, after a branch instruction is executed, the historical context information corresponding to that branch instruction is looked up based on the label, thereby determining the historical context snapshot within that historical context information. This historical context snapshot is then used to update the prediction structure. This mechanism facilitates the parallel generation of multiple prediction requests on the hardware structure and keeps the prediction behavior of multiple branches aligned on the historical reference frame, thus avoiding errors.

[0066] According to one embodiment of this specification, in order to record the complete execution order of branch instructions in the historical context information, thereby facilitating subsequent verification, rollback, and training organization, this embodiment of the specification, for the first branch instruction, concatenates the actual branch behavior information of the first branch instruction with the historical context snapshot to obtain the historical context snapshot of the first branch instruction; for any second branch instruction, the actual branch behavior information of the second branch instruction is concatenated with the historical context snapshot of the branch instructions whose execution order precedes the second branch instruction to obtain the historical context information of the second branch instruction.

[0067] like Figure 5 The diagram illustrates the implementation mechanism of the historical context record queue in this embodiment. It can be understood that the historical context snapshot concatenation of the second branch instruction in this embodiment is based on the historical context snapshot HS1 already formed by its preceding branch instruction. The concatenation operation adds the actual execution result information of the second branch instruction to the historical context information HS1 of the preceding branch instruction, forming a historical record HS2 containing complete execution order information. This concatenation method ensures that no execution information of any branch instruction is omitted from the historical context, maintaining the integrity of the branch execution order.

[0068] When multiple consecutive branch instructions exist, each subsequent branch instruction adopts the same concatenation principle. The generation of the historical context snapshot of any branch instruction is based on the historical context snapshot of the preceding branch instructions in its execution order. By concatenating its actual branch behavior information with the preceding snapshot, an accumulated historical context record is formed and recorded in a queue. This allows the corresponding historical context information to be retrieved from the queue after the branch instruction is executed, thereby obtaining the historical context snapshot used in the prediction phase.

[0069] This concatenation method ensures that each branch instruction's historical context snapshot contains complete execution history information from the first branch instruction to the current branch instruction. The concatenated historical context snapshot provides an accurate historical benchmark for subsequent branch prediction and training updates, ensuring that the prediction and training phases are conducted within the same historical reference system, thus avoiding the problem of decreased prediction accuracy due to inconsistent historical benchmarks.

[0070] The above splicing method enables the orderly generation and management of historical context snapshots of multiple branch instructions, supporting the processor front end to perform efficient parallel prediction processing of multiple branch instructions within a single prediction cycle.

[0071] In some implementations, to support rollback, inspection, or training organization, logging information describing the execution order and prediction reference relationships can be maintained. This includes recording branch identifiers, prediction results, and historical context snapshot identifiers referenced during the prediction phase. When the execution result is returned, the corresponding historical context snapshot is located based on the logging information to complete the training update. The maintenance of historical context information can be performed independently according to a preset strategy (e.g., selective recording, compression, or sampling), and this maintenance method does not affect the reuse of the same historical reference during the prediction phase.

[0072] Based on the same inventive concept, embodiments of this specification also provide a high-throughput prediction device that supports parallel prediction of multiple dynamic branches, such as... Figure 6 As shown, the device includes: The branch information acquisition unit 601 is used to acquire branch information of a first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction. The historical context snapshot acquisition unit 602 is used to acquire a historical context snapshot selected during the prediction phase when predicting the first branch instruction. The prediction unit 603 is used to determine the prediction result of the first branch instruction based on the historical context snapshot and the branch information of the first branch instruction; when predicting the second branch instruction, the prediction result of the second branch instruction is determined based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

[0073] The beneficial effects obtained by the above-described device are the same as those obtained by the above-described method, and will not be described in detail in the embodiments of this specification.

[0074] like Figure 7 The diagram shown is a structural schematic of a computer device according to an embodiment of this specification. The methods described in this specification can be applied to the computer device of this embodiment.

[0075] like Figure 7 The diagram illustrates the structure of a computer device according to an embodiment of this specification. The computer device in this embodiment is capable of executing the methods described in the embodiments of this specification. The computer device 702 may include one or more processing devices 704, such as one or more central processing units (CPUs), each of which may implement one or more hardware threads. The computer device 702 may also include any storage resource 706 for storing information of any kind, such as code, settings, data, etc. Without limitation, for example, the storage resource 706 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any storage resource can use any technology to store information. Furthermore, any storage resource may provide volatile or non-volatile retention of information. Furthermore, any storage resource may represent a fixed or removable component of the computer device 702. In one case, when the processing device 704 executes associated instructions stored in any storage resource or combination of storage resources, the computer device 702 may perform any operation of the associated instructions. The computer device 702 also includes one or more drive systems 708 for interacting with any storage resources, such as hard disk drive systems, optical disk drive systems, etc.

[0076] Computer device 702 may also include an input / output module 710 (I / O) for receiving various inputs (via input device 712) and providing various outputs (via output device 714). A specific output mechanism may include a presentation device 716 and an associated graphical user interface (GUI) 718. In other embodiments, the input / output module 710 (I / O), input device 712, and output device 714 may be omitted, and the device may function solely as a computer device within a network. Computer device 702 may also include one or more network interfaces 720 for exchanging data with other devices via one or more communication links 722. One or more communication buses 724 couple the components described above together.

[0077] Communication link 722 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 722 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0078] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0079] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the above-described method.

[0080] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0081] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the embodiments of this specification, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0082] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments in this specification.

[0083] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0084] In the embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0085] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0086] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0087] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this specification, in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] This specification describes the principles and implementation methods of the embodiments using specific examples. The above descriptions of the embodiments are only for the purpose of helping to understand the methods and core ideas of the embodiments in this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments in this specification. Therefore, the content of this specification should not be construed as a limitation on the embodiments in this specification.

Claims

1. A high-throughput prediction method supporting parallel prediction of multiple dynamic branches, characterized in that, The method includes: Obtain branch information for the first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction; When predicting the first branch instruction, a snapshot of the historical context selected during the prediction phase is obtained; The prediction result of the first branch instruction is determined based on the historical context snapshot and the branch information of the first branch instruction; When predicting the second branch instruction, the prediction result of the second branch instruction is determined based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

2. The method according to claim 1, characterized in that, The prediction times of both the first branch instruction and the second branch instruction are within the target prediction period.

3. The method according to claim 1, characterized in that, The first branch instruction and the second branch instruction may be contiguous or non-contiguous in the instruction address space.

4. The method according to claim 1, characterized in that, The prediction of the second branch instruction does not depend on the historical context information updated based on the prediction result or execution result of the first branch instruction.

5. The method according to claim 1, characterized in that, The method further includes: After the first or second branch instruction is completed, the prediction structure is trained and updated based on the actual execution results of the branch instruction. The training update is based on a historical reference state that is consistent with the historical context snapshot used in the corresponding branch instruction prediction phase.

6. The method according to claim 5, characterized in that, The method further includes: After the branch instruction is executed, the actual branch behavior information of the first branch and / or the second branch instruction is updated to the historical context information according to the preset historical maintenance rules.

7. The method according to claim 6, characterized in that, The historical maintenance rules include any one or a combination of the following: The selection rules for whether to include branch instructions in the history; Rules for compressing, sampling, or filtering historical information; The actual rules for updating historical information.

8. The method according to claim 1, characterized in that, The branch information includes program count information.

9. A high-throughput prediction device supporting parallel prediction of multiple dynamic branches, characterized in that, The device includes: The branch information acquisition unit is used to acquire branch information of a first branch instruction and at least one second branch instruction within the target prediction period, wherein the program execution order of the second branch instruction is after the first branch instruction. The historical context snapshot acquisition unit is used to select a historical context snapshot during the prediction phase when predicting the first branch instruction. The prediction unit is configured to determine the prediction result of the first branch instruction based on the historical context snapshot and the branch information of the first branch instruction; and when predicting the second branch instruction, to determine the prediction result of the second branch instruction based on the same historical context snapshot used when predicting the first branch instruction and the branch information of the second branch instruction.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of any one of claims 1 to 8.

11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 8.

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