Memory access method, address transmission method and related products

Abstract

The invention provides a memory access method and device, an address transmission method and device, a chip, a chip network, an electronic device and electronic equipment, and relates to the technical field of chips. According to the method, when memory access among the chip nodes is realized in the chip network, access is performed by adopting the target unique identifier of the second chip node and the target local physical address of the memory space to be accessed in the second chip node, so that the physical address transmission can be reserved, and the memory access efficiency is improved. And routing of the accessed chip nodes is performed by adding the target unique identifier, so that memory access among the chip nodes in the chip network is realized. Compared with a scheme using a global physical address, the security change of address transmission is more adaptive to the dynamic change condition of the chip network, and the routing table overhead in the chip network can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a memory access method, an address transmission method, a device, a chip, a chip network, an electronic device, and an electronic device. Background Technology

[0002] In large-scale chip networks, numerous chip nodes exchange data point-to-point with each other. During this data exchange, addresses serve as unique identifiers throughout the entire network system.

[0003] Currently, chip networks require unified address orchestration based on the transmitting nodes to transmit global physical addresses. However, directly using global physical addresses for data transmission cannot guarantee address transmission security. Furthermore, since global physical addresses are uniformly allocated, adding or modifying chip nodes in the chip network necessitates a unified modification of the global physical addresses, resulting in a significant workload and hindering dynamic changes to the chip network. Additionally, using global physical addresses for routing in chip networks requires the routing table to record the complete global physical addresses, thus incurring substantial routing table overhead. Summary of the Invention

[0004] The purpose of this application is to provide a memory access method, address transmission method, apparatus, chip, chip network, electronic device, and electronic device to improve the security of address transmission, better adapt to dynamic changes in the chip network, and reduce routing table overhead in the chip network.

[0005] This application provides a memory access method applied to a first chip node in a chip network; the chip network includes multiple chip nodes, which are communicatively connected through a first switch node; the first chip node is any chip node in the chip network; the method includes: in response to obtaining a target virtual address of a memory space to be accessed, obtaining a target physical address corresponding to the target virtual address from a local page table; wherein, when the target physical address belongs to a second chip node, the target physical address includes a target unique identifier of the second chip node and a target local physical address of the memory space to be accessed in the second chip node; the second chip node is any chip node in the chip network other than the first chip node; when the target physical address belongs to the second chip node, sending a memory access request to the second chip node having the target unique identifier through the first switch node; the memory access request includes the target local physical address; and receiving feedback from the second chip node through the first switch node.

[0006] In the above implementation scheme, when implementing memory access between chip nodes within the chip network, access is achieved by using the target unique identifier of the second chip node and the target local physical address of the memory space to be accessed within the second chip node. This allows for memory access between chip nodes in the chip network while preserving physical address transmission, and by adding the target unique identifier for routing the accessed chip node. Compared to related technologies, the transmitted physical address is no longer the global physical address. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and its internal physical address allocation scheme are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to a certain extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0007] Optionally, in response to obtaining the target virtual address of the memory space to be accessed, obtaining the target physical address corresponding to the target virtual address from the local page table includes: in response to obtaining the target virtual address of the memory space to be accessed, searching for the target page table entry corresponding to the target virtual address from the local page table; determining the value at a first specified position of the target page table entry; if the value at the first specified position is a first value, obtaining the target unique identifier from a second specified position of the target page table entry, and obtaining the target local physical address from a third specified position of the target page table entry; concatenating the target unique identifier and the target local physical address to obtain the target physical address.

[0008] In the above implementation, the value at the first specified position in the page table entry is used to distinguish whether the memory access is an inter-chip node access operation. In the case of inter-chip node memory access, the target unique identifier is obtained from the second specified position and the target local physical address is obtained from the third specified position. The target physical address is then concatenated to obtain the target physical address. This enables the differentiation and processing of inter-chip node access operations and non-inter-chip node access operations.

[0009] Optionally, the method further includes: if the target physical address belongs to the first chip node, accessing the memory space to be accessed in the memory of the first chip node according to the target physical address.

[0010] In the above implementation, if the target physical address belongs to the first chip node, that is, this is a local memory space access, then it is only necessary to directly access the memory space corresponding to the target physical address in the memory of the first chip node.

[0011] Optionally, in response to obtaining the target virtual address of the memory space to be accessed, obtaining the target physical address corresponding to the target virtual address from the local page table includes: in response to obtaining the target virtual address of the memory space to be accessed, searching for the target page table entry corresponding to the target virtual address from the local page table; determining the value at a first specified position of the target page table entry; and if the value at the first specified position is a second value, obtaining the target physical address from a third specified position of the target page table entry.

[0012] In the above implementation, the value at the first specified position in the page table entry is used to distinguish whether the memory access is a local access operation of the chip node. In the case of a local memory access of the chip node, the target local physical address is directly obtained from the third specified position for access, thereby realizing the distinction between access operations between chip nodes and access operations local to the chip node.

[0013] Optionally, the chip node is a Deepin Computer Chip (DCU), and the target unique identifier is the DCU identifier of the second chip node.

[0014] This application also provides a memory access method applied to a first switch node in a chip network; the chip network includes multiple chip nodes, which are communicatively connected through the first switch node; the method includes: in response to receiving a first memory access request from the first chip node, obtaining a target unique identifier from the memory access request; forwarding a second memory access request to a second chip node having the target unique identifier; the second memory access request includes a target local physical address; receiving feedback information from the second chip node, and forwarding the feedback information to the first chip node.

[0015] In the above implementation, the global physical address is no longer transmitted. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and the internal physical address allocation scheme of each chip node are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to a certain extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0016] Optionally, the second memory access request is the first memory access request.

[0017] This application also provides a memory access method applied to a second chip node in a chip network; the chip network includes multiple chip nodes, which are connected to each other via a first switch node; the second chip node is any chip node in the chip network; the method includes: receiving a memory access request from the first switch node; wherein the first switch node determines the second chip node based on a target unique identifier transmitted by the first chip node; the first chip node is any chip node in the chip network other than the second chip node; the memory access request includes a target local physical address of the second chip node; if the memory access request is a data read request, feeding back the data at the target local physical address to the first switch node; if the memory access request is a data write request, writing the data corresponding to the data write request to the target local physical address, and feeding back write response information to the first switch node.

[0018] In the above implementation, the global physical address is no longer transmitted. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and the internal physical address allocation scheme of each chip node are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to a certain extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0019] This application also provides an address transmission method applied to a first chip node in a chip network; the chip network includes multiple chip nodes, which are connected to each other via a second switch node and an interface node; the first chip node is any chip node in the chip network; the method includes: receiving a physical address of a second chip node to be used for table creation from the second switch node; the physical address to be used for table creation includes a unique identifier of the second chip node and a local physical address of the second chip node; the second chip node is any chip node in the chip network other than the first chip node; establishing a page table entry in a local page table based on the unique identifier of the second chip node and the local physical address of the second chip node; the page table entry records the unique identifier of the second chip node and the local physical address of the second chip node, and the page table entry uniquely corresponds to a virtual address.

[0020] In the above implementation, page table entries in the local page table are established based on the unique identifier and local physical address of the second chip node. This means that subsequent memory accesses no longer transmit the global physical address. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and its internal physical address allocation scheme are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to some extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0021] Optionally, before receiving the physical address of the table to be built from the second chip node transmitted by the second switch node, the method further includes: sending an access request to the second chip node.

[0022] In the above implementation, the unique identifier of the second chip node and the local physical address of the second chip node are reported by sending an access request to the second chip node, thereby enabling the local page table to be built on demand and reducing the overhead of the local page table.

[0023] Optionally, the value at the first specified position of the page table entry is a first value.

[0024] This application also provides an address transmission method applied to an interface node in a chip network; the chip network includes multiple chip nodes, and each chip node is communicatively connected to the interface node through a second switch node; the method includes: receiving a unique identifier of a second chip node and a local physical address of the second chip node transmitted through the second switch node; the second chip node is any chip node in the chip network; concatenating the unique identifier and the local physical address to obtain a physical address for a table to be created in the second chip node; sending the physical address for a table to be created to a peer interface node, so that the peer interface node sends the physical address for a table to be created to a first chip node through the peer's second switch node; the first chip node is any chip node in the chip network other than the second chip node.

[0025] In the above implementation, by forwarding the unique identifier and local physical address of the second chip node to the page table entry in the local page table of the first chip, subsequent memory accesses no longer transmit the global physical address. Even if the target physical address is leaked during transmission, if the sender is unaware of the unique identifiers of each chip node and the internal physical address allocation scheme of each chip node, it cannot directly locate the data based on the target physical address, thus improving security to a certain extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifiers in the routing table need to be changed accordingly, without modifying the physical addresses, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifiers of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0026] This application also provides an address transmission method applied to a second chip node in a chip network; the chip network includes multiple chip nodes, which are connected to each other via a second switch node and an interface node; the second chip node is any chip node in the chip network; the method includes: obtaining its own unique identifier and local physical address in local memory; and sending its own unique identifier and local physical address to the first chip node via communication between the second switch node and the interface node.

[0027] In the above implementation, by sending the unique identifier and local physical address of the second chip node to the page table entry in the local page table of the first chip, subsequent memory accesses no longer transmit the global physical address. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and its internal physical address allocation scheme are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to a certain extent. Furthermore, based on the scheme of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus making it more adaptable to dynamic changes in the chip network. In addition, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0028] Optionally, before obtaining its own unique identifier and the local physical address of local memory, the method further includes: in response to receiving an access request from a first chip node, requesting memory space in local memory; wherein: the first chip node is any chip node in the chip network other than the second chip node; and the local physical address is the local physical address of the requested memory space.

[0029] Optionally, the chip node is a Deepin Computer Chip (DCU), and the unique identifier is the DCU identifier of the second chip node.

[0030] This application also provides a chip, including a memory management unit and memory; the memory management unit is used to execute any of the above-described methods applied to a first chip node or a second chip node.

[0031] This application also provides a chip network, characterized in that it includes multiple chip nodes, each chip node is connected to the other through a first switch node, and each chip node is also connected to the other through a second switch node and an interface node; wherein each chip node is implemented using the aforementioned chip.

[0032] This application also provides an electronic device, including the chip network described above.

[0033] This application also provides an electronic device, including the electronic components described above. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a chip network structure provided in an embodiment of this application; Figure 2 A flowchart illustrating the address transmission method provided in this application embodiment; Figure 3 A more specific schematic diagram of a chip network structure is provided for an embodiment of this application; Figure 4 A schematic diagram of a page table entry provided for an embodiment of this application; Figure 5 A flowchart illustrating the interaction of a memory access method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a DCU chip network provided in an embodiment of this application. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0037] Currently, in large-scale chip networks, chip nodes exchange data through switch nodes (such as switch chips). During data exchange, the target chip nodes interact based on pre-arranged global physical addresses. This method suffers from the aforementioned security deficiencies, hinders dynamic changes in the chip network, and incurs significant routing table overhead. To address these issues, this application introduces a unique identifier for each chip node, combined with localized physical address arrangement for each chip node, to achieve data interaction and location between chip nodes in the chip network, thereby resolving the aforementioned problems to some extent.

[0038] See also Figure 1 As shown, Figure 1 This is a schematic diagram of a chip network structure provided in an embodiment of this application. The chip network includes multiple chip nodes ( Figure 1 Taking two chip nodes as an example (in practical applications there can be more chip nodes), there is a first switch node, a second switch node, and an interface node. The chip nodes communicate with each other through the first switch node, and also through the second switch node and the interface node.

[0039] In the embodiments of this application, the chip node may be implemented using, but is not limited to, a Deep Computing Unit (DCU), a Graphics Processing Unit (GPU) chip, a General-purpose Computing on Graphics Processing (GPGPU) chip, a Central Processing Unit (CPU) chip, a Neural Network Processing Unit (NPU), etc.

[0040] In the embodiments of this application, the first switch node and the second switch node may be implemented using, but are not limited to, a Switch chip.

[0041] In the embodiments of this application, the interface node may be implemented using, but is not limited to, a Network Interface Card (NIC).

[0042] Further integration Figure 2 As shown, Figure 2 The address transfer process between any two chip nodes is illustrated, including: S201: The second chip node obtains its own unique identifier and the local physical address of its local memory.

[0043] In this embodiment of the application, the second chip node is any chip node in the chip network.

[0044] In this embodiment of the application, the topology of the entire chip network can be drawn by the upper layer of the chip network, for example, by the topology management driver, and a unique identifier for each chip node can be generated and assigned to each chip node.

[0045] In the embodiments of this application, such as Figure 3 As shown, each chip node can have a memory management unit (MMU) and memory (e.g., including but not limited to high-bandwidth memory (HBM), DDR5, DDR4, etc.). Each chip node's memory management unit can independently manage and allocate its own memory's physical address (referred to as local physical address in this paper).

[0046] In the embodiments of this application, the specific operation process executed by any chip node can be executed by the memory management unit within the chip node.

[0047] In one feasible embodiment of this application, the second chip node can execute the appended provisions after its own memory management unit has allocated a local physical address for any memory space in its own memory. Figure 2 The process is shown below.

[0048] In this feasible implementation, the second chip node can broadcast its unique identifier and local physical address of local memory in the chip network, so that every chip node other than the second chip node can receive the unique identifier and local physical address of the second chip node, and then construct page table entries for the local page table.

[0049] In this feasible implementation, the second chip node may also send its own unique identifier and local physical address in local memory together with the unique identifier of one or more designated first chip nodes, so that the subsequent second switch node can route the unique identifier and local physical address of the second chip node to one or more designated first chip nodes, so that the one or more designated first chip nodes can construct page table entries for their local page tables.

[0050] In this embodiment of the application, the first chip node can be any chip node in the chip network other than the second chip node.

[0051] In another feasible embodiment of this application, the first chip node may send an access request to the second chip node (this access request can be sent from the first switch node to the second chip node, or it can be sent from the second switch node and the interface node to the second chip node. The access request may carry the unique identifier of the first chip node). In response to receiving the access request from the first chip node, the second chip node requests memory space in its local memory and obtains the local physical address of the requested memory space, and then feeds it back to the first chip node along with the unique identifier of the second chip node in subsequent steps. When feeding back the unique identifier and local physical address of the second chip node, the unique identifier of the first chip node may be included, thereby enabling the second switch node to route the unique identifier and local physical address of the second chip node to the first chip node.

[0052] S202: Send the obtained unique identifier and local physical address to the second switch node on this end.

[0053] In this embodiment of the application, the second switch node at this end refers to the second switch node connected to the second chip node.

[0054] S203: The second switch node on this end sends the unique identifier and local physical address to the interface node on this end.

[0055] In this embodiment of the application, the interface node of the local end refers to the interface node connected to the second switch node of the local end.

[0056] In one alternative implementation, the local interface node can be integrated onto the local second switch node.

[0057] S204: The local interface node concatenates the unique identifier and the local physical address to obtain the physical address of the table to be built on the second chip node.

[0058] S205: The local interface node sends the physical address of the table to be created to the remote interface node.

[0059] In this embodiment, the local interface node refers to the interface node connected to the second switch node at the peer end. The second switch node at the peer end is the second switch node connected to the destination node to which the data is to be forwarded, i.e., the first chip node.

[0060] In one alternative implementation, the interface node at the other end can be integrated onto the second switch node at the other end.

[0061] S206: The interface node at the other end sends the physical address of the table to be created to the second switch node at the other end.

[0062] S207: The second switch node on the other end sends the physical address of the table to be created to the first chip node.

[0063] In this embodiment of the application, each second switch node and interface node constitute a transmission network. Each second switch node can maintain a routing table, which can record the unique identifier and path of each chip node. Thus, the physical address of the table to be built can be routed to the first chip node based on the unique identifier of the first chip node.

[0064] In this embodiment of the application, if the second switch node on the local end receives a broadcast instruction, then every chip node in the chip network other than the second chip node is treated as the first chip node, thereby performing routing.

[0065] S208: The first chip node creates page table entries in its local page table based on the unique identifier in the physical address of the table to be created and the local physical address.

[0066] In this embodiment of the application, the first chip node can establish page table entries, which can record the unique identifier and local physical address of the received second chip node, and configure a virtual address that uniquely corresponds to the page table entry.

[0067] In this embodiment of the application, the virtual address corresponding to the physical address of the table to be built can be determined by using the existing physical address and virtual address correspondence configuration method. This embodiment of the application does not limit this.

[0068] In this embodiment of the application, a second designated location in the page table entry can be configured to record the unique identifier of the chip node, and a third designated location can be configured to record the local physical address. For example, see... Figure 4 As shown, Figure 4 A page table entry is shown, wherein bits 12 to 20 and 49 to 50 are used to record bits 0 to 8 and 9 to 10 of a unique identifier, respectively; bits 21 to 47 of the page table entry are used to record the local physical address.

[0069] In this embodiment of the application, in order to reduce the page table size and facilitate searching, an index can be built for each page table entry in the local page table. For example, the Virtual Machine Identifier (VMID) can be used as the index, and the VMID can be carried in the virtual address, thereby enabling fast determination of page table entries in the page table based on the VMID.

[0070] In this embodiment, after generating a local physical address, the second chip node can also generate a page table entry in its local page table based on that local physical address. This page table entry contains the local physical address. That is, for any given chip node, its constructed local page table entry can contain its own local physical address for accessing its own memory, and it can also contain unique identifiers and local physical addresses of other chip nodes for accessing the memory of those other chip nodes.

[0071] To distinguish whether a page table entry is used to access its own memory or the memory of other chip nodes, in an optional embodiment of this application, a unique identifier may not be recorded in the page table entry used for accessing its own memory, or a specific value (e.g., all 0s or all 1s, or the chip node's own unique identifier) ​​may be recorded at a second specified location where a unique identifier is recorded. Thus, during subsequent memory access, if the page table entry corresponding to the virtual address does not record a unique identifier or the recorded unique identifier is a preset specific value, then the page table entry is determined to be used for accessing its own memory. If the page table entry corresponding to the virtual address records a unique identifier or the recorded unique identifier is not a preset specific value, then the page table entry is determined to be used for accessing the memory of other chip nodes.

[0072] In another optional embodiment of this application, when generating page table entries, different values ​​can be written at the first specified position of the page table entry based on whether the local physical address originates from itself or from other chip nodes. For example, when generating page table entries based on the received physical address to be created, a first value (e.g., 1) can be set at the first specified position of the page table entry; when generating page table entries based on its own local physical address, a second value (e.g., 0) can be set at the first specified position of the page table entry. In this way, based on the value at the first specified position of the page table entry, it can be determined whether the page table entry is used to access its own memory or to access the memory of other chip nodes. This method only requires directly identifying the value at the first specified position to achieve differentiation, which can improve differentiation efficiency. For example, as shown... Figure 4 As shown, the 48th position of a page table entry can be used as the first designated position.

[0073] Understandable. Figure 4 This is merely an example of a page table entry in an embodiment of this application and is not intended to limit the scope of this application.

[0074] Further integration is possible Figure 5 As shown, Figure 5 The process of memory access between any two chip nodes is illustrated, including: S501: In response to obtaining the target virtual address of the memory space to be accessed, the first chip node retrieves the target physical address corresponding to the target virtual address from the local page table.

[0075] In this embodiment of the application, the target virtual address may be obtained by the first chip node based on the currently executing task.

[0076] In one optional embodiment of this application, the corresponding target page table entry can be indexed from the local page table based on the VMID of the target virtual address.

[0077] In this embodiment, after finding the target page table entry, it can be first determined whether the target page table entry is used to access its own memory or to access the memory of other chip nodes. That is, it can be determined whether the target physical address belongs to the first chip node itself or to the second chip node. The specific confirmation method can be found above, and will not be repeated here.

[0078] When a target page table entry is used to access its own memory (i.e., the target physical address belongs to the first chip node itself), the memory space to be accessed in the first chip node's memory is accessed based on the target physical address. In this case, the target physical address can be directly obtained from the third specified location of the target page table entry.

[0079] Correspondingly, when the target page table entry is used to access the memory of other chip nodes (i.e., the target physical address belongs to the second chip node), the target unique identifier can be obtained from the second specified position of the target page table entry, and the target local physical address can be obtained from the third specified position of the target page table entry. Then, the target unique identifier and the target local physical address are concatenated to obtain the target physical address.

[0080] S502: If the target physical address belongs to the second chip node, send a memory access request to the first switch node.

[0081] In this embodiment, the memory access request sent by the first chip node to the first switch node may contain a target physical address. For ease of description, in this embodiment, the memory access request sent by the first chip node to the first switch node is referred to as the first memory access request.

[0082] S503: The first switch node sends a memory access request to the second chip node.

[0083] The first switch node can find the route to the second chip node through its routing table based on the unique identifier in the target physical address, and thus send the memory access request to the second chip node. For ease of description, in this embodiment, the memory access request sent by the first switch node to the second chip node is referred to as the second memory access request.

[0084] In one optional embodiment of this application, the second memory access request may be the first memory access request.

[0085] In another optional embodiment of this application, the first switch node can remove the unique identifier from the first memory access request to obtain the second memory access request, and send the second memory access request to the second chip node.

[0086] S504: The second chip node performs memory access based on the target local physical address in the memory access request.

[0087] In this embodiment, the memory access request can be either a data read request or a data write request. When making a data write request, the data to be written is also sent along with the memory access request.

[0088] In this embodiment of the application, when the memory access request is a data read request, the second chip node accesses the memory space corresponding to the target local physical address, obtains the data in the memory space as feedback information, and executes subsequent steps.

[0089] When the memory access request is a data write request, the second chip node writes the data corresponding to the data write request to the target local physical address and generates write response information as feedback information to execute subsequent steps.

[0090] S505: The second chip node sends feedback information to the first switch node.

[0091] In this embodiment, the feedback information may include a unique identifier of the first chip node. Alternatively, the unique identifier of the first chip node may be sent together with the feedback information to the first switch node.

[0092] S506: The first switch node sends feedback information to the first chip node.

[0093] The first switch node can route feedback information to the first chip node based on the unique identifier of the first chip node.

[0094] In this embodiment, the unique identifier of a chip node can be a chip ID (identity identifier) ​​used to implement the chip node. For example, when the chip node is a DCU, the unique identifier of the chip node can be a DCU identifier (i.e., DCUID).

[0095] In this embodiment, when the chip network changes, such as modifying the unique identifier of any chip node, the chip node can report its original unique identifier and the latest unique identifier to the chip network. This allows each chip node in the chip network to update the unique identifier of that chip node in its local page table to the latest unique identifier, thus satisfying the modification requirements of the chip network. Similarly, after deleting any chip node, the unique identifier of the deleted chip node can be reported to the chip network, causing each chip node in the chip network to delete the relevant page table entries of the deleted chip node from its local page table, thus satisfying the modification requirements of the chip network. Furthermore, after adding any chip node, the new chip node can achieve address interaction with the existing chip nodes in the chip network through the methods described above.

[0096] The solution provided in this application, when implementing memory access between chip nodes within a chip network, uses the target unique identifier of the second chip node and the target local physical address of the memory space to be accessed within the second chip node. This allows for memory access between chip nodes in the chip network while preserving physical address transmission, by adding the target unique identifier for routing the accessed chip node. Compared to related technologies, the transmitted physical address is no longer the global physical address. Even if the target physical address is leaked during transmission, if the unique identifier of each chip node and its internal physical address allocation scheme are unknown, data location cannot be directly achieved based on the target physical address, thus improving security to a certain extent. Furthermore, based on the solution of this application, when the chip network changes, only the chip node identifier in the routing table needs to be changed accordingly, without modifying the physical address, thus better adapting to dynamic changes in the chip network. Additionally, the routing table in the first switch node only needs to record the unique identifier of each chip node, without recording the global physical address. Since the size of the unique identifier of each chip node is much smaller than the size of the global physical address, the routing table overhead in the chip network can be reduced.

[0097] To facilitate understanding of the solutions in the embodiments of this application, the following will be used as examples. Figure 6 The specific chip network shown is used as an example to further illustrate this application.

[0098] The chip network includes two DCUs, referred to as the source DCU and the destination DCU. Each DCU includes a compute unit (CU), a memory management unit (MMU), a high-bandwidth memory (HBM), a PCIe (peripheral component interconnect express, a high-speed serial computer expansion bus standard) interface, and a network on chip (NOC).

[0099] The MMUs in the two DCUs are connected to the first switch via their respective on-chip networks. The MMUs in the two DCUs are also connected to their respective second switches via their respective PCIe interfaces and communicate through the NIC.

[0100] Initially, the chip network topology management driver draws the topology of the entire chip network and generates DCUIDs for each DCU, which are then assigned to each DCU.

[0101] The source DCU sends an access request to the destination DCU via the second Switch1-NIC1-NIC2-second Switch2.

[0102] The destination DCU requests memory space in its local HBM and obtains the local physical address of the requested memory space. It then sends the local physical address PA along with the destination DCU's DCUID to NIC2 via the second switch 2. NIC2 concatenates the DCUID and PA to obtain NPA, which is then transmitted to the source DCU via NIC1 and the second switch 1.

[0103] After the source DCU obtains the NPA, it establishes a local page table and sets up a mapping relationship from VA to NPA.

[0104] When the source DCU accesses the virtual address VA, it queries the page table using the VMID to find the target page table entry. If the value at the first specified position of the target page table entry is 1, it indicates that the access is a remote access. The DCUID recorded at the second specified position and the PA recorded at the third specified position in the target page table entry are concatenated to obtain the NPA, and the access is initiated to the destination DCU through the first switch.

[0105] If the value at the first specified position of the target page table entry is 0, it indicates that the access is a near-end access. The PA of the record at the third specified position in the target page table entry is directly obtained, and the destination corresponding to the PA is accessed.

[0106] In the above process, whether it is the first switch or the second switch, when transmitting the NPA, the DCUID carried in the NPA is used for network node routing.

[0107] After the NPA reaches the destination DCU, the destination DCU uses the PA carried in the NPA for internal address routing.

[0108] Based on the same inventive concept, embodiments of this application also provide a chip, including a memory management unit and memory; the memory management unit is used to execute the above-described method flow executed by the first chip node or the second chip node.

[0109] The chip provided in this application embodiment may also have more modules, such as Figure 6 As shown, it can also have a PCIe interface, NOC, CUD, etc.

[0110] Based on the same inventive concept, embodiments of this application also provide an electronic device, including the aforementioned chip network.

[0111] In this application embodiment, electronic device refers to an electronic device that can be independently manufactured or sold and that works in conjunction with other devices to provide services. For example, electronic device may include, but is not limited to, motherboard, circuit board, graphics card, processor module, host, monitor, etc.

[0112] Based on the same inventive concept, embodiments of this application also provide an electronic device, including the electronic device described above.

[0113] In this application embodiment, the electronic device is a device that includes various electronic components and can provide services. For example, the electronic device may include, but is not limited to, servers, smart terminals (such as smartphones, laptops, tablets, smart wearable devices, smart cars, etc.).

[0114] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The embodiments described above are merely illustrative. Furthermore, the communication connections shown or discussed may be via communication interfaces and may be electrical, mechanical, or other forms.

[0115] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0117] In this article, "multiple" refers to two or more.

[0118] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A memory access method, characterized in that, It is applied to the first chip node of a chip network; the chip network includes multiple chip nodes, and the chip nodes are connected to each other through a first switch node. The first chip node is any chip node in the chip network; the method includes: In response to obtaining the target virtual address of the memory space to be accessed, the target physical address corresponding to the target virtual address is obtained from the local page table; the second chip node is any chip node in the chip network other than the first chip node; If the target physical address belongs to the second chip node, a memory access request is sent through the first switch node to the second chip node that has the target unique identifier in the target physical address; the memory access request includes the target local physical address in the target physical address; the target local physical address is the physical address of the memory space to be accessed in the second chip node. The feedback from the second chip node is received through the first switch node.

2. The memory access method as described in claim 1, characterized in that, In response to obtaining the target virtual address of the memory space to be accessed, the target physical address corresponding to the target virtual address is obtained from the local page table, including: In response to obtaining the target virtual address of the memory space to be accessed, the target page table entry corresponding to the target virtual address is retrieved from the local page table; Determine the value at the first specified position of the target page table entry; If the value at the first specified position is the first value, the target unique identifier is obtained from the second specified position of the target page table entry, and the target local physical address is obtained from the third specified position of the target page table entry; The target's unique identifier and its local physical address are concatenated to obtain the target's physical address.

3. The memory access method as described in claim 1, characterized in that, The method further includes: If the target physical address belongs to the first chip node, the memory space to be accessed in the memory of the first chip node is accessed according to the target physical address.

4. The memory access method as described in claim 3, characterized in that, In response to obtaining the target virtual address of the memory space to be accessed, the target physical address corresponding to the target virtual address is obtained from the local page table, including: In response to obtaining the target virtual address of the memory space to be accessed, the target page table entry corresponding to the target virtual address is retrieved from the local page table; Determine the value at the first specified position of the target page table entry; If the value at the first specified location is the second value, the target physical address is obtained from the third specified location of the target page table entry.

5. The memory access method according to any one of claims 1-4, characterized in that, The chip node is a Deepin Computer Chip (DCU), and the target unique identifier is the DCU identifier of the second chip node.

6. A memory access method, characterized in that, The method is applied to a first switch node in a chip network; the chip network includes multiple chip nodes, and the chip nodes are communicatively connected through the first switch node; the method includes: In response to receiving a first memory access request from the first chip node, a unique target identifier is obtained from the memory access request; The second memory access request is forwarded to a second chip node that has the unique identifier of the target; the second memory access request includes the target's local physical address; The system receives feedback information from the second chip node and forwards the feedback information to the first chip node.

7. The memory access method as described in claim 6, characterized in that, The second memory access request is the same as the first memory access request.

8. A memory access method, characterized in that, It is applied to a second chip node in a chip network; the chip network includes multiple chip nodes, and the chip nodes are connected to each other through a first switch node. The second chip node is any chip node in the chip network; the method includes: The system receives a memory access request from the first switch node; wherein the first switch node determines the second chip node based on the target unique identifier transmitted by the first chip node; the first chip node is any chip node in the chip network other than the second chip node; the memory access request includes the target local physical address of the second chip node. When the memory access request is a data read request, the data at the target local physical address is fed back to the first switch node; When the memory access request is a data write request, the data corresponding to the data write request is written to the target local physical address, and write response information is fed back to the first switch node.

9. An address transmission method, characterized in that, The method is applied to a first chip node in a chip network; the chip network includes multiple chip nodes, and the chip nodes are communicatively connected to each other through a second switch node and an interface node; the first chip node is any chip node in the chip network; the method includes: The system receives the physical address of the second chip node to be created from the second switch node; the physical address of the table to be created includes the unique identifier of the second chip node and the local physical address of the second chip node; the second chip node is any chip node in the chip network other than the first chip node. A page table entry is created in the local page table based on the unique identifier of the second chip node and the local physical address of the second chip node; the page table entry records the unique identifier of the second chip node and the local physical address of the second chip node, and the page table entry uniquely corresponds to a virtual address.

10. The address transmission method as described in claim 9, characterized in that, Before receiving the physical address of the second chip node to be built from the second switch node, the method further includes: Send an access request to the second chip node.

11. The address transmission method as described in claim 9, characterized in that, The value at the first specified position of the page table entry is the first value.

12. An address transmission method, characterized in that, The method is applied to interface nodes in a chip network; the chip network includes multiple chip nodes, and each chip node is communicatively connected to the interface node through a second switch node; the method includes: Receive the unique identifier of the second chip node and the local physical address of the second chip node transmitted through the second switch node; the second chip node is any chip node in the chip network; By concatenating the unique identifier and the local physical address, the physical address of the table to be built on the second chip node is obtained; The physical address of the table to be created is sent to the interface node at the other end, so that the interface node at the other end sends the physical address of the table to be created to the first chip node through the second switch node at the other end; the first chip node is any chip node in the chip network other than the second chip node.

13. An address transmission method, characterized in that, The method is applied to a second chip node in a chip network; the chip network includes multiple chip nodes, and the chip nodes are communicatively connected to each other through a second switch node and an interface node; the second chip node is any chip node in the chip network; the method includes: Obtain its own unique identifier and local physical address in local memory; The second switch node and interface node communicate with the first chip node to send their unique identifier and local physical address.

14. The address transmission method as described in claim 13, characterized in that, Before obtaining its own unique identifier and the local physical address of local memory, the method further includes: In response to receiving an access request from a first chip node, memory space is requested in the local memory; wherein: the first chip node is any chip node in the chip network other than the second chip node; and the local physical address is the local physical address of the requested memory space.

15. The address transmission method as described in claim 13 or 14, characterized in that, The chip node is a Deepin Computer Chip (DCU), and the unique identifier is the DCU identifier of the second chip node.

16. A chip, characterized in that, It includes a memory management unit and memory; the memory management unit is used to perform the method as described in any one of claims 1-5, 8-11, and 13-15.

17. A chip network, characterized in that, It includes multiple chip nodes, which are connected to each other through a first switch node, and are also connected to each other through a second switch node and an interface node; wherein each chip node is implemented using the chip as described in claim 16.

18. An electronic device, characterized in that, Including the chip network as described in claim 17.

19. An electronic device, characterized in that, Including the electronic device as described in claim 18.

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