Online upgrading circuit and method for logic configuration of FPGA (Field Programmable Gate Array) chip

Abstract

The invention discloses an FPGA chip logic configuration online upgrading circuit and method. The circuit comprises a USB interface, a USB to serial port chip, an MCU, an analog switch chip and a configuration Flash. The USB interface is connected with the MCU serial communication interface through the USB to serial port chip; the analog switch chip is provided with a first input channel, a second input channel and an output channel, the first input channel is connected with an SPI interface of the MCU, the second input channel is connected with a configuration SPI interface of the FPGA, the output channel is connected with an SPI pin of the configuration Flash, and a gating signal is controlled by the MCU. The MCU receives configuration data and an upgrading instruction sent by an external host, controls the analog switch to be switched between Flash writing by the MCU and Flash reading by the FPGA, and performs online writing on the configuration Flash through the USB and is used for configuration loading of the FPGA. The circuit can be uncovered without disassembling a machine, field upgrading can be completed without JTAG, and the maintenance cost is reduced.

Description

Technical Field

[0001] This application relates to the field of online upgrade technology for FPGA chip logic configuration, and in particular to an online upgrade circuit and method for FPGA chip logic configuration. Background Technology

[0002] In industrial control equipment such as servo drives, field-programmable gate arrays (FPGAs) are often used as core logic devices to achieve functions such as high-speed timing control, interface protocol processing, and parallel computing. In order for the FPGA to enter the expected logic function state after the device is powered on, the logic configuration data usually needs to be pre-written into an external non-volatile memory, and the FPGA automatically completes the configuration loading upon power-up, thereby entering user mode and starting to work.

[0003] In existing technologies, the configuration of FPGA chips for servo drives generally follows this process: First, the required circuit function is described using a prepared hardware description language (such as VHDL) or schematic diagram. The code is then converted into a netlist composed of basic logic gates such as AND gates, OR gates, NOT gates, and flip-flops, generating a bitstream file. Subsequently, a dedicated programmer is used to connect the USB port to the FPGA's JTAG port, and the bitstream is programmed into the FPGA's external SPI Flash. After the device is powered on again, the FPGA automatically enters the configuration process. The internal configuration controller reads the configuration data from the Flash and configures the internal SRAM. After configuration, the FPGA enters user mode and begins operation. This method is typically used for factory configuration. However, when users need to upgrade the FPGA configuration later, it often requires disassembling and opening the casing in an industrial setting and performing the upgrade via the JTAG interface, resulting in high manpower and material costs for batch processing. Furthermore, if upgrade logic is written within the FPGA itself and the configuration Flash is upgraded online via an external interface, accidental power loss or other freezes during the upgrade process can easily lead to upgrade failure, resulting in problems such as the FPGA being unable to reset and restart, or initialization failing.

[0004] Therefore, in the process of configuring and upgrading FPGA chips for servo drives, on-site upgrades require disassembling and opening the cover and rely on JTAG operations, resulting in high maintenance costs. Online upgrades are easily affected by accidental power outages, leading to upgrade failures and difficulty in resetting and restarting, which have become urgent problems to be solved. Summary of the Invention

[0005] This application provides an online upgrade circuit and method for FPGA chip logic configuration, aiming to solve the problems in the existing technology of FPGA chip configuration and upgrade of servo drivers, such as the need for on-site upgrades to disassemble and open the cover and rely on JTAG operation, resulting in high maintenance costs, and the online upgrade process being easily affected by accidental power outages, leading to upgrade failures and difficulty in resetting and restarting.

[0006] In a first aspect, there is an online upgrade circuit for FPGA chip logic configuration, the circuit including a USB interface, a USB to serial port chip, a microcontroller (MCU), an analog switch chip, and a configuration Flash chip;

[0007] The USB interface is connected to the USB end of the USB-to-serial chip, and the serial end of the USB-to-serial chip is connected to the serial communication interface of the MCU.

[0008] The analog switch chip has a first input channel, a second input channel, and an output channel. The first input channel is connected to the SPI interface of the MCU, the second input channel is connected to the configuration SPI interface of the FPGA, and the output channel is connected to the SPI interface pin of the configuration Flash chip.

[0009] The analog switch chip also has a gating signal input terminal, which is connected to the MCU.

[0010] The MCU is used to receive configuration data and upgrade instructions sent by an external host through the USB interface via the serial communication interface, and control the strobe signal according to the upgrade instructions so that when the analog switch chip selects the first input channel, the MCU writes to the configuration Flash chip through the SPI interface; when the analog switch chip selects the second input channel, the FPGA reads the configuration data from the configuration Flash chip through the configuration SPI interface for configuration loading.

[0011] In the above scheme, optionally, the SPI interface pins of the configured Flash chip include a chip select signal CS, a serial clock signal SCLK, a master output / slave input signal MOSI, and a master input / slave output signal MISO;

[0012] The analog switch chip sets corresponding switching paths for CS, SCLK, MOSI and MISO to select between the first input channel and the second input channel.

[0013] Optionally, in the above scheme, the serial communication interface of the MCU is a UART interface or an SCI interface;

[0014] The USB-to-serial chip is used to convert USB data from the USB interface into serial data that matches the UART interface or SCI interface.

[0015] In the above scheme, optionally, the analog switch chip is a 2-to-1 multiplexer or a multi-channel analog switch device;

[0016] The strobe signal input terminal receives the GPIO control signal output by the MCU to control the selection state of the first input channel and the second input channel.

[0017] Optionally, in the above scheme, the upgrade instruction includes: an instruction to enter upgrade mode, writing start address information, and writing length information;

[0018] The MCU controls the analog switch chip to select the first input channel according to the enter upgrade mode instruction, and writes to the configuration Flash chip according to the write start address information and the write length information.

[0019] Optionally, in the above scheme, the configuration Flash chip is an SPI NOR Flash; the configuration data is stored in a predetermined storage area of ​​the configuration Flash chip.

[0020] Optionally, in the above scheme, the MCU performs an erase operation on the predetermined storage area before writing to the configuration Flash chip; the writing includes writing by page or writing by sector.

[0021] Optionally, after the MCU completes writing to the configuration Flash chip, it reads a portion of the data in the configuration Flash chip and performs verification; the verification includes verification based on checksum and / or verification based on cyclic redundancy check (CRC).

[0022] Optionally, in the above scheme, the MCU is used to output a control signal during the writing of the configuration Flash chip to put the FPGA in a reset state and / or to put the configuration SPI interface of the FPGA in a state that prohibits access to the configuration Flash chip.

[0023] In a second aspect, a method for online upgrade of FPGA chip logic configuration is provided, characterized in that it is applied to the online upgrade circuit for FPGA chip logic configuration as described in the first aspect, the method comprising:

[0024] The MCU receives configuration data and upgrade commands sent by the external host via the USB interface through the serial communication interface;

[0025] The MCU controls the analog switch chip to select the first input channel according to the upgrade instruction, so that the MCU's SPI interface is connected to the configuration Flash chip;

[0026] The MCU erases the configuration Flash chip and writes the configuration data through the SPI interface;

[0027] The MCU controls the analog switch chip to select the second input channel, enabling the FPGA's configuration SPI interface to connect with the configuration Flash chip, so that the FPGA can read the configuration data from the configuration Flash chip via the configuration SPI interface for configuration loading.

[0028] Compared with the prior art, this application has at least the following beneficial effects:

[0029] Based on further analysis and research of existing technical problems, this application recognizes that existing technologies for configuring and upgrading FPGA chips in servo drives suffer from several issues. Firstly, on-site upgrades require disassembly and JTAG operation, leading to high maintenance costs. Secondly, online upgrades are susceptible to power outages, resulting in upgrade failures and difficulties in resetting and restarting. This application addresses these problems by sending configuration data and upgrade commands to a USB-to-serial chip via a USB interface. The USB-to-serial chip converts the USB data into serial data, which is then received by the MCU's serial communication interface. Therefore, a communication path between the external host and the MCU can be established without needing to expose a JTAG port externally. Upon receiving the upgrade command, the MCU uses its input signal, along with the analog switch chip's selection signal, to... The connection relationship output strobe signal enables the analog switch chip to select between the first input channel and the second input channel. When the first input channel is selected, the SPI interface pin of the configuration Flash chip is switched to connect with the SPI interface of the MCU, so that the configuration data can be written by the MCU to the configuration Flash chip via SPI to complete the online update without disassembling the device and connecting a dedicated programmer to program the JTAG port. When the second input channel is selected, the SPI interface pin of the configuration Flash chip is switched to connect with the configuration SPI interface of the FPGA, so that the FPGA can read the configuration data from the configuration Flash chip and load the configuration to enter the user working state.

[0030] Therefore, this solution shifts the upgrade writing process from the traditional factory programming method that relies on JTAG to a field-oriented USB online writing path by using a "USB-to-MCU communication link and MCU-controlled SPI master switching mechanism". At the same time, it achieves hardware isolation and switching between the writing path and the loading path through an analog switch, so that the configuration Flash is written by the MCU during the upgrade phase and read and loaded by the FPGA during the operation phase. This provides a corresponding solution to the problems in the background technology that field upgrades require disassembly and opening of the device and rely on JTAG, as well as the high cost of batch upgrade maintenance. Attached Figure Description

[0031] Figure 1 This is a schematic block diagram of an online upgrade circuit for FPGA chip logic configuration provided in one embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] In one embodiment, such as Figure 1 As shown, an online upgrade circuit for FPGA chip logic configuration is provided. The circuit includes a USB interface, a USB to serial port chip, a microcontroller (MCU), an analog switch chip, and a configuration Flash chip.

[0034] The USB interface is connected to the USB end of the USB-to-serial chip, and the serial end of the USB-to-serial chip is connected to the serial communication interface of the MCU.

[0035] The analog switch chip has a first input channel, a second input channel, and an output channel. The first input channel is connected to the SPI interface of the MCU, the second input channel is connected to the configuration SPI interface of the FPGA, and the output channel is connected to the SPI interface pin of the configuration Flash chip.

[0036] The analog switch chip also has a gating signal input terminal, which is connected to the MCU.

[0037] The MCU is used to receive configuration data and upgrade instructions sent by an external host through the USB interface via the serial communication interface, and control the strobe signal according to the upgrade instructions so that when the analog switch chip selects the first input channel, the MCU writes to the configuration Flash chip through the SPI interface; when the analog switch chip selects the second input channel, the FPGA reads the configuration data from the configuration Flash chip through the configuration SPI interface for configuration loading.

[0038] In one embodiment, the FPGA chip logic configuration online upgrade circuit is located on the servo driver or control board. The circuit includes a USB interface, a USB-to-serial chip, a microcontroller (MCU), an analog switch chip, and a configuration Flash chip. An external host (such as an industrial computer or maintenance laptop) connects to the USB interface via a USB cable to issue upgrade commands and configuration data.

[0039] The USB-to-serial chip has its USB end connected to the USB interface and its serial end connected to the serial communication interface of the MCU. The USB-to-serial chip can convert USB protocol data into serial data frames (such as UART / SCI) and send upgrade commands and configuration data sent by the external host to the MCU serially; conversely, it can also convert information returned by the MCU (such as handshake, progress, and verification results) into USB-side data for display or recording by the external host.

[0040] The analog switch chip has at least a first input channel, a second input channel, and an output channel. The first input channel is connected to the SPI interface of the MCU, the second input channel is connected to the configuration SPI interface of the external FPGA, and the output channel is connected to the SPI interface pin of the configuration Flash chip. The strobe signal input terminal of the analog switch chip is connected to the control pin (e.g., GPIO) of the MCU. The MCU controls the analog switch to switch between the first input channel and the second input channel by outputting the strobe signal, thereby realizing the switching between the two connection relationships of the configuration Flash chip "accessed by MCU" and "accessed by FPGA".

[0041] In upgrade mode, the external host sends upgrade commands and configuration data via USB interface. The MCU receives these via serial communication interface and, according to the upgrade command, controls the strobe signal to cause the analog switch chip to select the first input channel. At this time, the MCU performs erase and program operations on the configuration Flash chip via its SPI interface, writing the configuration data to the target area of ​​the configuration Flash chip. In non-upgrade mode (e.g., normal power-on operation), the MCU controls the strobe signal to cause the analog switch chip to select the second input channel, connecting the FPGA configuration SPI interface to the configuration Flash chip. The FPGA reads the configuration data from the configuration Flash chip and completes configuration loading upon power-on or reset.

[0042] To ensure stable bus timing during writing, the MCU can use fixed SPI mode parameters (such as CPOL / CPHA mode, clock frequency, and chip select timing) when writing to Flash, and employ packet buffering and flow control strategies (such as receiving data in fixed block lengths and receiving confirmation acknowledgments after writing) when receiving configuration data, in order to adapt to different external host transmission rates and device resource constraints.

[0043] This embodiment uses an MCU to control an analog switch to switch the SPI access master terminal of the configuration Flash, so that the configuration Flash is written by the MCU during upgrades and read and loaded by the FPGA during operation. This realizes the switching of configuration data writing and configuration loading paths using the USB interface, meeting the requirements of on-site online upgrades.

[0044] In this embodiment, the SPI interface pins of the configured Flash chip include a chip select signal CS, a serial clock signal SCLK, a master output / slave input signal MOSI, and a master input / slave output signal MISO.

[0045] The analog switch chip sets corresponding switching paths for CS, SCLK, MOSI and MISO to select between the first input channel and the second input channel.

[0046] In one embodiment, the SPI interface pins of the configured Flash chip include a chip select signal CS, a serial clock signal SCLK, a master-to-slave input signal MOSI, and a master-to-slave output signal MISO. The analog switch chip sets corresponding switching paths for each of these signals: when the first input channel is activated, the CS / SCLK / MOSI / MISO pins on the MCU side are connected to the corresponding pins of the configured Flash chip; when the second input channel is activated, the CS / SCLK / MOSI / MISO pins on the FPGA side are connected to the corresponding pins of the configured Flash chip.

[0047] To avoid signal interference, the switching path can adopt a "one signal, one switch" structure, that is, each SPI signal line is provided with an independent analog switch channel or multiplexed channel. For the MISO signal, since it is a direction signal from device output to master device input, it can be ensured on the output channel side that it only connects to the currently selected master device side; the unselected side maintains high impedance isolation, thereby avoiding bus conflicts.

[0048] In terms of circuit implementation, analog switch chips can be selected from multiple analog switch arrays or SPI dedicated multiplexing devices. When the SPI operating frequency is high, the wiring on edge-sensitive signal lines such as SCLK and MOSI can be short and the impedance continuous. If necessary, series resistors or terminations can be added to improve signal integrity.

[0049] This embodiment sets switching paths for CS, SCLK, MOSI, and MISO respectively, so that the SPI signal for configuring Flash is clearly switched between the MCU side and the FPGA side, reducing the risk of competition and crosstalk caused by signal sharing, and ensuring that the interface connectivity between upgrade writing and configuration reading is clear and controllable.

[0050] In this embodiment, the serial communication interface of the MCU is a UART interface or an SCI interface;

[0051] The USB-to-serial chip is used to convert USB data from the USB interface into serial data that matches the UART interface or SCI interface.

[0052] In one embodiment, the MCU's serial communication interface uses a UART or SCI interface, and the USB-to-serial chip converts USB-side data into serial data frames recognizable by UART / SCI. An external host can establish a connection with the device via a virtual serial port through host computer software and send upgrade commands and configuration data according to a pre-agreed upgrade protocol.

[0053] A serial data frame can contain a frame header, command word, address field, length field, data field, and checksum field (e.g., CRC16 / CRC32 or simple checksum). After receiving the data, the MCU first performs frame verification, then parses the command word and executes the corresponding action. To accommodate larger configuration data volumes, serial communication can use packet transmission: the external host sends data blocks in fixed packet lengths, and the MCU verifies each packet and sends back an acknowledgment; if verification fails, it requests a retransmission to ensure transmission reliability.

[0054] For baud rate settings, commonly used baud rates (such as 115200, 921600, etc.) can be selected based on hardware capabilities, and flow control strategies can be used to prevent MCU buffer overflow. USB-to-serial chips can be selected that support stable baud rates and low latency to meet the continuous data stream transmission requirements during upgrades.

[0055] This embodiment uses a USB-to-serial chip in conjunction with the MCU serial communication interface to enable an external host to stably send upgrade commands and configuration data to the device via USB, facilitating the completion of the online upgrade data communication link without adding an extra dedicated interface.

[0056] In this embodiment, the analog switch chip is a 2-to-1 multiplexer or a multi-channel analog switch device.

[0057] The strobe signal input terminal receives the GPIO control signal output by the MCU to control the selection state of the first input channel and the second input channel.

[0058] In one embodiment, the analog switch chip employs a 2-to-1 multiplexer or a multiplexed analog switch device. Its selection signal input is driven by a GPIO control signal output from the MCU; the high / low level of the GPIO corresponds to the selection of the first or second input channel. Before entering the upgrade process, the MCU sets the GPIO to the upgrade channel level, and after the upgrade is complete, it sets it to the running channel level.

[0059] To prevent uncertain states at the moment of power-on, GPIO can be initialized to a definite level as soon as possible after the MCU is reset and released; alternatively, the strobe signal can be set to a default state through pull-up / pull-down resistors, so that the analog switch remains on a predetermined channel (e.g., maintaining the FPGA read channel) when the MCU is not started or is abnormally reset, in order to avoid abnormal startup caused by uncertain Flash connection relationships.

[0060] In terms of hardware selection, an analog switch array with a sufficient number of channels can be chosen based on the number of SPI signals, while also meeting the requirements for signal bandwidth and on-resistance. For higher-frequency SPI applications, devices with low on-resistance and low parasitic capacitance should be prioritized to reduce waveform distortion.

[0061] This embodiment uses MCU to output GPIO control signals to drive the analog switch selection state, thereby realizing direct hardware switching control of the configuration Flash access path, and making the path switching between upgrade state and running state explicitly managed by programmable logic.

[0062] In this embodiment, the upgrade instruction includes: an instruction to enter upgrade mode, writing start address information, and writing length information;

[0063] The MCU controls the analog switch chip to select the first input channel according to the enter upgrade mode instruction, and writes to the configuration Flash chip according to the write start address information and the write length information.

[0064] In one embodiment, the upgrade instruction includes an entry into upgrade mode instruction, write start address information, and write length information. Before sending configuration data, the external host first sends an entry into upgrade mode instruction to trigger the MCU to enter the upgrade process; after the MCU parses the entry into upgrade mode instruction, it controls the analog switch to select the first input channel, enabling the MCU's SPI interface to connect with the configuration Flash.

[0065] The write start address information indicates the starting offset address of the write area in the configuration Flash; the write length information indicates the total data length written this time. After receiving the address and length, the MCU can check the validity of the parameters, such as whether the start address and length fall within the predetermined storage area, whether they are page-aligned / sector-aligned, and whether they exceed the Flash capacity boundary; after the check passes, the MCU writes the configuration data in address order.

[0066] During data transmission, the external host can send data in the form of "command frame + data frame": the command frame carries the address and length, and the data frame carries the actual configuration data block and block verification; the MCU can send back an acknowledgment frame after writing a data block, and the external host can decide whether to continue sending the next block or retransmit the current block, thereby completing the complete writing process.

[0067] This embodiment structures the upgrade command into entering upgrade mode, writing start address and writing length, enabling the MCU to perform write operations according to clear write boundaries and target areas, which facilitates controllable data writing process management in online upgrades.

[0068] In this embodiment, the configuration Flash chip is an SPI NOR Flash; the configuration data is stored in a predetermined storage area of ​​the configuration Flash chip.

[0069] In one embodiment, the configuration Flash chip is an SPI NOR Flash with sector / block erasure and page programming capabilities. The configuration data is stored in a predetermined storage area of ​​the configuration Flash, which can be fixed during product design. For example, it may occupy several sectors consecutively starting from a certain base address of the Flash to store FPGA-recognizable configuration data.

[0070] During the upgrade write, the MCU writes the configuration data to the predetermined storage area; during the configuration loading phase, the FPGA reads the configuration data from the predetermined storage area. To facilitate compatibility with Flash memory of different capacities, the starting address and length of the predetermined storage area can be stored as fixed parameters in the MCU firmware, or issued by an external host via an upgrade command and verified by the MCU.

[0071] To avoid accidentally writing to other data areas of the system (such as parameter area, log area, boot area), the designated storage area can be logically isolated from other storage areas, and an address range check can be added on the MCU side to ensure that writing only occurs in the designated area.

[0072] This embodiment defines the configuration Flash as SPI NOR Flash and sets a predetermined storage area, making the storage location of the configuration data clear. This facilitates the MCU to erase and write according to a fixed area, and also facilitates the FPGA to read the configuration data according to the predetermined area.

[0073] In this embodiment, the MCU performs an erase operation on the predetermined storage area before writing to the configuration Flash chip; the writing includes page-by-page writing or sector-by-sector writing.

[0074] In one embodiment, the MCU performs an erase operation on a predetermined storage area before writing to the configuration Flash. The erase operation can be performed by sector or by block: the MCU calculates the range of sectors / blocks to be covered based on the starting address and the write length, sequentially sends erase instructions (such as Sector Erase or Block Erase) to the SPI NOR Flash, and polls the status register to confirm that the erase is complete before entering the write stage.

[0075] The write phase can adopt a "page-by-page write" method: the MCU divides the configuration data into Flash page sizes (e.g., 256 bytes per page), and repeatedly executes write enable, page programming, and write completion polling operations until the write length is completed. For the "sector-by-sector write" implementation, it can be understood as organizing and submitting data in units of sectors: the external host distributes data in sector blocks, and the MCU first erases each sector and then sequentially writes all pages within that sector, thus achieving a sector-based data write process.

[0076] To improve write reliability, the MCU can read the status register after each page is written to determine whether the write was successful; if a write error is detected, the write can be retried or an error code can be reported to the external host.

[0077] This embodiment performs a predetermined storage area erase before writing and adopts a write process that organizes writing by page or by sector, so that the configuration Flash meets the SPI NOR Flash erase and write timing requirements, which facilitates the formation of a repeatable and controllable online write implementation.

[0078] In this embodiment, after the MCU completes writing to the configuration Flash chip, it reads a portion of the data in the configuration Flash chip and performs verification; the verification includes verification based on checksum and / or verification based on cyclic redundancy check (CRC).

[0079] In one embodiment, after completing the writing to the configuration Flash, the MCU reads a portion of the data from the configuration Flash and performs verification. The "partial data" may be: the beginning and end segments of each data block, data sampled at fixed intervals, or data containing key verification areas; it may also be extended to reading the full data for comparison if resources permit.

[0080] Verification methods may include checksum-based verification and / or CRC-based verification. When sending configuration data, the external host can simultaneously send a global checksum (e.g., CRC32) or a block checksum. After the MCU completes the write operation, it recalculates the checksum value for the corresponding data in the Flash memory and compares it with the checksum sent by the external host. If the verification fails, the MCU can send an error status back to the external host and request a retransmission of the relevant data block, or re-execute the erase and write process.

[0081] In terms of implementation, the MCU can reduce computational overhead by accumulating CRC while writing, and then sampling and reading the Flash for verification after writing is completed; or it can use the "write-after-read verification" method to compare each page / block in real time so that errors can be located as early as possible.

[0082] This embodiment improves the verifiability of configuration data after it is written by reading back part of the data and using a checksum or CRC for consistency verification, thus giving the online upgrade process a clear data integrity check step.

[0083] In this embodiment, the MCU is used to output control signals during the writing of the configuration Flash chip to put the FPGA in a reset state and / or to put the configuration SPI interface of the FPGA in a state that prohibits access to the configuration Flash chip.

[0084] In one embodiment, the MCU outputs a control signal during the configuration Flash write to reset the FPGA. Specifically, one of the MCU's GPIO pins is connected to the FPGA's reset pin (or connected via a reset control circuit). When the MCU enters the upgrade write phase and switches the analog switch to the first input channel, it sets this GPIO to a valid reset level, keeping the FPGA in a reset state, thus preventing the FPGA from driving its configuration SPI interface signal during the write process.

[0085] In another alternative embodiment, in addition to resetting the FPGA, "access denied" can also be achieved through hardware isolation. For example, a tri-state buffer / bus transceiver can be set between the FPGA's configuration SPI interface and the analog switch chip. During the write operation, the MCU outputs an enable control signal to disable the buffer, making the FPGA-side SPI signal high-impedance. Alternatively, the FPGA-side chip select signal CS can be gated (e.g., using AND / OR gate logic) to force the FPGA chip select to a non-gated level during the upgrade, thereby preventing the FPGA from accessing the Flash.

[0086] The above "reset state" and / or "access denied state" can be used alone or in combination: at the start of the upgrade, first reset the FPGA and turn off the FPGA-side isolator, then switch the analog switch to the MCU side to write; after writing is completed, restore the isolator enable and release the FPGA reset, then switch the analog switch to the FPGA side to allow it to read configuration data subsequently.

[0087] This embodiment applies a reset control to the FPGA during the writing process by the MCU and / or implements hardware isolation / chip select gating on the FPGA configuration SPI interface, so that the FPGA side does not access the configuration Flash during the writing process, reducing the possibility of Flash bus contention and access conflicts, and ensuring that the writing operation is completed as expected.

[0088] This embodiment establishes an FPGA online upgrade circuit. Users can physically connect to the FPGA upgrade circuit via the panel USB communication interface, avoiding the need to open the servo driver cover and use JTAG for FPGA configuration upgrades. Users can directly download the configuration file to the FPGA configuration FLASH through the host computer operation interface of the panel communication interface. The FPGA configuration FLASH can switch between external interface programming and FPGA configuration programming states, thereby enabling online upgrade operations of the FPGA configuration FLASH via the servo driver panel USB interface.

[0089] In summary, if the online upgrade process fails due to accidental power loss, freezing, or other reasons, the program can be rewritten after a reset. This will prevent situations where the FPGA cannot be reset and becomes bricked.

[0090] The online upgrade circuit of the servo driver FPGA goes through the panel USB interface, the USB to serial port chip, the MCU, the analog switch chip, and finally to the FPGA configuration FLASH chip.

[0091] The USB port is connected to the input terminal of the USB-to-serial chip;

[0092] The output SCI signal of the USB to serial port chip is connected to the SCI pin of the MCU;

[0093] The MCU's SPI is connected to the first input channel of the analog switch chip;

[0094] The selection switch signal of the analog switch chip is connected to the MCU;

[0095] The first input channel of the analog switch chip is connected to the SPI pin of the MCU;

[0096] The second input channel of the analog switch chip is connected to the FPGA's configuration SPI;

[0097] The output channel of the analog switch chip is connected to the SPI pin of the FPGA's configuration FLASH chip.

[0098] The servo drive's FPGA configuration online upgrade function allows users to perform on-site online FPGA configuration upgrades by connecting a computer's USB cable to the servo drive panel. The host computer software then transmits the prepared FPGA configuration file and upgrade instructions to the USB-to-serial chip via the USB port. The configuration file is then transmitted to the MCU via serial communication. The MCU triggers the analog switch chip at the back end to change the SPI connection of the FPGA configuration FLASH to the first input channel of the analog switch and connect it to the MCU. Finally, the configuration file in the FLASH is configured for online upgrade.

[0099] After the upgrade is completed, the MCU configures the analog switch's strobe signal as an output signal and connects it to the second input channel. The FPGA is then restarted to reload the configuration file in the FLASH, completing the FPGA configuration upgrade.

[0100] In this embodiment, users can perform online upgrades of FPGAs in industrial settings without opening the driver; the existing USB debugging interface is used without increasing interface costs; no additional upgrade logic needs to be configured in the FPGA, and the upgrade operation does not rely on the FPGA itself, thus avoiding the problem of power-off upgrade failure and inability to reset during the FPGA upgrade process.

[0101] In this embodiment, the servo driver's USB-to-serial converter connects to the MCU. The MCU uses an SPI interface and configuration FLASH to establish a hardware communication link between the host computer software and the configuration FLASH. The MCU controls the path of the FPGA configuration FLASH SPI communication. The MCU controls the selection signal of the analog switch chip to achieve SPI communication connection between the configuration FLASH and the FPGA for online upgrade operations. The MCU also controls the selection signal of the analog switch chip to achieve SPI communication between the configuration FLASH and the FPGA configuration SPI pin. When the FPGA is working normally, it automatically enters the configuration process: the internal configuration controller reads the data in the FLASH, configures the SRAM, and after configuration, the FPGA enters user mode and begins operation.

[0102] In one embodiment, an online upgrade method for FPGA chip logic configuration is provided, characterized in that it is applied to the online upgrade circuit for FPGA chip logic configuration, and the method includes:

[0103] The MCU receives configuration data and upgrade commands sent by the external host via the USB interface through the serial communication interface;

[0104] The MCU controls the analog switch chip to select the first input channel according to the upgrade instruction, so that the MCU's SPI interface is connected to the configuration Flash chip;

[0105] The MCU erases the configuration Flash chip and writes the configuration data through the SPI interface;

[0106] The MCU controls the analog switch chip to select the second input channel, enabling the FPGA's configuration SPI interface to connect with the configuration Flash chip, so that the FPGA can read the configuration data from the configuration Flash chip via the configuration SPI interface for configuration loading.

[0107] In one embodiment, the online upgrade method is applied to the online upgrade circuit described in the above embodiment. The external host runs the upgrade tool, establishes a communication connection with the device via a USB interface, and sends upgrade commands and configuration data to the MCU. The MCU receives and parses the upgrade commands via a serial communication interface and enters the upgrade process.

[0108] During the switching process, the MCU controls the analog switch chip to select the first input channel according to the upgrade instruction, enabling the MCU's SPI interface to connect with the configuration Flash. Subsequently, the MCU erases the configuration Flash and writes the configuration data: the erasure range is determined by the write start address and write length; writing can be performed page-by-page or block-by-block, and status polling and error handling mechanisms can be used in conjunction with the writing process.

[0109] After writing is complete, the MCU controls the analog switch chip to select the second input channel, enabling the FPGA's configuration SPI interface to connect with the configuration Flash, so that the FPGA can read configuration data from the configuration Flash for configuration loading. To adapt to different hardware platforms, the FPGA's "read and configuration loading" in this embodiment can be triggered in the following ways: the device is powered on again to trigger the FPGA configuration process, or the MCU / external host triggers a reset operation on the FPGA to cause it to re-enter the configuration read process; the above triggering methods can be used as optional steps in specific implementations.

[0110] In the implementation of the method, a verification step can be added after writing and the verification result can be sent back to the external host to determine whether to end the upgrade or perform a retransmission / rewrite operation to complete the closed-loop upgrade process.

[0111] This embodiment achieves an online upgrade process by having the configuration data written from an external host to the configuration Flash via a USB link and then read and loaded by the FPGA through a process of "receiving upgrade instructions and configuration data, switching to the MCU channel, erasing and writing, switching back to the FPGA channel, and FPGA reading and loading the configuration data". This forms a repeatable upgrade operation step.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. An online logic configuration upgrade circuit for an FPGA chip, characterized in that, The circuit includes a USB interface, a USB-to-serial chip, a microcontroller (MCU), an analog switch chip, and a configuration Flash chip. The USB interface is connected to the USB end of the USB-to-serial chip, and the serial end of the USB-to-serial chip is connected to the serial communication interface of the MCU. The analog switch chip has a first input channel, a second input channel, and an output channel. The first input channel is connected to the SPI interface of the MCU, the second input channel is connected to the configuration SPI interface of the FPGA, and the output channel is connected to the SPI interface pin of the configuration Flash chip. The analog switch chip also has a gating signal input terminal, which is connected to the MCU. The MCU is used to receive configuration data and upgrade instructions sent by an external host through the USB interface via the serial communication interface, and control the strobe signal according to the upgrade instructions so that when the analog switch chip selects the first input channel, the MCU writes to the configuration Flash chip through the SPI interface; when the analog switch chip selects the second input channel, the FPGA reads the configuration data from the configuration Flash chip through the configuration SPI interface for configuration loading.

2. The circuit according to claim 1, characterized in that, The SPI interface pins configured for the Flash chip include a chip select signal CS, a serial clock signal SCLK, a master output / slave input signal MOSI, and a master input / slave output signal MISO. The analog switch chip sets corresponding switching paths for CS, SCLK, MOSI and MISO to select between the first input channel and the second input channel.

3. The circuit according to claim 1, characterized in that, The serial communication interface of the MCU is either a UART interface or an SCI interface. The USB-to-serial chip is used to convert USB data from the USB interface into serial data that matches the UART interface or SCI interface.

4. The circuit according to claim 1, characterized in that, The analog switch chip is a 2-to-1 multiplexer or a multi-channel analog switch device; The strobe signal input terminal receives the GPIO control signal output by the MCU to control the selection state of the first input channel and the second input channel.

5. The circuit according to claim 1, characterized in that, The upgrade instructions include: an instruction to enter upgrade mode, write start address information, and write length information; The MCU controls the analog switch chip to select the first input channel according to the enter upgrade mode instruction, and writes to the configuration Flash chip according to the write start address information and the write length information.

6. The circuit according to claim 1, characterized in that, The configuration Flash chip is an SPI NOR Flash; the configuration data is stored in a predetermined storage area of ​​the configuration Flash chip.

7. The circuit according to claim 6, characterized in that, Before writing to the configured Flash chip, the MCU performs an erase operation on the predetermined storage area; the writing includes writing by page or writing by sector.

8. The circuit according to claim 1, characterized in that, After completing the writing to the configuration Flash chip, the MCU reads a portion of the data in the configuration Flash chip and performs verification; the verification includes verification based on checksum and / or verification based on cyclic redundancy check (CRC).

9. The circuit according to claim 1, characterized in that, The MCU is used to output control signals during the writing of the configuration Flash chip to put the FPGA in a reset state and / or to put the FPGA's configuration SPI interface in a state that prohibits access to the configuration Flash chip.

10. A method for online upgrade of FPGA chip logic configuration, characterized in that, The method, applied to the FPGA chip logic configuration online upgrade circuit as described in any one of claims 1 to 9, comprises: The MCU receives configuration data and upgrade commands sent by the external host via the USB interface through the serial communication interface; The MCU controls the analog switch chip to select the first input channel according to the upgrade instruction, so that the MCU's SPI interface is connected to the configuration Flash chip; The MCU erases the configuration Flash chip and writes the configuration data through the SPI interface; The MCU controls the analog switch chip to select the second input channel, enabling the FPGA's configuration SPI interface to connect with the configuration Flash chip, so that the FPGA can read the configuration data from the configuration Flash chip via the configuration SPI interface for configuration loading.

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