Simulation, storage and calculation integrated circuit based on magnetic tunnel junction array and calculation method

Abstract

The invention discloses an analog storage and calculation integrated circuit based on a magnetic tunnel junction array and a calculation method, and belongs to the field of storage and calculation integration. The analog storage and calculation integrated circuit comprises a plurality of basic processing units (Xbrp), a buffer (Buffer), a multiplexer and an analog-to-digital converter (ADC); the core of each Xbrp is a 1T1MTJ storage array, the resistance states of the MTJs of the front part and the rear part of each Xbrp storage array correspond to the positive weight and the negative weight respectively, and a read-write circuit and an analog calculation circuit are integrated; when the analog calculation circuit performs calculation enabling, the resistance states of the selected multiple rows of MTJs are converted into analog currents related to the proportion of high and low resistance states in the rows of MTJs in parallel, and analog voltages representing vector dot product operation results are output; after the analog voltage is gated through the buffer and the multiplexer, the ADC differentially quantizes the difference value of the positive weight voltage and the negative weight voltage, and a digital calculation result is directly obtained. According to the method, the calculation of the data in the storage unit is realized, the data handling is greatly reduced, and the energy efficiency and throughput of neural network reasoning are improved.

Description

Technical Field

[0001] This invention belongs to the field of in-memory computing, and more specifically, relates to an analog in-memory computing circuit and computing method based on a magnetic tunnel junction array. Background Technology

[0002] With the rapid development of artificial intelligence computing, especially deep neural network processing, the memory wall problem of traditional computing architectures has become increasingly prominent. In the von Neumann architecture, the separation of the processor and memory leads to huge energy and time overhead when performing large-scale vector-matrix multiplications, due to the frequent transfer of massive weights between the processor and memory, which severely restricts the improvement of energy efficiency and computing power.

[0003] To address this challenge, in-memory computing technology has become a research focus, its core being the integration of computing functions into storage units. Among existing technologies, SRAM-based solutions, while fast, suffer from low density and high static power consumption; while solutions based on non-volatile memories such as RRAM or Flash have limitations in terms of reliability and durability. Magnetic random access memory (MRAM), with its advantages of non-volatility, high durability, and compatibility with CMOS processes, demonstrates enormous potential.

[0004] However, some existing in-memory computing designs can only implement simple Boolean logic operations, or they generate huge energy consumption due to a large number of digital operations, making them unable to efficiently support the core multiply-accumulate operations of neural networks. Others attempt analog computing, but mostly adopt a read-first, process-later architecture, that is, the magnetic tunnel junction (MTJ) resistance state must first be converted into an analog signal through external circuitry before being transmitted to a separate computing module for processing. This approach fails to achieve true in-situ computing, introduces additional power consumption and area overhead, and is also prone to accuracy loss during signal transmission and conversion, limiting the improvement of computational parallelism and energy efficiency.

[0005] Therefore, there is an urgent need for an innovative MRAM in-memory computing solution that can directly utilize analog characteristics within the storage array to perform high-parallel multiplication and addition operations and achieve efficient differential quantization of positive and negative weights, thereby fundamentally overcoming data transfer bottlenecks and meeting the urgent needs of edge intelligent devices for high-energy-efficiency and high-throughput computing. Summary of the Invention

[0006] To address the shortcomings and improvement needs of existing technologies, this invention provides an analog-in-memory computing circuit and computing method based on a magnetic tunnel junction array. Its purpose is to directly utilize the analog characteristics within the memory array to perform high-parallel multiplication and addition operations, effectively improving energy efficiency and throughput.

[0007] To achieve the above objectives, according to one aspect of the present invention, an analog-to-in-memory computing circuit based on a magnetic tunnel junction array is provided, comprising: OK The basic processing unit array of the column, A buffer, Multiplexer and One analog-to-digital converter; The basic processing unit includes: OK Array of magnetic tunnel junctions and One simulation calculation module; in the magnetic tunnel junction array, the front The resistance of the magnetic tunnel junction corresponds to the positive weight, and then... The resistance of the magnetic tunnel junction corresponds to the negative weight, and the first... Magnetic tunnel junction and the first The resistance values ​​of the magnetic tunnel junctions are complementary; Each simulation module is connected to the magnetic tunnel junction array. The unit lines are connected; after the calculation is started, the word lines in the magnetic tunnel junction array are... Vie Signal vector activation, complete The calculation involves multiplying the signal vector with the resistance matrix stored in the magnetic tunnel junction array; the analog calculation module converts the calculation results of the corresponding bit lines into analog voltages. ; ; No. The first basic processing unit and the first Each buffer is connected to the next; after computation begins, the selected basic processing unit outputs... The analog voltage is sampled and held in the buffer to which it is connected; For natural numbers, ; Multiplexer is Select 1 multiplexer; each buffer has The output signals of the paths are respectively with There are 10 multiplexers; every two adjacent multiplexers are grouped together to obtain 100 multiplexers. Group multiplexer, number The two multiplexers in the group are used to connect to the second... Series analog voltage and the first Series of analog voltages; the first The two differential inputs of the analog-to-digital converter are respectively connected to the first... The two outputs of the group multiplexer are connected to complete the quantization of the corresponding calculation results; in, , , and All are positive integers.

[0008] Furthermore, the analog computing module includes: an operational amplifier, a current mirror unit, and a computing resistor; An operational amplifier whose negative input terminal is connected to a reference voltage. Its output terminal is connected to the control terminal of the current mirror unit; The current mirror unit has its input branch connected to the corresponding bit line in the magnetic tunnel junction array, and its output branch connected to one end of the calculated resistor. The analog voltage generated across the resistor is proportional to the conductance of the selected magnetic tunnel junction on the corresponding bit line. .

[0009] Furthermore, the analog in-memory computing circuit based on magnetic tunnel junction array provided by the present invention further includes a read module and a write module in its basic processing unit; The read module is used to read the resistance state of the magnetic tunnel junctions in the magnetic tunnel junction array and convert it into a digital signal; The write module is used to set and reset the magnetic tunnel junctions in the magnetic tunnel junction array.

[0010] Furthermore, the read module includes a digitally adjustable reference resistor network, the overall resistance of which is adjustable; for the same magnetic tunnel junction, different overall resistance values ​​of the reference resistor network result in different digital signals converted by the read module. Furthermore, the calculated resistance can be digitally adjusted; Furthermore, the combination of the resistance values ​​of the reference resistor network and the calculation resistor in the reading module was determined through simulation verification. During the simulation verification process, the goal was to maximize the compensation for changes in the resistance characteristics of the magnetic tunnel junction and the deviation of CMOS device parameters, as well as to minimize the fluctuation range of the calculation gain.

[0011] Furthermore, the buffer includes: 64 time-division multiplexed source followers to reduce area overhead.

[0012] Furthermore, the analog-to-digital converter is a SAR ADC.

[0013] Furthermore, the analog-to-in-memory computing circuit based on magnetic tunnel junction array provided by the present invention also includes: a timing control module; the timing control module is connected to each analog computing module, buffer, multiplexer and analog-to-digital converter; the timing control module is used to generate control signals, including computing enable signal, sample and hold signal, multiplexer address and analog-to-digital converter clock.

[0014] Furthermore, the timing control module of the analog in-memory computing circuit based on magnetic tunnel junction array provided by the present invention is also used to control the calculation and quantization operations to be executed in a pipeline manner. The pipeline includes: while performing a quantization operation on the calculation result of the previous basic processing unit, starting the calculation process of the next basic processing unit, and sampling and storing the calculation result in the corresponding buffer.

[0015] Furthermore, the magnetic tunnel junction array is a 1T1MTJ array.

[0016] According to another aspect of the present invention, a computing method based on the above-described analog in-memory computing circuit is provided, comprising: Set the resistance state of the magnetic tunnel junctions in each magnetic tunnel junction array, so that in each magnetic tunnel junction array, the front The resistance of the magnetic tunnel junction corresponds to the positive weight, and then... The resistance of the magnetic tunnel junction corresponds to the negative weight, and the first... Magnetic tunnel junction and the first The resistance values ​​of the magnetic tunnel junctions are complementary; All are positive integers. ; The target basic processing unit is selected by address signal, based on Vie The signal vector activates the word line in the target basic unit, and after starting the calculation, from... An analog-to-digital converter acquires the quantized calculation results.

[0017] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: (1) This invention utilizes the resistance state of the magnetic tunnel junction in the magnetic tunnel junction array to store the positive and negative weight matrix. The word lines in the magnetic tunnel junction array are activated according to the input vector, so the total current flowing through the selected magnetic tunnel junction can be used to characterize the calculation result of vector-matrix multiplication. Furthermore, this invention utilizes an analog computing module to convert this into an analog voltage signal. On the one hand, the computing function is directly embedded into the storage array, realizing in-situ computation. Moreover, multiple rows of magnetic tunnel junction units can be activated simultaneously within a single clock cycle by setting the input vector, naturally realizing parallel multiplication and addition operations of multiple input vectors and multiple weights. This avoids data transfer between the memory and the processor, improving throughput while reducing power consumption. On the other hand, the relevant calculation process is mainly completed in the analog domain, avoiding the switching power consumption caused by large-scale digital circuits. Overall, this invention directly utilizes analog characteristics within the storage array to complete high-parallel multiplication and addition operations, effectively improving energy efficiency and throughput, and effectively solving the problems of large data transfer overhead and low parallelism of analog computation in the prior art.

[0018] (2) In this invention, the analog calculation module in the basic processing unit specifically includes an operational amplifier, a current mirror unit and a calculation resistor, which maximizes energy utilization efficiency while ensuring calculation accuracy.

[0019] (3) The present invention uses adjustable read reference resistors and calculation resistors to effectively compensate for the impact of process deviations on calculation accuracy. In a further preferred embodiment, the combination of the values ​​of the read reference resistor and the calculation resistor is determined by simulation verification. During the simulation verification process, the goal is to maximize the compensation for changes in the resistance characteristics of the magnetic tunnel junction and the deviation of CMOS device parameters, as well as to minimize the fluctuation range of the calculation gain, thereby further ensuring the calculation accuracy and calculation stability.

[0020] (4) In this invention, the analog-to-digital converter used for quantizing the calculation results adopts differential input to directly quantize the voltage difference between the positive and negative weights, thus avoiding accuracy loss on the analog signal link. At the same time, the calculation accuracy is limited to the quantization accuracy of the analog-to-digital converter, ensuring the accuracy and consistency of the calculation results, which can meet the accuracy requirements of most neural network applications.

[0021] (5) In this invention, the computation and quantization operations of the basic processing unit are executed in a pipeline manner, compressing the original serial computation-quantization cycle into parallel execution, thereby increasing the overall computation throughput of the system by nearly 100%. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of an analog in-memory computing circuit based on a magnetic tunnel junction array, provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of a 1T1MTJ array provided in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the simulation calculation module provided in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of a buffer provided in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of a SAR ADC provided in an embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of a pulse generation circuit provided in an embodiment of the present invention.

[0028] Figure 7 The schematic diagram of the successive approximation logic provided in the embodiment of the present invention.

[0029] Figure 8 The timing diagram of the computational operation provided in the embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0032] To effectively address the problems of high data transfer overhead and low parallelism in analog computation in existing technologies, and to achieve high-energy-efficiency, high-throughput neural network vector-matrix multiplication operations, this invention provides an analog-in-memory computing circuit and computation method based on magnetic tunnel junction arrays. Its core concept lies in constructing an innovative architecture that integrates storage, read / write, and computation functions. This architecture uses a basic processing unit containing a magnetic tunnel junction array as its core. The analog computation module directly converts the resistance state of one or more activated rows of magnetic tunnel junctions into analog voltages representing the results of multiplication-addition operations.

[0033] The analog-to-in-memory computing circuit based on a magnetic tunnel junction array provided by this invention comprises the following core components: multiple parallel basic processing units, which are used to perform data storage, reading and writing, and analog calculations; multiple buffers connected to the output terminals of the basic processing units, which are used to enhance the driving capability of analog signals and implement sample-and-hold functions; a multiplexer array connected to the output terminals of the buffers, which is used to select a specific path from multiple buffered signals; and an analog-to-digital converter array connected to the output terminals of the multiplexers, which is used to convert the final analog calculation results into digital code values; wherein, each basic processing unit performs... The system integrates a 1T1MTJ memory array consisting of multiple one-bit selectors connected in series with a magnetic tunnel junction, a write module responsible for setting and resetting the magnetic tunnel junction, a read module for reading the resistance state of the magnetic tunnel junction and converting it into a digital signal, and a key analog calculation module. Under the control of the calculation enable signal, the analog calculation module can perform parallel summation of the resistance states of the currently selected multiple rows of magnetic tunnel junctions and directly convert them into an analog output voltage that is proportional to the weighted sum of the resistance states of the multiple rows, thereby completing the analog calculation part of the vector dot product operation in situ inside the memory cell.

[0034] During the calculation process, by activating multiple word lines simultaneously, the total current flowing through the selected magnetic tunnel junction accurately reflects the distribution pattern of the storage weights, and the analog voltage output by the simulation calculation module is obtained based on this current.

[0035] In this invention, the voltage generation circuit in the analog computing module employs a high-gain operational amplifier, a precision current mirror structure, and a fixed computing resistor. The specific connections and operating principle are as follows: the negative input terminal of the operational amplifier is connected to a constant reference voltage, and its output terminal is connected to the gate of an NMOS transistor. The source of the NMOS transistor is fed back to the negative input terminal of the operational amplifier, forcing the voltage applied to the 1T1MTJ array to remain stable. Its drain is connected to the current mirror, which replicates the current to the computing resistor. This total current accurately reflects the sum of the conductances of all magnetic tunnel junctions under the simultaneously activated multi-line word lines, representing the digital pattern of the storage weights. This total current is mirrored by the current mirror structure and guided to the computing resistor, generating an analog output voltage proportional to the mirrored current through Ohm's law. This voltage is the output of the analog computing module.

[0036] Multiple basic processing units are spatially organized into an array with a multi-row and multi-column topology to achieve higher computational parallelism. Within the array of basic processing units, the basic processing units in adjacent rows are connected to each buffer, which is responsible for receiving and temporarily storing the computation results of its respective basic processing unit. The multiplexer acts as a configurable signal network, with its input connected to the outputs of all buffers and its output connected to the analog-to-digital converter. By applying an address control signal to the multiplexer, the analog voltage output of any buffer can be dynamically selected and transmitted to the analog-to-digital converter for subsequent quantization.

[0037] The analog-to-digital converter (ADC) employs a successive approximation architecture, with its key design feature being a differential analog input port. The positive terminal of this differential input is configured to receive the analog voltage output from the analog calculation module representing positive weights, while the negative terminal is configured to receive the analog voltage output from the analog calculation module representing negative weights. Through this connection method, the object quantized by the ADC is directly the instantaneous difference between the positive and negative weight voltages, which precisely corresponds to the sum of the positive and negative weights in the neural network calculation. The ADC converts this analog voltage difference into a set of multi-bit digital code values ​​in one step through its internal capacitor-to-analog converter array, comparator, and successive approximation logic, without requiring additional subtraction operations by the digital processing unit.

[0038] The read module integrates a digitally adjustable reference resistor network, which consists of a series of precision resistor units controlled by switches. By receiving externally input multi-bit adjustment control signals, the combination of reference resistors connected to the circuit can be dynamically switched, thereby changing the total resistance value of the reference resistors. This adjustment function enables the read module to adapt to the natural fluctuations in the resistance values ​​of the magnetic tunnel junction in high and low resistance states under different manufacturing processes, as well as the effects of changes in operating voltage and temperature. This ensures that the sensitive amplifier always has sufficient discrimination margin when comparing the magnetic tunnel junction resistance with the reference resistance, guaranteeing the correctness and reliability of the read operation.

[0039] The computational resistor in the analog computing module is implemented as a digitally adjustable resistor array. The resistance value of this resistor array can be precisely adjusted in steps by receiving a multi-bit adjustment control signal from an external input. By adjusting the resistance value of this computational resistor, the voltage conversion gain of the analog computing module can be directly calibrated, that is, the mapping relationship from the magnetic tunnel junction conductance to the output voltage can be adjusted. This calibration mechanism effectively compensates for the changes in circuit characteristics caused by semiconductor manufacturing process deviations, so that the entire analog-in-memory computing circuit can maintain the consistency and accuracy of calculation results across different chips and under different operating environments.

[0040] This invention achieves in-situ parallel computation of data within the storage unit by deeply integrating the simulation computing module with the storage array. It also adopts a pipelined operation strategy for computation and quantization, which effectively solves the data handling bottleneck problem in the traditional architecture and significantly improves the energy efficiency and throughput of neural network computing.

[0041] Based on the analog-in-memory computing circuit provided by this invention, the method for performing vector-matrix multiplication includes a multi-stage operation process organized according to a specific timing sequence: The first stage is the calculation preparation stage, in which the analog computing modules in all basic processing units participating in the calculation are enabled, and sufficient time is reserved for their internal operational amplifiers to reach a stable operating state. The second stage is the analog computing stage, in which calculation word line signals are applied to the selected basic processing units, and multiple rows of memory cells are activated, so that the analog computing modules of each basic processing unit generate analog output voltages representing partial calculation results in parallel and synchronously. The third stage is the sample and hold stage, in which the analog output voltage is quickly sampled and stably held on the input capacitor of the buffer or a specific memory node using control signals. The fourth stage is the quantization output stage, in which the analog voltage held in the buffer is sequentially selected to the analog-to-digital converter by operating the multiplexer in a predetermined order, and the analog-to-digital converter completes the quantization of the positive and negative weighted voltage differences and outputs the final digital result.

[0042] To further improve throughput, this invention also designs a refined pipeline that allows the quantization operation of the calculation result of the previous row of basic processing units to completely overlap with the calculation operation of the next row of basic processing units on the time axis, forming a highly efficient pipeline. This compresses the originally serial calculation-quantization cycle into parallel execution, thereby nearly doubling the overall computational throughput of the system. Specifically, when the quantization output stage has begun but the quantization operation of the first row of basic processing units has not yet been completed, the control signal required for the calculation stage is sent to the next group of basic processing units to be calculated, initiating its simulation calculation process. This timing arrangement allows the simulation calculation of the next row to partially overlap with the quantization conversion of the result of the previous row in time, thereby hiding the settling time required by the simulation calculation module at the system level, effectively improving the overall computational throughput of the macrocell and the utilization rate of hardware resources.

[0043] Without loss of generality, in the following embodiments, the magnetic tunnel junction array is organized in a 1T1MTJ structure, and each memory cell contains a magnetic tunnel junction and a gate transistor.

[0044] The following is an example.

[0045] Example 1: An analog-to-in-memory computing circuit based on a magnetic tunnel junction array, such as Figure 1 As shown, it includes a 4x4 array of basic processing units consisting of 16 basic processing units (hereinafter referred to as Xbrp), as well as 8 buffers, 64 8-to-1 multiplexers (AMUX) and 32 analog-to-digital converters (ADCs).

[0046] like Figure 2 As shown, each Xbrp contains a 1T1MTJ memory array, read / write control circuitry, and analog computing circuitry. The 1T1MTJ array is organized in a 32x64 row format, with each memory cell consisting of an NMOS select transistor and an MTJ device connected in series. Before starting the calculation, the resistance states of the 1T1MTJ cells in the 1T1MTJ array are set according to the weight matrix in the matrix-multiplication calculation. The resistance states of the first 32 columns of 1T1MTJ cells correspond to positive weights, and the resistance states of the last 32 columns correspond to negative weights. Furthermore, in columns with a 32-column difference in index, the resistance states of the 1T1MTJ cells are complementary; that is, column 0 is complementary to column 32, column 1 to column 33, column 2 to column 34, and so on. It is easy to understand that in two 1T1MTJ cells with complementary resistance states, one cell is in a high-resistance state, and the other is in a low-resistance state.

[0047] like Figure 3As shown, in this embodiment, the analog calculation module includes: an operational amplifier, a current mirror unit, and a calculation resistor; the negative input terminal of the operational amplifier is connected to an external reference voltage, and the output terminal is connected to the control terminal of the current mirror unit; the input branch of the current mirror unit is connected to the bit line / source line of the magnetic tunnel junction array, and the output branch is connected to the calculation resistor; the calculation resistor generates an analog output voltage that is proportional to the conductance of the magnetic tunnel junction.

[0048] The read / write control circuit specifically includes a read module and a write module. The read module is used to read the resistance state of the magnetic tunnel junctions in the magnetic tunnel junction array and convert it into a digital signal; the write module is used to set and reset the magnetic tunnel junctions in the magnetic tunnel junction array.

[0049] During the calculation operation, the target Xbrp is first selected using the preset address signal ADR<8:11>, and the calculation enable signal CAL_EN is simultaneously enabled to indicate the start of the calculation. The operational amplifier in the analog calculation module then begins operation, clamping the voltage at its negative input terminal to the reference voltage. After a 180ns stabilization period, the word line selection signal C_WL<0:31> is used to simultaneously activate multiple word lines. At this time, the total current flowing through the selected MTJ... satisfy:

[0050] in, The activated row is in a low-resistance state The number of MTJs In a high-resistivity state The number of MTJs. The word line selection signal C_WL<0:31> also represents the input vector, the resistance state of the MTJs in the magnetic tunnel junction array corresponds to the weight matrix, and the total current flowing through the selected MTJ. This reflects the results of vector-matrix multiplication calculations. The related calculations are performed directly within the magnetic tunnel junction array, representing an in-situ calculation that does not involve the movement of weighted data. Current The current mirror unit in the simulation module accurately mirrors the calculated resistor. , generate output voltage .

[0051] In a magnetic tunnel junction array, each bit line outputs an analog voltage. A total of 64 analog voltage channels were generated. .

[0052] like Figure 1As shown, the 16 Xbrp instances are organized into a 4x4 topology. To improve parallelism, in this embodiment, the computation results of every two rows of Xbrp outputs can be simultaneously stored in 8 buffers, using Xbrp_row. <0> Control signals and Xbrp_row <1> Control signals are used to trigger the first and second rows of Xbrp corresponding to the buffer. Specifically, when Xbrp_row <0> When the control signal is valid, the first line of Xbrp will be triggered, and when Xbrp_row <1> When the control signal is valid, the second line of Xbrp will be triggered. When Xbrp_row <0> The control signal is valid, and Xbrp_clk1 <0> When the signal is valid, the first row of 4 Xbrp outputs generates 64 channels of analog voltage. It is sampled and stored in the corresponding buffer.

[0053] like Figure 4 As shown, in this embodiment, the buffer circuit adopts a source follower structure, including an input sampling switch and a holding capacitor, providing sufficient driving capability and achieving signal isolation. Subsequently, Xbrp_row_adc... <0> In conjunction with the Xbrp_col_adc<0:3> signal, the 8-to-1 multiplexer sequentially selects the 64 analog signals output from the buffer to 32 ADCs. Specifically, As a positive weighted voltage As a negative weighted voltage, in differential form and ( The input is fed into the corresponding ADC.

[0054] It is readily understood that the number of basic processing units, the array configuration of the basic processing units, and the configuration of the magnetic tunnel junction array in this embodiment are merely illustrative examples and should not be construed as the sole limitation of the present invention. In other embodiments of the present invention, the corresponding parameters can also be flexibly set according to actual needs.

[0055] like Figure 5 As shown, in this embodiment, the analog-to-digital converter is a SAR ADC, specifically a 5-bit 200MS / s successive approximation (SAR) architecture. The SAR ADC includes: a sample-and-hold circuit, the input of which is connected to a multiplexer, used to acquire and hold the analog voltage of the in-memory computing result under clock control; A high-precision dynamic comparator is used to successively compare the analog voltage with the feedback voltage; a digital-to-analog converter (DAC) employs a charge-redistribution capacitor array structure, with the total capacitance of the array matched according to a 5-bit resolution, and its output is fed back to the second input of the high-precision dynamic comparator; a successive approximation register and control logic, whose input is connected to the output of the high-precision dynamic comparator, is used to generate and latch the digital code of the current bit based on the result of each comparison, and control the switching of the corresponding capacitor in the DAC; its output outputs the final 5-bit digital result; the operating clock frequency of the successive approximation register and control logic is not less than 200MHz to ensure that the overall 200MHz sampling rate requirement is met within the 5 clock cycles required to complete each conversion.

[0056] The working process of the SAR ADC is as follows: When the ADC_CLK clock is valid, the pulse generation circuit (such as...) Figure 6 As shown, a 1ns sampling pulse CLKS is generated, which samples the differential input voltage onto the capacitor array via a bootstrap switch. After sampling, the asynchronous comparator starts working in the SAR logic circuit (such as...). Figure 7 Under the control of (as shown), five successive comparisons are performed. The result of each comparison is stored through a dynamic logic unit and used to control the switching of the capacitor array. Quantization is completed within five clock cycles, outputting a 5-bit digital code value. The differential input voltage Vin of the ADC satisfies:

[0057] in ,express This indicates that the activated row has a corresponding positive weight and is in a low-resistance state. The number of MTJs This indicates that the activated row has a corresponding negative weight and is in a low-resistance state. The number of MTJs This indicates a positive weight and a high-resistance state. The number of MTJs This indicates a negative weight and a high-resistance state. The number of MTJs; This reflects the statistical difference in the MTJ states of the positive and negative weighted paths. By setting the positive weighted reference voltage Vrefp=900mV and the negative weighted reference voltage Vrefn=716mV in the SAR ADC, the ADC can accurately quantize the input voltage in the range of -184mV to +184mV.

[0058] Figure 1 The basic processing unit Xbrp is illustrated in the example. <15> The connection relationships between buffers and multiplexers are similar to those between other basic processing units.

[0059] Preferably, the analog-to-in-memory computing circuit based on a magnetic tunnel junction array provided in this embodiment further includes a timing control module. This timing control module generates control signals such as compute enable, sample-and-hold, multiplexer address, and analog-to-digital converter clock. The timing control module is connected to the analog computing module, buffer module, multiplexer module, and analog-to-digital converter module. In this embodiment, the timing control module supports pipelined execution of computation and quantization operations, allowing the next computation process to start simultaneously with the quantization of the previous computation result. The timing diagram corresponding to this pipeline is shown below. Figure 8 As shown, "read" represents the read enable signal, "cal" represents the calculation enable signal, and "Xbrp_row_sh" represents the calculation enable signal. <0> “Xbrp_row_sh <1> “Xbrp_row_sh <2> "and "Xbrp_row_sh <3> "These represent the row signals that control the generation of calculation results during the calculation operation, "Xbrp_clk1 <0> “Xbrp_clk1” <1> “Xbrp_clk1” <2> "and "Xbrp_clk1 <3> "Xbrp_row_adc" represents the row signal that controls the sampling and holding of the calculation result during the calculation operation. <0> “Xbrp_row_adc” <1> “Xbrp_row_adc” <2> "and "Xbrp_row_adc <3> "When performing calculations, select 4" One output of the 4Xbrp is fed into an AD converter for signal quantization, "Xbrp_col_adc" <0> “Xbrp_col_adc” <1> “Xbrp_col_adc” <2> "and "Xbrp_col_adc <3> "When performing calculations, select 4" One output of the 4Xbrp is fed into the ADC for signal quantization. The entire calculation process employs sophisticated pipelined control: at time t0, the CAL_EN signal is enabled, and all analog calculation modules in the Xbrp begin power-on and setup; after a 180ns stabilization wait, at time t1, Xbrp_row... <0> With the control signal valid, the four Xbrp instances in the first row simultaneously begin calculation, and their internal voltage generation circuits start working; after the calculation voltage stabilizes, at time t2 (approximately 10 ns later), Xbrp_clk1... <0> When the sampling clock is valid, the 64 analog output voltages generated by the first row of Xbrp are synchronously sampled and held in their corresponding buffers. After entering time t3, the system initiates the quantization process for the first row's calculation results. The multiplexer sequentially selects the signals output from the buffers to 32 ADCs for quantization. Simultaneously, Xbrp_row... <1> The control signal takes effect immediately, triggering the second row of Xbrp to start a new round of calculations. This ingenious timing arrangement allows the calculation operations of different rows of Xbrp to completely overlap with the quantization operations of the previous row on the time axis, forming a highly efficient pipelined processing. This compresses the originally serial calculation-quantization cycle into parallel execution, thereby increasing the overall computing throughput of the system by nearly 100%.

[0060] To ensure computational accuracy, this embodiment provides a comprehensive trimming mechanism: the reference resistor in the read module can be precisely trimmed in eight resistance states within the range of 2.0kΩ to 2.7kΩ using the REF_TRIM<2:0> three-bit trimming signal, while the critical computation resistor Rcal in the computation module can be adjusted in eight levels with equivalent precision within the range of 1.6kΩ to 2.3kΩ using the cal_i_trim<2:0> signal; by configuring the optimal trimming code combination verified by pre-simulation under different process angles (including typical process conditions such as FF, TT, SS, FS, SF, etc.), the simulation verification process aims to maximize the compensation for changes in the resistance characteristics of the magnetic tunnel junction and the deviation of CMOS device parameters, as well as minimize the fluctuation range of computational gain.

[0061] This approach effectively compensates for variations in MTJ resistance characteristics and CMOS device parameter deviations caused by fluctuations in semiconductor manufacturing processes, thereby controlling the fluctuation range of computational gain Δ=(Vcal / Rp - Vcal / Rap)×Rcal within ±5%. Through the innovative architecture design that deeply integrates storage and computation, coupled with a precise resistance adjustment mechanism, this implementation not only achieves the groundbreaking function of completing analog computation within the storage unit, significantly improving the energy efficiency and throughput of neural network computation, but more importantly, it ensures the consistency of computational accuracy across the entire process voltage and temperature variation range through a system-level error compensation scheme, laying a solid foundation for the practical industrial application of analog-in-memory computing technology.

[0062] Example 2: The calculation method based on the analog in-memory computing circuit provided in Embodiment 1 above includes: The resistance values ​​of the magnetic tunnel junctions in each array are set such that the resistance values ​​of the first 32 columns of magnetic tunnel junctions correspond to the positive weights, and the resistance values ​​of the last 32 columns correspond to the negative weights. Magnetic tunnel junction and the first The resistance values ​​of the magnetic tunnel junctions are complementary; ; The target basic processing unit is selected by address signal, based on 32-dimensional... The signal vector activates the word lines in the target basic unit, and after starting the calculation, the quantized calculation results are obtained from 32 analog-to-digital converters.

[0063] The analog in-memory computing circuit based on magnetic tunnel junction array provided in Embodiment 1 above can realize in-situ parallel computing, and the calculation and quantization operations can be executed in a fine pipeline. At the same time, it has high energy efficiency and calculation accuracy. Therefore, the calculation method provided in this embodiment has high calculation efficiency and calculation accuracy, while low energy consumption, and can realize high energy efficiency and high throughput neural network vector-matrix multiplication operations.

[0064] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An analog-to-in-memory computing circuit based on a magnetic tunnel junction array, characterized in that, include: OK The basic processing unit array of the column, A buffer, Multiplexer and One analog-to-digital converter; The basic processing unit includes: OK Array of magnetic tunnel junctions and A simulation computing module; in the magnetic tunnel junction array, the front The resistance of the magnetic tunnel junction corresponds to the positive weight, and then... The resistance of the magnetic tunnel junction corresponds to the negative weight, and the first... Magnetic tunnel junction and the first The resistance values ​​of the magnetic tunnel junctions are complementary; Each simulation computing module is connected to the magnetic tunnel junction array. The unit lines are connected; after the calculation is started, the word lines in the magnetic tunnel array are... Vie Signal vector activation, complete The calculation involves multiplying the signal vector with the resistance matrix stored in the magnetic tunnel junction array; the analog calculation module converts the calculation results of the corresponding bit lines into analog voltages. ; ; No. The first basic processing unit and the first Each buffer is connected to the next; after computation begins, the selected basic processing unit outputs... The analog voltage is sampled and held in the buffer to which it is connected; For natural numbers, ; The multiplexer is Select 1 multiplexer; each buffer has The output signals of the paths are respectively with There are 10 multiplexers; every two adjacent multiplexers are grouped together to obtain 100 multiplexers. Group multiplexer, number The two multiplexers in the group are used to connect to the first... Series analog voltage and the first Series of analog voltages; the first The two differential inputs of the analog-to-digital converter are respectively connected to the first... The two outputs of the group multiplexer are connected to complete the quantization of the corresponding calculation results; in, , , and All are positive integers.

2. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in claim 1, characterized in that, The analog computing module includes: an operational amplifier, a current mirror unit, and a computing resistor; The operational amplifier has its negative input terminal connected to a reference voltage. Its output terminal is connected to the control terminal of the current mirror unit; The current mirror unit has its input branch connected to the corresponding bit line in the magnetic tunnel junction array, and its output branch connected to one end of the calculation resistor. The calculated resistor generates an analog voltage across its terminals that is proportional to the conductance of the selected magnetic tunnel junction on the corresponding bit line. .

3. The analog-in-memory computing circuit based on a magnetic tunnel junction array as described in claim 2, characterized in that, The basic processing unit also includes a read module and a write module; The read module is used to read the resistance state of the magnetic tunnel junctions in the magnetic tunnel junction array and convert it into a digital signal; The write module is used to set and reset the magnetic tunnel junctions in the magnetic tunnel junction array.

4. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in claim 3, characterized in that, The reading module includes a digitally adjustable reference resistor network, the overall resistance of which is adjustable. For the same magnetic tunnel junction, different overall resistance values ​​of the reference resistor network result in different digital signals converted by the reading module. Furthermore, the calculated resistance can be digitally adjusted; Furthermore, the combination of the resistance values ​​of the reference resistor network and the calculation resistor in the reading module was determined through simulation verification. During the simulation verification process, the goal was to maximize the compensation for changes in the resistance characteristics of the magnetic tunnel junction and the deviation of CMOS device parameters, as well as to minimize the fluctuation range of the calculation gain.

5. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in any one of claims 1 to 4, characterized in that, The buffer includes: a 64-channel time-division multiplexed source follower.

6. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in any one of claims 1 to 4, characterized in that, The analog-to-digital converter is a SAR ADC.

7. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in any one of claims 1 to 4, characterized in that, Also includes: A timing control module is connected to each analog computing module, buffer, multiplexer, and analog-to-digital converter. The timing control module is used to generate control signals, including a computing enable signal, a sample-and-hold signal, a multiplexer address, and an analog-to-digital converter clock.

8. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in claim 7, characterized in that, The timing control module is also used to control the calculation and quantization operations to be executed in a pipeline manner; The pipeline includes: while performing a quantization operation on the calculation result of the previous basic processing unit, starting the calculation process of the next basic processing unit, and sampling and storing the calculation result in the corresponding buffer.

9. The analog-to-in-memory computing circuit based on a magnetic tunnel junction array as described in any one of claims 1 to 4, characterized in that, The magnetic tunnel junction array is a 1T1MTJ array.

10. A computational method based on the analog-in-memory computing circuit based on a magnetic tunnel junction array as described in any one of claims 1 to 9, characterized in that, include: Set the resistance state of the magnetic tunnel junctions in each magnetic tunnel junction array, so that in each magnetic tunnel junction array, the front The resistance of the magnetic tunnel junction corresponds to the positive weight, and then... The resistance of the magnetic tunnel junction corresponds to the negative weight, and the first... Magnetic tunnel junction and the first The resistance values ​​of the magnetic tunnel junctions are complementary; All are positive integers. ; The target basic processing unit is selected by address signal, based on Vie The signal vector activates the word line in the target basic unit, and after starting the calculation, from... An analog-to-digital converter acquires the quantized calculation results.

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