Hybrid reconfigurable PUF circuit, electronic device and method
By connecting RRAM cells in series in the critical path of SRAM and introducing a feedback structure, the advantages of SRAM and RRAM are combined, solving the problem of the difficulty in balancing stability and speed in traditional PUF circuits, and realizing a highly stable, non-volatile, reconfigurable and high-speed hybrid PUF circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional PUF circuits struggle to balance stability and speed, SRAM's volatility leads to unstable output, and RRAM's slow read/write speed and high cost limit its adoption in high-performance, low-cost applications.
A hybrid reconfigurable PUF circuit is adopted, which combines the high-speed read and write capability of SRAM with the non-volatility of RRAM by connecting RRAM cells in series to the critical path of SRAM and introducing a feedback structure.
It achieves a physically unclonable functional circuit with high stability, non-volatility, reconfigurability, and high-speed response, while also having high area efficiency, making it suitable for applications with stringent security and performance requirements.
Smart Images
Figure CN122020737A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a hybrid reconfigurable PUF circuit, electronic device, and method. Background Technology
[0002] A Physically Unclonable Function (PUF) is a hardware security technology that utilizes inherent microscopic random deviations in semiconductor manufacturing to generate unique identifiers for chips. Due to its true randomness, unclonability, and low overhead, it is widely used in security scenarios such as key generation, device authentication, and copyright protection. Traditional PUF structures are mostly implemented based on single units such as SRAM, RRAM, ring oscillators, or arbitrators, which have limitations such as insufficient response stability, high hardware overhead, and non-reconfigurability.
[0003] In related technologies, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the basic structure of a PUF based on SRAM in related technologies. The traditional basic structure of a PUF based on SRAM uses the random initial state of the SRAM cell caused by process deviation during power-on as a response signal, which has the advantages of fast response speed and high integration.
[0004] However, the inherent volatility of SRAM means it cannot retain its state after power loss, requiring the randomization of responses upon each power-on. This limits the stability of the PUF output and makes it more sensitive to environmental fluctuations and aging effects. On the other hand, RRAM, as a newer non-volatile memory, is also used to implement PUF circuits, with a typical structure as follows: Figure 2 As shown, Figure 2 This is a typical structural diagram of a PUF circuit implemented with RRAM in related technologies. Thanks to the non-volatile nature of RRAM, the stability of the PUF is significantly improved. However, RRAM's read / write speed is generally lower than SRAM, and its cell area and manufacturing cost are relatively high, which to some extent limits its potential for widespread adoption in high-performance, low-cost applications, and this issue urgently needs to be addressed. Summary of the Invention
[0005] This application provides a hybrid reconfigurable PUF circuit, electronic device, and method to solve the problem that traditional PUFs cannot balance stability and speed.
[0006] The first aspect of this application provides a hybrid reconfigurable PUF circuit, including: The SRAM memory cell includes a first inverter and a second inverter, which are cross-coupled. The first RRAM unit has one end electrically connected to the first power access node and the other end electrically connected to the first inverter. The second RRAM unit has one end electrically connected to the first power access node and the other end electrically connected to the second inverter.
[0007] Optionally, it also includes: A feedback resistor, one end of which is electrically connected to the first bit line, and the other end of which is electrically connected to the second bit line, wherein... The feedback resistor is configured to adjust the voltage across the first RRAM unit when the first RRAM unit is configured, or to adjust the voltage across the second RRAM unit when the second RRAM unit is configured.
[0008] Optionally, the first RRAM cell and the second RRAM cell are integrated in the back metal layer of the SRAM memory cell.
[0009] Optionally, the first inverter includes: a first MOSFET, a second MOSFET, and a first NOT gate, wherein, The gate of the first MOS transistor is electrically connected to one end of the first NOT gate, the source of the first MOS transistor is electrically connected to the first RRAM cell, and the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor. The other end of the first NOT gate is electrically connected to the gate of the second MOS transistor and the second inverter, respectively; The drain of the second MOSFET is electrically connected to the second power supply access node.
[0010] Optionally, the second inverter includes: a third MOSFET, a fourth MOSFET, and a second NOT gate, wherein... The gate of the third MOS transistor is electrically connected to one end of the second NOT gate, the source of the third MOS transistor is electrically connected to the second RRAM cell, and the drain of the third MOS transistor is electrically connected to the source of the fourth MOS transistor. The other end of the second NOT gate is electrically connected to the gate of the fourth MOS transistor, the drain of the first MOS transistor, and the source of the second MOS transistor, respectively. The drain of the fourth MOS transistor is electrically connected to the second power access node.
[0011] Optionally, the first MOS transistor and the third MOS transistor are PMOS transistors, and the second MOS transistor and the fourth MOS transistor are NMOS transistors.
[0012] Optionally, it also includes: The fifth MOS transistor has its first terminal electrically connected to the connection node between the first MOS transistor and the second MOS transistor, its second terminal electrically connected to the first bit line, and its control terminal electrically connected to the first word line. The sixth MOS transistor has its first terminal electrically connected to the connection node between the third and fourth MOS transistors, its second terminal electrically connected to the second bit line, and its control terminal electrically connected to the first word line.
[0013] A second aspect of this application provides an electronic device, such as the hybrid reconfigurable PUF circuit described in any of the preceding embodiments.
[0014] A third aspect of this application provides a hybrid reconfigurable PUF method, employing a hybrid reconfigurable PUF circuit as shown in any of the above embodiments, including the following steps: The first bit line and the second bit line of the hybrid reconfigurable PUF circuit are both set to the first reference potential. A first pulse signal is applied to the first power access node. Based on the first pulse signal, a FORMING operation is performed in parallel on the first RRAM cell and the second RRAM cell to convert the first RRAM cell and the second RRAM cell into a resistive state. The first bit line and the second bit line are electrically connected, and a second reference potential is applied to the first bit line and the second bit line. In the case that there is a positive feedback effect between the first bit line and the second bit line, a second pulse signal is applied to the first power access node, and based on the second pulse signal, a SET operation is performed on the first RRAM cell and the second RRAM cell to switch the first RRAM cell and the second RRAM cell to a complementary resistive state. The first power access node and the second bit line are both set to the third reference potential, and a third pulse signal is applied to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line. A RESET operation is performed on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state.
[0015] Optionally, the step of applying a third pulse signal to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line, and performing a RESET operation on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state includes: When the target bit line is the first bit line, the third pulse signal is applied to the first bit line to generate a unidirectional conductive path through the first RRAM cell, and a RESET operation is performed on the first RRAM cell to restore the resistance state of the first RRAM cell to a preset resistance state. And / or, when the target bit line is the second bit line, the third pulse signal is applied to the second bit line to generate a unidirectional conductive path through the second RRAM cell, and a RESET operation is performed on the second RRAM cell to restore the resistance state of the second RRAM cell to a preset resistance state.
[0016] Therefore, the embodiments of this application include an SRAM memory cell, a first RRAM cell, and a second RRAM cell. The SRAM memory cell includes a first inverter and a second inverter, which are cross-coupled. The first RRAM cell has one end electrically connected to a first power access node and the other end electrically connected to the first inverter. The second RRAM cell has one end electrically connected to a second power access node and the other end electrically connected to the second inverter. Thus, by connecting the RRAM in series to the critical path of the SRAM and introducing a feedback structure, the problems of balancing stability and speed in traditional PUFs are solved, achieving a highly stable, non-volatile, reconfigurable, and physically unclonable functional circuit with both high-speed response and high area efficiency.
[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the basic structure of SRAM-based PUF in related technologies; Figure 2 This is a typical structural diagram of a PUF circuit implemented with RRAM in related technologies; Figure 3 This is a schematic diagram of a hybrid reconfigurable PUF circuit according to an embodiment of this application; Figure 4 This is a schematic diagram of the main structure of a hybrid RRAM-SRAM hybrid PUF circuit according to an embodiment of this application; Figure 5 This is a schematic diagram of a hybrid PUF circuit structure with positive feedback, according to an embodiment of this application; Figure 6 This is a flowchart illustrating the operation of a hybrid PUF circuit for implementing hybrid reconfigurable PUF circuit according to an embodiment of this application. Figure 7 This is a schematic diagram of the operation waveforms for the implementation of a hybrid reconfigurable PUF circuit according to an embodiment of this application. Figure 8 This is a flowchart of a hybrid reconfigurable PUF method provided according to an embodiment of this application. Detailed Implementation
[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0020] The following description, with reference to the accompanying drawings, describes a hybrid reconfigurable PUF circuit, electronic device, and method according to embodiments of this application. Addressing the problem of balancing stability and speed in traditional PUFs mentioned in the background, this application provides a hybrid reconfigurable PUF circuit. The embodiment includes an SRAM memory cell, a first RRAM cell, and a second RRAM cell. The SRAM memory cell includes a first inverter and a second inverter, which are cross-coupled. One end of the first RRAM cell is electrically connected to a first power access node, and the other end is electrically connected to the first inverter. One end of the second RRAM cell is electrically connected to a second power access node, and the other end is electrically connected to the second inverter. Thus, by connecting the RRAM in series to the critical path of the SRAM and introducing a feedback structure, the problem of balancing stability and speed in traditional PUFs is solved, achieving a highly stable, non-volatile, reconfigurable circuit with both high-speed response and high area efficiency—a physically unclonable functional circuit.
[0021] Specifically, Figure 3 This is a schematic diagram of a hybrid reconfigurable PUF circuit provided in an embodiment of this application.
[0022] like Figure 3 As shown, the hybrid reconfigurable PUF circuit 10 includes: an SRAM storage cell 100, a first RRAM cell 200, and a second RRAM cell 300.
[0023] Among them, the SRAM storage cell 100 includes a first inverter and a second inverter, and the first inverter and the second inverter are cross-coupled. The first RRAM cell 200 has one end electrically connected to the first power access node and the other end electrically connected to the first inverter. The second RRAM unit 300 has one end electrically connected to the second power supply access node and the other end electrically connected to the second inverter.
[0024] Specifically, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the main structure of a hybrid reconfigurable PUF circuit based on an embodiment of this application, comprising an RRAM-SRAM hybrid PUF circuit. The SRAM base cell 100 is composed of a first inverter and a second inverter cross-coupled, providing high-speed read / write and random initial state response capabilities. One end of each RRAM cell is connected to a common first power access node, and the other end is connected to a corresponding inverter in the SRAM cell. By directly connecting the RRAM cells in series in the power path of the SRAM cells, the circuit retains the high-speed read / write performance advantages of SRAM while introducing non-volatile storage and reconfigurability through RRAM, thereby effectively solving the shortcomings of single technical solutions in terms of stability and functionality.
[0025] Optionally, in some embodiments, it further includes: a feedback resistor, one end of which is electrically connected to the first bit line and the other end of which is electrically connected to the second bit line, wherein the feedback resistor is configured to adjust the voltage across the first RRAM unit when the first RRAM unit is configured, or to adjust the voltage across the second RRAM unit when the second RRAM unit is configured.
[0026] It is understandable that, such as Figure 5 As shown, Figure 5 This is a schematic diagram of a hybrid reconfigurable PUF circuit with positive feedback according to one embodiment of this application. By connecting a feedback resistor (RF) between BL (first bit line) and BLB (second bit line), the PUF performance can be further enhanced. The function of the feedback resistor is to adjust the voltage across the RRAM to different degrees according to the resistance values of the two RRAMs during FORMING / SET operations, forming a resistance-voltage positive feedback to achieve adaptive resistance adjustment and resistance separation, thereby enhancing the stability of the PUF.
[0027] Optionally, in some embodiments, the first RRAM cell and the second RRAM cell are integrated into the back metal layer of the SRAM memory cell.
[0028] Understandably, in terms of manufacturing process, RRAM can be directly integrated into the back metal layer of SRAM cells, taking up almost no additional chip area, which greatly improves the area efficiency of the overall structure, making it particularly suitable for application scenarios with strict requirements on power consumption, area and security.
[0029] Optionally, in some embodiments, the first inverter includes: a first MOS transistor, a second MOS transistor, and a first NOT gate, wherein the gate of the first MOS transistor is electrically connected to one end of the first NOT gate, the source of the first MOS transistor is electrically connected to a first RRAM cell, and the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor; the other end of the first NOT gate is electrically connected to the gate of the second MOS transistor and the second inverter, respectively; and the drain of the second MOS transistor is electrically connected to a second power access node.
[0030] Optionally, in some embodiments, the second inverter includes: a third MOS transistor, a fourth MOS transistor, and a second NOT gate, wherein the gate of the third MOS transistor is electrically connected to one end of the second NOT gate, the source of the third MOS transistor is electrically connected to a second RRAM cell, and the drain of the third MOS transistor is electrically connected to the source of the fourth MOS transistor; the other end of the second NOT gate is electrically connected to the gate of the fourth MOS transistor, the drain of the first MOS transistor, and the source of the second MOS transistor; and the drain of the fourth MOS transistor is electrically connected to a second power access node.
[0031] Optionally, in some embodiments, the first and third MOS transistors are PMOS transistors, and the second and fourth MOS transistors are NMOS transistors.
[0032] Optionally, in some embodiments, it further includes: a fifth MOS transistor, the first end of which is electrically connected to the connection node between the first MOS transistor and the second MOS transistor, the second end of which is electrically connected to the first bit line, and the control terminal of which is electrically connected to the first word line; and a sixth MOS transistor, the first end of which is electrically connected to the connection node between the third MOS transistor and the fourth MOS transistor, the second end of which is electrically connected to the second bit line, and the control terminal of which is electrically connected to the first word line.
[0033] It is understood that the main circuit structure of this application embodiment consists of 6 MOS transistors and 2 memristor devices. The 6 MOS transistors are arranged in the standard SRAM cell transistor arrangement, that is, two inverters are connected end to end, and the tails of each are connected to BL / BLB through an NMOS transistor (the fifth MOS transistor and the sixth MOS transistor), and the gates are connected to WL (the first word line) to control the control unit for selection. On this basis, two RRAMs (RA, RB) (the first RRAM cell and the second RRAM cell) are respectively connected in series above the two PMOS transistors (the first MOS transistor and the third MOS transistor) in the SRAM cell, with one end connected to the PMOS transistors and the other end connected to the power supply voltage VDD.
[0034] Therefore, this invention proposes a hybrid reconfigurable PUF circuit based on the combination of RRAM and SRAM. This structure, based on a traditional SRAM-type PUF, introduces non-volatile storage capability and reconfigurability by cascading RRAM cells in the critical path, significantly enhancing the reliability and practicality of the PUF. Compared to a single RRAM-type PUF, this structure fully utilizes the non-volatile and reconfigurable characteristics of RRAM while retaining the high-speed read / write capabilities of SRAM. It effectively compensates for the shortcomings of single-structure PUFs in terms of stability, functional flexibility, and area efficiency, thus achieving non-volatile and reconfigurable PUF operation while maintaining the high-speed performance advantage of SRAM, significantly improving the overall performance of the PUF.
[0035] To facilitate a better understanding of the hybrid reconfigurable PUF circuit of the embodiments of this application by those skilled in the art, the following is combined with... Figures 6 to 7 The embodiments shown will be described in detail.
[0036] Specifically, the operations that can be implemented in the embodiments of this application include: FORMING, SET, RESET, and reading and writing of cell data, and the specific operation flow is as follows: Figure 6 As shown, Figure 6 This is a flowchart illustrating the operation of a hybrid reconfigurable PUF circuit according to one embodiment of this application. During formatting, the WL of the operating unit is turned on, BL and BLB are simultaneously grounded, and a high-voltage triangular pulse is input to VDD to better observe the unit's operating state during power-on and power-off. At this time, RA to BL and RB to BLB each form two relatively independent current paths, allowing simultaneous formatting of two RRAMs. Furthermore, the RRAM that reaches a low-resistance state first will not affect the formatting operation of the other RRAM. The operation waveform is shown below. Figure 7 As shown in (a), Figure 7 (a) is a schematic diagram of the FORMING operation waveform of a hybrid reconfigurable PUF circuit according to an embodiment of this application.
[0037] Furthermore, once the RRAM formatting is complete, a SET / RESET operation can be performed. During the SET operation, a high voltage pulse is still input to VDD, and BL and BLB are no longer grounded but connected to the feedback resistor RF. Appropriate positive feedback is provided by adjusting the resistance value of RF. The operation waveform is as follows: Figure 7 As shown in (b), Figure 7 (b) is a schematic diagram of the SET operation waveform of a hybrid reconfigurable PUF circuit according to an embodiment of this application. The principle of positive feedback is that after adding RF, the two points connected end-to-end of the inverter in the SRAM structure are partially turned on, so that the "1" at one end is not a strictly digital voltage VDD, but an analog voltage lower than VDD. This causes the PMOS on the other side to be in a semi-conducting state, and there is also a voltage drop across the RRAM. Therefore, if RA < RB, the voltage drop across RA > the voltage drop across RB, meaning the SET voltage is stronger for the RRAM with the smaller resistance. Furthermore, as the difference in resistance between the two RRAMs gradually increases, the difference in voltage drops across them decreases accordingly. This principle enables the PUF circuit to more quickly and accurately separate the resistance values of the two RRAMs during the SET process, further ensuring the stability of the PUF stored data.
[0038] Furthermore, the RESET operation is performed unilaterally. Taking the RESET of RA as an example: VDD and BLB are grounded, and high-voltage pulses are input to both BL and WL. At this time, a unilateral RESET path is formed from RA to BL. The operation of RB is similar, and the operation waveform is as follows. Figure 7 As shown in (c), Figure 7 (c) A schematic diagram of the RESET operation waveform of a hybrid reconfigurable PUF circuit according to an embodiment of this application; since the hybrid PUF circuit completely retains the cell structure of SRAM, the read and write operations of the PUF cell are basically the same as those of SRAM. During writing, BL is connected to a high level and BLB is connected to a low level, which means writing "1", and vice versa; during reading, BL / BLB are pre-charged simultaneously, and then the stored data value of the PUF cell is determined by the change in the voltage value of BL / BLB after power-down.
[0039] Therefore, this application proposes a hybrid PUF circuit structure based on the combination of RRAM and SRAM. The main structure consists of 6 MOS transistors and 2 RRAMs, and a feedback resistor is introduced. This structure can realize PUF functions more efficiently and reliably, including FORMING, SET, RESET, and reading and writing of cell data, and has both reconfigurable and erasable write capabilities and high-speed read and write characteristics.
[0040] According to the hybrid reconfigurable PUF circuit proposed in this application embodiment, the circuit includes an SRAM memory cell, a first RRAM cell, and a second RRAM cell. The SRAM memory cell includes a first inverter and a second inverter, which are cross-coupled. One end of the first RRAM cell is electrically connected to a first power access node, and the other end is electrically connected to the first inverter. One end of the second RRAM cell is electrically connected to a second power access node, and the other end is electrically connected to the second inverter. Thus, by connecting the RRAM in series to the critical path of the SRAM and introducing a feedback structure, the problem of balancing stability and speed in traditional PUFs is solved, achieving a highly stable, non-volatile, reconfigurable circuit with both high-speed response and high area efficiency—a physically unclonable functional circuit.
[0041] This application also provides an electronic device that implements the hybrid reconfigurable PUF circuit as described above.
[0042] Next, referring to the accompanying drawings, the hybrid reconfigurable PUF method proposed according to the embodiments of this application is described, employing the hybrid reconfigurable PUF circuit as shown above.
[0043] Figure 8 This is a flowchart of the hybrid reconfigurable PUF method according to an embodiment of this application.
[0044] In step S801, the first bit line and the second bit line of the hybrid reconfigurable PUF circuit are both set to the first reference potential, a first pulse signal is applied to the first power access node, and based on the first pulse signal, a FORMING operation is performed in parallel on the first RRAM cell and the second RRAM cell to convert the first RRAM cell and the second RRAM cell into a resistive switching state. In step S802, the first bit line and the second bit line are electrically connected, and a second reference potential is applied to the first bit line and the second bit line. In the case of a positive feedback effect between the first bit line and the second bit line, a second pulse signal is applied to the first power access node. Based on the second pulse signal, a SET operation is performed on the first RRAM cell and the second RRAM cell to switch the first RRAM cell and the second RRAM cell to a complementary resistive state.
[0045] In step S803, the first power access node and the second bit line are both set to the third reference potential, and a third pulse signal is applied to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line. A RESET operation is performed on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to the preset resistance state.
[0046] Optionally, in some embodiments, applying a third pulse signal to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line, and performing a RESET operation on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state includes: when the target bit line is the first bit line, applying a third pulse signal to the first bit line to generate a unidirectional conductive path through the first RRAM cell, performing a RESET operation on the first RRAM cell to restore the resistance state of the first RRAM cell to a preset resistance state; and / or, when the target bit line is the second bit line, applying a third pulse signal to the second bit line to generate a unidirectional conductive path through the second RRAM cell, performing a RESET operation on the second RRAM cell to restore the resistance state of the second RRAM cell to a preset resistance state.
[0047] It should be noted that the foregoing explanation of the hybrid reconfigurable PUF circuit embodiment also applies to the hybrid reconfigurable PUF method of this embodiment, and will not be repeated here.
[0048] According to the hybrid reconfigurable PUF method proposed in this application, the first bit line and the second bit line of the hybrid reconfigurable PUF circuit are both set to a first reference potential. A first pulse signal is applied to the first power access node, and based on the first pulse signal, a FORMING operation is performed in parallel on the first RRAM cell and the second RRAM cell to convert the first RRAM cell and the second RRAM cell into a resistive state. The first bit line and the second bit line are electrically connected, and a second reference potential is applied to the first bit line and the second bit line. In the case of a positive feedback effect between the first bit line and the second bit line, a second pulse signal is applied to the first power access node, and based on the second pulse signal, a SET operation is performed on the first RRAM cell and the second RRAM cell to convert the first RRAM cell and the second RRAM cell into a complementary resistive state. The first power access node and the second bit line are both set to a third reference potential, and a third pulse signal is applied to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line. A RESET operation is performed on the RRAM cell corresponding to the target bit line to restore the resistive state of the RRAM cell corresponding to the target bit line to a preset resistive state. Therefore, by connecting RRAM in series to the critical path of SRAM and introducing a feedback structure, the problem of difficulty in balancing stability and speed in traditional PUF is solved, realizing a physically unclonable functional circuit that is highly stable, non-volatile, reconfigurable, and has both high-speed response and high area efficiency.
[0049] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0051] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.
[0052] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0053] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
Claims
1. A hybrid reconfigurable PUF circuit, characterized in that, include: The SRAM memory cell includes a first inverter and a second inverter, which are cross-coupled. The first RRAM unit has one end electrically connected to the first power access node and the other end electrically connected to the first inverter. The second RRAM unit has one end electrically connected to the first power access node and the other end electrically connected to the second inverter.
2. The hybrid reconfigurable PUF circuit according to claim 1, characterized in that, Also includes: A feedback resistor, one end of which is electrically connected to the first bit line, and the other end of which is electrically connected to the second bit line, wherein... The feedback resistor is configured to adjust the voltage across the first RRAM unit when the first RRAM unit is configured, or to adjust the voltage across the second RRAM unit when the second RRAM unit is configured.
3. The hybrid reconfigurable PUF circuit according to claim 1, characterized in that, The first RRAM cell and the second RRAM cell are integrated in the back metal layer of the SRAM memory cell.
4. The hybrid reconfigurable PUF circuit according to claim 1, characterized in that, The first inverter includes: a first MOSFET, a second MOSFET, and a first NOT gate, wherein, The gate of the first MOS transistor is electrically connected to one end of the first NOT gate, the source of the first MOS transistor is electrically connected to the first RRAM cell, and the drain of the first MOS transistor is electrically connected to the source of the second MOS transistor. The other end of the first NOT gate is electrically connected to the gate of the second MOS transistor and the second inverter, respectively; The drain of the second MOSFET is electrically connected to the second power supply access node.
5. The hybrid reconfigurable PUF circuit according to claim 4, characterized in that, The second inverter includes: a third MOSFET, a fourth MOSFET, and a second NOT gate, wherein, The gate of the third MOS transistor is electrically connected to one end of the second NOT gate, the source of the third MOS transistor is electrically connected to the second RRAM cell, and the drain of the third MOS transistor is electrically connected to the source of the fourth MOS transistor. The other end of the second NOT gate is electrically connected to the gate of the fourth MOS transistor, the drain of the first MOS transistor, and the source of the second MOS transistor, respectively. The drain of the fourth MOS transistor is electrically connected to the second power access node.
6. The hybrid reconfigurable PUF circuit according to claim 5, characterized in that, The first MOS transistor and the third MOS transistor are PMOS transistors, and the second MOS transistor and the fourth MOS transistor are NMOS transistors.
7. The hybrid reconfigurable PUF circuit according to claim 6, characterized in that, Also includes: The fifth MOS transistor has its first terminal electrically connected to the connection node between the first MOS transistor and the second MOS transistor, its second terminal electrically connected to the first bit line, and its control terminal electrically connected to the first word line. The sixth MOS transistor has its first terminal electrically connected to the connection node between the third and fourth MOS transistors, its second terminal electrically connected to the second bit line, and its control terminal electrically connected to the first word line.
8. An electronic device, characterized in that, include: The hybrid reconfigurable PUF circuit as described in any one of claims 1-7.
9. A hybrid reconfigurable PUF method, characterized in that, The method is applied to the hybrid reconfigurable PUF circuit as described in any one of claims 1-7, wherein the method includes the following steps: The first bit line and the second bit line of the hybrid reconfigurable PUF circuit are both set to the first reference potential. A first pulse signal is applied to the first power access node. Based on the first pulse signal, a FORMING operation is performed in parallel on the first RRAM cell and the second RRAM cell to convert the first RRAM cell and the second RRAM cell into a resistive state. The first bit line and the second bit line are electrically connected, and a second reference potential is applied to the first bit line and the second bit line. In the case that there is a positive feedback effect between the first bit line and the second bit line, a second pulse signal is applied to the first power access node, and based on the second pulse signal, a SET operation is performed on the first RRAM cell and the second RRAM cell to switch the first RRAM cell and the second RRAM cell to a complementary resistive state. The first power access node and the second bit line are both set to the third reference potential, and a third pulse signal is applied to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line. A RESET operation is performed on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state.
10. The method according to claim 9, characterized in that, The step of applying a third pulse signal to the target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line, and performing a RESET operation on the RRAM cell corresponding to the target bit line to restore the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state includes: When the target bit line is the first bit line, the third pulse signal is applied to the first bit line to generate a unidirectional conductive path through the first RRAM cell, and a RESET operation is performed on the first RRAM cell to restore the resistance state of the first RRAM cell to a preset resistance state. And / or, when the target bit line is the second bit line, the third pulse signal is applied to the second bit line to generate a unidirectional conductive path through the second RRAM cell, and a RESET operation is performed on the second RRAM cell to restore the resistance state of the second RRAM cell to a preset resistance state.