Display module and automatic repair method thereof

Abstract

The invention discloses a display module and an automatic repairing method thereof. The display module comprises a first signal line, a target circuit and a fusing circuit. The first signal line is electrically connected with the target circuit through the fusing circuit, and the fusing circuit is disconnected under the condition that the target circuit breaks down. According to the invention, after the fault of the target circuit is detected, the connection between the fault target circuit and the first signal line is cut off through the fusing circuit, so that the voltage abnormity caused by the connection between the first signal line and the fault target circuit is avoided; therefore, the abnormal voltage of the first signal line in the display module is repaired through the fusing circuit after the target circuit breaks down, so that the display module can perform normal display.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display module and its automatic repair method. Background Technology

[0002] The display module can be configured with circuits and signal lines connected to the circuits. When a circuit fails, the voltage on the signal line connected to that circuit will change (for example, the voltage on the signal line will increase), which will cause other circuits connected to that signal line to malfunction, and in turn, cause the display module to malfunction.

[0003] Therefore, how to repair the display module's abnormal display problem caused by the fault after a short circuit fault is detected has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a display module and its automatic repair method. After a fault is detected in the target circuit, the application can cut off the connection between the faulty target circuit and the first signal line through a fuse circuit, thereby avoiding voltage abnormalities in the first signal line caused by the connection with the faulty target circuit. This enables the display module to repair the voltage abnormalities of the first signal line in the display module through the fuse circuit after the target circuit fails, so that the display module can display normally.

[0005] In a first aspect, this application provides a display module, including: a first signal line, a target circuit, and a fuse circuit; the first signal line is electrically connected to the target circuit through the fuse circuit, and the fuse circuit is disconnected in the event of a fault in the target circuit.

[0006] Secondly, this application provides an automatic repair method for a display module, applied to the display module of this application; the first signal line includes a first sub-signal line and a second sub-signal line; the target circuit includes multiple sub-target circuits; the detection trigger circuit of the display module includes a first detection unit and a second detection unit; the method includes: acquiring a first sub-signal line with abnormal voltage determined by the first detection unit, and a second sub-signal line with abnormal voltage determined by the second detection unit; determining the faulty sub-target circuit based on the first sub-signal line with abnormal voltage and the second sub-signal line; and controlling the fuse circuit corresponding to the faulty sub-target circuit to open.

[0007] This application provides a display module and its automatic repair method. The display module includes a first signal line, a target circuit, and a fuse circuit. The first signal line is electrically connected to the target circuit through the fuse circuit. In the event of a fault in the target circuit, the fuse circuit disconnects. Multiple identical or different target circuits can be connected to the first signal line, which provides voltage to the connected target circuits. In the event of a fault in the target circuit, the fuse circuit can disconnect the connection between the target circuit and the first signal line, thereby preventing voltage changes on the first signal line due to the connection between the first signal line and the faulty target circuit. Therefore, this application can, upon detecting a fault in the target circuit, disconnect the connection between the faulty target circuit and the first signal line through the fuse circuit, thereby ensuring that the voltage of the first signal line remains normal, allowing other circuits connected to the first signal line to operate normally. This, in turn, repairs the display module after a target circuit fault, enabling the display module to display normally. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of this application; Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of another display module provided in an embodiment of this application; Figure 4 This is a partial structural diagram of a display module provided in an embodiment of this application; Figure 5 This is a schematic diagram of the hierarchical structure of a display module provided in an embodiment of this application; Figure 6 A schematic diagram of the layout of a pixel driving circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of another display module provided in an embodiment of this application; Figure 8 is a flowchart illustrating an automatic repair method for a display module provided in an embodiment of this application; Figure 9 A flowchart illustrating another automatic repair method for a display module provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0010] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0011] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0012] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0013] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0014] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0015] In the embodiments of this application, the first node, the second node, and the third node are defined only for the convenience of describing the circuit structure, and the first node, the second node, and the third node are not actual circuit units.

[0016] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: Taking a pixel driving circuit as an example, if a short circuit occurs in a pixel driving circuit, the voltage of the sub-signal line connected to it will increase, which will cause all pixels connected to that sub-signal line to display abnormalities, and thus cause dark lines or dark spots to appear in a display area of ​​the display module.

[0018] In related technologies, to detect short-circuit faults in pixel driving circuits, the location of the short circuit is typically determined during the fabrication process using electrical or optical detection. Then, external equipment, such as a laser, is used to cut the metal trace at the short-circuit location. However, these technologies cannot detect short-circuit faults occurring outside the fabrication process. Furthermore, the detection methods used during fabrication can only detect short-circuit faults at the micrometer level, making it impossible to detect even smaller faults.

[0019] Based on the above-mentioned technical problems, this application provides a display module and its automatic repair method. The embodiments of this application will be described below with reference to the accompanying drawings.

[0020] Therefore, how to quickly detect pixel driving circuits that have short-circuited and how to repair display abnormalities caused by short-circuit faults in display modules have become technical problems that urgently need to be solved by those skilled in the art.

[0021] Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of this application, as shown below. Figure 1 As shown, the display module includes: a first signal line 10, a target circuit 20, and a fuse circuit 30.

[0022] For example, the target circuit 20 may be, for example, a pixel driving circuit, a touch circuit, a power supply circuit, etc., wherein the pixel driving circuit is used to drive the light-emitting element, the touch circuit is used to identify the touch position, and the power supply circuit is used to provide power supply voltage.

[0023] The first signal line 10 is electrically connected to the target circuit 20 through the fuse circuit 30. In the event of a fault in the target circuit 20, the fuse circuit 30 is disconnected.

[0024] For example, in the target circuit 20, which is a pixel driving circuit, the first signal line 10 is used to provide a reference voltage to the target circuit 20. The reference voltage is used to reset the gate of the driving transistor in the pixel driving circuit, and / or, the reference voltage is used to reset the anode of the light-emitting element. A fuse 30 is connected between the first signal line 10 and the fuse 30. In addition to the target circuit 20, multiple identical or different circuits may be connected to the first signal line 10.

[0025] As an example, the display module includes a detection control module. The target circuit 20 is, for example, a pixel driving circuit. Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the pixel driving circuit includes a storage capacitor C1. For example, if the storage capacitor C1 experiences a short circuit, it is equivalent to directly connecting the first signal line 10 to the first power signal line VDD, causing a change in the voltage on the first signal line 10. Therefore, the detection and control module monitors the voltage on the first signal line 10 in real time. When an abnormal change in the voltage on the first signal line 10 is detected, it is determined that the target circuit 20 has failed, and the fuse circuit 30 is controlled to open, thereby cutting off the connection between the first signal line 10 and the target circuit 20, causing the target circuit 20 to stop driving the corresponding pixel to emit light. Furthermore, since the connection between the target circuit 20 and the first signal line 10 is disconnected, the faulty target circuit 20 can be prevented from affecting the voltage on the first signal line 10, thus preventing other circuits connected to the first signal line 10 from malfunctioning due to changes in the voltage on the first signal line 10.

[0026] As another example, the fuse circuit 30 may be equipped with a fault detection unit, which is used to perform real-time fault detection on the target circuit 20. When a fault is detected in the target circuit 20, the fuse circuit 30 cuts off the connection between the first signal line 10 and the target circuit 20, thereby preventing the faulty target circuit 20 from affecting the first signal line 10.

[0027] The above examples illustrate some implementations of fault detection for target circuit 20, but are not intended to limit this application.

[0028] This application can disconnect the connection between the target circuit 20 and the first signal line 10 outside the manufacturing process of the display module, such as during normal use of the display module, when a fault is detected in the target circuit 20. Therefore, it can prevent voltage changes on the first signal line 10 due to its connection with the faulty target circuit 20, thereby preventing other target circuits from receiving abnormal voltages supplied by the first signal line 10 and ensuring that other target circuits connected to the first signal line 20 can maintain normal operation. Thus, this application can disconnect the connection between the faulty target circuit 20 and the first signal line 10 via the fuse circuit 30 after a fault is detected, thereby preventing voltage abnormalities on the first signal line 10 due to its connection with the faulty target circuit 20. This achieves voltage repair of the first signal line 10 in the display module after a target circuit fault occurs through the fuse circuit 30, enabling the display module to display normally.

[0029] In some embodiments, Figure 3 This is a schematic diagram of the structure of another display module provided in an embodiment of this application, as shown below. Figure 3 As shown, the display module also includes a detection trigger circuit 40.

[0030] The detection trigger circuit 40 is connected to the first signal line 10. The detection trigger circuit 40 is configured to detect the voltage of the first signal line 10 to determine whether the target circuit 20 has failed, and to trigger the fuse circuit 30 to open if the target circuit 20 has failed.

[0031] For example, the detection trigger circuit 40 is also connected to the fuse circuit 30. The detection trigger circuit 40 is used to detect the voltage on the first signal line 10. If it is determined that the target circuit 20 connected to the first signal line 10 has failed, for example, the first signal line 10 is a constant voltage signal under normal conditions. If the target circuit 20 has a short circuit fault, the target circuit 20 with a short circuit fault may cause the first signal line 10 to be directly connected to the first power signal line VDD, thereby causing the voltage on the first signal line 10 to change. Therefore, when the detection trigger circuit 40 detects a change in the voltage on the first signal line 10, it can determine that the target circuit 20 has failed and control the fuse circuit 30 corresponding to the failed target circuit 20 to open, thereby cutting off the connection between the failed target circuit 20 and the first signal line 10, so that the voltage on the first signal line 10 returns to normal. Thus, this application can realize the repair of the abnormal voltage of the first signal line 10 in the display module through the fuse circuit 30 after the target circuit fails, thereby repairing the abnormal state of the display module and enabling the display module to display normally.

[0032] In some embodiments, Figure 4 This is a partial structural diagram of a display module provided in an embodiment of this application, such as... Figure 4 As shown, the fuse circuit 30 includes a first transistor Q1 and a second transistor Q2.

[0033] The gate of the first transistor Q1 is connected to the first drive signal line 51, the first terminal of the first transistor Q1 is connected to the second drive signal line 52, the second terminal of the first transistor Q1 is connected to the first gate of the second transistor Q2, the first terminal of the second transistor Q2 is connected to the first signal line 10, and the second terminal of the second transistor Q2 is connected to the target circuit 20.

[0034] In the event of a fault in the target circuit 20, the first transistor Q1 is turned on, and the second drive signal on the second drive signal line 52 is transmitted to the first gate of the second transistor Q2, thereby melting the channel of the second transistor Q2.

[0035] For example, in the event of a fault in the target circuit 20, the first drive signal line 51 provides a first drive signal to the gate of the first transistor Q1, turning on the first transistor Q1. This connects the second drive signal line 52 to the first gate of the second transistor Q2, thereby providing the second drive signal in the second drive signal line 52 to the second transistor Q2. For example, the second drive signal is a high-voltage pulse signal provided by a high-voltage charge pump. Upon receiving the high-voltage pulse signal, the gate oxide layer of the second transistor Q2 is broken down, generating a momentary high temperature within a small area. This causes the channel of the second transistor Q2 to melt, disconnecting the connection between the first signal line 10 and the target circuit 20. Since the momentary high temperature only occurs within the range of the second transistor Q2, it does not affect other circuit components. Therefore, this application can completely disconnect the faulty target circuit 20 from the first signal line 10 at the physical level, ensuring that the voltage on the first signal line 10 is not affected by the target circuit 20.

[0036] In some embodiments, Figure 5 This is a schematic diagram of the hierarchical structure of a display module provided in an embodiment of this application, such as... Figure 5 As shown, the display module includes a substrate 61 and a buffer layer 62, a first insulating layer 63, a first semiconductor layer 641, a first gate insulating layer 642, a first gate layer 643, a second insulating layer 644, a second gate layer 651, a second gate insulating layer 652, a second semiconductor layer 653, and a third gate insulating layer 654, which are sequentially located away from the substrate.

[0037] The active layer of the first transistor Q1 is located on the first semiconductor layer 641, and the gate of the first transistor Q1 is located on the first gate layer 643.

[0038] The active layer of the second transistor Q2 is located in the second semiconductor layer 653, and the first gate of the second transistor Q2 is located in the second gate layer 651.

[0039] In some embodiments, see continue to see Figure 5 In the thickness direction of the display module, a first gate insulating layer 642 is provided between the gate of the first transistor Q1 and the active layer of the first transistor Q1, and a second gate insulating layer 652 is provided between the first gate of the second transistor Q2 and the active layer of the second transistor Q2.

[0040] For example, the thickness of the second gate insulating layer 652 is less than the thickness of the first gate insulating layer 642, and the thickness of the second gate insulating layer is less than or equal to 7 nanometers. The channel width-to-length ratio of the second transistor Q2 is greater than that of the first transistor Q1, and the channel width-to-length ratio of the second transistor Q2 is, for example, 10 / 2. That is, the design requirement for the second transistor Q2 is that the thickness of the second gate insulating layer 652 is sufficiently thin and the width of the second transistor Q2 is sufficiently wide. This ensures that after the channel of the second transistor Q2 is melted, the resistance at the open position of the second transistor Q2 is sufficiently large, satisfying the characteristics of an open circuit. Therefore, after the channel of the second transistor Q2 is melted, this application can physically ensure that the connection between the faulty target circuit 20 and the first signal line 10 is completely cut off, thereby ensuring that the voltage on the first signal line 10 is not affected by the target circuit 20.

[0041] In some embodiments, see continue to see Figure 5 In the thickness direction of the display module, the first transistor Q1 is located between the second transistor Q2 and the second drive signal line 52.

[0042] The second drive signal line 52 is located between the buffer layer 62 and the first insulating layer 63.

[0043] For example, since the second drive signal line 52 is used to provide a high-voltage pulse signal to the first gate of the second transistor Q2 to achieve the melting of the second transistor Q2, in order to avoid the high-voltage pulse signal provided by the second drive signal line 52 from affecting other film layers or signal lines, the second drive signal line 52 is disposed in the first insulating layer 63 or the buffer layer 62, or disposed between the buffer layer 62 and the first insulating layer 63, so that the second drive signal line 52 is staggered from the upper layer traces, thereby reducing the interlayer coupling between the second drive signal line 52 and other film layers or signal lines.

[0044] In some embodiments, the target circuit includes a pixel driving circuit, see below. Figure 2The pixel driving circuit includes a storage capacitor C1, a driving transistor M1, a threshold compensation transistor M2, a reset transistor M3, an initialization transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a data writing transistor M7.

[0045] like Figure 2 As shown in Figure A, the reset transistor M3 can be reused as the second transistor Q2. The gate of the driving transistor M1 is connected to the second terminal of the reset transistor M3. The first terminal of the reset transistor M3 is connected to the first signal line 10. The gate of the reset transistor M3 is connected to the first scan line Scan1. The gate of the reset transistor M3 is also connected to the second terminal of the first transistor Q1. The gate of the first transistor Q1 is connected to the first driving signal line 51. The first terminal of the first transistor Q1 is connected to the second driving signal line 52.

[0046] like Figure 2 As shown in Figure B, the reset transistor M3 and the second transistor Q2 are not multiplexed. The gate of the driving transistor M1 is connected to the second terminal of the reset transistor M3. The first terminal of the reset transistor M3 is connected to the second terminal of the second transistor Q2. The first terminal of the second transistor Q2 is connected to the first signal line 10. The gate of the reset transistor M3 is connected to the first scan line Scan1. The gate of the second transistor Q2 is connected to the second terminal of the first transistor Q1. The gate of the first transistor Q1 is connected to the first driving signal line 51. The first terminal of the first transistor Q1 is connected to the second driving signal line 52.

[0047] The first terminal of driving transistor M1 is connected to the first power signal line VDD via the first light-emitting control transistor M5. The gates of both the first and second light-emitting control transistors M5 and M6 are connected to the light-emitting control signal line EM. The second terminal of driving transistor M1 is connected to the positive terminal of light-emitting sub-pixel D1 via the second light-emitting control transistor M6, and the negative terminal of light-emitting sub-pixel D1 is connected to the second power signal line VSS. The gate of initialization transistor M4 is connected to the first scan line Scan1, the first terminal of initialization transistor M4 is connected to the first signal line 10, and the second terminal of initialization transistor M4 is connected to the positive terminal of light-emitting sub-pixel D1. The gates of threshold compensation transistor M2 and data writing transistor M7 are both connected to the second scan line Scan2. The first terminal of threshold compensation transistor M2 is connected to the first power signal line VDD via the storage capacitor C1, and the second terminal of threshold compensation transistor M2 is connected to the data signal line Data via the data writing transistor M7. Both threshold compensation transistor M2 and reset transistor M3 are dual-gate transistors. The first signal line 10 is the initial voltage signal line vref.

[0048] Figure 6This is a schematic diagram of the layout of a pixel driving circuit provided in an embodiment of this application, such as... Figure 6 As shown, the polysilicon active layer 70 overlaps with the first scan line Scan1 to form the gate of the initialization transistor M4. The polysilicon active layer 70 also overlaps with the first scan line Scan1 to form the first gate and the second gate of the reset transistor M3. The polysilicon active layer 70 overlaps with the second scan line Scan2 to form the gate of the data writing transistor M7. The polysilicon active layer 70 also overlaps with the second scan line Scan2 to form the first gate and the second gate of the threshold compensation transistor M2. The polysilicon active layer 70 overlaps with the light emission control signal line EM to form the gate of the first light emission control transistor M5 and the gate of the second light emission control transistor M6. The first metal layer 71 forms the first scan line Scan1 and the second scan line Scan2, and serves as the gate layer for the driving transistor M1, the threshold compensation transistor M2, the reset transistor M3, the initialization transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6, and the data writing transistor M7. The second metal layer 72 and the third metal layer 73 are used to form the first power supply signal line VDD, the light-emitting control signal line EM, and the first signal line 10.

[0049] See also Figure 6 The attached figure is labeled AA'. Figure 5 It can be in Figure 6 The cross-sectional view at reference AA' in the attached figure.

[0050] In some embodiments, the second transistor Q2 further includes a second gate connected to the first scan line Scan1.

[0051] For example, when the pixel driving circuit experiences a short circuit fault, such as a short circuit in the storage capacitor C1, the first signal line 10 will be connected to the first power signal line VDD through the conducting reset transistor M3. This will cause the voltage on the first signal line 10 to be affected by the voltage on the first power signal line VDD, thereby causing the voltage received by other circuits connected to the first signal line 10 through the first signal line 10 to change.

[0052] The second transistor Q2 reuses the gate of the reset transistor M3. When the first gate of the second transistor Q2 receives a high-voltage pulse signal provided by the second drive signal line 52, the channel of the second transistor Q2 is melted, thereby completely disconnecting the connection between the reset transistor M3 and the first signal line 10. That is, the reset transistor M3 cannot conduct, and the connection between the first signal line 10 and the first power supply signal line VDD through the faulty pixel drive circuit is broken, and the voltage on the first signal line 10 returns to normal. At the same time, the gate of the drive transistor M1 can no longer receive the signal provided by the first signal line 10 through the conducting reset transistor M3, so the drive transistor M1 cannot drive the corresponding light-emitting sub-pixel D1 to emit light. This avoids the faulty pixel driving circuit from affecting the voltage on the first signal line 10, and also avoids the faulty pixel driving circuit from driving the corresponding light-emitting sub-pixels to emit light. Thus, this application can avoid voltage abnormalities on the first signal line 10 due to connection with the faulty pixel driving circuit, thereby enabling the second transistor Q2 to repair the voltage abnormality of the first signal line 10 in the display module after the pixel driving circuit fails, so that the display module can display normally.

[0053] In some embodiments, see continue to see Figure 5 as well as Figure 6 In the thickness direction of the display module, the first gate and the second gate of the second transistor Q2 are located on both sides of its active layer, respectively.

[0054] For example, the active layer of the second transistor Q2 is located on the second semiconductor layer 653, the first gate of the second transistor Q2 is located on the side of the second semiconductor layer 653 close to the substrate 61, and the second gate of the second transistor Q2 is located on the side of the second semiconductor layer 653 away from the substrate 61. A third gate insulating layer 654 is disposed between the second gate of the second transistor Q2 and the second semiconductor layer 653, and a second gate insulating layer 652 is disposed between the first gate of the second transistor Q2 and the second semiconductor layer 653.

[0055] The second gate of the second transistor Q2 reuses the gate of the reset transistor M3 and is connected to the first scan line Scan1. The first gate of the second transistor Q2 is connected to the first transistor Q1. The first gate of the second transistor Q2 is used to receive the high-voltage pulse signal provided by the second drive signal line 52 when the first transistor Q1 is turned on, and to melt both the first and second gates of the second transistor Q2. Since the second gate of the second transistor Q2 is reused from the gate of the reset transistor M3, it can also melt the gate of the reset transistor M3, thereby physically cutting off the connection between the first signal line 10 and the faulty pixel drive circuit.

[0056] In some embodiments, Figure 7 This is a schematic diagram of the structure of another display module provided in an embodiment of this application, as shown below. Figure 7 As shown, the first signal line 10 includes a first sub-signal line 11 and a second sub-signal line 12. The first sub-signal line 11 extends along a first direction Y, and the second sub-signal line 12 extends along a second direction X. The first direction Y and the second direction X intersect.

[0057] The first sub-signal line 11 is electrically connected to the second sub-signal line 12.

[0058] For example, the display module includes a plurality of first signal lines 10, each first signal line 10 including a first sub-signal line 11 and a second sub-signal line 12, such as Figure 7 As shown, the first direction Y and the second direction X are perpendicular to each other. Therefore, the multiple first sub-signal lines 11 of the display module are arranged sequentially along the first direction Y, and the multiple second sub-signal lines 12 are arranged sequentially along the second direction X, so that the multiple first sub-signal lines 11 and the multiple second sub-signal lines 12 form a mesh structure.

[0059] In some embodiments, see continue to see Figure 7 The target circuit 20 also includes multiple sub-target circuits 21.

[0060] For example, each first sub-signal line 11 is connected to a plurality of sub-target circuits 21 in the second direction X, and each second sub-signal line 12 is connected to a plurality of first sub-signal lines 11 in the first direction Y.

[0061] The detection trigger circuit 40 includes a detection module 41.

[0062] The detection module 41 is configured to detect the voltage of a plurality of first sub-signal lines 11 to identify a sub-target circuit 21 that has failed in the first direction Y; the detection module 41 is also configured to detect the voltage of a plurality of second sub-signal lines 12 to identify a sub-target circuit 21 that has failed in the second direction X.

[0063] For example, the detection module 41 is used to detect the voltage of multiple first sub-signal lines 11 and multiple second sub-signal lines 12, and determine the first sub-signal lines 11 and second sub-signal lines 12 with abnormal voltage based on the voltage detection results, thereby determining the faulty sub-target circuit 21. For example, the multiple first sub-signal lines 11 can be sequentially labeled as Y1, Y2, Y3...Yn, and the multiple second sub-signal lines 12 can be sequentially labeled as X1, X2, X3...Xn.

[0064] If the detection module 41 detects an anomaly in the first sub-signal line 11 marked Y3, then it can be determined that a faulty sub-target circuit exists among the multiple sub-target circuits 21 on the third first sub-signal line 11 in the first direction Y. Similarly, if the detection module 41 detects an anomaly in the second sub-signal line 12 marked X2, then it can be determined that a faulty sub-target circuit exists among the multiple sub-target circuits 21 on the second second sub-signal line 12 in the second direction X. Therefore, it can be further determined that the sub-target circuit 21 connected to both the third first sub-signal line 11 and the second second sub-signal line 12 is the faulty sub-target circuit 21.

[0065] If the detection module 41 detects an anomaly in the first sub-signal line 11 marked Y2 and Y3, then it can be determined that among the multiple sub-target circuits 21 on the second and third first sub-signal lines 11 in the first direction Y, there is a faulty sub-target circuit 21. If the detection module 41 detects an anomaly in the second sub-signal line 12 marked X2, then it can be determined that among the multiple sub-target circuits 21 on the second second sub-signal line 12 in the second direction X, there is a faulty sub-target circuit. Therefore, it can be further determined that the sub-target circuit 21 connected to both the second first sub-signal line 11 and the second second sub-signal line 12, as well as the sub-target circuit 21 connected to both the third first sub-signal line 11 and the second second sub-signal line 12, are faulty sub-target circuits 21.

[0066] Therefore, this application can accurately locate the position of one or more faulty sub-target circuits 21, and then control the fuse circuit 30 to cut off the connection between the faulty sub-target circuit 21 and the first sub-signal line 11 and the second sub-signal line 12, thereby ensuring that the voltage of the first sub-signal line 11 and the second sub-signal line 12 can be maintained at normal voltage, and avoiding the situation where other sub-target circuits 21 will malfunction due to abnormal voltage of the first sub-signal line 11 and the second sub-signal line 12.

[0067] In some embodiments, see continue to see Figure 7 The detection module 41 includes at least two detection units.

[0068] The at least two detection units include: a first detection unit 411 and a second detection unit 412.

[0069] The first detection unit 411 is connected to a plurality of first sub-signal lines 11, and the second detection unit 412 is connected to a plurality of second sub-signal lines 12.

[0070] The first detection unit 411 is configured to detect the voltage of a plurality of first sub-signal lines 11 to determine the sub-target circuit 21 that has failed in the first direction Y; the second detection unit 412 is configured to detect the voltage of the second sub-signal lines 12 to determine the sub-target circuit 21 that has failed in the second direction X.

[0071] For example, the first detection unit 411 and the second detection unit 412 may be, for example, miniature voltage comparators.

[0072] For example, multiple first sub-signal lines 11 can be sequentially labeled as Y1, Y2, Y3...Yn, and multiple second sub-signal lines 12 can be sequentially labeled as X1, X2, X3...Xn.

[0073] The first detection unit 411 is used to detect the voltage of multiple first sub-signal lines 11, and the second detection unit 412 is used to detect the voltage of multiple second sub-signal lines 12. If the first detection unit 411 detects an abnormality in the first sub-signal line 11 marked Y1, it can be determined that a faulty sub-target circuit 21 exists among the multiple sub-target circuits 21 on the first first sub-signal line 11 in the first direction Y. Furthermore, if the second detection unit 412 detects an abnormality in the second sub-signal line 12 marked X2, it can be determined that a faulty sub-target circuit 21 exists among the multiple sub-target circuits 21 on the second second sub-signal line 12 in the second direction X. Therefore, it can be further determined that the sub-target circuit 21 connected to both the first first sub-signal line 11 and the second second sub-signal line 12 is a faulty sub-target circuit 21.

[0074] Therefore, this application can detect the faulty sub-target circuit 21 in the first direction Y through the first detection unit 411 and the faulty sub-target circuit 21 in the second direction X through the second detection unit 412. This allows for precise location of one or more faulty sub-target circuits 21. Furthermore, the connection between the faulty sub-target circuit 21 and the first sub-signal line 11 and the second sub-signal line 12 can be cut off by controlling the fuse circuit 30. This ensures that the voltage of the first sub-signal line 11 and the second sub-signal line 12 can be maintained at normal voltage, and avoids the abnormal operation of other sub-target circuits 21 due to the abnormal voltage of the first sub-signal line 11 and the second sub-signal line 12.

[0075] In some embodiments, the first detection unit 411 is configured to detect the voltage of a plurality of first sub-signal lines 11 to determine the first sub-signal line 11 among the plurality of first sub-signal lines 11 whose voltage is greater than a first voltage threshold.

[0076] The second detection unit 412 is configured to detect the voltage of a plurality of second sub-signal lines 12 to determine the second sub-signal line 12 among the plurality of second sub-signal lines 12 whose voltage is greater than a second voltage threshold.

[0077] For example, the voltages on multiple first sub-signal lines 11 are acquired, and the global voltage of the multiple first sub-signal lines 11 is calculated. The global voltage of the multiple first sub-signal lines 11 is used as a first voltage threshold. The voltages on multiple second sub-signal lines 12 are acquired, and the acquired global voltage of the multiple second sub-signal lines 12 is calculated. The global voltage of the multiple second sub-signal lines 12 is used as a second voltage threshold. The global voltage can be, for example, the average or median of the acquired voltages. Using the global voltage of the multiple first sub-signal lines 11 as the first voltage threshold and the global voltage of the multiple second sub-signal lines 12 as the second voltage threshold, when the voltages on all the first sub-signal lines 11 and second sub-signal lines 12 fluctuate together, the global voltage also changes accordingly, and the voltage threshold also changes accordingly. This avoids the situation where, when the voltages on all the first sub-signal lines 11 and second sub-signal lines 12 fluctuate together, a voltage anomaly is detected even though there is no voltage anomaly on the first sub-signal lines 11 and second sub-signal lines 12, due to a fixed voltage threshold.

[0078] When the first detection unit 411 detects that the voltage of a certain first sub-signal line 11 is greater than a first voltage threshold, it determines that a faulty sub-target circuit 21 is connected to that first sub-signal line 11. When the second detection unit 412 detects that the voltage of a certain second sub-signal line 12 is greater than a second voltage threshold, it determines that a faulty sub-target circuit 21 is connected to that second sub-signal line 12. This allows for the determination of the position of the faulty sub-target circuit 21 in the first direction Y and the second direction X, thereby enabling precise location of the faulty sub-target circuit 21.

[0079] In some embodiments, see continue to see Figure 7 At least two detection units also include a third detection unit 413.

[0080] The third detection unit 413 is connected to a plurality of first sub-signal lines 11; the third detection unit 413 is configured to detect the voltage of the plurality of first sub-signal lines 11 to determine the sub-target circuit 21 that has failed in a first direction.

[0081] For example, by simultaneously detecting the voltage of multiple first sub-signal lines 11 using the first detection unit 411 and the third detection unit 413, the problem of failing to detect the voltage of multiple first sub-signal lines 11 in the event of a detection unit failure can be avoided. Therefore, this application improves the fault tolerance capability during the voltage detection process of multiple first sub-signal lines 11, thereby ensuring the automatic repair capability of the display module and avoiding the problem of the display module being unable to automatically repair itself due to the inability to detect voltage normally. Furthermore, using the first detection unit 411 and the third detection unit 413 to simultaneously detect the voltage of multiple first sub-signal lines 11 makes the detected voltage information more accurate, thereby improving the voltage detection accuracy of multiple first sub-signal lines 11 and thus enabling more precise location of the faulty sub-target circuit 21.

[0082] In some embodiments, at least two detection units further include a fourth detection unit.

[0083] The fourth detection unit is connected to multiple second sub-signal lines; the fourth detection unit is configured to detect the voltage of the multiple second sub-signal lines to determine the sub-target circuit that has failed in the second direction.

[0084] For example, by simultaneously detecting the voltage of multiple second sub-signal lines using both the second and fourth detection units, the problem of failing to detect the voltage of multiple second sub-signal lines in the event of a detection unit failure can be avoided. Therefore, this application improves the fault tolerance during the voltage detection process of multiple second sub-signal lines, thereby ensuring the automatic repair capability of the display module and preventing the display module from failing to automatically repair itself due to the inability to detect voltage correctly. Furthermore, using both the second and fourth detection units to simultaneously detect the voltage of multiple second sub-signal lines makes the detected voltage information more accurate, thereby improving the voltage detection accuracy of multiple second sub-signal lines and enabling more precise location of the faulty sub-target circuit.

[0085] In some embodiments, see continue to see Figure 7 The detection trigger circuit 40 also includes a control unit 42 and a trigger unit 43.

[0086] The control unit 42 is connected to at least two detection units and a trigger unit 43.

[0087] For example, the control unit 42 may be connected to the first detection unit 411 and the second detection unit 412, and the control unit 42 may also be connected to the first detection unit 411, the second detection unit 412 and the third detection unit 413, and the control unit 42 may also be connected to the second detection unit 412 and the third detection unit 413.

[0088] Preferred, such as Figure 7 As shown, the control unit 42 is electrically connected to the trigger unit 43, the first detection unit 411, the second detection unit 412, and the third detection unit 413.

[0089] The control unit 42 is used to determine the faulty sub-target circuit 21 based on the first sub-signal line 11 and the second sub-signal line 12 of the voltage abnormality; the control unit 42 is also used to control the triggering unit 43 to provide a trigger signal to the fuse circuit corresponding to the faulty sub-target circuit 21 so as to control the fuse circuit to open.

[0090] For example, the first detection unit 411 and the third detection unit 413 detect the voltage on multiple first sub-signal lines 11 and provide the detected abnormal information to the control unit 42. The second detection unit 412 detects the voltage on multiple second sub-signal lines 12 and provides the detected abnormal information to the control unit 42. Based on the marking information of the first sub-signal lines 11 with abnormal voltage and the marking information of the second sub-signal lines 12 with abnormal voltage, the control unit 42 can further determine the location information of the faulty sub-target circuit 21. The control unit 42 then controls the triggering unit 43 to provide a trigger signal to the fuse module corresponding to the faulty sub-target circuit 21 based on the location information of the faulty sub-target circuit 21. Upon receiving the trigger signal, the fuse circuit cuts off the connection between the faulty sub-target circuit 21 and the first sub-signal line 11 and the second sub-signal line 12. This allows the voltage on the first sub-signal line 11 and the second sub-signal line 12 to return to normal after the faulty sub-target circuit 21 affects the voltage on the first sub-signal line 11 and the second sub-signal line 12. This achieves automatic repair of the first sub-signal line 11 and the second sub-signal line 12, thereby achieving automatic repair of the display module and enabling the display module to display normally.

[0091] In some embodiments, see continue to see Figure 4 as well as Figure 7 The triggering unit 43 includes a first sub-triggering unit 431 and a second sub-triggering unit 432.

[0092] The first sub-trigger unit 431 is connected to the first drive signal line 51, and the second sub-trigger unit 432 is connected to the second drive signal line 52.

[0093] The first sub-trigger unit 431 is used to provide a first driving signal to the first driving signal line 51, and the second sub-trigger unit 432 is used to provide a second driving signal to the second driving signal line 52.

[0094] The first drive signal is used to control the first transistor Q1 of the fuse circuit to turn on; the second drive signal is used to blow the channel of the second transistor Q2 of the fuse circuit.

[0095] For example, the first sub-trigger unit 431 is connected to a plurality of first drive signal lines 51, which are arranged sequentially along the first direction Y. The first drive signal lines 51 are connected to the gates of the first transistors Q1 of the fuse circuits corresponding to the plurality of sub-target circuits 21 in the second direction X. When the first sub-trigger unit 431 receives a control signal provided by the control unit 42, it causes the first drive signal line 51 connected to the faulty sub-target circuit 21 to provide a first drive signal.

[0096] The second sub-trigger unit 432 is connected to a plurality of second drive signal lines 52, which are arranged sequentially along the second direction X. Each second drive signal line 52 is connected in the first direction Y to the first terminal of the first transistor Q1 of the fuse circuit corresponding to the plurality of sub-target circuits 21. The second terminal of the first transistor Q1 is connected to the first gate of the second transistor Q2. When the first transistor Q1 is turned on, the second drive signal line 52 is connected to the first gate of the second transistor Q2. Upon receiving a control signal from the control unit 42, the second sub-trigger unit 432 causes the second drive signal line 52 connected to the faulty sub-target circuit 21 to provide a second drive signal.

[0097] The first sub-trigger unit 431 provides a first drive signal to the first drive signal line 51 connected to the faulty sub-target circuit 21. Therefore, the first transistor Q1 of the fuse circuits on multiple sub-target circuits 21 connected to the faulty sub-target circuit 21 via the same first drive signal line 51 is turned on. Simultaneously, the second sub-trigger unit 432 provides a second drive signal to the second drive signal line 52 connected to the faulty sub-target circuit 21. Therefore, although the fuse circuits on multiple sub-target circuits 21 connected to the faulty sub-target circuit 21 via the same second drive signal line 52 will all receive the second drive signal, only the first gate of the second transistor Q2 in the fuse circuit where the first transistor Q1 is turned on will receive the second drive signal. The second sub-trigger unit 432 is a high-voltage charge pump, and the second drive signal is a high-voltage pulse signal provided by the high-voltage charge pump. After receiving the high-voltage pulse signal, the gate oxide layer of the second transistor Q2 is broken down, causing a momentary high temperature to be generated within a small area, thereby causing the channel of the second transistor Q2 to melt. Therefore, this application can accurately melt the fuse corresponding to the faulty sub-target circuit 21, without melting the fuse corresponding to the non-faulty sub-target circuit 21. This avoids the problem of multiple sub-target circuits 21 malfunctioning due to the disconnection of other non-faulty sub-target circuits 21 from the first sub-signal line 11 and the second sub-signal line 12, thereby preventing display abnormalities in the display module.

[0098] Figure 8 This is a flowchart illustrating an automatic repair method for a display module provided in an embodiment of this application. The automatic repair method is applied to the display module provided in any of the above embodiments.

[0099] See Figure 7 The plurality of first signal lines 10 include a plurality of first sub-signal lines 11 and a plurality of second sub-signal lines 12; the target circuit 20 includes a plurality of sub-target circuits 21.

[0100] The detection trigger circuit of the display module includes a first detection unit 411 and a second detection unit 412.

[0101] like Figure 8 As shown, the automatic repair methods include: S110-S130.

[0102] S110. Obtain the first sub-signal line of voltage abnormality determined by the first detection unit, and the second sub-signal line of voltage abnormality determined by the second detection unit.

[0103] For example, a first detection unit is used to detect the voltage of multiple first sub-signal lines, and a second detection unit is used to detect the voltage of multiple second sub-signal lines. For instance, if the sub-target circuit is a pixel driving circuit, and the fault occurs due to a short circuit in the storage capacitor of the pixel driving circuit, this may cause the first and second sub-signal lines to connect to the power signal line, resulting in a change in the voltage on the first and second sub-signal lines. After detecting a first sub-signal line with an abnormal voltage among the multiple first sub-signal lines, the first detection unit provides the information of the abnormal first sub-signal line to the control unit. Similarly, after detecting a second sub-signal line with an abnormal voltage among the multiple second sub-signal lines, the second detection unit provides the information of the abnormal second sub-signal line to the control unit. Thus, the control unit can obtain the first sub-signal line with an abnormal voltage determined by the first detection unit and the second sub-signal line with an abnormal voltage determined by the second detection unit.

[0104] S120. Based on the first and second sub-signal lines with abnormal voltage, determine the faulty sub-target circuit.

[0105] For example, multiple first sub-signal lines can be sequentially labeled Y1, Y2, Y3...Yn in a first direction, and multiple second sub-signal lines can be sequentially labeled X1, X2, X3...Xn in a second direction. If the first detection unit detects an abnormality in the first sub-signal line labeled Y1, the control unit can determine that a faulty sub-target circuit exists among the multiple sub-target circuits on the first first sub-signal line in the first direction. Furthermore, if the second detection unit detects an abnormality in the second sub-signal line labeled X2, the control unit can determine that a faulty sub-target circuit exists among the multiple sub-target circuits on the second second sub-signal line in the second direction. Therefore, based on the voltage abnormality on the first first sub-signal line in the first direction and the voltage abnormality on the second second sub-signal line in the second direction, the control unit can further determine that the sub-target circuit connected to both the first first sub-signal line and the second second sub-signal line is a faulty sub-target circuit.

[0106] S130, the fuse circuit corresponding to the faulty sub-target circuit is disconnected.

[0107] For example, after identifying a faulty sub-target circuit, the control unit controls the corresponding fuse circuit to open, thereby cutting off the connection between the faulty sub-target circuit and the first and second sub-signal lines. This prevents the faulty sub-target circuit from affecting the voltage on the first and second sub-signal lines. Therefore, this application can disconnect the connection between the faulty sub-target circuit and the first and second sub-signal lines after a sub-target circuit fails, restoring the voltage on the first and second sub-signal lines to normal. This allows other sub-target circuits connected to the first and second sub-signal lines to return to normal operation. Thus, this application achieves automatic repair of abnormal voltage on the first and second sub-signal lines in the display module through a fuse circuit after a sub-target circuit fails, enabling the display module to automatically repair display faults and restore normal display.

[0108] In some embodiments, see continue to see Figure 4 as well as Figure 7 The detection trigger circuit 40 also includes a first sub-trigger unit 431 and a second sub-trigger unit 432.

[0109] The fuse circuit includes a first transistor Q1 and a second transistor Q2; a first sub-trigger unit 431 is connected to the gate of the first transistor Q1, a second sub-trigger unit 432 is connected to the first terminal of the first transistor Q1, and the second terminal of the first transistor Q1 is connected to the first gate of the second transistor Q2.

[0110] S130 includes: controlling the second sub-trigger unit to provide a second drive signal, and controlling the first sub-trigger unit to provide a first drive signal, so as to turn on the first transistor corresponding to the faulty sub-target circuit.

[0111] The second drive signal is used to melt the channel of the second transistor.

[0112] For example, the first sub-trigger unit is connected to a plurality of first drive signal lines, which are arranged sequentially along a first direction. The first drive signal lines are connected to the gates of first transistors corresponding to the plurality of sub-target circuits in a second direction. Upon detecting a faulty sub-target circuit, the control unit controls the first drive signal lines connected to the faulty sub-target circuit to provide a first drive signal.

[0113] The second sub-trigger unit is connected to multiple second drive signal lines, which are arranged sequentially along a second direction. Each second drive signal line is connected in a first direction to the first terminal of a first transistor corresponding to one of the multiple sub-target circuits. The second terminal of the first transistor is connected to the first gate of a second transistor. When the first transistor is turned on, the second drive signal line is connected to the first gate of the second transistor. Upon detecting a faulty sub-target circuit, the control unit controls the second drive signal line connected to the faulty sub-target circuit to provide a second drive signal.

[0114] The first sub-trigger unit provides a first drive signal to the first drive signal line connected to the faulty sub-target circuit. Therefore, the first transistors corresponding to multiple sub-target circuits connected to the faulty sub-target circuit on the same first drive signal line are all turned on. Simultaneously, the second sub-trigger unit provides a second drive signal to the second drive signal line connected to the faulty sub-target circuit. Therefore, although the fuses on multiple sub-target circuits connected to the faulty sub-target circuit on the same second drive signal line will all receive the second drive signal, only the first gate of the second transistor in the fuse circuit where the first transistor is turned on will receive the second drive signal. The second sub-trigger unit is a high-voltage charge pump, and the second drive signal is a high-voltage pulse signal provided by the high-voltage charge pump. After receiving the high-voltage pulse signal, the gate oxide layer of the second transistor is broken down, causing a momentary high temperature to be generated within a small area, thereby causing the channel of the second transistor to melt. Therefore, this application can accurately blow the fuse corresponding to the faulty sub-target circuit without blowing the fuse corresponding to the non-faulty sub-target circuit. This avoids the problem of multiple sub-target circuits malfunctioning due to the disconnection of other non-faulty sub-target circuits from the first and second sub-signal lines, and thus avoids the display module from displaying abnormalities.

[0115] In some embodiments, the automatic repair method further includes: Based on the fact that the fuse circuit corresponding to the faulty sub-target circuit is opened, the first detection unit is controlled to compare the voltages of multiple first sub-signal lines, and the second detection unit is controlled to compare the voltages of multiple second sub-signal lines.

[0116] For example, after determining that the first sub-trigger unit provides a first drive signal to the first drive signal line connected to the faulty sub-target circuit, and the second sub-trigger unit provides a second drive signal to the second drive signal line connected to the faulty sub-target circuit, the control unit determines that the fuse circuit corresponding to the faulty sub-target circuit is open. The control unit continues to control the first detection unit to compare the voltages of multiple first sub-signal lines, and controls the second detection unit to compare the voltages of multiple second sub-signal lines.

[0117] Based on the comparison results of the voltages of multiple first sub-signal lines with the first voltage threshold, and the comparison results of the voltages of multiple second sub-signal lines with the second voltage threshold, it is determined whether the display module has completed automatic repair.

[0118] Wherein, the first voltage threshold is the global voltage of the plurality of first sub-signal lines; the second voltage threshold is the global voltage of the plurality of second sub-signal lines.

[0119] For example, after a repair is completed, the control unit controls the first detection unit to re-acquire the voltage of all the first sub-signal lines and recalculate the global voltage of the multiple first sub-signal lines, using the global voltage of the multiple first sub-signal lines as the new first voltage threshold. The control unit also controls the second detection unit to re-acquire the voltage of all the second sub-signal lines and recalculate the global voltage of the multiple second sub-signal lines, using the global voltage of the multiple second sub-signal lines as the new second voltage threshold.

[0120] The first detection unit compares the voltages of multiple first sub-signal lines with a first voltage threshold. If the voltage of any first sub-signal line is greater than the first voltage threshold, and the absolute value of the first voltage difference between the voltage of the first sub-signal line and the first voltage threshold is greater than a first difference threshold, the first detection unit determines that there is still a first sub-signal line with abnormal voltage among the multiple first sub-signal lines. The second detection unit compares the voltages of multiple second sub-signal lines with a second voltage threshold. If the voltage of any second sub-signal line is greater than the second voltage threshold, and the absolute value of the second voltage difference between the voltage of the second sub-signal line and the second voltage threshold is greater than a second difference threshold, the second detection unit determines that there is still a second sub-signal line with abnormal voltage among the multiple second sub-signal lines. Therefore, the control unit can further determine that the display module has not completed automatic repair and needs to continue to perform fuse-breaking operations on the faulty sub-target circuit through the first and second sub-trigger units.

[0121] When the voltage of the first sub-signal line is less than the first voltage threshold and the voltage of the second sub-signal line is less than the second voltage threshold, the control unit can determine that the display module has completed automatic repair.

[0122] In some embodiments, Figure 9 A flowchart illustrating another automatic repair method for a display module provided in this application embodiment is shown below. Figure 9 As shown, before S110, the automatic repair method also includes S140 and S150.

[0123] S140. Based on the fact that the number of times the voltage of any first sub-signal line detected by the first detection unit is greater than the first voltage threshold is greater than the number threshold, the first sub-signal line with abnormal voltage determined by the first detection unit is obtained.

[0124] S150: Based on the fact that the number of times the voltage of any second sub-signal line detected by the second detection unit is greater than the second voltage threshold is greater than the number threshold, the second sub-signal line with abnormal voltage determined by the second detection unit is obtained.

[0125] For example, after the first detection unit detects that the voltage of any of the multiple first sub-signal lines is greater than the first voltage threshold, the first detection unit will detect the voltage of the multiple first sub-signal lines again until it is determined that the number of times the voltage of a certain first sub-signal line is greater than the first voltage threshold is greater than the number of times. The control unit determines that the first sub-signal line is a first sub-signal line with abnormal voltage through the first detection unit.

[0126] After the second detection unit detects that the voltage of any of the multiple second sub-signal lines is greater than the second voltage threshold, the second detection unit will detect the voltage of the multiple second sub-signal lines again until it is determined that the number of times the voltage of a certain second sub-signal line is greater than the second voltage threshold is greater than the number of times. The control unit determines that the second sub-signal line is a second sub-signal line with abnormal voltage through the second detection unit.

[0127] The number of attempts threshold could be, for example, three.

[0128] This application uses a first detection unit to perform multiple voltage checks on multiple first sub-signal lines before identifying the first sub-signal lines with abnormal voltage, and a second detection unit to perform multiple voltage checks on multiple second sub-signal lines before identifying the second sub-signal lines with abnormal voltage. Since voltage fluctuations may cause some first and second sub-signal lines to exceed their corresponding voltage thresholds even if they do not exhibit abnormal voltage behavior, this application uses multiple voltage checks to identify the signal lines with abnormal voltage. This avoids misjudging faulty sub-target circuits that are not actually faulty, thereby further improving the accuracy of identifying faulty sub-target circuits.

[0129] It should be noted that the threshold of three times is only an example, and the specific value of the threshold will be determined in actual circumstances, and no specific limit is made here.

[0130] This application also provides a display device, including the display module provided in this application. Please refer to... Figure 10 , Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 The provided display device 1000 includes the display module 100 provided in any of the above embodiments of this application. Figure 10 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display module provided in this application embodiment. For details, please refer to the specific descriptions of the display module in the above embodiments; these will not be repeated here.

[0131] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display module, characterized in that, include: First signal line; Target circuit; A fuse circuit is provided, through which the first signal line is electrically connected to the target circuit. In the event of a fault in the target circuit, the fuse circuit is disconnected.

2. The display module according to claim 1, characterized in that, It also includes a detection trigger circuit; The detection trigger circuit is connected to the first signal line and is configured to detect the voltage of the first signal line to determine whether the target circuit has failed, and to trigger the fuse circuit to open if the target circuit has failed.

3. The display module according to claim 1 or 2, characterized in that, The fuse circuit includes a first transistor and a second transistor; The gate of the first transistor is connected to the first driving signal line, the first terminal of the first transistor is connected to the second driving signal line, the second terminal of the first transistor is connected to the first gate of the second transistor, the first terminal of the second transistor is connected to the first signal line, and the second terminal of the second transistor is connected to the target circuit. In the event of a fault in the target circuit, the first transistor is turned on, and a second drive signal on the second drive signal line is transmitted to the first gate of the second transistor, thereby melting the channel of the second transistor.

4. The display module according to claim 3, characterized in that, In the thickness direction of the display module, a first gate insulating layer is disposed between the gate of the first transistor and the active layer of the first transistor, and a second gate insulating layer is disposed between the first gate of the second transistor and the active layer of the second transistor, wherein the thickness of the second gate insulating layer is less than the thickness of the first gate insulating layer.

5. The display module according to claim 3, characterized in that, The channel width-to-length ratio of the second transistor is greater than that of the first transistor.

6. The display module according to claim 3, characterized in that, In the thickness direction of the display module, the first transistor is located between the second transistor and the second drive signal line.

7. The display module according to claim 3, characterized in that, The display module includes a substrate and, in sequence away from the substrate, a buffer layer, a first insulating layer, a first semiconductor layer, a first gate insulating layer, a first gate layer, a second insulating layer, a second gate layer, a second gate insulating layer, and a second semiconductor layer; The active layer of the first transistor is located in the first semiconductor layer, and the gate of the first transistor is located in the first gate layer; The active layer of the second transistor is located in the second semiconductor layer, and the first gate of the second transistor is located in the second gate layer.

8. The display module according to claim 7, characterized in that, The second drive signal line is located between the buffer layer and the first insulating layer.

9. The display module according to claim 3, characterized in that, The target circuit includes a pixel driving circuit, which includes a driving transistor, and the second terminal of the second transistor is electrically connected to the gate of the driving transistor.

10. The display module according to claim 9, characterized in that, The second transistor also includes a second gate, which is connected to the first scan line.

11. The display module according to claim 10, characterized in that, In the thickness direction of the display module, the first gate and the second gate of the second transistor are located on both sides of its active layer, respectively.

12. The display module according to claim 2, characterized in that, The first signal line includes a first sub-signal line and a second sub-signal line, the first sub-signal line extending along a first direction and the second sub-signal line extending along a second direction; the first direction and the second direction intersect. The first sub-signal line is electrically connected to the second sub-signal line.

13. The display module according to claim 12, characterized in that, The target circuit includes multiple sub-target circuits; The detection trigger circuit includes a detection module; The detection module is configured to detect the voltage of a plurality of the first sub-signal lines to determine the sub-target circuit that has failed in the first direction; The detection module is also configured to detect the voltage of a plurality of second sub-signal lines to identify the sub-target circuit that has failed in the second direction.

14. The display module according to claim 13, characterized in that, The detection module includes at least two detection units; The at least two detection units include: a first detection unit and a second detection unit; The first detection unit is connected to a plurality of first sub-signal lines, and the second detection unit is connected to a plurality of second sub-signal lines; The first detection unit is configured to detect the voltage of a plurality of first sub-signal lines to determine the sub-target circuit that has failed in the first direction; the second detection unit is configured to detect the voltage of the second sub-signal lines to determine the sub-target circuit that has failed in the second direction.

15. The display module according to claim 14, characterized in that, The first detection unit is configured to detect the voltage of a plurality of first sub-signal lines to determine the first sub-signal line among the plurality of first sub-signal lines whose voltage is greater than a first voltage threshold; The second detection unit is configured to detect the voltage of a plurality of second sub-signal lines to determine the second sub-signal line among the plurality of second sub-signal lines whose voltage is greater than a second voltage threshold; Wherein, the first voltage threshold is the global voltage of the plurality of first sub-signal lines; the second voltage threshold is the global voltage of the plurality of second sub-signal lines.

16. The display module according to claim 14, characterized in that, The at least two detection units also include a third detection unit; The third detection unit is connected to multiple first sub-signal lines; The third detection unit is configured to detect the voltage of a plurality of the first sub-signal lines to identify the sub-target circuit that has failed in the first direction.

17. The display module according to claim 14 or 16, characterized in that, The detection triggering circuit also includes a control unit and a triggering unit; The control unit is connected to the at least two detection units and the triggering unit; The control unit is used to determine the faulty sub-target circuit based on the first sub-signal line and the second sub-signal line with abnormal voltage; the control unit is also used to control the triggering unit to provide a trigger signal to the fuse circuit corresponding to the faulty sub-target circuit, so as to control the fuse circuit to open.

18. The display module according to claim 17, characterized in that, The triggering unit includes a first sub-triggering unit and a second sub-triggering unit; The first sub-trigger unit is connected to the first drive signal line, and the second sub-trigger unit is connected to the second drive signal line; The first sub-trigger unit is used to provide a first drive signal to the first drive signal line, and the second sub-trigger unit is used to provide a second drive signal to the second drive signal line; The first driving signal is used to control the first transistor of the fuse circuit to turn on; the second driving signal is used to melt the channel of the second transistor of the fuse circuit.

19. An automatic repair method for a display module, characterized in that, Applied to the display module as described in any one of claims 1-18; The first signal line includes a first sub-signal line and a second sub-signal line; the target circuit includes multiple sub-target circuits; The detection triggering circuit of the display module includes a first detection unit and a second detection unit; The method includes: The first sub-signal line of voltage abnormality determined by the first detection unit and the second sub-signal line of voltage abnormality determined by the second detection unit are acquired. Based on the first and second sub-signal lines with abnormal voltage, the faulty sub-target circuit is determined. The fuse circuit corresponding to the sub-target circuit that caused the malfunction is disconnected.

20. The automatic repair method according to claim 19, characterized in that, The detection triggering circuit further includes a first sub-trigger unit and a second sub-trigger unit; The fuse circuit includes a first transistor and a second transistor; the first sub-trigger unit is connected to the gate of the first transistor, the second sub-trigger unit is connected to the first terminal of the first transistor, and the second terminal of the first transistor is connected to the first gate of the second transistor; The fuse circuit corresponding to the sub-target circuit where the control malfunction occurred is disconnected, including: The second sub-trigger unit is controlled to provide a second drive signal, and the first sub-trigger unit is controlled to provide a first drive signal, so as to turn on the first transistor corresponding to the faulty sub-target circuit; The second drive signal is used to melt the channel of the second transistor.

21. The automatic repair method according to claim 19, characterized in that, The method further includes: Based on the fact that the fuse circuit corresponding to the faulty sub-target circuit is opened, the first detection unit is controlled to compare the voltages of multiple first sub-signal lines, and the second detection unit is controlled to compare the voltages of multiple second sub-signal lines. Based on the comparison results of the voltages of multiple first sub-signal lines with a first voltage threshold, and the comparison results of the voltages of multiple second sub-signal lines with a second voltage threshold, it is determined whether the display module has completed automatic repair. Wherein, the first voltage threshold is the global voltage of the plurality of first sub-signal lines; the second voltage threshold is the global voltage of the plurality of second sub-signal lines.

22. The automatic repair method according to claim 19, characterized in that, Before acquiring the first sub-signal line of voltage abnormality determined by the first detection unit and the second sub-signal line of voltage abnormality determined by the second detection unit, the method further includes: Based on the fact that the number of times the voltage of any first sub-signal line detected by the first detection unit is greater than the first voltage threshold is greater than the number threshold, the first sub-signal line with abnormal voltage determined by the first detection unit is obtained. Based on the fact that the second detection unit detects that the voltage of any second sub-signal line is greater than the second voltage threshold a number of times, the second sub-signal line with abnormal voltage determined by the second detection unit is obtained.

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