Storage array and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a storage array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of data storage. The memory array comprises a substrate and a plurality of memory cells, each memory cell in turn comprises a transistor, and the transistor in turn comprises a source electrode, a drain electrode, a grid electrode and a channel. Wherein the source electrode comprises a source electrode doped region formed in the substrate, the drain electrode comprises a metal silicide layer, the channel is located in the substrate, one side of the channel is in contact with the metal silicide layer, and the other side of the channel is in contact with the source electrode doped region. The grid electrode is arranged on the channel. One side of the metal silicide layer of the drain electrode is in contact with the channel, so that a Schottky junction can be formed between the metal silicide layer and the channel, the electric field intensity of the drain electrode region is increased, the voltage required for causing collision ionization is reduced, and the turn-on voltage and the driving energy consumption of the device are further reduced.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a storage array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] In traditional memory, such as Dynamic Random Access Memory (DRAM), the memory cell typically employs a one-transistor capacitor-less (1T1C) structure, meaning it includes one transistor and one capacitor. However, with the increasing integration density of semiconductor memory devices, this type of memory cell, which uses a capacitor to store charge, has become an obstacle to reducing the layout of semiconductor memory.

[0003] To achieve higher packaging density and integration, memory that uses transistors instead of capacitors to store data (i.e., capacitor-free memory) has been disclosed. Figure 1 This is a schematic diagram showing a cross-sectional view of a conventional capacitorless memory, which fabricates a PNP or NPN metal-oxide-semiconductor field-effect transistor (MOSFET) structure on a silicon on insulator (SOI) substrate, and can store and read charges through the floating body effect.

[0004] In traditional capacitor-free memories, highly doped regions are typically used in the source and drain regions to form ohmic contacts in order to reduce contact resistance. While this design helps reduce current loss as it passes through the contact regions, it also results in a higher turn-on voltage required to induce impact ionization, leading to higher drive power consumption. Summary of the Invention

[0005] This application provides a memory array and its fabrication method, a memory, and an electronic device. The aim is to reduce the turn-on voltage and drive power consumption of the device by increasing the electric field strength in the drain region to reduce the voltage required for impact ionization.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] On the one hand, this application provides a storage array, which may be a dynamic memory storage array or a static memory storage array.

[0008] The memory array includes a substrate and multiple memory cells, each memory cell including a transistor, the transistor including a source, a drain, a gate and a channel; the source includes a source doped region formed in the substrate; the drain includes a metal silicide layer, and a channel is formed in a region of the substrate between the source doped region and the metal silicide layer; the gate is disposed on the channel.

[0009] In the memory array provided in this application, the drain of the transistor in the memory cell includes a metal silicide layer. That is, the transistor in this application does not use a doped region to form the drain, but instead uses a drain containing a metal silicide layer. Simultaneously, this application also forms a channel in the region of the substrate located between the source doped region and the metal silicide layer. In other words, one side of the channel contacts the source doped region, and the other side contacts the metal silicide layer, allowing a Schottky junction to be formed between the metal silicide layer and the channel. Because the Schottky contact has a low barrier height and a high electric field strength, the electric field distribution in the drain region is more concentrated at the same voltage. This concentrated electric field distribution helps to enhance the impact ionization effect (i.e., charge carriers are more likely to collide with lattice atoms when moving in the channel, thereby generating new electron-hole pairs). This allows this application to induce a more significant impact ionization effect with a lower voltage, thus reducing the turn-on voltage required to cause impact ionization. Because Schottky contacts reduce the turn-on voltage required for impact ionization, the memory array can operate normally at a lower voltage, reducing the device's drive power consumption.

[0010] In one possible implementation, the metal silicide layer includes a first portion; the first portion is located on the side of the channel away from the source doped region.

[0011] That is, the metal silicide layer may include a first portion located on the side of the channel away from the source doped region. In this way, the first portion can be contacted and connected to the side of the channel away from the source doped region. By providing a first portion in contact with the channel, the interface between the first portion and the channel can form a Schottky contact, thereby increasing the electric field strength of the transistor in the drain region, thus enhancing the impact ionization effect. Consequently, the device reduces the turn-on voltage required to induce impact ionization, thereby reducing drive power consumption.

[0012] In one possible implementation, the metal silicide layer further includes a second portion; the second portion is located on the side of the channel away from the substrate, and the second portion is connected to the first portion.

[0013] That is, the metal silicide layer may also include a second portion located on the side of the channel away from the substrate. In this way, by connecting the second portion to the first portion, the electrical signal of the first portion can be led out through the second portion. This second portion can serve as a lead-out terminal of the metal silicide layer, which facilitates the lead-out of the electrical signal of the metal silicide layer. At the same time, retaining the second portion of the metal silicide layer on the side of the channel away from the substrate simplifies the fabrication process compared to the scheme of setting the first portion on the side of the channel away from the source doped region, but without the second portion on the side of the channel away from the substrate. This is also relatively easier to implement in the transistor fabrication process.

[0014] In one feasible manner, the second portion is spaced apart from the gate along a direction parallel to the surface of the substrate.

[0015] In other words, in this application, a gap may exist between the second portion and the gate along a direction parallel to the surface of the substrate. This is equivalent to designing a gateless, lightly doped, high-resistivity region between the drain and the gate, thereby increasing the resistance of this region and limiting current flow. Thus, when the memory is in the off state, the high-resistivity region created by the gap between the second portion and the gate effectively reduces leakage current in the off state, resulting in lower current density, lower static power consumption, and extended device lifespan. This allows the device provided in this application to be used in low-power devices.

[0016] In one possible implementation, the transistor also includes a gate insulating layer; the gate has a gate insulating layer between it and the channel.

[0017] That is, this application can isolate the gate and the channel through a gate insulating layer, thus preventing direct current flow. In this way, the transistor can control the magnitude of the current in the channel by adjusting the gate voltage, thereby inducing charge in the gate insulating layer and changing the width of the channel.

[0018] In one possible implementation, the first portion has a dielectric layer on the side opposite to the channel; the metal silicide layer also includes a third portion stacked between the dielectric layer and the substrate, the third portion being connected to the first portion.

[0019] This application, by incorporating a dielectric layer, allows the dielectric layer to act as an isolation layer between the transistor and the external environment, protecting the transistor from external impurities, moisture, and other corrosive substances, thereby improving the transistor's reliability and lifespan. By adding a third portion located between the dielectric layer and the substrate, the metal silicide layer between the substrate and the dielectric layer can be omitted during transistor fabrication, simplifying the fabrication process.

[0020] In one possible implementation, the source doped region is a P-type doped region, and the metal silicide layer includes a first metal material with a work function greater than or equal to 4.5 eV; or, the source doped region is an N-type doped region, and the metal silicide layer includes a second metal material with a work function less than or equal to 4.5 eV. That is, the transistors in the memory cells of the memory of this application can be either PMOS or NMOS devices. In practical applications, the specific transistor type can be selected based on the application scenario requirements.

[0021] In one feasible manner, when the source doped region is a P-type doped region, the first metal material includes at least one of titanium nitride, gold, ruthenium, nickel, platinum, cobalt, or tungsten; when the source doped region is an N-type doped region, the second metal material includes at least one of silver, scandium, titanium, aluminum, or erbium.

[0022] That is, when the source doping region is a P-type doped region, the first metal material of the metal silicide layer can be at least one of titanium nitride, gold, ruthenium, nickel, platinum, cobalt, or tungsten. Because these metals have good conductivity, they can reduce current loss during transmission, thereby improving circuit speed and performance. When the source doping region is an N-type doped region, the second metal material of the metal silicide layer can be at least one of silver, scandium, titanium, aluminum, or erbium. Because these metal materials typically have good chemical and physical stability in the silicide layer, they can resist high temperatures and chemical reactions, improving the reliability of the device in harsh environments.

[0023] In one feasible implementation, the memory cell comprises a 1T0C memory cell. Because the 1T0C memory cell has a relatively simple structure, it reduces material consumption and process steps during manufacturing, helping to lower production costs and manufacturing complexity. Simultaneously, more memory cells can be integrated onto a limited chip area, thereby increasing memory capacity and density. Furthermore, the simplified structure may reduce potential points of failure in the device, thus improving the reliability and stability of the memory cell.

[0024] On the other hand, this application provides a memory that includes a controller and a memory array in any of the above implementations. The controller is electrically connected to the memory array and is used to control the reading and writing of the memory array.

[0025] The memory provided in this application includes a memory array as described in any of the above implementations. Because it employs Schottky contacts at the drain of the transistors in the memory cells, it can induce a significant impact ionization effect at a lower voltage, thereby effectively reducing the turn-on voltage required to induce impact ionization. Since the Schottky contacts reduce the turn-on voltage required for impact ionization, the memory array can operate normally at a lower voltage, reducing the device's drive power consumption.

[0026] In another aspect, this application provides an electronic device including a processor and the aforementioned memory, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

[0027] The electronic device provided in this application includes the memory described above. Therefore, the electronic device provided in this application and the memory of the above technical solution can solve the same technical problem and achieve the same expected effect.

[0028] Furthermore, this application also provides a method for fabricating a memory array, the method comprising:

[0029] Multiple memory cells are fabricated on a substrate, each memory cell including a transistor;

[0030] The process of manufacturing a transistor includes:

[0031] A source electrode is fabricated, the source electrode including a source electrode doped region formed in the substrate;

[0032] A drain electrode is fabricated, which includes a metal silicide layer. The region of the substrate located between the source doped region and the metal silicide layer forms the channel of the transistor.

[0033] A gate is fabricated and disposed on the channel.

[0034] In the memory array fabricated using the method provided in this application, the drain of the transistor in the memory cell includes a metal silicide layer, and the region of the substrate between the source doped region and the metal silicide layer forms the channel of the transistor. That is, one side of the channel is in contact with the metal silicide layer, and the other side is in contact with the source doped region. Thus, a Schottky junction can be formed between the metal silicide layer and the channel. Because the Schottky contact has a low barrier height and a high electric field strength, the electric field distribution in the drain region is more concentrated at the same voltage. This helps to enhance the impact ionization effect, allowing this application to induce a more significant impact ionization effect with a lower voltage, thereby reducing the turn-on voltage required for impact ionization. In this way, the memory array fabricated using the method provided in this application can operate normally at a lower voltage, reducing the device's driving power consumption.

[0035] In one feasible approach, the fabrication method further includes the following steps before the transistor is produced:

[0036] Multiple isolated memory regions are defined on the substrate, with grooves between adjacent memory regions;

[0037] The process of fabricating transistors includes:

[0038] The source and drain electrodes are fabricated in the storage region;

[0039] The metal silicide layer is prepared by:

[0040] A first portion is formed on the wall of the groove near the channel, a third portion is formed on the wall of the groove near the substrate, a second portion is formed on the side of the channel away from the substrate, and the first portion is connected between the second portion and the third portion.

[0041] This application prepares a second part, a first part, and a third part that are connected sequentially when preparing the metal silicide layer. In this way, during the transistor fabrication process, it is not necessary to remove a large area of ​​the metal silicide layer (at least part of the metal silicide layer located in the groove and part of the metal silicide layer located on the channel can be retained), which can reduce the difficulty of the process and simplify the fabrication process.

[0042] In one feasible manner, the second part is obtained, comprising:

[0043] The second part has a gap between it and the gate to separate the second part from the gate.

[0044] The fabrication method of this application forms a gap between the second portion and the gate, which is equivalent to designing a gate-free, low-doped, high-resistivity region between the second portion and the gate. This increases the resistance of the region, thereby limiting the flow of current. As a result, when the memory is in the off state, the high-resistivity region created by the gap between the second portion and the gate can effectively reduce the leakage current in the off state, thereby reducing the static power consumption of the device and extending its lifespan. Attached Figure Description

[0045] Figure 1 This is a cross-sectional schematic diagram of a traditional capacitor-free memory.

[0046] Figure 2 A circuit diagram of an electronic device provided in an embodiment of this application;

[0047] Figure 3 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0048] Figure 4 A circuit diagram of a memory provided in an embodiment of this application;

[0049] Figure 5 A circuit diagram of a storage array provided in an embodiment of this application;

[0050] Figure 6 A cross-sectional schematic diagram of a storage array provided in an embodiment of this application;

[0051] Figure 7 A cross-sectional schematic diagram of a storage cell provided in an embodiment of this application;

[0052] Figure 8 A cross-sectional schematic diagram of a storage cell in a first write state is provided as an embodiment of this application;

[0053] Figure 9 A cross-sectional schematic diagram of a storage cell in a second write state is provided as an embodiment of this application;

[0054] Figure 10 The diagram shows the electrical results of the PMOS device provided in the embodiments of this application, obtained through experimental fabrication.

[0055] Figure 11 A flowchart illustrating a method for fabricating a transistor, as provided in an embodiment of this application;

[0056] Figure 12 A flowchart illustrating a method for fabricating a storage array, as provided in an embodiment of this application;

[0057] Figure 13 This is one of the schematic cross-sectional views of the process structure after a corresponding step is completed in a method for fabricating a memory cell according to an embodiment of this application;

[0058] Figure 14 This is the second schematic cross-sectional view of the process structure after the corresponding step is completed in a method for fabricating a memory cell according to an embodiment of this application.

[0059] Figure 15 for Figure 14 Top view;

[0060] Figure 16 This is the third schematic diagram of the process structure after the corresponding step is completed in a method for fabricating a storage cell according to an embodiment of this application.

[0061] Figure 17 The fourth schematic diagram of the process structure after the corresponding step in the fabrication method of a storage cell provided in this application embodiment is completed;

[0062] Figure 18 Fifth schematic diagram of the process structure after the corresponding step in the fabrication method of a memory cell provided in this application embodiment;

[0063] Figure 19 This is the sixth schematic diagram of the process structure after the corresponding step is completed in a method for fabricating a storage cell according to an embodiment of this application;

[0064] Figure 20 The seventh schematic diagram of the process structure after the corresponding step in the method for fabricating a storage cell provided in this application embodiment is shown.

[0065] Figure 21 This is the eighth schematic diagram of the process structure after the corresponding step is completed in a method for fabricating a storage cell according to an embodiment of this application.

[0066] Figure 22 This is the ninth schematic diagram of the process structure after the corresponding step is completed in a method for fabricating a storage cell according to an embodiment of this application;

[0067] Figure 23 This is the tenth schematic diagram of the process structure after the corresponding step is completed in a method for fabricating a memory cell according to an embodiment of this application;

[0068] Figure 24 This is eleventh of the schematic cross-sectional views of the process structure after the corresponding steps are completed in a method for fabricating a storage cell according to an embodiment of this application.

[0069] Figure label:

[0070] 01 - Electronic device; 100 - Memory; 200 - Processor;

[0071] 10 - Memory array; 11 - Substrate; 111 - First silicon layer; 112 - First oxide layer; 113 - Second silicon layer; 1131 - First structure; A1 - Memory region; A2 - Isolation region; 114 - Trench; 1141 - First wall; 1142 - Second wall; 12 - Memory cell; Tr - Transistor; 121 - Source doped region; 122 - Metal silicide layer; 1221 - First portion; 1222 - Second portion; 12 23 - Third part; 123 - Gate; 124 - Channel; 125 - Gate insulating layer; 1251 - Silicon dioxide layer; 1252 - Second oxide layer; 1253 - First opening; 1254 - Second opening; 126 - Dielectric layer; 1261 - First lead-out hole; 1262 - Second lead-out hole; 1263 - Third lead-out hole; 127 - First lead-out electrode; 128 - Second lead-out electrode; 129 - Third lead-out electrode; B1 - Gap;

[0072] 20 - Controller; 210 - Decoder; 220 - Driver; 230 - Timing Controller; 240 - Buffer; 250 - Input / Output Driver. Detailed Implementation

[0073] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0074] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "one" or similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one.

[0075] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0076] This application provides an electronic device 01. The electronic device 01 can be a terminal device, such as a mobile phone, tablet computer, television, smart wearable products (e.g., smartwatches and smart bracelets), augmented reality (AR) terminal, or virtual reality (VR) terminal, or it can be a personal computer (PC), server, or workstation. This application does not impose any special limitations on the specific type of the electronic device 01.

[0077] Figure 2 A circuit diagram of an electronic device 01 provided in an embodiment of this application is shown below. Figure 2 The electronic device 01 includes at least a processor 200 and a memory 100. The processor 200 is electrically connected to the memory 100, and the memory 100 is used to store data generated by the processor 200. That is, the memory 100 is used for data storage; the processor 200 is the computing core and control unit of the electronic device 01, and is capable of accessing the memory 100 and other related components of the electronic device 01. It is understood that in the electronic device 01 provided in the embodiments of this application, Figure 2 This is merely a schematic illustration of some components of electronic device 01; the position, shape, and structure of these components are not subject to change. Figure 2 The limitations. In addition, the electronic device 01 provided in this application includes, besides... Figure 2In addition to the components shown (i.e., memory 100 and processor 200), other electronic devices may be included, such as communication interfaces and disks as secondary storage, etc., which are not specifically limited herein.

[0078] The processor 200 can be the control center of the electronic device 01. It can connect to various parts of the electronic device 01 through various interfaces and lines, thereby accessing the memory 100, cache, and secondary storage, etc. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 01 and processes data, thereby controlling the electronic device 01 as a whole. In the embodiments of this application, the processor 200 can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), or a neural network processor (NNP), or other application-specific integrated circuits (ASICs), etc.

[0079] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a data storage area and a program storage area. The data storage area can be used to store data from the electronic device 01 (such as audio data, image data, etc.); the program storage area can be used to store the operating system of the electronic device 01, currently running applications, etc. Furthermore, the memory 100 of the electronic device 01 of this application may include external memory and / or internal memory. Data stored in the external memory and internal memory can be transferred between each other. External memory may be, for example, a hard disk, a USB flash drive, a floppy disk, etc. Internal memory may be, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Read-Only Memory, etc.

[0080] Figure 3 This is a schematic diagram of the structure of a memory 100 provided in an embodiment of this application, as shown below. Figure 3In some embodiments, the memory 100 described above may include a memory array 10 and a controller 20, wherein the controller 20 is electrically connected to the memory array 10 and is used to control the reading and writing of the memory array 10. Of course, in addition to including the memory array 10 and the controller 20, the memory 100 may also include other components, such as a reference memory cell, which is used to improve a reference or comparison benchmark to ensure that data is accurately read during a read operation.

[0081] The controller 20 is used to access the storage array 10 to write data into or read data from the storage array 10.

[0082] Figure 4 A circuit diagram of a memory 100 provided for embodiments of this application is provided. In some embodiments, the controller 20 in the memory 100 may include... Figure 4 The circuit structure shown includes one or more of the following: decoder 210, driver 220, timing controller 230, buffer 240, or input / output driver 250.

[0083] exist Figure 4 In the memory 100 shown, decoder 210 decodes the received address to determine the memory cell 12 to be accessed. Driver 220 controls the level of signal lines based on the decoding result generated by decoder 210, thereby enabling access to the specified memory cell 12. Buffer 240 buffers the read data, for example, using a first-in-first-out (FIFO) buffering method. Timing controller 230 controls the timing of buffer 240 and controls driver 220 to drive the signal lines in memory array 10. Input / output driver 250 drives transmission signals, such as driven received data signals and driven data signals to be transmitted, enabling long-distance transmission of data signals.

[0084] The aforementioned storage array 10, controller 20, decoder 210, driver 220, timing controller 230, buffer 240 and input / output driver 250 can be integrated into one chip or into multiple chips respectively. This application does not impose any special restrictions on the specific integration method.

[0085] Figure 5 A circuit diagram of a memory array 10 provided for embodiments of this application; in some embodiments, the memory array 10 may include, for example: Figure 5The diagram shows multiple arrays of storage cells 12, each capable of storing one bit or more bits of data. The storage array 10 may also include word lines (WL) and bit lines (BL). Each storage cell 12 is electrically connected to its corresponding word line (WL) and bit line (BL). Different storage cells 12 can be electrically connected via WL and BL. One or more of the aforementioned WL and BL are used to select the storage cell 12 in the storage array 10 to be read or written by receiving a control level output from a control circuit, thereby enabling data read / write operations.

[0086] One of the memory cells 12 may include a transistor Tr. The first terminal of transistor Tr is electrically connected to ground and the board line PL, the gate 123 (Gate, G) of transistor Tr is electrically connected to the word line WL, and the second terminal of transistor Tr is electrically connected to the bit line BL.

[0087] The gates 123 of the transistors Tr of the plurality of memory cells 12 arranged in the same direction can be electrically connected to the same word line WL; the first terminals of the plurality of transistors Tr can be electrically connected to the same board line PL, for example, the board line PL can be grounded; and the second terminals of the transistors Tr of the plurality of memory cells 12 arranged in the same direction can be electrically connected to the same bit line BL.

[0088] In the embodiments described in this application, the transistor Tr can be selected as a metal-oxide-semiconductor field-effect transistor. For example, the above... Figure 5 The transistor Tr shown can be either an N-channel metal-oxide semiconductor (NMOS) or a P-channel metal-oxide semiconductor (PMOS).

[0089] Furthermore, in the embodiments involved in this application, one of the source (S) or drain (D) terminals of transistor Tr is called the first terminal, and the corresponding other terminal is called the second terminal. The control terminal of transistor Tr is the gate 123. The drain and source terminals of transistor Tr can be determined according to the direction of current flow.

[0090] For example, in some embodiments, the memory 100 involved in the embodiments of this application may be dynamic random access memory (DRAM). For example, it may be DRAM including 1T0C memory cells or DRAM including 1T1C memory cells.

[0091] In other embodiments, the memory 100 involved in the present application embodiments may also be a static random-access memory (SRAM).

[0092] With the rapid development of the data storage industry, the demand for storage systems is constantly increasing. Memory 100 using a 1TnC structure as storage cell 12 is gradually being dominated by capacitor-less memories (e.g., capacitor-less memories using a 1T0C structure as storage cell 12) due to the difficulty in reducing the integration density of semiconductor memory devices. However, the structure of capacitor-less memories in some embodiments can be referenced... Figure 1 As shown, it can be seen that highly doped regions are used in the source and drain regions to form ohmic contacts. While this design helps reduce current loss when passing through the contact region, it also results in a higher turn-on voltage required to induce impact ionization, leading to high drive power consumption and limiting the overall performance of the memory 100.

[0093] Based on this, this application provides a new memory array 10, which forms a Schottky junction in the drain region, thereby increasing the electric field strength in the drain region, reducing the voltage required to cause collisional ionization, and thus reducing the device's turn-on voltage and drive power consumption.

[0094] The storage array 10 provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0095] Figure 6 This is a cross-sectional schematic diagram of a storage array 10 provided in an embodiment of this application. The storage array 10 of this application is applicable to all static random access memories and dynamic random access memories that operate on the principle of the floating body effect.

[0096] In some embodiments, such as Figure 6 As shown, the above-mentioned storage array 10 may include a substrate 11 and a plurality of storage cells 12. Figure 6 Two transistors Tr are shown arranged in a direction parallel to the surface of substrate 11. Figure 7 This is a cross-sectional schematic diagram of a memory cell 12 provided in an embodiment of this application. Each memory cell 12 includes a transistor Tr.

[0097] In some feasible implementations, the substrate 11 can be an N-type substrate or a P-type substrate. This application does not impose any special restrictions on the specific type of substrate 11, which can be determined based on whether the transistor Tr adopts an N-channel metal-oxide-semiconductor structure or a P-channel metal-oxide-semiconductor structure.

[0098] For example, when the transistor Tr of the memory array 10 adopts an N-channel metal-oxide-semiconductor structure, the substrate 11 can be a P-type substrate; when the transistor Tr of the memory array 10 adopts a P-channel metal-oxide-semiconductor structure, the substrate 11 can be an N-type substrate.

[0099] In this embodiment, the substrate 11 can be a silicon-on-insulator (SOI) substrate.

[0100] Please refer to Figure 7 and Figure 13 As shown, Figure 13 This is a schematic diagram of the structure of a substrate 11 provided in an embodiment of this application. The silicon substrate on the insulating layer may include a first silicon layer 111, a first oxide layer 112, and a second silicon layer 113. The first oxide layer 112 is located on one side of the first silicon layer 111, and the second silicon layer 113 is located on the side of the first oxide layer 112 opposite to the first silicon layer 111. That is, with... Figure 13 Taking the orientation shown as an example, the first oxide layer 112 is located on the first silicon layer 111, and the second silicon layer 113 is located on the first oxide layer 112.

[0101] The substrate 11 of this application uses an SOI substrate. Thus, after the transistor Tr is disposed on the SOI substrate, it is equivalent to disposing the transistor Tr on a silicon layer over an insulator. This allows the formation of a transistor Tr with a floating body effect (or a floating cell). In this way, the transistor Tr formed on the SOI substrate forms a capacitor relative to the insulating layer (i.e., the first oxide layer 112) of the substrate 11, and charge can accumulate on this capacitor for data storage.

[0102] For some feasible implementation methods, please refer to Figure 5 As shown, the storage cell 12 may include multiple cells, which are arranged in an array on the substrate 11. Each storage cell 12 can store 1 bit or more bits of data. The storage array 10 may also include word lines WL and bit lines BL. Each storage cell 12 is electrically connected to a corresponding word line WL and bit line BL. Different storage cells 12 can be electrically connected via WL and BL. One or more of the aforementioned WL and BL are used to select the storage cell 12 to be read or written in the storage array 10 by receiving a control level output from the control circuit, thereby realizing the data read and write operation.

[0103] This application does not impose any restrictions on the specific number or arrangement of the storage units 12, which can be determined based on the storage capacity and density of the storage array 10.

[0104] In one possible implementation, storage unit 12 includes a 1T0C storage unit, please refer to... Figure 5 As shown. In other words, the storage cell 12 of the storage array 10 of this application can adopt an ITOC structure.

[0105] The 1T0C structure is simpler than other complex memory cell 12 structures, thus reducing material consumption and process steps during manufacturing, which helps lower production costs and manufacturing complexity. Simultaneously, the simple structure allows for the integration of more memory cells 12 within a limited chip area, thereby increasing the capacity and density of the memory 100. Furthermore, the simplified structure may reduce potential failure points, thereby improving the reliability and stability of the memory cells 12.

[0106] Please refer to Figure 7 As shown, transistor Tr includes a source, a drain, a gate 123, and a channel 124. It should be understood that the source, as the input terminal of transistor Tr, is used to provide current or a signal, and the drain, as the output terminal of transistor Tr, allows current and signals to flow out through the channel 124. The gate 123 can serve as the control terminal of transistor Tr, used to adjust the conductivity of the channel 124 by applying a voltage, thereby controlling the current between the source and drain.

[0107] The channel 124 is located between the source and drain, serving as a current flow path. Changes in the gate voltage 123 affect the conductivity of the channel 124, thereby controlling the switching state of the transistor Tr.

[0108] In this embodiment, the source may include a source doped region 121 formed in the substrate 11.

[0109] In some feasible implementations, the ion doping concentration of the source doped region 121 can be 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 Between. That is, the source doped region 121 can be a heavily doped region. For example, the ion doping concentration of the source doped region 121 can be 1 × 10⁻⁶. 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 Or 1×10 21 cm -3 wait.

[0110] This application establishes a source doped region 121, and allows the ion doping concentration of the source doped region 121 to be between 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm-3 In this way, it is equivalent to forming heavy doping in the source region. On the one hand, it can improve the conductivity of the semiconductor, so that the source can transmit current more effectively, thereby reducing the loss of current during transmission and thus reducing the power consumption of memory 100.

[0111] On the other hand, heavy doping increases the number of impurity atoms, which form stronger bonds in the semiconductor lattice structure, thereby enhancing lattice stability. Simultaneously, heavy doping improves conductivity, resulting in more efficient and smoother current transmission. This reduces thermal effects and mechanical stress caused by excessive current, thus improving the source's structural stability, minimizing performance degradation due to material aging or degradation, and enhancing the reliability and durability of the memory 100, enabling it to maintain relatively stable operation in various application scenarios.

[0112] In some feasible implementations, the ion doping concentration of channel 124 is less than the ion doping concentration of source doped region 121; that is, the ion doping concentration of channel 124 can be less than 1 × 10⁻⁶. 18 cm -3 For example, the ion doping concentration of channel 124 can be 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 Between. For example, the ion doping concentration of channel 124 can be 1 × 10⁻⁶. 14 cm -3 1×10 15 cm -3 Or 1×10 16 cm -3 wait.

[0113] The drain includes a metal silicide layer 122, and a channel 124 is formed in the region of the substrate 11 between the source doped region 121 and the metal silicide layer 122. That is, the drain of the transistor Tr of this application includes a metal silicide layer 122, and a channel 124 is formed between the metal silicide layer 122 and the source doped region 121. This channel 124 is located within the substrate 11, such as... Figure 7 As shown.

[0114] In this embodiment, a channel 124 is formed in the region of the substrate 11 between the source doped region 121 and the metal silicide layer 122. In other words, one side of the channel 124 is in contact with the source doped region 121, and the other side of the channel 124 is in contact with the metal silicide layer 122.

[0115] In this application, a metal silicide layer 122 is provided at the drain, and a channel 124 is formed between the metal silicide and the source doped region 121. One side of the channel 124 contacts the source doped region 121, and the other side contacts the metal silicide layer 122. Thus, a Schottky barrier junction can be formed at the interface between the metal silicide layer 122 and the channel 124. Because the Schottky contact has a low barrier height and a high electric field strength, the electric field distribution in the drain region is more concentrated at the same voltage. This concentrated electric field distribution helps to enhance the impact ionization effect (i.e., charge carriers moving in the channel 124 are more likely to collide with lattice atoms, thereby generating new electron-hole pairs). Therefore, this application can induce a more significant impact ionization effect with a lower voltage, thus reducing the turn-on voltage required to induce impact ionization. Since the Schottky contact reduces the turn-on voltage required for impact ionization, the memory array 10 provided in this application can operate normally at a lower voltage, reducing the device's driving power consumption.

[0116] In this embodiment, the gate 123 is disposed on the channel 124, such as Figure 7 As shown. That is, the gate 123 is disposed on the side of the channel 124 away from the substrate 11. In this way, the gate 123 can be used as the control terminal of the transistor Tr, which can be used to adjust the conductivity of the channel 124 by applying voltage, thereby controlling the current between the source and the drain.

[0117] Figure 8 A cross-sectional schematic diagram of a storage unit 12 in a first write state provided in an embodiment of this application; Figure 9 This is a cross-sectional schematic diagram of a storage cell 12 in a second write state, provided as an embodiment of this application. The following will be combined with... Figure 8 and Figure 9 The application describes the read and write operations and details how it reduces the device's turn-on voltage and drive power consumption.

[0118] For example, the data write operation of storage unit 12: Please refer to Figure 8 If 0.6V is applied to the gate 123, 0V to the source, and 2.3V to the drain, this voltage configuration creates an electric field between the source and drain. Under the influence of this electric field, electrons migrate from the source to the drain through the channel 124. During migration, electrons collide with atoms in the channel 124, causing collisional ionization and generating electron-hole pairs within the channel 124. Electrons are collected by the drain, while holes, due to the buoyancy effect, cannot easily migrate to the outside and thus accumulate in the channel 124. These accumulated holes are called excess holes, and they alter the potential distribution within the channel 124. This state of excess hole accumulation in the channel 124 is called the first state.

[0119] in, Figure 8 The arrows in the diagram indicate the direction of electron migration.

[0120] Since the drain of this application includes a metal silicide layer 122, and a channel 124 is formed between the metal silicide layer 122 and the source doped region 121, that is, one side of the channel 124 is in contact with the source doped region 121, and the other side is in contact with the metal silicide layer 122. Thus, a Schottky barrier junction is formed between the metal silicide layer 122 and the channel 124. Since a Schottky contact is a low-impedance contact between a metal and a semiconductor, it is characterized by the formation of a very thin depletion layer at the contact interface, and the electric field strength in this depletion layer is relatively high. Therefore, the electric field strength in the drain region is increased. This enhances the impact ionization effect during the aforementioned electron migration process. Therefore, this application can induce a more significant impact ionization effect with a lower voltage, reducing the turn-on voltage required to induce impact ionization. The memory array 10 can operate normally at a lower voltage, reducing the device's drive power consumption.

[0121] Please refer to Figure 9 If 0.6V is applied to the gate 123, 0V to the source, and -2.3V to the drain, a forward bias is applied between the channel 124 and the drain. This allows excess holes to be removed (or migrated) from the channel 124, while excess electrons can accumulate in the channel 124. This state of excess electron accumulation in the channel 124 is called the second state.

[0122] Because the resistance of channel 124 is different in the first state and the second state, the first state and the second state can correspond to the write operation of data "1" and "0" respectively.

[0123] Data read operation of storage cell 12: Due to the accumulation of charge, the threshold voltage (Vth) of transistor Tr changes. The threshold voltage of transistor Tr is different when writing data "1" and writing data "0". Therefore, when reading information, the read operation can be completed by applying a specific read voltage and measuring the magnitude of the current flowing through it (the magnitude of the current flowing through transistor Tr is different in the "0" and "1" states, and the difference in threshold voltage of transistor Tr caused by these two different states can be sensed by measuring the current, so as to realize the data read operation).

[0124] In one feasible approach, please refer to [the relevant documentation / reference]. Figure 7 The metal silicide layer 122 may include a first portion 1221; the first portion 1221 is located on the side of the channel 124 away from the source doped region 121.

[0125] In other words, the metal silicide layer 122 includes a first portion 1221, which is contacted and connected to the side of the channel 124 away from the source doped region 121. Thus, the first portion 1221 of the metal silicide layer 122 can contact the channel 124 to form a Schottky barrier junction, thereby increasing the electric field strength of the transistor Tr in the drain region, enhancing the impact ionization effect, and consequently reducing the turn-on voltage required to induce impact ionization, thereby reducing the device's drive power consumption.

[0126] In one possible implementation, the metal silicide layer 122 may further include a second portion 1222; the second portion 1222 is located on the side of the channel 124 away from the substrate 11, and the second portion 1222 is connected to the first portion 1221.

[0127] The second portion 1222 mentioned above can be located on the side of the channel 124 away from the substrate 11, that is, with Figure 7 Taking the orientation shown as an example, the second part 1222 can be located above the channel 124.

[0128] The second part 1222 is connected to the first part 1221, so that the electrical signal of the first part 1221 can be transmitted to the second part 1222. The second part 1222 can serve as a lead-out terminal of the metal silicide layer 122, that is, the electrical signal of the metal silicide layer 122 can be led out through the second part 1222.

[0129] In addition, the area of ​​the metal silicide layer 122 can be appropriately increased by including the second part 1222, which makes it easier for the transistor Tr to bring out the electrical signal of the metal silicide layer 122; at the same time, the setting of the second part 1222 also helps to reduce the processing difficulty during the fabrication of the metal silicide layer 122.

[0130] In one possible approach, please refer to Figure 7 Along a direction parallel to the surface of the substrate 11, the second portion 1222 may be spaced apart from the gate 123. The spaced-apart arrangement of the second portion 1222 and the gate 123 means that there is a gap B1 between the second portion 1222 and the gate 123.

[0131] Among them, with Figure 7 Taking the orientation shown as an example, the surface of substrate 11 corresponds to... Figure 7 The orientation shown refers to the upper or lower surface of substrate 11. A direction parallel to the surface of substrate 11 means either a direction parallel to the upper or lower surface of substrate 11, or a direction perpendicular to the thickness direction of substrate 11.

[0132] Thus, the second part 1222 and the gate 123 being spaced apart can also be represented as the second part 1222 and the gate 123 being spaced apart along a direction perpendicular to the thickness direction of the substrate 11.

[0133] by Figure 7 Taking the orientation shown as an example, the direction parallel to the surface of substrate 11 is... Figure 7 In the horizontal direction, that is, along the horizontal direction, there is a gap B1 between the gate 123 and the second part 1222.

[0134] In some implementations, the drain of transistor Tr in memory array 10 uses a highly doped region, which results in a higher carrier concentration and thus increases the current density in the off-state. Ideally, no current should flow when memory 100 is in the off-state, but due to the presence of the highly doped region, some current still flows, which is why the off-state current density is too high.

[0135] In some embodiments provided in this application, the second portion 1222 is spaced apart from the gate 123 along a direction parallel to the surface of the substrate 11. This effectively creates a low-doped, high-resistivity region without gate control between the drain and the gate 123, increasing the resistance of this region and thus limiting current flow. Consequently, when the memory 100 is in the off state, the presence of this high-resistivity region effectively reduces leakage current in the off state, thereby reducing the device's static power consumption and extending its lifespan.

[0136] Figure 10 This diagram illustrates the electrical performance of the PMOS device provided in this embodiment, fabricated through experimental fabrication. In this electrical performance diagram, the horizontal axis represents the gate-to-source voltage (V). GS The vertical axis represents the drain-source current (I). DS The multiple curves represent different drain-source voltages (V). DS The corresponding gate 123 to source voltage V GS With drain-source current I DS The changing trend of the relationship.

[0137] exist Figure 10 When the PMOS device provided in this embodiment was fabricated through experimental fabrication, it was annealed at 350°C for 30 seconds. During the etching process, the bottom was etched 250 nm more than the top, and the back gate voltage (V) was... BG The voltage was set to 0 volts. This means the following process was used: Annealed at 350℃ for 30s; Undercut = -250nm; V BG =00V.

[0138] As can be seen from the electrical results diagram, after introducing the Schottky contact structure into the transistor Tr, with the gate 123 to source voltage V... GS The decrease in drain-source current I DS It begins to increase significantly, essentially rising in a steep, linear fashion. This demonstrates that the transistor Tr can achieve this at a relatively small V... GS A large I can be achieved within the range of variation. DS The steep curve change during the transition between the on and off states of the device indicates a reduction in transition time, thereby lowering power consumption and improving circuit response speed. As can be seen from this electrical diagram, the transistor Tr provided in this embodiment exhibits excellent switching performance, contributing to improved circuit stability and reliability.

[0139] The above drain-source current I DS Also known as leakage current.

[0140] At the same time, from Figure 10 As can be seen from the electrical diagram, after introducing a Schottky structure into transistor Tr of memory array 10, the drain-source voltage V DS And the gate 123 to source voltage V, which serves as the driving voltage. GS All are less than 1.0V. This indicates that the device can operate effectively at lower voltages, which further confirms that the introduction of Schottky contacts in the transistor Tr of the memory array 10 can indeed reduce the turn-on voltage and drive power consumption.

[0141] Furthermore, in this application, the second portion 1222 is spaced apart from the gate 123 along a direction parallel to the surface of the substrate 11. That is, there is no overlapping region between the gate 123 and the drain (i.e., there is a gap B1). Therefore, it can also reduce the drain-source current I. DS The function, from Figure 10 It can also be seen that the drain-source current I DS It can reach 10 -7 μA / μm, drain-source current I in the off state DS Lower. That is, the transistor Tr of the memory array 10 in this application embodiment adopts Schottky contact, which can indeed reduce the leakage current in the off state, thereby reducing the static power consumption of the device and extending the life of the device.

[0142] In one possible implementation, the transistor Tr may further include a gate insulating layer 125. The gate insulating layer 125 may be present between the gate 123 and the channel 124. In this way, the gate insulating layer 125 can isolate the gate 123 and the channel 124, preventing direct current flow. Thus, the transistor Tr can control the magnitude of the current within the channel 124 by adjusting the voltage of the gate 123, thereby inducing a charge in the gate insulating layer 125 and changing the width of the channel 124.

[0143] In one feasible implementation, the second portion 1222 can directly cover the side of the channel 124 facing away from the substrate 11. This can effectively improve the reliability of the electrical connection between the drain and the channel 124.

[0144] like Figure 7 In some possible implementations, the gate insulating layer 125 may include a silicon dioxide layer 1251 and a second oxide layer 1252, wherein the dielectric constant of the second oxide layer 1252 is greater than that of the silicon dioxide layer 1251. The silicon dioxide layer 1251 is located between the channel 124 and the second oxide layer 1252, and the second oxide layer 1252 is located between the silicon dioxide layer 1251 and the gate 123.

[0145] The gate 123 can be a metal gate. That is, in some possible implementations, the gate 123 can be a metal gate in addition to polysilicon.

[0146] In other words, the gate insulating layer 125 may include a second oxide layer 1252 with a dielectric constant greater than that of the silicon dioxide layer 1251, and the gate 123 may be a metal gate. Thus, this application employs a high-K metal gate (HKMG) process using a high-K dielectric material and a metal gate. The use of the high-K material (i.e., the second oxide layer 1252) increases the equivalent oxide thickness (EOT) of the gate 123 dielectric, thereby effectively reducing leakage current. As a good conductor, the metal gate does not exhibit a depletion region, thus maintaining the stability of the gate 123 capacitance, which helps reduce leakage current and improve switching speed.

[0147] Of course, in other possible implementations, the gate insulating layer 125 may also include only the second oxide layer 1252; or, the gate insulating layer 125 may also include only the silicon dioxide layer 1251.

[0148] Alternatively, the gate insulating layer 125 may also include a silicon oxynitride (SiON) layer and a second oxide layer 1252. That is, a silicon oxynitride layer is first formed on the channel 124 as a transition layer, and then the second oxide layer 1252 is formed on the silicon oxynitride layer.

[0149] The second oxide layer 1252 can be made of materials such as hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), or titanium oxide (TiO2). These materials all have high dielectric constants, which can reduce the size of the transistor Tr while maintaining the gate capacitance, and help reduce leakage current, lower operating voltage, and reduce power consumption. Among them, hafnium oxide has a high dielectric constant and good thermal stability, aluminum oxide has good thermodynamic stability but a relatively low dielectric constant, tantalum oxide has a high dielectric constant but a low crystallization temperature and is prone to reaction with silicon, and titanium oxide has an extremely high dielectric constant but a small bandgap and is prone to incompatibility with silicon processes. Therefore, in practical applications, it is necessary to select appropriate materials according to specific requirements. This application does not impose any special restrictions on the specific material of the second oxide layer 1252.

[0150] Also, please continue to refer to Figure 7 The first portion 1221 has a dielectric layer 126 on the side opposite to the channel 124. That is, the transistor Tr also includes a dielectric layer 126, and the first portion 1221 is located between the dielectric layer 126 and the channel 124.

[0151] The dielectric layer 126 is also known as the interlayer dielectric (ILD).

[0152] In addition, besides being disposed on the side of the first portion 1221 opposite to the channel 124, the dielectric layer 126 can also cover the metal silicide layer 122, the gate 123, the source doped region 121, and the gate insulating layer 125. Of course, when the dielectric layer 126 completely covers the metal silicide layer 122, the gate 123, and the source doped region 121, in subsequent processes, vias need to be made in the dielectric layer 126 to bring out the metal silicide layer 122, the gate 123, and the source doped region 121 respectively.

[0153] By providing a dielectric layer 126, this application enables the dielectric layer 126 to act as an isolation layer between the transistor Tr and the external environment, thereby protecting the transistor Tr from external impurities, moisture, and other corrosive substances, and improving the reliability and lifespan of the transistor Tr.

[0154] For example, the metal silicide layer 122 may also include a third portion 1223, such as Figure 7 As shown, the third portion 1223 is stacked between the dielectric layer 126 and the substrate 11, and the third portion 1223 is connected to the first portion 1221. By retaining the third portion 1223 between the dielectric layer 126 and the substrate 11, it is not necessary to remove the metal silicide on the side of the substrate 11 near the dielectric layer 126 during the fabrication of the transistor Tr, which simplifies the fabrication process and is relatively easier to implement during the fabrication of the transistor Tr.

[0155] It should be understood that in the memory array 10 provided in this embodiment, the transistor Tr of the memory cell 12 can be a PMOS device or an NMOS device.

[0156] For example, in one feasible implementation, the transistor Tr can be a PMOS device. In this case, the source doped region 121 can be a P-type doped region, and the metal silicide layer 122 can include a first metal material with a work function greater than or equal to 4.5 eV.

[0157] PMOS devices exhibit lower flicker noise in memory 100 applications. This is particularly important for circuits requiring high sensitivity and low noise, contributing to improved stability and reliability of memory 100. Therefore, the use of PMOS devices can be selected based on the application scenario of memory 100. For example, when better stability and reliability are required for memory 100, transistor Tr can be a PMOS device.

[0158] When the transistor Tr uses a PMOS device, the drain can contain a metal with a high work function because the current flow in a PMOS device is from the drain to the source. When a negative bias voltage is applied between the gate 123 and the source, the current flows from the drain to the source. A metal with a high work function helps to better control the current under this negative bias condition, ensuring stable operation of the device.

[0159] Furthermore, for example, when the source doping region 121 is a P-type doped region, the aforementioned first metal material may include at least one of titanium nitride (TiN), gold (Au), ruthenium (Ru), nickel (Ni), platinum (Pt), cobalt (Co), or tungsten (W). That is, when the source doping region 121 is a P-type doped region, the metal silicide may be a silicide of at least one of titanium nitride, gold, ruthenium, nickel, platinum, cobalt, or tungsten. Because these metals have good conductivity, current loss during transmission can be reduced, thereby improving the speed and performance of the circuit.

[0160] In another feasible implementation, the transistor Tr can be an NMOS device. In this case, the source doped region 121 is an N-type doped region, and the metal silicide layer 122 includes a second metal material with a work function less than or equal to 4.5 eV.

[0161] Since the channel 124 of an NMOS device is composed of electrons, it has high electron mobility and relatively low on-resistance, which helps improve circuit efficiency and the switching speed of the NMOS device, thereby contributing to increased read and write speeds of the memory 100. Therefore, the choice of whether to use an NMOS device depends on the application scenario of the memory 100. For example, when a faster read and write speed is required for the memory 100, an NMOS device can be used for the transistor Tr.

[0162] When transistor Tr uses an NMOS device, the drain can be made of a metal with a low work function because the current flow in an NMOS device is from the source to the drain. When a forward bias voltage is applied between the gate 123 and the source, the current flows from the source to the drain. A metal with a low work function facilitates smooth current flow under this forward bias condition, improving device performance.

[0163] Furthermore, for example, when the source doping region 121 is an N-type doped region, the second metal material includes at least one of silver (Ag), scandium (Sc), titanium (Ti), aluminum (Al), or erbium (Er). That is, when the source doping region 121 is an N-type doped region, the metal silicide can be a silicide of at least one of silver, scandium, titanium, aluminum, or erbium. Because these metal materials typically possess good chemical and physical stability in the silicide layer, they can resist high temperatures and chemical reactions, improving the reliability of the device in harsh environments. Simultaneously, these metal materials are generally compatible with existing semiconductor manufacturing processes, allowing for easy integration into the production process, reducing production costs and improving production efficiency.

[0164] This application also provides some preparation methods, which can be used to prepare the memory array 10 provided in the above embodiments. The preparation method includes the following steps:

[0165] Multiple memory cells 12 are fabricated on substrate 11, each memory cell 12 including transistor Tr.

[0166] like Figure 11 As shown, Figure 11 This is a flowchart illustrating a method for fabricating a transistor Tr, as provided in an embodiment of this application. The method for fabricating the transistor Tr includes the following steps:

[0167] Step S100: A source electrode is obtained, which includes a source electrode doping region 121 formed in the substrate 11.

[0168] The aforementioned source doped region 121 can be obtained by ion implantation into the substrate 11.

[0169] The specific doping type of the source doped region 121, and the specific doping elements doped during ion implantation to form the source doped region 121, are not specifically limited in this application and can be determined according to the type of transistor Tr.

[0170] For example, when the transistor Tr uses a PMOS device, the source doped region 121 can be P-type doped. Correspondingly, when ion implantation is performed on the substrate 11 to form the source doped region 121, P-type doped ions can be implanted, such as boron (B), gallium (Ga), or aluminum (Al).

[0171] For example, when the transistor Tr uses an NMOS device, the source doped region 121 can be N-type doped. Correspondingly, when ion implantation is performed on the substrate 11 to form the source doped region 121, N-type doped ions can be implanted, such as phosphorus (P), antimony (Sb), or arsenic (As).

[0172] Furthermore, the ion concentration of the source doped region 121 can be referred to the above description. The parts of the preparation method of the memory array 10 provided in this application that are the same as those described above will not be repeated here, but can be referred to the relevant descriptions above.

[0173] Step S200: A drain electrode is formed, which includes a metal silicide layer 122. The region of the substrate 11 located between the source doped region 121 and the metal silicide layer 122 forms the channel 124 of the transistor Tr.

[0174] That is, in one feasible implementation, the drain of the transistor Tr of the memory cell 12 may include a metal silicide layer 122.

[0175] The channel 124 is located between the source doped region 121 and the metal silicide layer 122, that is, the source doped region 121 and the metal silicide layer 122 are located on both sides of the channel 124 of the transistor Tr.

[0176] That is, one side of the channel 124 contacts the source doped region 121, and the other side contacts the metal silicide layer 122. In this way, a Schottky barrier junction can be formed between the channel 124 and the metal silicide layer 122 of the memory array 10 fabricated by the method of this application. Since the Schottky contact has a low barrier height and a high electric field strength, the electric field strength in the drain region is higher at the same voltage. This helps to enhance the impact ionization effect, thus enabling this application to induce a more significant impact ionization effect with a lower voltage, thereby reducing the turn-on voltage required for impact ionization. Therefore, the memory array 10 fabricated by the method provided in this application can operate normally at a lower voltage, reducing the device's driving power consumption.

[0177] The metal silicide layer 122 can be formed by a deposition process. This application does not limit the specific process for forming the metal silicide layer 122, and it can be determined according to the actual application scenario.

[0178] For example, the metal silicide layer 122 described above can be formed by first depositing metal on the substrate 11 and then annealing it.

[0179] Step S300: A gate 123 is obtained and disposed on the channel 124.

[0180] In some feasible processes, the gate 123 can be formed using deposition processes, such as physical vapor deposition (PVD).

[0181] The order of steps S100, S200, and S300 in this application example can be interchanged as needed, and this application does not impose specific restrictions on the order of the steps. For example, the gate 123 can be fabricated first, followed by the drain; or the drain can be fabricated first, followed by the gate 123.

[0182] In one feasible manner, before fabricating the transistor Tr, the method for preparing the memory array 10 of this application may further include:

[0183] Multiple isolated memory regions A1 are defined on the substrate 11, with a groove 114 between adjacent memory regions A1. Please refer to... Figures 13 to 15 .

[0184] In other words, the substrate 11 is divided into multiple storage regions A1, and the multiple storage regions A1 are isolated from each other.

[0185] Furthermore, there is a groove 114 between two adjacent storage regions A1, so that the groove 114 can be used to form a drain electrode in a subsequent process.

[0186] For example, the fabrication of a transistor Tr may include:

[0187] The source and drain electrodes are fabricated in storage region A1;

[0188] The metal silicide layer 122 may include:

[0189] A first portion 1221 is formed on the wall of the groove 114 near the channel 124, a third portion 1223 is formed on the wall of the groove 114 near the substrate 11, and a second portion 1222 is formed on the side of the channel 124 away from the substrate 11. The first portion 1221 is connected between the second portion 1222 and the third portion 1223.

[0190] That is, the source and drain can be fabricated in the storage region A1. For example, when fabricating the metal silicide layer 122, a first portion 1221 can be formed on the wall surface of the recess 114 near the channel 124. In other words, the first portion 1221 can be formed on the first wall surface 1141, where the first wall surface 1141 is the wall surface of the recess 114 near the channel 124, i.e. Figure 14 and Figure 20 The sidewall of the groove 114 shown.

[0191] When fabricating the metal silicide layer 122, a third portion 1223 can be formed on the wall surface of the groove 114 near the substrate 11. That is, the third portion 1223 can be formed on the second wall surface 1142, where the second wall surface 1142 is the wall surface of the groove 114 near the substrate 11. Figure 14 The bottom surface of groove 114 in the indicated orientation.

[0192] When fabricating the metal silicide layer 122, a second portion 1222 can be formed on the side of the channel 124 away from the substrate 11. The first portion 1221 is connected to the second portion 1222 and the third portion 1223, respectively, and the second portion 1222, the first portion 1221 and the third portion 1223 can be continuous.

[0193] In this application, by retaining the first portion 1221, the second portion 1222, and the third portion 1223 when the metal silicide layer 122 is formed, a Schottky contact can be formed between the metal silicide layer 122 and the channel 124. Furthermore, after the metal silicide layer 122 is formed, it is not necessary to remove a large area of ​​metal silicide in subsequent processes, which can reduce the difficulty of the process and simplify the preparation steps.

[0194] In one feasible manner, obtaining the second part 1222 may include:

[0195] The second part 1222 has a gap B1 between it and the gate 123 to separate the second part 1222 from the gate 123.

[0196] That is, please refer to Figure 20 The second part 1222 is spaced apart from the gate 123 by a gap B1, which isolates the second part 1222 from the gate 123. The specific size of the gap B1 can be determined by those skilled in the art according to actual needs, and this application does not impose specific limitations.

[0197] The second portion 1222 and the gate 123 are separated by a gap B1. Alternatively, it can be considered that the projection of the second portion 1222 on the substrate 11 and the projection of the gate 123 on the substrate 11 have no overlapping area, and their edges do not coincide or contact each other.

[0198] The fabrication method of this application forms a gap B1 between the second portion 1222 and the gate 123, which is equivalent to designing a gate-free, low-doped, high-resistivity region between the second portion 1222 and the gate 123. This increases the resistance of the region, thereby limiting the current flow. Therefore, when the memory 100 is in the off state, the high-resistivity region generated by the gap B1 between the second portion 1222 and the gate 123 can effectively reduce the leakage current in the off state, thereby reducing the static power consumption of the device and extending its lifespan.

[0199] The following section will introduce some feasible process procedures in conjunction with the process structure diagram. Figure 12 This is a flowchart illustrating a method for fabricating a storage array 10 according to an embodiment of this application. Figures 13 to 24 An exemplary schematic diagram of each step in a method for fabricating a storage cell 12 is provided.

[0200] Step S101: Selectively etch the top silicon layer of the partially depleted silicon-on-insulator (PD-SOI) substrate 11 using photolithography to divide the top silicon layer into multiple independent first structures 1131. Please refer to [reference needed]. Figure 13 and Figure 14 .

[0201] The PD-SOI substrate 11 may include a first silicon layer 111, a first oxide layer 112 on the first silicon layer 111, and a second silicon layer 113 on the first oxide layer 112. In this case, step S101 is to selectively etch the second silicon layer 113 to divide the second silicon layer 113 into multiple independent first structures 1131.

[0202] The first structure 1131 can be strip-shaped, polygonal, or other irregular shapes. This application does not impose any special restrictions on the specific shape of the first structure 1131.

[0203] In addition, step S101 can be selected to have an etching depth greater than the thickness of the top silicon layer (i.e., the second silicon layer 113), thereby ensuring that the top silicon layer can be over-etched, so as to achieve the effect of electrical isolation between different devices.

[0204] The projection of the top silicon layer on substrate 11 can be referenced. Figure 15 As shown. It should be noted that... Figure 15 The shape of the storage region A1 and the arrangement of the storage region A1 on the substrate 11 shown are merely examples and should not be regarded as limitations on this application.

[0205] Furthermore, after selective etching of the top silicon layer, an isolation region A2 can be formed between two adjacent memory regions A1. The groove 114 mentioned earlier can be located within this isolation region A2.

[0206] Step S102: Selectively implant P-type ions onto the silicon substrate 11 on the partially depleted insulating layer using photolithography to form the source doped region 121. Please refer to [reference needed]. Figure 16 As shown.

[0207] In other words, the fabrication method in this application embodiment is based on the example of a PMOS device used for transistor Tr. When ion implantation is performed on substrate 11 to form source doped region 121, it can be achieved by implanting P-type ions, which can be boron (B), gallium (Ga), or aluminum (Al), etc.

[0208] Of course, if the transistor Tr uses an NMOS device, the source doping region 121 can be achieved by implanting N-type ions. For example, the N-type ions can be phosphorus (P), antimony (Sb), or arsenic (As).

[0209] For example, the ion doping concentration of the source doped region 121 can be 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 Between. That is, the source doped region 121 can be a heavily doped region. For example, the ion doping concentration of the source doped region 121 can be 1 × 10⁻⁶. 18 cm -3 1×10 19 cm -3 1×10 20 cm -3 Or 1×10 21 cm -3 wait.

[0210] In addition, the region in the first structure 1131 that has not undergone ion implantation in step S102 can serve as the channel 124 of the transistor Tr.

[0211] In some feasible implementations, the ion doping concentration of channel 124 is less than the ion doping concentration of source doped region 121; that is, the ion doping concentration of channel 124 can be less than 1 × 10⁻⁶. 18 cm -3 For example, the ion doping concentration of channel 124 can be 1×10⁻⁶. 14 cm -3 ~1×10 16 cm -3 Between. For example, the ion doping concentration of channel 124 can be 1 × 10⁻⁶. 14 cm-3 1×10 15 cm -3 Or 1×10 16 cm -3 wait.

[0212] Step S103: A silicon dioxide layer 1251 is grown on the top silicon surface by thermal oxidation, and a hafnium dioxide layer is grown by atomic layer deposition (ALD). A stacked structure of titanium nitride (TiN) and titanium (Ti) is then deposited as the gate 123. Please refer to [link to relevant documentation]. Figures 17 to 19 .

[0213] The silicon dioxide layer 1251 can be disposed as an interface layer (IL) between the hafnium dioxide layer and the top silicon layer, for example... Figure 17 and Figure 18 .

[0214] This fabrication method employs the classic HKMG process, which uses a silicon dioxide layer 1251 and a hafnium dioxide layer. The use of high-k material (i.e., the hafnium dioxide layer) increases the equivalent oxide thickness of the gate 123 dielectric, thereby effectively reducing leakage current. The use of a metal gate for the gate 123 prevents the formation of a depletion region, thus maintaining the stability of the gate 123 capacitance. This contributes to reducing leakage current and improving switching speed.

[0215] In some possible implementations, after step S103, the stacked layer of silicon dioxide layer 1251 and hafnium dioxide layer outside the gate 123 can also be removed by photolithography.

[0216] This can involve completely removing the gate insulating layer 125 (i.e., the stacked layer of silicon dioxide layer 1251 and hafnium dioxide layer) corresponding to the position of the second portion 1222 to be formed in subsequent processes. In other words, the gate insulating layer 125 (i.e., the stacked layer of silicon dioxide layer 1251 and hafnium dioxide layer) between the channel 124 and the second portion 1222 to be formed in subsequent processes is completely removed. That is, a first opening 1253 can be formed on the gate insulating layer 125 so that the channel 124 can be exposed through the first opening 1253, such as... Figure 20 As shown.

[0217] Furthermore, a portion of the gate insulating layer 125 located above the source doped region 121 can be removed to facilitate the extraction of the source doped region 121 in subsequent processes. Specifically, a second opening 1254 can be formed on the gate insulating layer 125 so that the source doped region 121 can be exposed through the second opening 1254, such as... Figure 20 As shown.

[0218] Step S104: Define the drain region using photolithography, deposit platinum metal as the drain, and perform annealing to form a platinum silicide layer. Please refer to [link to relevant documentation]. Figure 21 As shown.

[0219] Part of the drain region is located above the channel 124, and another part is located within the groove 114 of the isolation region A2. Thus, after platinum metal is deposited as the drain, part of the drain contacts the channel 124, and another part contacts the first oxide layer 112, as shown below. Figure 21 As shown.

[0220] Through the above-described configuration, the fabrication method allows one side of the drain electrode to contact the channel 124 to form a Schottky contact, thereby enhancing the electric field in the drain region and further enhancing the impact ionization effect. This enables the present application to induce a more significant impact ionization effect with a lower voltage, thereby reducing the turn-on voltage required for impact ionization. In this way, the memory array 10 fabricated in this embodiment can operate normally at a lower voltage, reducing the driving power consumption of the device.

[0221] Step S105: Deposit dielectric layer 126, which covers a platinum silicide layer, a hafnium dioxide layer, a gate 123, and a source doped region 121, as shown below. Figure 22 As shown.

[0222] That is, after performing step S104, a dielectric layer 126 is formed on the entire surface of the device prepared in step S104.

[0223] The dielectric layer 126 is the interlayer dielectric (ILD). The deposited dielectric layer 126 can prevent current crosstalk between the source doped region 121, the drain, and the gate 123, ensuring the normal operation of the circuit.

[0224] Of course, dielectric layer 126 can also serve as an isolation layer between transistor Tr and the external environment, protecting transistor Tr from external impurities, moisture, etc., and improving the reliability and lifespan of transistor Tr.

[0225] The material of the dielectric layer 126 can be a dielectric with good insulating properties, such as silicon oxide and silicon nitride.

[0226] Step S106: A first lead-out hole 1261 corresponding to the source doped region 121, a second lead-out hole 1262 corresponding to the platinum silicide layer, and a third lead-out hole 1263 corresponding to the gate 123 are formed on the dielectric layer 126 using photolithography. Metal material is then filled into the first lead-out hole 1261, the second lead-out hole 1262, and the third lead-out hole 1263 to obtain the first lead-out electrode 127, the second lead-out electrode 128, and the third lead-out electrode 129. Please refer to [reference needed]. Figure 23 and Figure 24 .

[0227] That is, a first lead-out hole 1261, a second lead-out hole 1262, and a third lead-out hole 1263 of appropriate size are defined on the dielectric layer 126 using photolithography. Among them, the first lead-out hole 1261 corresponds to the source doped region 121, the second lead-out hole 1262 corresponds to the platinum silicide layer, and the third lead-out hole 1263 corresponds to the gate 123.

[0228] The first lead-out hole 1261, the second lead-out hole 1262 and the third lead-out hole 1263 respectively penetrate the dielectric layer 126.

[0229] A first lead-out electrode 127 can be formed by filling the first lead-out hole 1261 with metal material, through which the source doped region 121 can be led out of the dielectric layer 126; a second lead-out electrode 128 can be formed by filling the second lead-out hole 1262 with metal material, through which the platinum silicide layer can be led out of the dielectric layer 126; a third lead-out electrode 129 can be formed by filling the third lead-out hole 1263 with metal material, through which the gate 123 can be led out of the dielectric layer 126.

[0230] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: A substrate and a plurality of memory cells, each of the memory cells including a transistor, the transistor including a source, a drain, a gate, and a channel; The source includes a source doped region formed in the substrate; The drain includes a metal silicide layer, and the channel is formed in the region of the substrate between the source doped region and the metal silicide layer; A gate is disposed on the channel.

2. The storage array according to claim 1, characterized in that, The metal silicide layer includes a first portion; The first portion is located on the side of the channel away from the source doped region.

3. The storage array according to claim 2, characterized in that, The metal silicide layer also includes a second portion; The second portion is located on the side of the channel away from the substrate, and the second portion is connected to the first portion.

4. The storage array according to claim 3, characterized in that, The second portion is spaced apart from the gate along a direction parallel to the surface of the substrate.

5. The storage array according to claim 3 or 4, characterized in that, The transistor further includes a gate insulating layer; The gate insulating layer is present between the gate and the channel.

6. The storage array according to any one of claims 2-5, characterized in that, The first part has a medium layer on the side opposite to the channel; The metal silicide layer further includes a third portion, which is stacked between the dielectric layer and the substrate, and is connected to the first portion.

7. The storage array according to any one of claims 1-6, characterized in that, The source doped region is a P-type doped region, and the metal silicide layer includes a first metal material, the work function of which is greater than or equal to 4.5 eV. Alternatively, the source doped region is an N-type doped region, and the metal silicide layer includes a second metal material, the work function of which is less than or equal to 4.5 eV.

8. The storage array according to claim 7, characterized in that, When the source doped region is a P-type doped region, the first metal material includes at least one of titanium nitride, gold, ruthenium, nickel, platinum, cobalt, or tungsten; When the source doped region is an N-type doped region, the second metal material includes at least one of silver, scandium, titanium, aluminum, or erbium.

9. The storage array according to any one of claims 1-8, characterized in that, The storage unit includes a 1T0C storage unit.

10. A memory, characterized in that, include: Controller; as well as The storage array as described in any one of claims 1-9, wherein the controller is electrically connected to the storage array and is used to control the reading and writing of the storage array.

11. An electronic device, characterized in that, include: processor; as well as The memory of claim 10, wherein the processor is electrically connected to the memory, and the memory is used to store data generated by the processor.

12. A method for fabricating a memory array, characterized in that, The preparation method includes: Multiple memory cells are fabricated on a substrate, each memory cell including a transistor; The process of fabricating the transistor includes: A source electrode is fabricated, wherein the source electrode includes a source electrode doped region formed in the substrate; A drain electrode is fabricated, the drain electrode including a metal silicide layer, and the region of the substrate located between the source doped region and the metal silicide layer forms the channel of the transistor; A gate is formed and disposed on the channel.

13. The method for fabricating a storage array according to claim 12, characterized in that, Before obtaining the transistor, the fabrication method further includes: Multiple isolated storage regions are defined on the substrate, with a groove between two adjacent storage regions; The transistor is fabricated by: The source and drain are fabricated in the storage region; The metal silicide layer is prepared by: A first portion is formed on the wall of the groove near the channel, a third portion is formed on the wall of the groove near the substrate, a second portion is formed on the side of the channel away from the substrate, and the first portion is connected between the second portion and the third portion.

14. The method for fabricating a storage array according to claim 13, characterized in that, The second part is prepared by: The second portion has a gap with the gate to separate the second portion from the gate.

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