Method of manufacturing semiconductor device
By forming a uniform profile in the SONOS structure and adjusting the heating element and gas flow rate, the problem of uneven silicon nitride film thickness was solved, the uniformity of the deposited layer and the interface quality were improved, and the manufacturing efficiency and yield of semiconductor devices were increased.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- EMEMORY TECH INC
- Filing Date
- 2025-11-05
- Publication Date
- 2026-05-12
AI Technical Summary
In the prior art, the stoichiometry of the silicon nitride thin film in the SONOS structure is not uniform and the thickness distribution is not optimized, which leads to significant process challenges and affects the quality of the trapped charge layer.
By forming a uniform profile on the deposited layer, utilizing in-situ steam generation to adjust the temperature and gas flow of the heating element, selecting an appropriate process formulation, consuming a portion of the deposited layer to form a uniform oxide layer, and optimizing the thickness distribution.
This improved the uniformity of the deposited layer thickness and the interface quality, thereby increasing the manufacturing efficiency and yield of semiconductor devices and reducing manufacturing costs.
Smart Images
Figure CN122028431A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by utilizing in-situ steam generation in conjunction with adjusting heating elements to precisely oxidize and deposit a layer to achieve a uniform thickness. Background Technology
[0002] Oxide-nitride-oxide (ONO) stacks in silicon-oxide-nitride-oxide-silicon (SONOS) transistors can be effectively used as a charge trapping layer, or as an isolation layer between gates in split-gate flash memory. However, the charge trapping quality in SONOS structures depends primarily on the silicon nitride (SiN) thin film. Its non-uniform stoichiometry and unoptimized thickness distribution pose significant fabrication challenges. Summary of the Invention
[0003] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a first trapped charge layer on a first oxide layer of a first wafer in a batch of wafers by a deposition process; obtaining a first uniformity profile of the first trapped charge layer; determining first feedforward compensation information of the first wafer based on one of the first uniformity profile and a target uniformity profile; selecting a first process recipe from a plurality of process parameter recipes based on the first feedforward compensation information; and forming a second oxide layer by a first oxidation process that consumes a portion of the first trapped charge layer according to the first process recipe.
[0004] In some embodiments, the method further includes: removing the second oxide layer; and forming a third oxide layer on the first captured charge layer.
[0005] In some embodiments, determining the first feedforward compensation information includes: comparing the thickness of the first captured charge layer at different locations in the first uniformity profile; and determining the first feedforward compensation information, wherein the first feedforward compensation information compensates for locations having a plurality of first thicknesses more than compensates for locations having a plurality of second thicknesses, wherein the plurality of first thicknesses are greater than the plurality of second thicknesses.
[0006] In some embodiments, the first process formulation includes at least a plurality of heating temperatures for a plurality of heating elements. Selecting the first process formulation based on the first feedforward compensation information includes: selecting a process formulation in which the heating temperature corresponding to a position having a plurality of first thicknesses is higher than the heating temperature corresponding to a position having a plurality of second thicknesses.
[0007] In some embodiments, the method further includes: adjusting the positions of a plurality of heating elements located above the first captured charge layer according to the first uniformity profile.
[0008] In some embodiments, determining the first feedforward compensation information includes: comparing multiple thicknesses of the first captured charge layer at different locations in the first uniformity profile with a target thickness in the target uniformity profile to generate multiple thickness differences; and determining the first feedforward compensation information, wherein the first feedforward compensation information is greater for thermal compensation at locations with larger thickness differences than for locations with smaller thickness differences.
[0009] In some embodiments, a plurality of heating elements are disposed above the first wafer. Selecting the first process recipe based on the first feedforward compensation information includes: selecting a process recipe in which the heating temperature corresponding to the heating element at the location with a larger thickness difference is higher than the heating temperature corresponding to the heating element at the location with a smaller thickness difference.
[0010] In some embodiments, determining the first feedforward compensation information further includes: comparing the average thickness of the first captured charge layer in the first uniformity profile with the target average thickness of the target uniformity profile to generate an average thickness difference; and determining gas flow compensation in the first feedforward compensation information based on the average thickness difference.
[0011] In some embodiments, selecting the first process formulation based on the first feedforward compensation information further includes selecting the process formulation having a gas flow rate and corresponding process time that matches the gas flow compensation.
[0012] In some embodiments, the first process formulation includes at least one of a heating temperature of a plurality of heating elements located above the first wafer, a process time, and a gas flow rate that reacts with the first trapped charge layer.
[0013] In some embodiments, the method further includes: forming a second trapped charge layer on a third oxide layer of a second wafer in the batch of wafers by means of the deposition process; obtaining a second uniformity profile of the second trapped charge layer; determining second feedforward compensation information of the second wafer based on the second uniformity profile and the target uniformity profile; selecting a second process formulation from the plurality of process parameter formulations based on the second feedforward compensation information; and forming a fourth oxide layer by means of a second oxidation process that consumes a portion of the second trapped charge layer according to the second process formulation.
[0014] In some embodiments, the average thickness of the first uniformity profile and the average thickness of the second uniformity profile are substantially the same, and the first process formulation is the same as the second process formulation.
[0015] In some embodiments, determining the first feedforward compensation information includes: comparing the average thickness of the first uniformity profile with the target average thickness of the target uniformity profile to generate a first average thickness difference; and determining the first feedforward compensation information based on the first average thickness difference. Determining the second feedforward compensation information includes: comparing the average thickness of the second uniformity profile with the target average thickness to generate a second average thickness difference; and determining the second feedforward compensation information based on the second average thickness difference.
[0016] In some embodiments, when the first average thickness difference is less than the second average thickness difference, selecting the first process formulation includes selecting a process formulation corresponding to a first reaction rate that consumes the first captured charge layer; and selecting the second process formulation includes selecting a process formulation corresponding to a second reaction rate that consumes the second captured charge layer, wherein the first reaction rate is slower than the second reaction rate.
[0017] In some embodiments, the method further includes: when the thickness of the first captured charge layer at a location on the first wafer is different from the thickness of the second captured charge layer at the same location on the second wafer, adjusting a plurality of process parameters for forming the fourth oxide layer from parameters in the first process formulation to parameters in the second process formulation.
[0018] In some embodiments, the thickness of the remaining portion of the first captured charge layer is the same as the thickness of the remaining portion of the second captured charge layer.
[0019] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: obtaining multiple uniformity profiles of multiple deposited layers in a batch of wafers; determining feedforward compensation information based on multiple thickness mapping profiles generated by comparing the multiple uniformity profiles with target uniformity profiles; and adjusting multiple process parameters of an oxidation process based on the feedforward compensation information to consume portions of the multiple deposited layers in the wafers.
[0020] In some embodiments, comparing the plurality of uniformity profiles with the target uniformity profile includes: comparing a plurality of average thicknesses of the deposited layers in the plurality of wafers with a target thickness to generate a plurality of thickness differences in the plurality of thickness mapping profiles.
[0021] In some embodiments, comparing the plurality of uniformity profiles with the target uniformity profile includes: comparing the plurality of thicknesses of the plurality of deposited layers at different locations in each of the plurality of uniformity profiles with the target thickness in the target uniformity profile to generate a corresponding one of the plurality of thickness mapping profiles.
[0022] In some embodiments, adjusting the plurality of process parameters in the oxidation process includes: adjusting the plurality of process parameters according to selecting a process formulation from a plurality of process parameter formulations that matches the feedforward compensation information. Attached Figure Description
[0023] The various elements of this invention will be fully understood when read in conjunction with the following detailed description and accompanying drawings. As is customary in the industry, features are not drawn to scale for ease of explanation. Actual dimensions may be enlarged or reduced arbitrarily for clarity of discussion.
[0024] Figure 1 This is a flowchart of a method according to some embodiments of the present invention.
[0025] Figure 2 This is a schematic diagram of a semiconductor device according to some embodiments of the present invention.
[0026] Figure 3 According to some embodiments of the present invention, Figure 2 A schematic diagram of a semiconductor device.
[0027] Figure 4 To provide corresponding embodiments according to the present invention Figure 3 A schematic diagram of a semiconductor device wafer.
[0028] Figure 5 According to some embodiments of the present invention, Figures 2 to 4 A schematic diagram of a semiconductor device.
[0029] Figure 6 According to some embodiments of the present invention, Figure 5 A schematic diagram of a semiconductor device.
[0030] Figure 7 According to some embodiments of the present invention, Figure 5 A schematic diagram of a semiconductor device. Detailed Implementation
[0031] The following figures and detailed description will illustrate the core essence of the present invention. Those skilled in the art can make changes and modifications to its teachings without departing from the spirit and scope of the present invention.
[0032] Now refer to Figure 1 . Figure 1This is a flowchart of a method M100 according to some embodiments of the present invention. It should be understood that additional operations may be performed in the pre-, mid-, and post-stages shown in the flowchart, as well as in other embodiments, and some of the operations described later may be replaced or omitted. Method M100 includes the methods referenced below. Figures 2 to 7 Steps S101 to S107 are described above. In some embodiments, method M100 manufactures a semiconductor device 200 having a silicon-oxide-oxynitride-oxide-silicon (SONOS) structure composed of multiple thin films.
[0033] In step S101, as Figure 2 As shown, an oxide layer 204 is formed on substrate 202 as the bottom layer of semiconductor device 200. In some embodiments, the oxide layer 204 can be formed or deposited by any suitable method, such as thermal oxidation growth or deposition using chemical vapor deposition (CVD). In another embodiment, the oxide layer 204 can be grown in an in-situ steam generation (ISSG) chamber via a free-body oxidation process involving the interaction of oxygen (O2) and hydrogen (H2).
[0034] In some embodiments, substrate 202 may comprise any known silicon-based semiconductor material, such as silicon, silicon-germanium, silicon-on-insulator (SOI), or sapphire-on-silicon substrate. Alternatively, substrate 202 may comprise a silicon layer formed on a non-silicon-based semiconductor material, such as gallium arsenide, germanium, gallium nitride, or aluminum phosphide. In certain embodiments, substrate 202 is a doped or undoped silicon substrate. Oxide layer 204 may comprise a relatively thin silicon dioxide layer.
[0035] After the bottom oxide layer 204 is formed, in step S102, the thickness of the oxide layer 204 is measured to check whether it meets the process specifications. When the properties of the oxide layer 204 meet the process standards, step S103 is performed.
[0036] In step S103, as Figure 3 The diagram illustrates that a deposition layer 206 is formed through a deposition process as a charge trapping layer in a semiconductor device 200. In some embodiments, the semiconductor device 200 constitutes and functions as at least one transistor. In some embodiments, the deposition layer 206 comprises silicon nitride (SiN). The deposition layer 206 is deposited in a reaction chamber by chemical vapor deposition (CVD), preferably by plasma-enhanced CVD (PECVD) to facilitate low-temperature compatibility. Silane (SiH4) and ammonia (NH3) precursors, along with a carrier gas (such as nitrogen), are introduced into the reaction chamber, and plasma is generated using radio frequency (RF) power to decompose the gas and deposit a SiN thin film on the oxide layer 204.
[0037] In other words, the distribution of the deposited layer 206 on the semiconductor device 200 exhibits a thickness non-uniformity, being thicker at the edges and thinner in the center. In some cases, the semiconductor device 200 is formed on a wafer 402 placed among other wafers in the same batch. Due to the consumption of precursor gases (silane, ammonia, etc.) during the deposition process, the wafer edges are exposed to a higher concentration of fresh gas than the central region, resulting in a higher deposition rate at the edges than in the central region.
[0038] To ensure uniformity of the thickness of the deposition layer 206, in step S104, the thickness of the deposition layer 206 is measured at different locations to obtain its uniformity profile. For example... Figures 4 to 5 As shown, to generate a uniformity profile, the locations of each measurement point of the semiconductor device on the wafer and the thickness of its deposited layer 206 are recorded. In some embodiments, the uniformity profile is also referred to as a thickness mapping profile.
[0039] like Figure 5 As shown, the thicknesses TK1 and TK2 at the two side edges are greater than the thickness TK3 in the central region. In some embodiments, to obtain a more complete uniformity profile, the thickness can be measured at other measurement points, for example, the thickness TK4 at the peripheral points is between TK2 and TK3.
[0040] Furthermore, an oxidation process is performed on the deposited layer 206 to consume a portion of it and unify the remaining thickness. In some embodiments, the oxidation process parameters determined for a specific thickness are referred to as the process formulation, one of which is the heating temperature during oxidation.
[0041] For example, such as Figure 4 and Figure 5 As shown, a wafer 402 is placed in an ISSG chamber equipped with a plurality of heating elements 510 located above the wafer 402 and serving as radiant energy components. In some embodiments, the heating elements 510 are configured to be independently controllable to provide highly uniform or non-uniform heating of the wafer 402 as required by the process. In one embodiment, the heating elements 510 are grouped generally in concentric regions. This allows for variation in the radial or desired temperature distribution of the wafer 402. The fineness and symmetry of thermal control can vary depending on the specific process requirements. In such cases, precise temperature control enables the control required for oxidation growth to be achieved in the subsequent step S107.
[0042] In step S105, feedforward compensation information for wafer 402 is determined based on at least one of the first uniformity profile and the target uniformity profile. In some embodiments, the feedforward compensation information is generated based on the output of the previous step before the subsequent oxide layer formation step. For example, the thickness of the deposited layer 206 formed in step S103 is used to optimize the process parameters of the subsequent step S106 to achieve the target standard. Unlike the feedback method of adjusting the manufacturing tool based on the performance of the current batch of finished products after step S106 to avoid wasting the current batch, this invention actively adjusts the manufacturing tool using information from previous steps to optimize the process of the current batch. This method improves manufacturing efficiency and optimizes manufacturing costs.
[0043] According to some embodiments, such as Figure 5 As shown, determining the feedforward compensation information involves comparing the thicknesses TK1 to TK4 of the deposited layer 206 at different locations in the uniformity profile with the target thickness GTK in the target uniformity profile to generate a thickness difference. In some embodiments, the target thickness GTK is the desired thickness of the deposited layer 206 in the semiconductor device 200. In some embodiments, based on the thickness difference, it is determined that the thermal compensation for locations with larger thickness differences is greater than the thermal compensation for locations with smaller thickness differences. For example, as... Figure 5 As shown, the thermal compensation in the edge region is greater than that in the center region.
[0044] Next, in step S106, a process formula is selected from multiple process formulas based on feedforward compensation information. For example, the first process formula sets the heating temperature of all heating elements 510 to the same value; while the second process formula sets the heating temperature of heating elements 510 corresponding to locations with larger thickness differences (such as edges) higher than the heating temperature of heating elements 510 corresponding to locations with smaller thickness differences (such as the center area). To conform to the feedforward compensation information, the second process formula is selected for subsequent operations.
[0045] In step S107, as Figure 6 As shown, based on the selected process formulation, the oxidation process consumes heat energy and gas flow 502. Figure 5 The top layer of the deposition layer 206 in the middle is used to form an oxide layer O2O6. Specifically, as Figure 6 As shown, a gas stream 502, consisting of a mixture of oxygen-containing gas and hydrogen-containing gas, is fed into the ISSG reaction chamber of the semiconductor device 200. The oxygen-containing gas reacts with the hydrogen-containing gas to generate water vapor (H2O). As a result, the thickness of the remaining portion of the deposited layer 206 is uniformly matched to the target thickness GTK.
[0046] like Figure 6As shown in the ISSG wet oxidation process, the top region of the deposited layer 206 (e.g., a SiN thin film) is selectively converted into a stable oxide layer O2O6 (e.g., a SiO2 thin film). This conversion removes sensitive silicon nitride variations from the active region, improving interface quality and dielectric performance. In some embodiments, the oxide layer O2O6 is retained and configured as the top oxide layer of the SONOS structure of the semiconductor device 200.
[0047] In other embodiments, method M100 further includes removing the oxide layer O206 using a suitable process (e.g., chemical mechanical planarization / polishing (CMP)) and forming an oxide layer on the deposited layer 206. Figure 7 As shown in the schematic diagram, after removing the oxide layer O206, a deposition layer 208 is formed on the deposition layer 206 by an appropriate process (e.g., CVD). In some embodiments, the deposition layer 208 is configured as the top oxide layer of the SONOS structure of the semiconductor device 200.
[0048] In other embodiments, instead of comparing the measured thickness with the target thickness, the thicknesses at different locations of the deposited layer 206 (e.g., thicknesses TK1, TK2, TK3, TK4) are compared with each other. Then, in step S105, it is determined that the compensation for thicker locations (e.g., edges) is greater than the compensation for thinner locations (e.g., the central region). Therefore, when selecting the corresponding process formulation in step S106, the heating temperature of the heating element 510 corresponding to the thicker location is higher than the heating temperature of the heating element 510 corresponding to the thinner location.
[0049] Furthermore, in some embodiments, method M100 also includes adjusting the configuration position of the heating element 510 located above the deposition layer 206 according to the uniformity profile. For example, based on the thickness gradient of the deposition layer 206, the density of the heating element 510 is higher in regions with a larger thickness variation rate than in regions with a smaller thickness variation rate.
[0050] In addition to adjusting the heating temperature of the heating element 510, the process parameters of the oxidation process formulation may also include the flow rate of the gas stream 502 and / or the process duration. In some embodiments, determining the feedforward compensation information includes gas flow rate compensation.
[0051] For example, refer to Figure 4 Based on the thickness of all measurement points on wafer 402, the average thickness of the deposited layer 206 is calculated and compared with the target average thickness in the target uniformity profile to generate an average thickness difference. Then, gas flow rate compensation in the feedforward compensation information is determined based on this average thickness difference. For example, for a larger average thickness difference, the gas flow rate compensation is greater than for a smaller average thickness difference. Accordingly, a process formulation with a matching gas flow rate compensation and process duration is selected.
[0052] For example, to meet the requirement of larger gas flow rate compensation, at least one of the gas flow rate and / or process duration is adjusted to a value higher than that required for smaller gas flow rate compensation, so as to consume more of the deposition layer 206 thickness and achieve the target average thickness.
[0053] In some embodiments, the target average thickness applies to all wafers in a process batch comprising multiple wafers. To monitor the process, method M100 can be performed on several wafers in the batch (e.g., a first wafer, a wafer at one-third of the batch, and a wafer at two-thirds of the batch). The average thickness of these wafers is compared to a target average thickness in a target uniformity profile to generate an average thickness difference. Feedforward compensation information for each wafer is then determined based on the average thickness difference. In some embodiments, when the average thickness difference of the first wafer is less than the average thickness difference of the second wafer, the deposition layer consumption reaction rate corresponding to the process formulation selected for the first wafer is slower. For example, the formulation is adjusted to at least one of a lower temperature, a slower gas flow rate, or a longer reaction time. Conversely, the process formulation selected for the second wafer corresponds to a faster consumption reaction rate.
[0054] The selection of each wafer process formulation is similar to that discussed above, so it will not be repeated here.
[0055] In other embodiments, when the average thickness of the deposited layer 206 in the uniformity profile of the first wafer is substantially the same as the average thickness of another monitored wafer (e.g., the wafer located at one-third of the way down), the process parameters used for the first wafer up to the two-thirds-way point are kept unchanged. Next, it is determined whether the average thickness of the wafer located at the two-thirds-way point matches that of the wafer located at the one-third-way point; if the difference is too large, another process formulation is selected to perform step S107 on the wafer located at the two-thirds-way point and subsequent wafers.
[0056] In some embodiments, by selecting an appropriate process formulation, the heating temperature of the heating element 510 is spatially adjusted according to the thickness at different locations on a single wafer, and the gas flow rate and reaction time are controlled, so that the oxidation process targets the portion of the deposited layer consumed in each region, suppressing variations in the deposited layer thickness. Thus, for example, the remaining thickness of the deposited layer 206 on the first wafer is substantially the same as the remaining thickness on the second wafer, achieving optimal uniformity of the deposited layer within the process batch.
[0057] This invention proactively utilizes data from previous steps to optimize manufacturing tools for the current batch, avoiding waste and improving efficiency. Unlike feedback adjustments made after batch processing, this method strategically employs feedforward information. By selecting the process formulation, it spatially controls the heating element temperature, gas flow rate, and reaction time, consuming a portion of the deposited layer during the oxidation step and suppressing thickness variations. This ensures uniform deposited layer thickness across different wafers, optimizes manufacturing costs, and improves yield and throughput through spatial control of thickness gradients.
[0058] While the present invention has been described above with reference to examples and preferred embodiments, it is not limited thereto. Those skilled in the art can make various changes, substitutions, and modifications without departing from the spirit and scope of the invention. In view of the foregoing description, anything falling within the scope of the appended claims is covered by the present invention.
[0059] [Symbol Explanation] M100: Method S101-S107: Steps 200: Semiconductor devices 202: Substrate 204: Oxide layer 206: Sedimentary layer 208: Sedimentary layer 402: Wafer 502: Gas Flow 510: Heating element TK1, TK2, TK3, TK4: Thickness GTK: Target Thickness O2O6: Oxide layer x, z: direction.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, Include: A first charge trapping layer is formed on the first oxide layer of the first wafer in a batch of wafers through a deposition process; Obtain the first uniformity profile of the first captured charge layer; The first feedforward compensation information of the first wafer is determined based on either the first uniformity profile or the target uniformity profile. Based on the first feedforward compensation information, a first process formulation is selected from multiple process parameter formulations; and According to the first process formulation, a second oxide layer is formed by a first oxidation process that consumes a portion of the first captured charge layer.
2. The method according to claim 1, wherein, Further includes: Remove the second oxide layer; and A third oxide layer is formed on the first captured charge layer.
3. The method of claim 1, wherein determining the first feedforward compensation information comprises: Compare the thickness of the first captured charge layer at different locations within the first uniformity profile; and The first feedforward compensation information is determined, wherein the compensation for a location having a plurality of first thicknesses is greater than the compensation for a location having a plurality of second thicknesses, wherein the plurality of first thicknesses are greater than the plurality of second thicknesses.
4. The method of claim 3, wherein the first process formulation comprises at least a plurality of heating elements at a plurality of heating temperatures. The selection of the first process formulation based on the first feedforward compensation information includes: The selected process formulation is such that the heating temperature of the heating element corresponding to the position having the plurality of first thicknesses is higher than the heating temperature of the heating element corresponding to the position having the plurality of second thicknesses.
5. The method according to claim 1, wherein, Further includes: The positions of the plurality of heating elements located above the first captured charge layer are adjusted according to the first uniformity profile.
6. The method of claim 1, wherein determining the first feedforward compensation information comprises: Multiple thicknesses of the first captured charge layer at different locations in the first uniformity profile are compared with the target thickness in the target uniformity profile to generate multiple thickness differences; and The first feedforward compensation information is determined, wherein the thermal compensation for a location with a larger thickness difference is greater than the thermal compensation for a location with a smaller thickness difference.
7. The method according to claim 6, wherein a plurality of heating elements are provided above the first wafer. The selection of the first process formulation based on the first feedforward compensation information includes: The selected process formula is a heating temperature for heating elements at locations with larger thickness differences that is higher than the heating temperature for heating elements at locations with smaller thickness differences.
8. The method of claim 6, wherein determining the first feedforward compensation information further comprises: The average thickness of the first captured charge layer in the first uniformity profile is compared with the target average thickness of the target uniformity profile to generate an average thickness difference; and The gas flow compensation in the first feedforward compensation information is determined based on the average thickness difference.
9. The method of claim 8, wherein selecting the first process formulation based on the first feedforward compensation information further comprises: Select the process formulation, which has a gas flow rate and corresponding process time that match the gas flow compensation.
10. The method of claim 1, wherein the first process formulation comprises at least one of a heating temperature of a plurality of heating elements located above the first wafer, a process time, and a gas flow rate reacting with the first captured charge layer.
11. The method according to claim 1, wherein, Further includes: A second charge trapping layer is formed on the third oxide layer of the second wafer in the batch using the deposition process. Obtain the second uniformity profile of the second captured charge layer; The second feedforward compensation information of the second wafer is determined based on the second uniformity profile and the target uniformity profile. Based on the second feedforward compensation information, a second process formulation is selected from the plurality of process parameter formulations; and According to the second process formulation, a fourth oxide layer is formed by a second oxidation process that consumes a portion of the second captured charge layer.
12. The method of claim 11, wherein the average thickness of the first uniformity profile and the average thickness of the second uniformity profile are substantially the same, and the first process formulation and the second process formulation are the same.
13. The method of claim 11, wherein determining the first feedforward compensation information comprises: The average thickness of the first uniformity profile is compared with the target average thickness of the target uniformity profile to generate a first average thickness difference; and The first feedforward compensation information is determined based on the first average thickness difference. The information that determines the second feedforward compensation includes: The average thickness of the second uniformity profile is compared with the target average thickness to generate a second average thickness difference; and The second feedforward compensation information is determined based on the second average thickness difference.
14. The method of claim 13, wherein when the first average thickness difference is less than the second average thickness difference, Selecting the first process formulation includes selecting a process formulation corresponding to the first reaction rate that consumes the first captured charge layer; and Selecting the second process formulation includes selecting a process formulation corresponding to the second reaction rate that consumes the second captured charge layer. The first reaction rate is slower than the second reaction rate.
15. The method according to claim 11, wherein, Further includes: When the thickness of the first captured charge layer at a location on the first wafer is different from the thickness of the second captured charge layer at the same location on the second wafer, The multiple process parameters for forming the fourth oxide layer are adjusted from those in the first process formulation to those in the second process formulation.
16. The method of claim 11, wherein the thickness of the remaining portion of the first captured charge layer is the same as the thickness of the remaining portion of the second captured charge layer.
17. A method for manufacturing a semiconductor device, characterized in that, Include: Obtain multiple uniformity profiles of multiple deposited layers in a batch of wafers; Based on the multiple thickness mapping profiles generated by comparing the multiple uniformity profiles with the target uniformity profile, the feedforward compensation information is determined; and Based on the feedforward compensation information, multiple process parameters of the oxidation process are adjusted to consume a portion of the multiple deposited layers in the batch of wafers.
18. The method of claim 17, wherein comparing the plurality of uniformity profiles with the target uniformity profile comprises: The average thicknesses of the multiple deposited layers in the multiple wafers are compared with the target thickness to generate multiple thickness differences in the multiple thickness mapping profiles.
19. The method of claim 17, wherein comparing the plurality of uniformity profiles with the target uniformity profile comprises: The thicknesses of the multiple deposited layers at different locations in each of the multiple uniformity profiles are compared with the target thickness in the target uniformity profile to generate a corresponding one of the multiple thickness mapping profiles.
20. The method of claim 17, wherein adjusting the plurality of process parameters in the oxidation process comprises: The multiple process parameters are adjusted based on a process formulation selected from multiple process parameter formulations that matches the feedforward compensation information.