Manufacturing method of gallium nitride device

Abstract

The invention provides a manufacturing method of a gallium nitride device. The manufacturing method comprises the following steps: sequentially forming a GaN channel layer and a barrier layer on a provided substrate layer; covering the formed structure to form a first P-GaN layer, and forming a first etching barrier layer on the first P-GaN layer; forming a second P-GaN layer on the first etching barrier layer; covering the formed structure to form a gate metal layer; forming a pattern through a photoetching process, then etching the gate metal layer to form a gate, and then continuously performing downward etching by taking the gate as a mask until the first etching barrier layer; forming a pattern through a photoetching process, and then etching the first etching barrier layer and the first P-GaN layer; source electrode metal and drain electrode metal are formed on the two sides of the remaining first P-GaN layer respectively, and a step shape is formed between the second P-GaN layer and the first P-GaN layer on the side close to the drain electrode metal.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride device technology, and more specifically to a method for manufacturing a gallium nitride device. Background Technology

[0002] With the continuous development of semiconductor process technology, gallium nitride (GaN) HEMTs (High Electron Mobility Transistors) have made significant progress in high-power microwave applications. GaN HEMTs are typically depletion-mode devices, meaning they are in the on-state when the threshold voltage Vth < 0V and the gate voltage Vg = 0V. To ensure circuit safety and simplify circuitry, normally-off devices, i.e., enhancement-mode devices, are preferred in practical applications. GaN devices using P-GaN cap technology have easily controllable threshold voltages, good breakdown characteristics, and high device stability, making them the mainstream technology for enhancement-mode GaN devices in the market. However, GaN devices using conventional P-GaN cap technology still suffer from concentrated electric field lines on the gate electrode side and high electric field spikes at the channel, affecting the device's breakdown characteristics and causing current collapse problems. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method for manufacturing gallium nitride devices to improve the voltage withstand level of gallium nitride devices.

[0004] This invention provides a method for manufacturing a gallium nitride device, comprising:

[0005] S10: GaN channel layer and barrier layer are sequentially formed on the provided substrate layer;

[0006] S20: The structure formed by the cover is used to form a first P-GaN layer, and a first etch barrier layer is formed on the first P-GaN layer;

[0007] S30: Form a second P-GaN layer on the first etch barrier layer;

[0008] S40: The structure formed by the cover creates a gate metal layer;

[0009] S50: A pattern is formed by photolithography, and then the gate metal layer is etched to form a gate. Then, the gate is used as a mask to continue etching downwards until the first etch barrier layer is reached.

[0010] S60: A pattern is formed by photolithography, and then the first etch barrier layer and the first P-GaN layer are etched. The remaining second P-GaN layer and the first P-GaN layer after etching form the P-GaN region of the device.

[0011] S70: Source metal and drain metal are formed on both sides of the P-GaN region, respectively. On the side closer to the drain metal, the second P-GaN layer and the first P-GaN layer are stepped.

[0012] Furthermore, the material of the first etch barrier layer is AlGaN or AlN.

[0013] Furthermore, step S10 includes:

[0014] A GaN channel layer and a barrier layer are sequentially formed on the provided substrate;

[0015] A second etch barrier layer is formed on the barrier layer.

[0016] Furthermore, the material of the second etch barrier layer is AlGaN or AlN.

[0017] Furthermore, step S30 includes:

[0018] A second P-GaN layer is formed on the first etch barrier layer;

[0019] A high-resistivity layer is formed on the second P-GaN layer.

[0020] Furthermore, the high-resistivity layer is made of AlGaN or AlN, and the high-resistivity layer is doped with carbon or iron ions.

[0021] Furthermore, it also includes step S80:

[0022] The structure formed by the covering layer constitutes the first dielectric layer;

[0023] A field plate is formed on the first dielectric layer between the P-GaN region and the drain metal, the field plate being located above the barrier layer and extending above the first P-GaN layer.

[0024] Furthermore, the material of the first dielectric layer is silicon nitride.

[0025] The present invention provides a method for manufacturing a gallium nitride (GaN) device. By setting a first etch barrier layer between adjacent P-GaN layers, the thickness of each P-GaN layer can be precisely controlled through the growth process. Furthermore, when etching the second P-GaN layer, etching stops at the first etch barrier layer, which protects the underlying P-GaN layer from being etched, thereby accurately controlling the shape of the formed step. At the same time, since the first etch barrier layer is made of a III-V group material and is relatively thin, it does not affect the gate control capability of the gallium nitride device. Attached Figure Description

[0026] Figures 1-7This is a cross-sectional structural diagram of the main process nodes of an embodiment of a gallium nitride device manufacturing method provided by the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0028] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0029] Figures 1-7 This is a cross-sectional structural diagram of the main process nodes of an embodiment of a gallium nitride device manufacturing method provided by the present invention, as shown below. Figures 1-7 As shown, a method for manufacturing a gallium nitride device according to the present invention includes:

[0030] First, such as Figure 1 As shown, a GaN channel layer 102 and a barrier layer 103 are sequentially formed on the provided substrate layer 101. The substrate layer 101 typically includes a substrate layer, such as silicon or silicon carbide, an AlN nucleation layer, an AlGaN buffer layer, etc. The material of the channel layer 102 is typically GaN, and the material of the barrier layer 103 is typically AlGaN. Next, a thin second etch stop layer 104b is formed on the barrier layer 103. The material of the second etch stop layer 104b is AlGaN or AlN, and its thickness is preferably 2-10 nanometers.

[0031] Next, as Figure 2As shown, the structure formed by covering the first P-GaN layer 105a is formed, and a thin first etch barrier layer 104a is formed on the first P-GaN layer 105a. The material of the first etch barrier layer 104a is AlGaN or AlN, and its thickness is preferably 2-10 nanometers. Then, a second P-GaN layer 105b is formed on the first etch barrier layer 104a. By setting the first etch barrier layer 104a between the first P-GaN layer 105a and the second P-GaN layer 105b, the thicknesses of the formed first P-GaN layer 105a and the second P-GaN layer 105b can be precisely controlled by the growth process.

[0032] Next, as Figure 3 As shown, a high-resistivity layer 106 is formed on the second P-GaN layer 105b. The material of the high-resistivity layer 106 is preferably AlGaN or AlN, and the high-resistivity layer 106 is doped with carbon or iron ions. Then, a gate metal layer 107 is formed over the formed structure. The high-resistivity layer 106 is an optional structure. After forming the high-resistivity layer 106, a MIS (Metal-Insulator-Semiconductor) structure can be formed between the gate metal layer 107, the high-resistivity layer 106, and the second P-GaN layer 105b, which can reduce gate leakage current in gallium nitride devices.

[0033] Next, as Figure 4 As shown, a pattern is formed using photolithography, and then the gate metal layer 107 is etched. The remaining gate metal layer after etching forms the gate 107 of the gallium nitride device. Then, using the gate 107 as a mask, etching continues downwards until the first etch barrier layer 104a is reached. When etching the second P-GaN layer 105b, the first etch barrier layer 104a protects the underlying first P-GaN layer 105a from being etched, thus accurately controlling the shape of the formed step. Simultaneously, since the first etch barrier layer 104a is made of a III-V group material and is relatively thin, it does not affect the gate control capability of the gallium nitride device.

[0034] Next, as Figure 5 As shown, a pattern is formed using photolithography, and then the first etch barrier layer 104a and the first P-GaN layer 105a are etched up to the second etch barrier layer 104b. The remaining first P-GaN layer 105a and second P-GaN layer 105b after etching form the P-GaN region of the device. The second etch barrier layer 104b is an optional structure. Since the etching time for the first P-GaN layer 105a is relatively long, forming the second etch barrier layer 104b protects the barrier layer 103 from damage during the etching of the first P-GaN layer 105a.

[0035] Next, as Figure 6As shown, source metal 108 and drain metal 109 are formed on both sides of the P-GaN region, respectively. The specific steps include first etching away the exposed second etch barrier layer 104b, then forming a metal layer, and finally forming the source metal 108 and drain metal 109 through photolithography and etching processes. On the side near the drain metal 109, the second P-GaN layer 105b and the first P-GaN layer 105a form a step, meaning the extension length of the first P-GaN layer 105a is greater than the extension length of the second P-GaN layer 105b, and the first P-GaN layer 105a is closer to the drain metal 109 than the second P-GaN layer 105b. It should be noted that... Figure 5 The explanation uses only the example of a P-GaN region comprising a first P-GaN layer 105a and a second P-GaN layer 105b. In reality, a P-GaN region may include at least two stacked P-GaN layers, such as three, four, or more layers. In two adjacent P-GaN layers, the lower P-GaN layer is closer to the drain metal 109 than the upper P-GaN layer, thus forming a P-GaN region with a multi-step structure.

[0036] Next, as Figure 7 As shown, the structure formed by the covering creates a first dielectric layer 111, which is typically made of silicon nitride. A field plate 110 is then formed on the first dielectric layer 111, between the P-GaN region and the drain metal 109. The field plate 110 is located above the barrier layer 103 and extends above the first P-GaN layer 105a. The field plate 110 is electrically connected to the source metal 108, which can improve the breakdown voltage of the gallium nitride device.

[0037] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for manufacturing a gallium nitride device, characterized in that, include: S10: GaN channel layer and barrier layer are sequentially formed on the provided substrate layer; S20: The structure formed by the cover is used to form a first P-GaN layer, and a first etch barrier layer is formed on the first P-GaN layer; S30: Form a second P-GaN layer on the first etch barrier layer; S40: The structure formed by the cover creates a gate metal layer; S50: A pattern is formed by photolithography, and then the gate metal layer is etched to form a gate. Then, the gate is used as a mask to continue etching downwards until the first etch barrier layer is reached. S60: A pattern is formed by photolithography, and then the first etch barrier layer and the first P-GaN layer are etched. The remaining second P-GaN layer and the first P-GaN layer after etching form the P-GaN region of the device. S70: Source metal and drain metal are formed on both sides of the P-GaN region, respectively. On the side closer to the drain metal, the second P-GaN layer and the first P-GaN layer are stepped.

2. The method for manufacturing a gallium nitride device according to claim 1, characterized in that, The material of the first etching barrier layer is AlGaN or AlN.

3. The method for manufacturing a gallium nitride device according to claim 1, characterized in that, Step S10 includes: A GaN channel layer and a barrier layer are sequentially formed on the provided substrate; A second etch barrier layer is formed on the barrier layer.

4. The method for manufacturing a gallium nitride device according to claim 3, characterized in that, The material of the second etching barrier layer is AlGaN or AlN.

5. The method for manufacturing a gallium nitride device according to claim 1, characterized in that, Step S30 includes: A second P-GaN layer is formed on the first etch barrier layer; A high-resistivity layer is formed on the second P-GaN layer.

6. The method for manufacturing a gallium nitride device according to claim 5, characterized in that, The high-resistivity layer is made of AlGaN or AlN and is doped with carbon or iron ions.

7. The method for manufacturing a gallium nitride device according to claim 1, characterized in that, It also includes step S80: The structure formed by the covering layer constitutes the first dielectric layer; A field plate is formed on the first dielectric layer between the P-GaN region and the drain metal, the field plate being located above the barrier layer and extending above the first P-GaN layer.

8. The method for manufacturing a gallium nitride device according to claim 7, characterized in that, The material of the first dielectric layer is silicon nitride.

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