Semiconductor device, manufacturing method thereof and electronic equipment
By forming catalytic droplets on the substrate during semiconductor device manufacturing and inducing semiconductor layer reactions using an annealing process, the lattice mismatch problem caused by heteroepitaxial processes is solved, improving yield and storage density while reducing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-11-12
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, the lattice mismatch caused by heteroepitaxial processes affects the performance and yield of semiconductor devices during manufacturing, and the number of stacked layers is limited, making it difficult to form devices with high storage density.
By forming alternating layers of dielectric and insulating layers on a substrate, and by forming catalytic droplets in the first groove and inducing the semiconductor layer reaction using an annealing process, a transistor channel layer is formed, avoiding lattice mismatch and reducing manufacturing difficulty and cost.
It improves the yield and storage density of semiconductor devices, reduces the difficulty and cost of manufacturing processes, and avoids the limitation of the number of stacked layers on heteroepitaxial growth.
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Figure CN122028448A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect the performance of semiconductor devices.
[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention
[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A stacked structure is formed on a substrate, the stacked structure including multiple layers of first dielectric layers and multiple layers of first insulating layers stacked alternately; the stacked structure has a plurality of first trenches arranged at intervals along a first direction, and a first groove in the same layer as the first insulating layer; the first trenches and the first grooves are connected and both extend along a second direction; the first direction and the second direction intersect and are both parallel to the substrate; Catalytic droplets are formed at the end of the first groove along the second direction; A semiconductor layer is deposited to cover the outer surface of the catalytic droplet and the inner surface of the first groove; The annealing process causes the catalytic droplets to move in a second direction, inducing a reaction in the semiconductor layer to form a transistor semiconductor structure.
[0006] In some possible embodiments, the semiconductor structure includes at least one of monocrystalline silicon, monocrystalline germanium, or silicon-germanium.
[0007] In some possible embodiments, a catalytic droplet is formed at the end of the first groove along the second direction, including: A catalyst layer is deposited in the first trench and the first groove of the first region; the first region is located at the end of the stacked structure along the second direction; The catalyst layer is condensed into catalytic droplets using plasma processing technology, and the catalytic droplets are located in the first region.
[0008] In some possible embodiments, the catalyst layer is made of at least one of indium, gold, nickel, iron, or aluminum.
[0009] In some possible embodiments, the plasma used in the plasma processing technology is formed from hydrogen gas.
[0010] In some possible embodiments, a catalyst layer is deposited within the first trench and the first recess in the first region, including: A first sacrificial layer is filled into the first trench and the first recess; Remove the first sacrificial layer within the first trench and the first recess in the first region; A catalyst layer is deposited in the first trench and the first groove of the first region; Remove the catalyst layer at the bottom of the first trench.
[0011] In some possible embodiments, a semiconductor layer is deposited to cover the outer surface of the catalytic droplet and the inner surface of the first groove, including: A semiconductor material layer is deposited in the first trench and the first recess, such that the semiconductor material layer covers the outer surface of the catalytic droplet and the inner surface of the first recess; Remove the semiconductor material layer in the first trench to form a semiconductor layer.
[0012] In some possible embodiments, after the annealing process causes the catalytic droplets to move in the second direction, inducing a semiconductor layer reaction to form the semiconductor structure of the transistor, the process further includes: The semiconductor structures in the second and third regions are doped to form the first source / drain and the second source / drain, respectively. A gate dielectric structure and a gate are sequentially formed on the outer periphery of the semiconductor structure in the fourth region to form a transistor; the second region, the fourth region and the third region are arranged sequentially along the second direction.
[0013] Secondly, embodiments of this application also provide a semiconductor device, including: a multilayer transistor, each layer of transistors including a plurality of transistors arranged at a distance along a first direction; each transistor including a semiconductor structure extending along a second direction, the semiconductor structure being obtained by inducing the semiconductor layer through catalytic droplet movement based on an annealing process.
[0014] In some possible embodiments, the transistor further includes: The first source and the second source are formed by semiconductor structures located in the second region and the third region, respectively. The gate dielectric structure and the gate are sequentially arranged around the outer periphery of the semiconductor structure in the fourth region; the second region, the fourth region and the third region are arranged sequentially along the second direction.
[0015] Thirdly, embodiments of this application also provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.
[0016] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a catalytic droplet is formed at the end of a first groove co-layered with the first insulating layer, forming a semiconductor layer covering the catalytic droplet. Based on an annealing process, the catalytic droplet rolls within the first groove, gradually inducing the amorphous semiconductor material in the semiconductor layer within the first groove to transform into a crystalline state, forming a semiconductor structure that serves as the channel layer of a transistor. Compared to related technologies that use heteroepitaxial growth of a single-crystal silicon layer as the channel layer, this embodiment avoids dislocation phenomena caused by lattice mismatch in heteroepitaxial growth, reducing the manufacturing difficulty and cost of semiconductor devices and improving their yield. Furthermore, this embodiment does not require consideration of the limitations on the number of stacked layers imposed by heteroepitaxial growth, which is beneficial for forming semiconductor devices with higher storage density.
[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 This is a side view of the film structure after forming alternating layers of first dielectric layer 210 and multiple layers of first insulating layer 220 on a substrate 100 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 3 This is a top view schematic diagram of the film structure after the frame 800 is formed on the substrate 100 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 4 for Figure 3 Schematic diagram of the cross section at point AA'; Figure 5 This is a top view schematic diagram of the film structure after forming a plurality of first trenches 230 arranged along a first direction in a semiconductor device manufacturing method provided in this application embodiment; Figure 6 for Figure 5 Schematic diagram of the cross section at point BB'; Figure 7A cross-sectional schematic diagram of the film structure after forming multiple first grooves 240 in a semiconductor device manufacturing method provided in this application embodiment; Figure 8 A top view schematic diagram of the film structure after filling the first sacrificial layer 500 in the first trench 230 and the first groove 240 in a semiconductor device manufacturing method provided in this application embodiment; Figure 9 for Figure 8 Schematic diagram of the cross section at point BB'; Figure 10 This is a top view of the film structure after removing the first sacrificial layer 500 from the first trench 230 and the first groove 240 of the first region 250 in a semiconductor device manufacturing method provided in this application embodiment. Figure 11 for Figure 10 Schematic diagram of the cross section at point BB'; Figure 12 A top view schematic diagram of the film structure after depositing a catalyst layer 310 in the first trench 230 and the first groove 240 of the first region 250 in a semiconductor device manufacturing method provided in this application embodiment; Figure 13 for Figure 12 Schematic diagram of the cross section at point AA'; Figure 14 for Figure 12 Schematic diagram of the cross section at point BB'; Figure 15 A top view schematic diagram of the film structure after removing the catalyst layer 310 at the bottom of the first trench 230 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 16 for Figure 15 Schematic diagram of the cross section at point BB'; Figure 17 A top view schematic diagram of the film structure after removing all of the first sacrificial layer 500 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 18 A cross-sectional schematic diagram of the film structure after the catalyst layer 310 is condensed into catalytic droplets 300 based on plasma processing technology in a semiconductor device manufacturing method provided in this application embodiment; Figure 19 A top view schematic diagram of the film structure after depositing a semiconductor material layer 412 in the first trench 230 and the first groove 240 in a semiconductor device manufacturing method provided in this application embodiment; Figure 20 for Figure 19 Schematic diagram of the cross section at point AA'; Figure 21for Figure 19 Schematic diagram of the cross section at point BB'; Figure 22 A top view schematic diagram of the film structure after removing the semiconductor material layer 412 in the first trench 230 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 23 for Figure 22 Schematic diagram of the cross section at point AA'; Figure 24 for Figure 22 Schematic diagram of the cross section at point BB'; Figure 25 A cross-sectional schematic diagram of the film structure when the catalytic droplet 300 moves along the second direction based on the annealing process in a semiconductor device manufacturing method provided in this application embodiment; Figure 26 A side view schematic diagram of the film structure after the catalytic droplet 300 moves along the second direction based on the annealing process in a semiconductor device manufacturing method provided in this application embodiment; Figure 27 A schematic cross-sectional view of the film structure in the first direction after the catalytic droplet 300 moves along the second direction based on the annealing process in a semiconductor device manufacturing method provided in this application embodiment; Figure 28 A top view schematic diagram of the film structure after removing the first dielectric layer 210 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 29 for Figure 28 Schematic diagram of the cross section at point AA'; Figure 30 for Figure 28 Schematic diagram of the cross section at point BB'; Figure 31 This is a top view of the film structure after the first insulating layer 220 is filled in the channels between semiconductor structures 410 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 32 for Figure 31 Schematic diagram of the cross section at point AA'; Figure 33 for Figure 31 Schematic diagram of the cross section at point BB'; Figure 34 A top view schematic diagram of the film structure after removing the first insulating layer 220 of the second region 413 and the third region 414 in a semiconductor device manufacturing method provided in this application embodiment; Figure 35 for Figure 34 Schematic diagram of the cross section at point AA'; Figure 36 This is a top view schematic diagram of the film structure after doping the semiconductor structure 410 of the second region 413 and the third region 414 in a semiconductor device manufacturing method provided in an embodiment of this application. Figure 37 for Figure 36 Schematic diagram of the cross section at point AA'; Figure 38 This is a top view of the film structure after the gaps in the second region 413 and the third region 414 are filled with the first insulating layer 220 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 39 for Figure 38 Schematic diagram of the cross section at point AA'; Figure 40 This is a top view schematic diagram of the film structure after removing the first insulating layer 220 of the fourth region 415 in a semiconductor device manufacturing method provided in this application embodiment; Figure 41 for Figure 40 Schematic diagram of the cross section at point AA'; Figure 42 This is a top view of the film structure after a gate dielectric structure 440 and a gate electrode 450 are sequentially formed on the outer periphery of the semiconductor structure 410 in the fourth region 415 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 43 for Figure 42 Schematic diagram of the cross section at point AA'; Figure 44 for Figure 42 Schematic diagram of the cross section at point BB'; Figure 45 This is a three-dimensional structural diagram of a semiconductor device provided in an embodiment of this application.
[0019] Figure label: 100-substrate; 200 - Stacked structure; 210 - First dielectric layer; 220 - First insulating layer; 230 - First trench; 240 - First groove; 250 - First region; 300 - Catalyst droplet; 310 - Catalyst layer; 400 - Transistor; 410 - Semiconductor structure; 411 - Semiconductor layer; 412 - Semiconductor material layer; 413 - Second region; 414 - Third region; 415 - Fourth region; 420 - First source / drain; 430 - Second source / drain; 440 - Gate dielectric structure; 450 - Gate; 500 - First sacrificial layer; 600 - Bit line; 700 - Capacitor; 800 - Frame. Detailed Implementation
[0020] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."
[0022] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0023] The research and development ideas of this application include: in order to achieve higher storage density, better performance and smaller device size, related technologies will use heteroepitaxial technology to form alternating dielectric layers and single-crystal silicon channel layers on the substrate, and form multilayer transistors through multiple deposition, etching and other processes.
[0024] However, heteroepitaxial processes may produce dislocations due to lattice mismatch, which can affect the performance of the channel layer and reduce product yield.
[0025] Moreover, heteroepitaxial processes have limitations on the number of stacked layers. Too many stacked layers may lead to problems such as a higher risk of drop or poor channel layer quality.
[0026] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.
[0027] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.
[0028] This application provides a method for manufacturing a semiconductor device, the process flow diagram of which is shown below. Figure 1 As shown, the method includes steps S101 to S104: S101: As Figures 2-7 As shown, a stacked structure 200 is formed on a substrate 100. The stacked structure 200 includes multiple layers of first dielectric layers 210 and multiple layers of first insulating layers 220 stacked alternately. The stacked structure 200 has a plurality of first trenches 230 arranged at intervals along a first direction and a first groove 240 on the same layer as the first insulating layer 220. The first trenches 230 and the first grooves 240 are connected and both extend along a second direction. The first direction intersects the second direction and is parallel to the substrate 100.
[0029] S102: As Figures 8-18 As shown, a catalytic droplet 300 is formed at the end of the first groove 240 along the second direction.
[0030] S103: As Figures 19-24 As shown, a semiconductor layer 411 is deposited covering the outer surface of the catalytic droplet 300 and the inner surface of the first groove 240.
[0031] S104: As Figures 25-27 As shown, the annealing process causes the catalytic droplets 300 to move along the second direction, inducing the semiconductor layer 411 to react and form the semiconductor structure 410 of the transistor 400.
[0032] In this embodiment, a catalytic droplet 300 is formed at the end of the first groove 240, which is on the same layer as the first insulating layer 220. A semiconductor layer 411 covering the catalytic droplet 300 is formed. Based on the annealing process, the catalytic droplet 300 rolls within the first groove 240, gradually inducing the amorphous semiconductor material of the semiconductor layer 411 within the first groove 240 to transform into a crystalline state, forming a semiconductor structure 410, which serves as the channel layer of the transistor 400. Compared with the method in related technologies that uses heteroepitaxial growth of a single-crystal silicon layer as the channel layer, this embodiment avoids the dislocation phenomenon caused by lattice mismatch in heteroepitaxial growth, reducing the manufacturing difficulty and cost of semiconductor devices and improving the yield of semiconductor devices. Moreover, this embodiment does not need to consider the limitation on the number of stacked layers due to heteroepitaxial growth, which is beneficial for forming semiconductor devices with higher storage density.
[0033] Optionally, in step S101 above, forming a stacked structure 200 on the substrate 100 includes: A multilayer first dielectric layer 210 and a multilayer first insulating layer 220 are alternately stacked on the substrate 100, and the resulting film structure is shown in the schematic diagram below. Figure 2As shown; the first dielectric layer 210 and the first insulating layer 220 at the ends along the second direction are removed, and a frame material is deposited to form a frame 800 that is fixedly connected to both the first insulating layer 220 and the first dielectric layer 210, serving as a support structure for the laminated structure. The resulting film structure is shown in the schematic diagram. Figures 3-4 As shown; the multilayer first dielectric layer 210 and multilayer first insulating layer 220 are patterned to form multiple first trenches 230 arranged along the first direction, and the resulting film structure is shown in the schematic diagram. Figures 5-6 As shown; the first insulating layer 220 exposed at both ends along the first direction is etched back to form multiple first grooves 240, and the resulting film structure is shown in the schematic diagram. Figure 7 As shown.
[0034] It should be noted that, as Figure 6 As shown, the first groove 230 is not formed at the left and right edges (the two ends of the first direction), but the first insulating layer 220 is exposed and simultaneously etched back to form the first groove 240.
[0035] In some possible embodiments, the material of the semiconductor structure 410 includes at least one of single-crystal silicon, single-crystal germanium, or silicon-germanium, obtained by inducing the amorphous semiconductor material of the semiconductor layer 411 in the first groove 240 to transform into a crystalline state, which can reduce the manufacturing process difficulty and cost of semiconductor devices and improve the yield of semiconductor devices.
[0036] In some possible embodiments, the formation of catalytic droplets 300 at the end of the first groove 240 along the second direction in step S102 above includes the following steps: like Figures 8-17 As shown, a catalyst layer 310 is deposited in the first trench 230 and the first groove 240 of the first region 250; the first region 250 is located at the end of the stacked structure 200 along the second direction.
[0037] The catalyst layer 310 is condensed into catalytic droplets 300 using plasma processing technology. The catalytic droplets 300 are located in the first region 250. The schematic diagram of the resulting film structure is shown below. Figure 18 As shown.
[0038] In this step, a catalyst layer 310 is deposited within the first trench 230 and the first groove 240, covering the inner walls of the first trench 230 and the first groove 240, respectively. The catalyst layer 310 is then subjected to plasma treatment to alter its morphology, forming droplet-shaped catalytic droplets 300. The catalytic droplets 300 are spherical and can roll along the first groove 240 during heating. During this rolling process, they absorb amorphous silicon material and catalyze it into monocrystalline silicon material.
[0039] In some possible embodiments, the deposition of the catalyst layer 310 in the first trench 230 and the first recess 240 of the first region 250 in the above steps includes the following steps: like Figures 8-9 As shown, a first sacrificial layer 500 is filled in the first trench 230 and the first groove 240.
[0040] like Figures 10-11 As shown, the first sacrificial layer 500 is removed from the first trench 230 and the first groove 240 of the first region 250.
[0041] like Figures 12-14 As shown, a catalyst layer 310 is deposited in the first trench 230 and the first groove 240 of the first region 250.
[0042] like Figures 15-16 As shown, the catalyst layer 310 at the bottom of the first trench 230 is removed.
[0043] In this embodiment, the first trench 230 and the first recess 240 outside the first region 250 are filled by the first sacrificial layer 500 to prevent the deposition of the catalyst layer 310 therein. This ensures that the catalyst layer 310 is deposited in the first recess 240, allowing the subsequent formation of catalytic droplets 300, thereby promoting the transformation of the amorphous semiconductor material of the semiconductor layer 411 to a crystalline state, forming a semiconductor structure 410 including single-crystal silicon material.
[0044] Optionally, the method for manufacturing a semiconductor device in this application embodiment further includes: grinding and removing the top catalyst layer 310.
[0045] Optionally, the method for manufacturing a semiconductor device in this embodiment of the application further includes: as follows Figures 17-18 As shown, all of the first sacrificial layer 500 is removed, and the first trench 230 and the first groove 240 are opened to provide a channel for the subsequent film formation.
[0046] In some possible embodiments, the catalyst layer 310 is made of at least one of indium, gold, nickel, iron, or aluminum.
[0047] In this embodiment, the catalyst layer 310 is made of at least one metal material selected from indium, gold, nickel, iron or aluminum, which can act as a catalyst in the metal-induced crystallization process to promote the transformation of the amorphous semiconductor material of the semiconductor layer 411 to a crystalline state, forming a semiconductor structure 410 including single-crystal silicon material.
[0048] In some possible embodiments, the plasma used in the plasma processing technology is formed from hydrogen gas.
[0049] In this embodiment, hydrogen plasma is used to treat the surface of the metal catalyst layer 310, so that the deposited layer on the surface of the catalyst layer 310 forms a spherical droplet shape.
[0050] In some possible embodiments, in step S103 above, depositing a semiconductor layer 411 covering the outer surface of the catalytic droplet 300 and the inner surface of the first groove 240 includes: like Figures 19-21 As shown, a semiconductor material layer 412 is deposited in the first trench 230 and the first groove 240, such that the semiconductor material layer 412 covers the outer surface of the catalytic droplet 300 and the inner surface of the first groove 240.
[0051] like Figures 22-24 As shown, the semiconductor material layer 412 in the first trench 230 is removed to form a semiconductor layer 411.
[0052] In this embodiment, a semiconductor material layer 412 is deposited on the inner wall of the first trench 230, the inner wall of the first groove 240, and the surface of the catalytic droplet 300. The semiconductor material layer 412 in the first trench 230 is removed, and only the semiconductor material layer 412 in the first groove 240 is retained, i.e., the semiconductor layer 411, to facilitate the formation of the semiconductor structure 410.
[0053] Optionally, step S103 may further include: grinding to remove the semiconductor material layer 412 on top of the stacked structure 200.
[0054] In some possible embodiments, after the annealing process in step S104 causes the catalytic droplets 300 to move along the second direction and induces the semiconductor layer 411 to react and form the semiconductor structure 410 of the transistor 400, the following steps are also included: like Figures 28-30 As shown, the first dielectric layer 210 is removed by wet etching, so that the semiconductor structure 410 is arranged in multiple layers with spacing, and both ends are supported and fixed by the frame 800.
[0055] like Figures 31-33 As shown, the channels between the semiconductor structures 410 are filled with a first insulating layer 220, which encloses each semiconductor structure 410, and the top of the first insulating layer 220 is ground flat.
[0056] Optionally, before forming the first source / drain 420 and the second source / drain 430, the method further includes: Figure 34 and Figure 35 As shown, by removing the first insulating layer 220 of the second region 413 and the third region 414, the second region 413 and the third region 414 can be opened by photolithography. Then, the exposed semiconductor structure 410 of the second region 413 and the third region 414 is doped to make it conductive.
[0057] In some possible embodiments, after the annealing process in step S104 causes the catalytic droplets 300 to move along the second direction and induces the semiconductor layer 411 to react and form the semiconductor structure 410 of the transistor 400, the following steps are also included: The semiconductor structure 410 in the second region 413 and the third region 414 is doped to form the first source / drain 420 and the second source / drain 430, respectively. The schematic diagram of the resulting film structure is shown below. Figures 36-37 As shown.
[0058] A gate dielectric structure 440 and a gate 450 are sequentially formed around the semiconductor structure 410 in the fourth region 415 to form a transistor 400; the second region 413, the fourth region 415, and the third region 414 are arranged sequentially along the second direction, and the resulting film structure is shown in the schematic diagram below. Figures 42-44 As shown.
[0059] Optionally, after forming the first source / drain 420 and the second source / drain 430, and before forming the gate dielectric structure 440 and the gate 450, the method further includes: Figures 38-39 As shown, the gaps in the second region 413 and the third region 414 are filled with the first insulating layer 220; as Figures 40-41 As shown, by removing the first insulating layer 220 of the fourth region 415, the fourth region 415 can be opened by photolithography.
[0060] Optionally, such as Figure 44 As shown, along a direction perpendicular to the substrate 100, the gates 450 of each layer of transistors 400 are in contact with each other to form the word lines of the memory.
[0061] After forming the gate dielectric structure 440 and the gate 450, the process further includes: fabricating a bit line 600 at one end of the first source / drain 420 of the semiconductor structure 410, and fabricating a capacitor 700 at one end of the second source / drain 430 of the semiconductor structure 410, thereby forming a semiconductor device, such as a three-dimensional memory. A schematic diagram of the three-dimensional memory structure can be found in [reference needed]. Figure 45 .
[0062] Optionally, the second region 413, the fourth region 415 and the third region 414 are arranged sequentially along the second direction.
[0063] It should be noted that the frame 800 serves to support the internal structure of the semiconductor device. This application does not limit the specific location of the frame 800 in the semiconductor device, as long as it can support the multilayer transistor 400. Therefore, it is not shown in the structural diagram of the semiconductor device.
[0064] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.
[0065] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.
[0066] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".
[0067] Based on the same inventive concept, such as Figure 44 and Figure 45 As shown, this application embodiment also provides a semiconductor device, including: a multilayer transistor 400, each transistor 400 including a plurality of transistors 400 arranged at intervals along a first direction; each transistor 400 includes a semiconductor structure 410 extending along a second direction, the semiconductor structure 410 being obtained by inducing the movement of catalytic droplets 300 to the semiconductor layer 411 based on an annealing process.
[0068] In this embodiment, each transistor 400 is formed one-to-one with each semiconductor structure 410. The arrangement of the transistors 400 is similar to that of the semiconductor structures 410, with multiple layers arranged, each layer including multiple transistors 400 disposed along the first direction. Specifically, based on the annealing process, catalytic droplets 300 roll within the first groove 240, gradually inducing the amorphous semiconductor material of the semiconductor layer 411 within the first groove 240 to transform into a crystalline state, forming the semiconductor structure 410, which serves as the channel layer for the transistors 400. Compared to the method in related technologies that uses heteroepitaxial growth of a single-crystal silicon layer as the channel layer, this embodiment avoids dislocation phenomena caused by lattice mismatch in heteroepitaxial growth, reducing the manufacturing difficulty and cost of semiconductor devices and improving the yield rate. Moreover, this embodiment does not need to consider the limitation on the number of stacked layers due to heteroepitaxial growth, which is beneficial for forming semiconductor devices with higher storage density.
[0069] In some possible embodiments, transistor 400 further includes: The first source / drain 420 and the second source / drain 430 are formed by semiconductor structure 410 located in the second region 413 and semiconductor structure 410 located in the third region 414, respectively.
[0070] The gate dielectric structure 440 and the gate 450 are sequentially arranged around the outer periphery of the semiconductor structure 410 in the fourth region 415; the second region 413, the fourth region 415 and the third region 414 are arranged sequentially along the second direction.
[0071] In this embodiment, the first source / drain 420 and the second source / drain 430 are spaced apart at the ends of the semiconductor structure 410, and the undoped semiconductor structure 410 between the first source / drain 420 and the second source / drain 430 forms the channel layer of the semiconductor structure 410. The gate dielectric structure 440 and the gate 450 are formed on the outer periphery of the semiconductor structure 410 (i.e., the channel layer) between the first source / drain 420 and the second source / drain 430, forming a complete transistor 400 structure. Figure 45 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. The semiconductor structure 410 is surrounded by the gate dielectric structure 440 and the gate 450, and therefore is not shown in the reference numerals. However, those skilled in the art can understand the position of the semiconductor structure 410.
[0072] Optionally, the semiconductor device further includes bit lines 600 and capacitors 700 located at both ends of the transistor 400. Exemplarily, the bit lines 600 extend along a first direction and are spaced apart in a direction perpendicular to the substrate 100, such as... Figure 45 As shown, the first source and drain electrodes 420 of a plurality of transistors spaced apart along a first direction are connected to the same bit line 600. Other features of the semiconductor device are similar to those in related technologies and will not be described in detail here.
[0073] Based on the same inventive concept, this application also provides an electronic device, including: any of the semiconductor devices provided in the above embodiments, or a semiconductor device manufactured by the manufacturing method of any of the semiconductor devices provided in the above embodiments.
[0074] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments or the semiconductor devices manufactured by the manufacturing methods of any of the semiconductor devices provided in the foregoing embodiments, the principles and technical effects are as described in the foregoing embodiments and will not be repeated here.
[0075] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.
[0076] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.
[0077] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.
[0078] By applying the embodiments of this application, at least the following beneficial effects can be achieved: 1. A catalytic droplet 300 is formed at the end of the first groove 240, which is on the same layer as the first insulating layer 220. A semiconductor layer 411 covering the catalytic droplet 300 is formed. Based on the annealing process, the catalytic droplet 300 rolls within the first groove 240, gradually inducing the amorphous semiconductor material of the semiconductor layer 411 within the first groove 240 to transform into a crystalline state, forming a semiconductor structure 410, which serves as the channel layer of the transistor 400. Compared with the method in related technologies that uses heteroepitaxial growth of a single-crystal silicon layer as the channel layer, the embodiments of this application can avoid the dislocation phenomenon caused by lattice mismatch in heteroepitaxial growth, which can reduce the manufacturing process difficulty and cost of semiconductor devices and improve the yield of semiconductor devices. Moreover, the embodiments of this application do not need to consider the limitation on the number of stacked layers due to heteroepitaxial growth, which is beneficial for forming semiconductor devices with higher storage density.
[0079] 2. A catalyst layer 310 is deposited within the first trench 230 and the first groove 240, covering the inner walls of the first region 250. The catalyst layer 310 is then subjected to plasma treatment technology to change its morphology, forming droplet-shaped catalytic droplets 300. The catalytic droplets 300 are spherical and can roll along the first groove 240 during heating. During the rolling process, they absorb amorphous silicon material and catalyze it into monocrystalline silicon material.
[0080] 3. The surface of the metal catalyst layer 310 is treated with hydrogen plasma to form a spherical droplet-shaped deposition layer on the surface of the catalyst layer 310.
[0081] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.
[0082] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0083] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0084] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0085] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure is formed on a substrate, the stacked structure comprising alternating layers of first dielectric layers and layers of first insulating layers; The stacked structure has a plurality of first trenches arranged at intervals along a first direction, and a first groove in the same layer as the first insulating layer; the first trenches and the first groove are connected and both extend along a second direction; the first direction intersects the second direction and are both parallel to the substrate; Catalytic droplets are formed at the end of the first groove along the second direction; A semiconductor layer is deposited to cover the outer surface of the catalytic droplet and the inner surface of the first groove; The annealing process causes the catalytic droplets to move along the second direction, inducing the semiconductor layer to react and form a semiconductor structure for a transistor.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The semiconductor structure includes at least one of monocrystalline silicon, monocrystalline germanium, or silicon-germanium.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a catalytic droplet at the end of the first groove along the second direction includes: A catalyst layer is deposited in the first trench and the first recess in the first region; the first region is located at the end of the stacked structure along the second direction; The catalyst layer is condensed into catalytic droplets using plasma processing technology, and the catalytic droplets are located in the first region.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The catalyst layer is made of at least one of indium, gold, nickel, iron, or aluminum.
5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, The plasma used in the plasma processing technology is formed from hydrogen gas.
6. The method for manufacturing a semiconductor device according to claim 3, characterized in that, Depositing a catalyst layer within the first trench and the first recess in the first region includes: A first sacrificial layer is filled into the first trench and the first recess; Remove the first sacrificial layer from the first trench and the first recess in the first region; A catalyst layer is deposited in the first trench and the first groove in the first region; Remove the catalyst layer at the bottom of the first trench.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Depositing to form a semiconductor layer covering the outer surface of the catalytic droplet and the inner surface of the first groove includes: A semiconductor material layer is deposited in the first trench and the first groove, such that the semiconductor material layer covers the outer surface of the catalytic droplet and the inner surface of the first groove. Remove the semiconductor material layer within the first trench to form the semiconductor layer.
8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After the catalytic droplets move along the second direction based on the annealing process to induce the semiconductor layer to react and form a transistor semiconductor structure, the process further includes: The semiconductor structures in the second and third regions are doped to form a first source / drain and a second source / drain, respectively. A gate dielectric structure and a gate electrode are sequentially formed on the outer periphery of the semiconductor structure in the fourth region to form a transistor; the second region, the fourth region and the third region are arranged sequentially along the second direction.
9. A semiconductor device, characterized in that, include: A multilayer transistor, each layer comprising a plurality of transistors arranged at a distance along a first direction; Each of the transistors includes a semiconductor structure extending along a second direction, the semiconductor structure being obtained by inducing a semiconductor layer through catalytic droplet movement via an annealing process.
10. The semiconductor device according to claim 9, characterized in that, The transistor also includes: The first source / drain and the second source / drain are respectively formed by the semiconductor structure located in the second region and the semiconductor structure located in the third region; A gate dielectric structure and a gate electrode are sequentially arranged around the outer periphery of the semiconductor structure in the fourth region; the second region, the fourth region, and the third region are arranged sequentially along the second direction.
11. An electronic device, characterized in that, include: A semiconductor device manufactured by the manufacturing method of any of the semiconductor devices described in claims 1-8 above, or a semiconductor device described in any of the semiconductor devices described in claims 9-10 above.