Power device package

Abstract

The invention discloses a power device package, which comprises a ceramic-based circuit board, and the ceramic-based circuit board comprises a bottom circuit layer and a ceramic substrate layer. The gallium nitride or silicon carbide transistor wafer is welded on the bottom circuit layer of the ceramic-based circuit board; the structure further comprises a circuit board frame, the ceramic-based circuit board is welded to the circuit board frame, and the gallium nitride or silicon carbide transistor wafer is located in a hole of the circuit board frame. The silicon-based transistor or the silicon-based driving circuit is welded on the top circuit layer of the circuit board frame; a novel high-temperature-resistant transistor is arranged on a high-temperature-resistant ceramic circuit board layer, and a silicon-based transistor or a driving circuit which is relatively low in temperature resistance is arranged on a common circuit board layer which is relatively low in temperature resistance. Higher working temperature of integral packaging is realized; and meanwhile, the high-temperature-resistant novel transistor wafer is arranged in the hole of the circuit board frame, so that the packaging cost is reduced, and the packaging process is optimized.

Description

Technical Field

[0001] This invention relates to the optimization of packaging processes and chip heat dissipation processes for power devices, as well as architecture design, and to the co-packaging technology of silicon-based transistors or chips and third- and fourth-generation semiconductor transistors. Background Technology

[0002] Ceramic-based circuit boards consist of a ceramic substrate and one or two conductive layers. It refers to a special process in which copper foil is directly bonded to the surface of a ceramic substrate at high temperature, resulting in high thermal conductivity.

[0003] Third-generation semiconductor materials GaN (gallium nitride) and SiC (silicon carbide) are representative of wide-bandgap semiconductors. GaN's bandgap bandwidth is three times that of Si, and its breakdown electric field is ten times that of Si. Therefore, power devices made of gallium nitride have significant advantages such as fast switching speed, low on-resistance, and small chip area, and are widely used in power adapters, industrial power supplies, and automotive electronics.

[0004] GaN power devices are generally classified into normally open (depletion-mode) and normally closed (enhancement-mode) gallium nitride. Currently, depletion-mode GaN solutions on the market mainly combine depletion-mode GaN power devices with low-voltage Si (silicon) MOSFETs (field-effect transistors). These GaN power devices can be flexibly paired with low-voltage Si devices in consumer electronics applications, which can fully utilize the high-frequency and high-conversion-efficiency characteristics of GaN, while also being fully compatible with Si MOSFETs in terms of driving.

[0005] Fourth-generation semiconductor materials, mainly represented by diamond and gallium oxide, have begun to be used in ultra-wide bandgap power devices; they can also operate at higher temperatures.

[0006] The operating temperatures that third- and fourth-generation semiconductor power devices can withstand are much higher than those of Si (silicon) devices. When Si power devices or Si driver devices are packaged with third- and fourth-generation semiconductor power devices (such as GaN or SiC transistors), the operating temperature of this packaged device is the operating temperature of the Si device. However, the actual operating temperature of the GaN or SiC transistors within the package is much higher than that of the Si device. This prevents the third- and fourth-generation semiconductor power devices from fully utilizing their capabilities and limits the application range of these new power devices.

[0007] Since the driving voltage of enhancement-mode GaN transistors is lower than that of Si MOS transistors, if an electronic system uses a Si MOS transistor driver chip, the output driving signal needs to be stepped down before it can be used to drive the enhancement-mode GaN transistor. Summary of the Invention

[0008] To address the aforementioned issues, this invention aims to provide a power device package that integrates Si MOS transistors or Si driver devices with third- or fourth-generation semiconductor power devices (such as GaN or SiC transistors) on different circuit board layers within the same package, thereby achieving a higher operating temperature for the overall package and leveraging the advantages of novel power devices.

[0009] To achieve this technical objective, the present invention provides a power device package, including a ceramic-based circuit board, which comprises a bottom circuit layer and a ceramic substrate layer; it also includes a gallium nitride or silicon carbide transistor wafer, which is soldered onto the bottom circuit layer of the ceramic-based circuit board; the bottom circuit layer of the ceramic-based circuit board has a set of pads for soldering the gallium nitride or silicon carbide transistor wafer, and also has two or more sets of external pads; it further includes a circuit board frame, which consists of a top circuit layer, a substrate layer, and a bottom circuit layer of the circuit board frame, with the top circuit layer of the circuit board frame having a circuit layer connected to the bottom circuit layer of the ceramic-based circuit board. The circuit includes a set of external pads that are connected to a set of external pads on the bottom layer of the ceramic-based circuit board. The gallium nitride or silicon carbide transistor wafers soldered to the bottom layer of the ceramic-based circuit board are located in holes in the circuit board frame. The holes are filled with colloid to cover and protect the gallium nitride or silicon carbide transistor wafers. The circuit also includes silicon-based transistors or silicon-based driving circuits, which are soldered to corresponding pads on the top layer of the circuit board frame via pins. The bottom layer of the circuit board frame has two or more sets of package pads, which are connected to corresponding pads on the top layer of the circuit board frame via vias.

[0010] Preferably, the gallium nitride or silicon carbide transistor wafers soldered onto the bottom circuit layer of the ceramic-based circuit board are a group of two or more gallium nitride or silicon carbide transistor wafers.

[0011] Preferably, the ceramic-based circuit board is a multilayer ceramic-based circuit board, including a top circuit layer, a ceramic substrate layer, and a bottom circuit layer. A heat sink can be installed on the top circuit layer to further improve the operating efficiency of the device.

[0012] The beneficial effects of this technical solution are: increasing the overall operating temperature of the package; achieving greater current carrying capacity and better performance; and optimizing the packaging process and cost. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the stacked cross-section of a specific embodiment of the present invention.

[0014] Figure 2 This is a top view of a specific embodiment two of the present invention.

[0015] Figure 3This is a cross-sectional schematic diagram of a ceramic-based circuit board according to a specific embodiment of the present invention.

[0016] Figure 4 This is a top view of the circuit board frame according to a specific embodiment of the present invention.

[0017] Figure 5 This is a bottom view of a specific embodiment two of the present invention.

[0018] Figure 6 This is a schematic diagram of the electrical connections of each pad in a specific embodiment two of the present invention.

[0019] Figure 7 This is a schematic diagram of the electrical connections of each pad in a specific embodiment three of the present invention.

[0020] Figure 8 This is a schematic diagram of the electrical connections of each pad in a specific embodiment four of the present invention.

[0021] Figure 9 This is a schematic diagram of the electrical connections of the pads on the bottom circuit layer of a ceramic-based circuit board according to a specific embodiment of the present invention, which is a fourth embodiment of the present invention.

[0022] Figure 10 This is a top view of a specific embodiment five of the present invention. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] like Figure 1As shown, a schematic cross-sectional view of a power device package according to Embodiment 1 of the present invention includes a ceramic-based circuit board 1, which includes a bottom circuit layer 11 and a ceramic substrate layer 12; it also includes a gallium nitride or silicon carbide transistor wafer 2, which is soldered onto the bottom circuit layer 11 of the ceramic-based circuit board 1 using direct soldering or wire bonding; the bottom circuit layer 11 of the ceramic-based circuit board 1 has a set of pads for soldering the gallium nitride or silicon carbide transistor wafer, and also has two or more sets of external pads; it also includes a circuit board frame 3, which is composed of a top circuit layer 31, a substrate layer 32, and a bottom circuit layer 33 of the circuit board frame. The top circuit layer 31 of the board frame is provided with a set of docking pads that are connected to a set of external pads on the bottom circuit layer 11 of the ceramic substrate circuit board 1. The set of docking pads are correspondingly soldered to the set of external pads on the bottom circuit layer 11 of the ceramic substrate circuit board 1. The gallium nitride or silicon carbide transistor wafer 2 soldered to the bottom circuit layer 11 of the ceramic substrate circuit board 1 is located in the hole 34 of the board frame 3. It also includes silicon-based transistors or silicon-based driving circuits 4, which are soldered to the corresponding pads on the top circuit layer 31 of the board frame through pins. The bottom circuit layer 33 of the board frame is provided with two or more sets of package pads, which are connected to the corresponding pads on the top circuit layer 31 of the board frame through corresponding through holes in a set of through holes 35.

[0025] like Figure 2 The image shown is a top view of a specific embodiment two of the present invention. It includes a ceramic-based circuit board 1, a Si MOS transistor 4, and a circuit board frame 3. The ceramic-based circuit board 1 and the Si MOS transistor 4 are soldered to the top layer 31 of the circuit board frame. A depletion-mode gallium nitride transistor wafer is soldered to the bottom layer 11 of the ceramic-based circuit board 1.

[0026] like Figure 3 The diagram shown is a cross-sectional view of a ceramic-based circuit board according to a specific embodiment of the present invention. The ceramic-based circuit board 1 includes a bottom circuit layer 11, a ceramic substrate layer 12, and a top circuit layer 13. A heat sink can be connected to the top circuit layer 13 to further increase the heat dissipation capacity of the power device package, thereby improving the operating efficiency and lifespan of the power device.

[0027] like Figure 4The image shown is a top view of the circuit board frame according to a specific embodiment of the present invention. The top layer 31 of the circuit board frame is provided with a set of bonding pads 3141, 3142, and 3143 that are connected to a set of external bonding pads on the bottom layer 11 of the ceramic substrate circuit board 1; a set of bonding pads 3121, 3122, and 3123 are also provided for bonding Si MOS transistors. Pad 3121 corresponds to the drain pin of the Si MOS transistor, pad 3122 corresponds to the source pin of the Si MOS transistor, and pad 3123 corresponds to the gate pin of the Si MOS transistor.

[0028] like Figure 5 The image shown is a bottom view of a specific embodiment of the present invention. The circuit board frame 3 has holes 34. After the ceramic-based circuit board 1 is soldered onto the circuit board frame 3, the depletion-type gallium nitride transistor wafer 2, soldered to the bottom circuit layer 11 of the ceramic-based circuit board 1, resides in the holes 34 of the circuit board frame 3. The holes 34 are filled with colloid, covering the depletion-type gallium nitride transistor wafer 2. A set of packaging pads 3341, 3322, and 3323 are arranged on the bottom circuit layer 33 of the circuit board frame, respectively connected to corresponding pads on the top circuit layer 31 of the circuit board frame through corresponding through-holes in a set of through-holes 35.

[0029] like Figure 6The diagram shows the electrical connections of the pads in a specific embodiment two of the present invention. The drain pin 41, source pin 42, and gate pin 43 of the Si MOS transistor are correspondingly soldered to a set of pads 3121, 3122, and 3123 arranged on the top layer of the circuit board frame 31. The depletion-type gallium nitride transistor wafer 2 is soldered to the bottom layer 11 of the ceramic substrate circuit board 1. A set of external pads 111, 112, and 113 are also arranged on the bottom layer 11 of the ceramic substrate circuit board 1. Pad 111 is connected to the drain pad of the depletion-type gallium nitride transistor wafer 2, pad 112 is connected to the source pad of the depletion-type gallium nitride transistor wafer 2, and pad 113 is connected to the gate pad of the depletion-type gallium nitride transistor wafer 2. The set of external pads 111, 112, and 113 on the bottom layer 11 of the ceramic substrate circuit board 1 are connected to the top layer of the circuit board frame 31. A set of pads 3141, 3142, and 3143 are soldered to each other. After soldering, the depletion-type gallium nitride transistor wafer 2 is located in the hole 34 of the circuit board frame 3. A set of package pads 3341, 3322, and 3323 on the bottom circuit layer 33 of the circuit board frame are respectively connected to the corresponding pads on the top circuit layer 31 of the circuit board frame through corresponding through holes in a set of through holes 35. Pad 3341 is connected to 3141 on the top circuit layer 31 of the circuit board frame through through holes. Pad 3322 is connected to 3122 on the top circuit layer 31 of the circuit board frame through through holes. Pad 3323 is connected to 3123 on the top circuit layer 31 of the circuit board frame through through holes.

[0030] like Figure 7The diagram shown is a schematic of the electrical connections of the pads in a specific embodiment three of the present invention. The voltage conversion circuit is soldered onto the top layer 31 of the circuit board frame. The voltage input pin pad is 4121, and the voltage output pin pad is 4122. The voltage conversion circuit is a DC-DC chip or an LDO chip, or a discrete voltage divider circuit can be used. The enhancement-mode gallium nitride transistor wafer 2 is soldered onto the bottom layer 11 of the ceramic substrate circuit board 1. A set of external pads 111, 112, and 113 are also provided on the bottom layer 11 of the ceramic substrate circuit board 1. Pad 111 is connected to the drain pad of the enhancement-mode gallium nitride transistor wafer 2, pad 112 is connected to the source pad of the enhancement-mode gallium nitride transistor wafer 2, and pad 113 is connected to the gate pad of the enhancement-mode gallium nitride transistor wafer 2. External pads 111, 112, and 113 are soldered to the mating pads 3141, 3142, and 3143 of the ceramic-based circuit board 1 arranged on the top circuit layer 31 of the circuit board frame. Pad 3143 is connected to the voltage output pin pad 4122. A set of package pads 3341, 3322, and 3323 are arranged on the bottom circuit layer 33 of the circuit board frame. Pad 3341 is connected to pad 3141 arranged on the top circuit layer 31 of the circuit board frame through a through hole. Pad 3322 is connected to pad 3142 arranged on the top circuit layer 31 of the circuit board frame through a through hole. Pad 3323 is connected to the voltage input pin pad 4121 arranged on the top circuit layer 31 of the circuit board frame through a through hole.

[0031] like Figure 8 The diagram shown illustrates the electrical connections of the pads in a specific embodiment four of the present invention. The enhancement-mode gallium nitride (GNU) transistor wafers soldered onto the bottom circuit layer 11 of the ceramic substrate circuit board 1 are two GNU transistor wafers 2-1 and 2-2 connected in parallel to achieve greater current carrying capacity. The connections of the other pads are the same as in Example three.

[0032] like Figure 9 The diagram shows the electrical connections of the pads on the bottom layer of the ceramic-based circuit board according to a specific embodiment of the present invention. Two enhancement-mode gallium nitride (GaN) transistor wafers 2-1 and 2-2 are connected in parallel. Pads 11-2-11 and 11-2-21, disposed on the bottom layer 11 of the ceramic-based circuit board 1, correspond to the drain pads of GaN transistor wafers 2-1 and 2-2, and are connected in parallel to the external pad 111 on the bottom layer 11. Pads 11-2-12 and 11-2-22 correspond to the source pads of GaN transistor wafers 2-1 and 2-2, and are connected in parallel to the external pad 112 on the bottom layer 11. Pads 11-2-13 and 11-2-23 correspond to the gate pads of GaN transistor wafers 2-1 and 2-2, and are connected in parallel to the external pad 113 on the bottom layer 11.

[0033] like Figure 10The image shown is a top view of a specific embodiment five of the present invention. It includes two sets of Si MOS transistors and depletion-mode gallium nitride (GaN) transistor wafers. The two Si MOS transistors are designated as 4-1 and 4-2. The GaN transistor wafers are respectively soldered to the bottom layer of ceramic substrate circuit boards 1-1 and 1-2. The Si MOS transistors and the ceramic substrate circuit board are soldered to the top layer of circuit board frame 3. Packaging pads are provided on the bottom layer of circuit board frame 3. The two sets of Si MOS transistors and the GaN transistor wafers are packaged together, realizing a half-bridge power module package.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any minor modifications, equivalent substitutions, and improvements made to the above embodiments based on the technical essence of the present invention should be included within the protection scope of the present invention.

Claims

1. A power device package, characterized in that: The system includes a ceramic-based circuit board, which comprises a bottom circuit layer and a ceramic substrate layer; it also includes gallium nitride (GaN) or silicon carbide (SiC) transistor wafers soldered onto the bottom circuit layer of the ceramic-based circuit board; the bottom circuit layer of the ceramic-based circuit board has a set of pads for soldering the GaN or SiC transistor wafers, and also has two or more sets of external pads; it also includes a circuit board frame, which consists of a top circuit layer, a substrate layer, and a bottom circuit layer, with the top circuit layer of the circuit board frame having pads connected to the bottom circuit layer of the ceramic-based circuit board. A set of external pads on the circuit layer are connected to a set of external pads on the bottom circuit layer of the ceramic-based circuit board. The gallium nitride or silicon carbide transistor wafers on the bottom circuit layer of the ceramic-based circuit board are located in the holes of the circuit board frame. It also includes silicon-based transistors or silicon-based driving circuits, which are soldered to corresponding pads on the top circuit layer of the circuit board frame through pins. Two or more sets of package pads are provided on the bottom circuit layer of the circuit board frame, which are connected to the corresponding pads on the top circuit layer of the circuit board frame through through holes.

2. The power device package according to claim 1, characterized in that: The gallium nitride or silicon carbide transistor wafers soldered onto the bottom circuit layer of the ceramic-based circuit board are a group of two or more gallium nitride or silicon carbide transistor wafers.

3. The power device package according to claim 1, characterized in that: The ceramic-based circuit board is a multilayer ceramic-based circuit board, including a top circuit layer, a ceramic substrate layer, and a bottom circuit layer.

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